correct linker script generation

cmake/FindCMSIS.cmake

@@ -22,6 +22,7 @@ function(cmsis_generate_default_linker_script FAMILY DEVICE CORE)
     stm32_get_memory_info(FAMILY ${FAMILY} DEVICE ${DEVICE} CORE ${CORE} FLASH SIZE FLASH_SIZE ORIGIN FLASH_ORIGIN)
     stm32_get_memory_info(FAMILY ${FAMILY} DEVICE ${DEVICE} CORE ${CORE} RAM SIZE RAM_SIZE ORIGIN RAM_ORIGIN)
     stm32_get_memory_info(FAMILY ${FAMILY} DEVICE ${DEVICE} CORE ${CORE} CCRAM SIZE CCRAM_SIZE ORIGIN CCRAM_ORIGIN)
+    stm32_get_memory_info(FAMILY ${FAMILY} DEVICE ${DEVICE} CORE ${CORE} RAM_SHARE SIZE RAM_SHARE_SIZE ORIGIN RAM_SHARE_ORIGIN)
     stm32_get_memory_info(FAMILY ${FAMILY} DEVICE ${DEVICE} CORE ${CORE} HEAP SIZE HEAP_SIZE)
     stm32_get_memory_info(FAMILY ${FAMILY} DEVICE ${DEVICE} CORE ${CORE} STACK SIZE STACK_SIZE)
     
@@ -30,9 +31,11 @@ function(cmsis_generate_default_linker_script FAMILY DEVICE CORE)
             -DFLASH_ORIGIN="${FLASH_ORIGIN}" 
             -DRAM_ORIGIN="${RAM_ORIGIN}" 
             -DCCRAM_ORIGIN="${CCRAM_ORIGIN}" 
+            -DRAM_SHARE_ORIGIN="${RAM_SHARE_ORIGIN}" 
             -DFLASH_SIZE="${FLASH_SIZE}" 
             -DRAM_SIZE="${RAM_SIZE}" 
-            -DCCRAM_SIZE="${CCRAM_SIZE}" 
+            -DCCRAM_SIZE="${CCRAM_SIZE}"
+            -DRAM_SHARE_SIZE="${RAM_SHARE_SIZE}" 
             -DSTACK_SIZE="${STACK_SIZE}" 
             -DHEAP_SIZE="${HEAP_SIZE}" 
             -DLINKER_SCRIPT="${OUTPUT_LD_FILE}"

cmake/stm32/common.cmake

@@ -168,7 +168,7 @@ function(stm32_get_cores CORES)
 endfunction()
 
 function(stm32_get_memory_info)
-    set(ARG_OPTIONS FLASH RAM CCRAM STACK HEAP)
+    set(ARG_OPTIONS FLASH RAM CCRAM STACK HEAP RAM_SHARE)
     set(ARG_SINGLE CHIP FAMILY DEVICE CORE SIZE ORIGIN)
     set(ARG_MULTIPLE "")
     cmake_parse_arguments(INFO "${ARG_OPTIONS}" "${ARG_SINGLE}" "${ARG_MULTIPLE}" ${ARGN})
@@ -196,7 +196,6 @@ function(stm32_get_memory_info)
     elseif(SIZE_CODE STREQUAL "B")
         set(FLASH "128K")
     elseif(SIZE_CODE STREQUAL "C")
-        # Note there is a problem with STM32WB15CC (320kB flash)
         set(FLASH "256K")
     elseif(SIZE_CODE STREQUAL "D")
         set(FLASH "384K")
@@ -222,10 +221,13 @@ function(stm32_get_memory_info)
     list(FIND STM32_${INFO_FAMILY}_TYPES ${INFO_TYPE} TYPE_INDEX)
     list(GET STM32_${INFO_FAMILY}_RAM_SIZES ${TYPE_INDEX} RAM)
     list(GET STM32_${INFO_FAMILY}_CCRAM_SIZES ${TYPE_INDEX} CCRAM)
+    list(GET STM32_${INFO_FAMILY}_RAM_SHARE_SIZES ${TYPE_INDEX} RAM_SHARE)
     set(FLASH_ORIGIN 0x8000000)
     set(RAM_ORIGIN 0x20000000)
     set(CCRAM_ORIGIN 0x10000000)
-    
+    set(RAM_SHARE_ORIGIN 0x20030000)
+
+    unset(TWO_FLASH_BANKS)
     if(FAMILY STREQUAL "F1")
         stm32f1_get_memory_info(${INFO_DEVICE} ${INFO_TYPE} FLASH RAM)
     elseif(FAMILY STREQUAL "L1")
@@ -236,11 +238,16 @@ function(stm32_get_memory_info)
         stm32f3_get_memory_info(${INFO_DEVICE} ${INFO_TYPE} FLASH RAM)
     elseif(FAMILY STREQUAL "H7")
         stm32h7_get_memory_info(${INFO_DEVICE} ${INFO_TYPE} "${INFO_CORE}" RAM FLASH_ORIGIN RAM_ORIGIN TWO_FLASH_BANKS)
-        if(TWO_FLASH_BANKS)
-            string(REGEX MATCH "([0-9]+)K" FLASH_KB ${FLASH})
-            math(EXPR FLASH_KB "${CMAKE_MATCH_1} / 2")
-            set(FLASH "${FLASH_KB}K")   
-        endif()
+    elseif(FAMILY STREQUAL "WL")
+        stm32wl_get_memory_info(${INFO_DEVICE} ${INFO_TYPE} "${INFO_CORE}" RAM FLASH_ORIGIN RAM_ORIGIN TWO_FLASH_BANKS)
+    elseif(FAMILY STREQUAL "WB")
+        stm32wb_get_memory_info(${INFO_DEVICE} ${INFO_TYPE} "${INFO_CORE}" RAM RAM_ORIGIN TWO_FLASH_BANKS)
+    endif()
+    # when a device is dual core, each core uses half of total flash
+    if(TWO_FLASH_BANKS)
+        string(REGEX MATCH "([0-9]+)K" FLASH_KB ${FLASH})
+        math(EXPR FLASH_KB "${CMAKE_MATCH_1} / 2")
+        set(FLASH "${FLASH_KB}K")   
     endif()
     
     if(INFO_FLASH)
@@ -252,6 +259,9 @@ function(stm32_get_memory_info)
     elseif(INFO_CCRAM)
         set(SIZE ${CCRAM})
         set(ORIGIN ${CCRAM_ORIGIN})
+    elseif(INFO_RAM_SHARE)
+        set(SIZE ${RAM_SHARE})
+        set(ORIGIN ${RAM_SHARE_ORIGIN})
     elseif(INFO_STACK)
         if (RAM STREQUAL "2K")
             set(SIZE 0x200)

cmake/stm32/h7.cmake

@@ -25,11 +25,6 @@ set(STM32_H7_CCRAM_SIZES
       0K   0K   0K   0K   0K   0K
 )
 
-set(STM32_H7_NO_FLASH_SPLIT
-      H723xx H725xx H730xx H730xxQ H733xx H735xx
-      H750xx H7B0xx H7B0xxQ
-)
-
 set(STM32_H7_DUAL_CORE
       H745xx H755xx H747xx H757xx
 )
@@ -59,10 +54,10 @@ target_compile_definitions(STM32::H7::M4 INTERFACE
 )
 
 function(stm32h7_get_memory_info DEVICE TYPE CORE RAM FLASH_ORIGIN RAM_ORIGIN TWO_FLASH_BANKS)
-    if(${TYPE} IN_LIST STM32_H7_NO_FLASH_SPLIT)
-        set(${TWO_FLASH_BANKS} FALSE PARENT_SCOPE)  
+    if(${TYPE} IN_LIST STM32_H7_DUAL_CORE)
+        set(${TWO_FLASH_BANKS} TRUE PARENT_SCOPE)  
     else()
-        set(${TWO_FLASH_BANKS} TRUE PARENT_SCOPE)
+        set(${TWO_FLASH_BANKS} FALSE PARENT_SCOPE)
     endif()
     if(NOT CORE)
         set(CORE "M7")

cmake/stm32/linker_ld.cmake

@@ -16,7 +16,19 @@ _eccmram = .;\n\
 } >CCMRAM AT> FLASH\n\
         ")
 endif()
-    
+
+if((NOT RAM_SHARE_SIZE) OR (RAM_SHARE_SIZE STREQUAL "0K"))
+    set(RAM_SHARE_DEFINITION "")
+    set(RAM_SHARE_SECTION "")
+else()
+    set(RAM_SHARE_DEFINITION "    RAM_SHARED (rw) : ORIGIN = ${RAM_SHARE_ORIGIN}, LENGTH = ${RAM_SHARE_SIZE}\n")
+    set(RAM_SHARE_SECTION "
+MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED\n\
+MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED\n\
+MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED\n\
+    ")
+endif()
+
 set(SCRIPT_TEXT 
 "ENTRY(Reset_Handler)\n\
 \n\
@@ -29,6 +41,7 @@ MEMORY\n\
     FLASH (rx)      : ORIGIN = ${FLASH_ORIGIN}, LENGTH = ${FLASH_SIZE}\n\
     RAM (xrw)      : ORIGIN = ${RAM_ORIGIN}, LENGTH = ${RAM_SIZE}\n\
 ${CCRAM_DEFINITION}\n\
+${RAM_SHARE_DEFINITION}\n\
 }\n\
 \n\
 SECTIONS\n\
@@ -137,6 +150,7 @@ ${CCRAM_SECTION}\n\
   }\n\
 \n\
   .ARM.attributes 0 : { *(.ARM.attributes) }\n\
+${RAM_SHARE_SECTION}\n\
 }"
 )
 file(WRITE "${LINKER_SCRIPT}" "${SCRIPT_TEXT}")

cmake/stm32/wb.cmake

@@ -5,9 +5,16 @@ set(STM32_WB_TYPE_MATCH
    "WB55.C" "WB55.[EGY]" "WB35.." "WB15.." "WB50.." "WB30.." "WB10.." "WB5M.."
 )
 
+# this is not full RAM of the chip but only the part allocated to M4 core (SRAM1 in datasheet)
 set(STM32_WB_RAM_SIZES 
-    128K 256K  96K  48K 128K  96K  48K 256K
+     64K 192K  32K  12K 64K  32K  12K 192K
 )
+
+# WB series need special area for SRAM2 shared with core M0PLUS
+set(STM32_WB_RAM_SHARE_SIZES 
+     10K  10K  10K  10K  10K  10K  10K  10K
+)
+
 set(STM32_WB_CCRAM_SIZES 
       0K   0K   0K   0K   0K   0K   0K   0K
 )
@@ -20,3 +27,12 @@ target_compile_options(STM32::WB::M4 INTERFACE
 target_link_options(STM32::WB::M4 INTERFACE 
     -mcpu=cortex-m4 -mfpu=fpv5-sp-d16 -mfloat-abi=hard
 )
+
+function(stm32wb_get_memory_info DEVICE TYPE CORE RAM RAM_ORIGIN TWO_FLASH_BANKS)
+    set(${TWO_FLASH_BANKS} TRUE PARENT_SCOPE)
+    list(FIND STM32_WB_TYPES ${TYPE} TYPE_INDEX)
+    list(GET STM32_WB_RAM_SIZES ${TYPE_INDEX} RAM_VALUE)
+    set(${RAM} "${RAM_VALUE}-4" PARENT_SCOPE)
+    set(${RAM_ORIGIN} 0x20000004 PARENT_SCOPE)
+endfunction()
+

cmake/stm32/wl.cmake

@@ -5,9 +5,19 @@ set(STM32_WL_TYPE_MATCH
    "WL54.." "WL55.." "WLE4.8" "WLE5.8" "WLE4.B" "WLE5.B" "WLE4.C" "WLE5.C" 
 )
 
+# this is RAM size allocated to M4 core
+# Note devices with 20 and 48K RAM can use only half of available RAM because 
+# there are 2 split sections of RAM and our default linker script only manages 
+# one section.
 set(STM32_WL_RAM_SIZES 
-     64K  64K  20K  20K  48K  48K  64K  64K
+     32K  32K  10K  10K  24K  24K  64K  64K
 )
+
+# this is RAM size allocated to M0PLUS core
+set(STM32_WL_M0PLUS_RAM_SIZES 
+     32K  32K   0K   0K   0K   0K   0K   0K
+)
+
 set(STM32_WL_CCRAM_SIZES 
       0K   0K   0K   0K   0K   0K   0K   0K
 )
@@ -34,6 +44,30 @@ target_link_options(STM32::WL::M0PLUS INTERFACE
     -mcpu=cortex-m0plus -mfloat-abi=soft
 )
 
+function(stm32wl_get_memory_info DEVICE TYPE CORE RAM FLASH_ORIGIN RAM_ORIGIN TWO_FLASH_BANKS)
+    if(${TYPE} IN_LIST STM32_WL_DUAL_CORE)
+        set(${TWO_FLASH_BANKS} TRUE PARENT_SCOPE)  
+    else()
+        set(${TWO_FLASH_BANKS} FALSE PARENT_SCOPE)
+    endif()
+    list(FIND STM32_WL_TYPES ${TYPE} TYPE_INDEX)
+    if(CORE STREQUAL "M4")
+        list(GET STM32_WL_RAM_SIZES ${TYPE_INDEX} RAM_VALUE)
+        set(${RAM} ${RAM_VALUE} PARENT_SCOPE)
+        set(${FLASH_ORIGIN} 0x8000000 PARENT_SCOPE)
+        set(${RAM_ORIGIN} 0x20000000 PARENT_SCOPE)
+    elseif((${TYPE} IN_LIST STM32_WL_DUAL_CORE) AND (CORE STREQUAL "M0PLUS"))
+        list(GET STM32_WL_M0PLUS_RAM_SIZES ${TYPE_INDEX} RAM_VALUE)
+        set(${RAM} ${RAM_VALUE} PARENT_SCOPE)
+        set(${FLASH_ORIGIN} 0x8020000 PARENT_SCOPE)
+        set(${RAM_ORIGIN} 0x20008000 PARENT_SCOPE)
+    else()
+        message(FATAL_ERROR "Unknown core ${CORE}")
+    endif()
+endfunction()
+
+
+
 function(stm32wl_get_device_cores DEVICE TYPE CORES)
     if(${TYPE} IN_LIST STM32_WL_DUAL_CORE)
         set(${CORES} M4 M0PLUS PARENT_SCOPE)