Add airmouse/lib/lsm6dso-api from https://github.com/STMicroelectronics/stm32-lsm6dso

git-subtree-dir: airmouse/lib/lsm6dso-api
git-subtree-mainline: 4f3c5f303b1f28716dffbcdd4d7eb0507bc7ca48
git-subtree-split: 24788033c89e3148989e8d99d7e417edde0ae477

airmouse/lib/lsm6dso-api/.gitsubtree

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+https://github.com/STMicroelectronics/stm32-lsm6dso main /

airmouse/lib/lsm6dso-api/CODE_OF_CONDUCT.md

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+# Contributor Covenant Code of Conduct
+
+## Our Pledge
+
+In the interest of fostering an open and welcoming environment, we as
+contributors and maintainers pledge to making participation in our project and
+our community a harassment-free experience for everyone, regardless of age, body
+size, disability, ethnicity, sex characteristics, gender identity and expression,
+level of experience, education, socio-economic status, nationality, personal
+appearance, race, religion, or sexual identity and orientation.
+
+## Our Standards
+
+Examples of behavior that contributes to creating a positive environment
+include:
+
+* Using welcoming and inclusive language
+* Being respectful of differing viewpoints and experiences
+* Gracefully accepting constructive criticism
+* Focusing on what is best for the community
+* Showing empathy towards other community members
+
+Examples of unacceptable behavior by participants include:
+
+* The use of sexualized language or imagery and unwelcome sexual attention or
+ advances
+* Trolling, insulting/derogatory comments, and personal or political attacks
+* Public or private harassment
+* Publishing others' private information, such as a physical or electronic
+ address, without explicit permission
+* Other conduct which could reasonably be considered inappropriate in a
+ professional setting
+
+## Our Responsibilities
+
+Project maintainers are responsible for clarifying the standards of acceptable
+behavior and are expected to take appropriate and fair corrective action in
+response to any instances of unacceptable behavior.
+
+Project maintainers have the right and responsibility to remove, edit, or
+reject comments, commits, code, wiki edits, issues, and other contributions
+that are not aligned to this Code of Conduct, or to ban temporarily or
+permanently any contributor for other behaviors that they deem inappropriate,
+threatening, offensive, or harmful.
+
+## Scope
+
+This Code of Conduct applies both within project spaces and in public spaces
+when an individual is representing the project or its community. Examples of
+representing a project or community include using an official project e-mail
+address, posting via an official social media account, or acting as an appointed
+representative at an online or offline event. Representation of a project may be
+further defined and clarified by project maintainers.
+
+## Enforcement
+
+Instances of abusive, harassing, or otherwise unacceptable behavior may be
+reported by contacting the project team via this [link](https://www.st.com/content/st_com/en/contact-us.html).
+All complaints will be reviewed and investigated and will result in a response that
+is deemed necessary and appropriate to the circumstances. The project team is
+obligated to maintain confidentiality with regard to the reporter of an incident.
+Further details of specific enforcement policies may be posted separately.
+
+Project maintainers who do not follow or enforce the Code of Conduct in good
+faith may face temporary or permanent repercussions as determined by other
+members of the project's leadership.
+
+## Attribution
+
+This Code of Conduct is adapted from the [Contributor Covenant](https://www.contributor-covenant.org), version 1.4,
+available [here](https://www.contributor-covenant.org/version/1/4/code-of-conduct.html).
+
+For answers to common questions about this code of conduct, see the [FAQ section](https://www.contributor-covenant.org/faq).

airmouse/lib/lsm6dso-api/CONTRIBUTING.md

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+# Contributing guide
+
+This guide serves as a checklist before contributing to this repository. It mainly focuses on the steps to follow to submit an issue or a pull-request.
+
+## 1. Issues
+
+### 1.1 Before opening an issue
+
+Please check the following points before posting an issue:
+* Make sure you are using the latest commit (major releases are tagged, but corrections are available as new commits).
+* Make sure your issue is a question/feedback/suggestions **related to** the software provided in this repository. Otherwise, please refer to section [3](CONTRIBUTING.md#3-support-requests-and-questions) below.
+* Make sure your issue is not already reported/fixed on GitHub or discussed on a previous issue. Do not forget to browse into the **closed** issues.
+
+### 1.2 Posting the issue
+
+When you have checked the previous points, create a new report from the **Issues** tab of this repository. A template is available [here](../../issues/new/choose) to help you report the issue you are facing or the enhancement you would like to propose.
+
+## 2. Pull Requests
+
+### 2.1 Before opening a pull-request
+
+STMicrolectronics is happy to receive contributions from the community, based on an initial Contributor License Agreement (CLA) procedure.
+
+* If you are an individual writing original source code and you are sure **you own the intellectual property**, then you need to sign an Individual [CLA](https://cla.st.com).
+* If you work for a company that wants also to allow you to contribute with your work, your company needs to provide a Corporate [CLA](https://cla.st.com) mentioning your GitHub account name.
+* If you are not sure that a CLA (Individual or Corporate) has been signed for your GitHub account you can check the [CLA](https://cla.st.com) dedicated page.
+
+Please note that:
+* The Corporate CLA will always take precedence over the Individual CLA.
+* One CLA submission is sufficient, for any project proposed by STMicroelectronics.
+
+### 2.2 How to proceed
+
+* We recommend to engage first a communication thru an issue, in order to present your proposal, just to confirm that it corresponds to STMicroelectronics' domain or scope.
+* Then fork the project to your GitHub account to further develop your contribution. Please use the latest commit version.
+* Please, submit one pull-request per new feature or proposal. This will ease the analysis and the final merge if accepted.
+
+## 3. Support requests and questions
+
+For support requests or any other question related to the product, the tools, the environment, you can submit a post to the **ST Community** on the appropriate topic [page](https://community.st.com/s/topiccatalog).

airmouse/lib/lsm6dso-api/LICENSE.md

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+Copyright 2019 STMicroelectronics.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice,
+this list of conditions and the following disclaimer in the documentation and/or
+other materials provided with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its contributors
+may be used to endorse or promote products derived from this software without
+specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

airmouse/lib/lsm6dso-api/README.md

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+# BSP LSM6DSO Component
+
+![latest tag](https://img.shields.io/github/v/tag/STMicroelectronics/stm32-lsm6dso.svg?color=brightgreen)
+
+## Overview
+
+**STM32Cube** is an STMicroelectronics original initiative to ease the developers life by reducing efforts, time and cost.
+
+**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform delivered for each STM32 series.
+   * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product.
+   * The STM32 HAL-LL drivers, an abstraction layer offering a set of APIs ensuring maximized portability across the STM32 portfolio.
+   * The BSP drivers of each evaluation, demonstration or nucleo board provided for this STM32 series.
+   * A consistent set of middleware components such as RTOS, USB, FatFS, graphics, touch sensing library...
+   * A full set of software projects (basic examples, applications, and demonstrations) for each board provided for this STM32 series.
+
+Two models of publication are proposed for the STM32Cube embedded software:
+   * The monolithic **MCU Package**: all STM32Cube software modules of one STM32 series are present (Drivers, Middleware, Projects, Utilities) in the repository (usual name **STM32Cubexx**, xx corresponding to the STM32 series).
+   * The **MCU component**: each STM32Cube software module being part of the STM32Cube MCU Package, is delivered as an individual repository, allowing the user to select and get only the required software functions.
+
+## Description
+
+This **lsm6dso** MCU component repository is one element **common to all** STM32Cube MCU embedded software packages, providing the **LSM6DSO** BSP MEMS component part.
+
+## Release note
+
+Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/lsm6dso/blob/main/Release_Notes.html).
+
+## Compatibility information
+
+Please refer to the repository of the BSP **board** driver you are using to know which version of this BSP component driver to use. It is **crucial** that you use a consistent set of versions.
+
+## Troubleshooting
+
+Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide.

airmouse/lib/lsm6dso-api/Release_Notes.html

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+<!DOCTYPE html>
+<html xmlns="http://www.w3.org/1999/xhtml" lang="en" xml:lang="en">
+<head>
+  <meta charset="utf-8" />
+  <meta name="generator" content="pandoc" />
+  <meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" />
+  <title>Release Notes for LSM6DSO Component</title>
+  <style>
+    code{white-space: pre-wrap;}
+    span.smallcaps{font-variant: small-caps;}
+    div.columns{display: flex; gap: min(4vw, 1.5em);}
+    div.column{flex: auto; overflow-x: auto;}
+    div.hanging-indent{margin-left: 1.5em; text-indent: -1.5em;}
+    ul.task-list{list-style: none;}
+    ul.task-list li input[type="checkbox"] {
+      width: 0.8em;
+      margin: 0 0.8em 0.2em -1.6em;
+      vertical-align: middle;
+    }
+    .display.math{display: block; text-align: center; margin: 0.5rem auto;}
+  </style>
+  <link rel="stylesheet" href="_htmresc/mini-st_2020.css" />
+  <link rel="icon" type="image/x-icon" href="_htmresc/favicon.png" />
+  <!--[if lt IE 9]>
+    <script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script>
+  <![endif]-->
+</head>
+<body>
+<div class="row">
+<div class="col-sm-12 col-lg-4">
+<center>
+<h1 id="release-notes-for-lsm6dso-component-driver">Release Notes for
+LSM6DSO Component Driver</h1>
+<p>Copyright © 2022 STMicroelectronics<br />
+</p>
+<a href="https://www.st.com" class="logo"><img
+src="_htmresc/st_logo_2020.png" alt="ST logo" /></a>
+</center>
+<h1 id="purpose">Purpose</h1>
+<p>This directory contains the LSM6DSO component drivers.</p>
+</div>
+<section id="update-history" class="col-sm-12 col-lg-8">
+<h1>Update history</h1>
+<div class="collapse">
+<input type="checkbox" id="collapse-section15" checked aria-hidden="true">
+<label for="collapse-section15" aria-hidden="true">V1.7.0 /
+31-October-2022</label>
+<div>
+<h2 id="main-changes">Main changes</h2>
+<h3 id="maintenance-release">Maintenance release</h3>
+<ul>
+<li>Synchronized PID with currently latest version on ST GitHub</li>
+<li>Added Delay function</li>
+</ul>
+<h2 id="section"></h2>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section14" aria-hidden="true">
+<label for="collapse-section14" aria-hidden="true">V1.6.0 /
+23-March-2022</label>
+<div>
+<h2 id="main-changes-1">Main changes</h2>
+<h3 id="maintenance-release-1">Maintenance release</h3>
+<ul>
+<li>Synchronized PID with currently latest version on ST GitHub</li>
+</ul>
+<h2 id="section-1"></h2>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section13" aria-hidden="true">
+<label for="collapse-section13" aria-hidden="true">V1.5.4 /
+09-February-2022</label>
+<div>
+<h2 id="main-changes-2">Main changes</h2>
+<h3 id="patch-release">Patch release</h3>
+<ul>
+<li>Update License to new format</li>
+</ul>
+<h2 id="section-2"></h2>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section12" aria-hidden="true">
+<label for="collapse-section12" aria-hidden="true">V1.5.3 /
+17-November-2021</label>
+<div>
+<h2 id="main-changes-3">Main changes</h2>
+<h3 id="patch-release-1">Patch release</h3>
+<ul>
+<li>Fix C++ compiler errors</li>
+</ul>
+<h2 id="section-3"></h2>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section11" aria-hidden="true">
+<label for="collapse-section11" aria-hidden="true">V1.5.2 /
+21-April-2021</label>
+<div>
+<h2 id="main-changes-4">Main changes</h2>
+<h3 id="patch-release-2">Patch release</h3>
+<ul>
+<li>Update Release Notes to new format</li>
+</ul>
+<h2 id="section-4"></h2>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section10" aria-hidden="true">
+<label for="collapse-section10" aria-hidden="true">V1.5.1 /
+15-April-2021</label>
+<div>
+<h2 id="main-changes-5">Main changes</h2>
+<h3 id="patch-release-3">Patch release</h3>
+<ul>
+<li>Fix issues on INT2 events</li>
+</ul>
+<h2 id="section-5"></h2>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section9" aria-hidden="true">
+<label for="collapse-section9" aria-hidden="true">V1.5.0 /
+03-March-2021</label>
+<div>
+<h2 id="main-changes-6">Main changes</h2>
+<h3 id="maintenance-release-2">Maintenance release</h3>
+<ul>
+<li>Synchronize PID with latest version on ST GitHub</li>
+</ul>
+<h2 id="section-6"></h2>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section8" aria-hidden="true">
+<label for="collapse-section8" aria-hidden="true">V1.4.0 /
+28-October-2020</label>
+<div>
+<h2 id="main-changes-7">Main changes</h2>
+<h3 id="maintenance-release-3">Maintenance release</h3>
+<ul>
+<li>Update PID</li>
+</ul>
+<h2 id="section-7"></h2>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section7" aria-hidden="true">
+<label for="collapse-section7" aria-hidden="true">V1.3.0 /
+03-March-2020</label>
+<div>
+<h2 id="main-changes-8">Main changes</h2>
+<h3 id="maintenance-release-4">Maintenance release</h3>
+<ul>
+<li>Update PID</li>
+<li>Add MISRA 2012 compliancy</li>
+</ul>
+<h2 id="section-8"></h2>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section6" aria-hidden="true">
+<label for="collapse-section6" aria-hidden="true">V1.2.3 /
+10-February-2020</label>
+<div>
+<h2 id="main-changes-9">Main changes</h2>
+<h3 id="patch-release-4">Patch release</h3>
+<ul>
+<li>Align ODR values like PID</li>
+</ul>
+<h2 id="section-9"></h2>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section5" aria-hidden="true">
+<label for="collapse-section5" aria-hidden="true">V1.2.2 /
+11-October-2019</label>
+<div>
+<h2 id="main-changes-10">Main changes</h2>
+<h3 id="patch-release-5">Patch release</h3>
+<ul>
+<li>Rename context type to universal stmdev_ctx_t</li>
+<li>Move unions from PID to HLD</li>
+</ul>
+<h2 id="section-10"></h2>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section4" aria-hidden="true">
+<label for="collapse-section4" aria-hidden="true">V1.2.1 /
+23-July-2019</label>
+<div>
+<h2 id="main-changes-11">Main changes</h2>
+<h3 id="patch-release-6">Patch release</h3>
+<ul>
+<li>Update license</li>
+</ul>
+<h2 id="section-11"></h2>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section3" aria-hidden="true">
+<label for="collapse-section3" aria-hidden="true">V1.2.0 /
+28-May-2019</label>
+<div>
+<h2 id="main-changes-12">Main changes</h2>
+<h3 id="maintenance-release-5">Maintenance release</h3>
+<ul>
+<li>PID update from ST GitHub</li>
+<li>Add new APIs for VibrationMonitoring to HLD</li>
+<li>HLD coding style update</li>
+</ul>
+<h2 id="section-12"></h2>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section2" aria-hidden="true">
+<label for="collapse-section2" aria-hidden="true">V1.1.0 /
+04-April-2019</label>
+<div>
+<h2 id="main-changes-13">Main changes</h2>
+<h3 id="maintenance-release-6">Maintenance release</h3>
+<ul>
+<li>Add new APIs</li>
+</ul>
+<h2 id="section-13"></h2>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section1" aria-hidden="true">
+<label for="collapse-section1" aria-hidden="true">V1.0.0 /
+31-January-2019</label>
+<div>
+<h2 id="main-changes-14">Main changes</h2>
+<h3 id="first-release">First release</h3>
+<ul>
+<li>First official release</li>
+</ul>
+<h2 id="section-14"></h2>
+</div>
+</div>
+</section>
+</div>
+<footer class="sticky">
+<div class="columns">
+<div class="column" style="width:95%;">
+<p>For complete documentation on LSM6DSO, visit: <a
+href="https://www.st.com/content/st_com/en/products/mems-and-sensors/inemo-inertial-modules/lsm6dso.html">LSM6DSO</a></p>
+</div><div class="column" style="width:5%;">
+<p><abbr title="Based on template cx566953 version 2.0">Info</abbr></p>
+</div>
+</div>
+</footer>
+</body>
+</html>

airmouse/lib/lsm6dso-api/SECURITY.md

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+# Report potential product security vulnerabilities
+
+ST places a high priority on security, and our Product Security Incident
+Response Team (PSIRT) is committed to rapidly addressing potential security
+vulnerabilities affecting our products. PSIRT's long history and vast experience
+in security allows ST to perform clear analyses and provide appropriate guidance
+on mitigations and solutions when applicable.
+
+If you wish to report potential security vulnerabilities regarding our products,
+**please do not report them through public GitHub issues.** Instead, we
+encourage you to report them to our ST PSIRT following the process described at:
+**https://www.st.com/content/st_com/en/security/report-vulnerabilities.html**
+
+### IMPORTANT - READ CAREFULLY:
+
+STMicroelectronics International N.V., on behalf of itself, its affiliates and
+subsidiaries, (collectively “ST”) takes all potential security vulnerability
+reports or other related communications (“Report(s)”) seriously. In order to
+review Your Report (the terms “You” and “Yours” include your employer, and all
+affiliates, subsidiaries and related persons or entities) and take actions as
+deemed appropriate, ST requires that we have the rights and Your permission to
+do so.
+
+As such, by submitting Your Report to ST, You agree that You have the right to
+do so, and You grant to ST the rights to use the Report for purposes related to
+security vulnerability analysis, testing, correction, patching, reporting and
+any other related purpose or function.
+
+By submitting Your Report, You agree that ST’s
+[Privacy Policy](https://www.st.com/content/st_com/en/common/privacy-portal.html)
+applies to all related communications.

airmouse/lib/lsm6dso-api/_htmresc/mini-st_2020.css

@@ -0,0 +1,1711 @@
+@charset "UTF-8";
+/*
+  Flavor name: Custom (mini-custom)
+  Generated online - https://minicss.org/flavors
+  mini.css version: v3.0.1
+*/
+/*
+  Browsers resets and base typography.
+*/
+/* Core module CSS variable definitions */
+:root {
+  --fore-color: #03234b;
+  --secondary-fore-color: #03234b;
+  --back-color: #ffffff;
+  --secondary-back-color: #ffffff;
+  --blockquote-color: #e6007e;
+  --pre-color: #e6007e;
+  --border-color: #3cb4e6;
+  --secondary-border-color: #3cb4e6;
+  --heading-ratio: 1.2;
+  --universal-margin: 0.5rem;
+  --universal-padding: 0.25rem;
+  --universal-border-radius: 0.075rem;
+  --background-margin: 1.5%;
+  --a-link-color: #3cb4e6;
+  --a-visited-color: #8c0078; }
+
+html {
+  font-size: 13.5px; }
+
+a, b, del, em, i, ins, q, span, strong, u {
+  font-size: 1em; }
+
+html, * {
+  font-family: -apple-system, BlinkMacSystemFont, Helvetica, arial, sans-serif;
+  line-height: 1.25;
+  -webkit-text-size-adjust: 100%; }
+
+* {
+  font-size: 1rem; }
+
+body {
+  margin: 0;
+  color: var(--fore-color);
+  @background: var(--back-color);
+  background: var(--back-color) linear-gradient(#ffd200, #ffd200) repeat-y left top;
+  background-size: var(--background-margin);
+  }
+
+details {
+  display: block; }
+
+summary {
+  display: list-item; }
+
+abbr[title] {
+  border-bottom: none;
+  text-decoration: underline dotted; }
+
+input {
+  overflow: visible; }
+
+img {
+  max-width: 100%;
+  height: auto; }
+
+h1, h2, h3, h4, h5, h6 {
+  line-height: 1.25;
+  margin: calc(1.5 * var(--universal-margin)) var(--universal-margin);
+  font-weight: 400; }
+  h1 small, h2 small, h3 small, h4 small, h5 small, h6 small {
+    color: var(--secondary-fore-color);
+    display: block;
+    margin-top: -0.25rem; }
+
+h1 {
+  font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); }
+
+h2 {
+  font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) );
+  border-style: none none solid none ; 
+  border-width: thin;
+  border-color: var(--border-color); }
+h3 {
+  font-size: calc(1rem * var(--heading-ratio) ); }
+
+h4 {
+  font-size: calc(1rem * var(--heading-ratio)); }
+
+h5 {
+  font-size: 1rem; }
+
+h6 {
+  font-size: calc(1rem / var(--heading-ratio)); }
+
+p {
+  margin: var(--universal-margin); }
+
+ol, ul {
+  margin: var(--universal-margin);
+  padding-left: calc(3 * var(--universal-margin)); }
+
+b, strong {
+  font-weight: 700; }
+
+hr {
+  box-sizing: content-box;
+  border: 0;
+  line-height: 1.25em;
+  margin: var(--universal-margin);
+  height: 0.0714285714rem;
+  background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); }
+
+blockquote {
+  display: block;
+  position: relative;
+  font-style: italic;
+  color: var(--secondary-fore-color);
+  margin: var(--universal-margin);
+  padding: calc(3 * var(--universal-padding));
+  border: 0.0714285714rem solid var(--secondary-border-color);
+  border-left: 0.3rem solid var(--blockquote-color);
+  border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; }
+  blockquote:before {
+    position: absolute;
+    top: calc(0rem - var(--universal-padding));
+    left: 0;
+    font-family: sans-serif;
+    font-size: 2rem;
+    font-weight: 800;
+    content: "\201c";
+    color: var(--blockquote-color); }
+  blockquote[cite]:after {
+    font-style: normal;
+    font-size: 0.75em;
+    font-weight: 700;
+    content: "\a—  " attr(cite);
+    white-space: pre; }
+
+code, kbd, pre, samp {
+  font-family: Menlo, Consolas, monospace;
+  font-size: 0.85em; }
+
+code {
+  background: var(--secondary-back-color);
+  border-radius: var(--universal-border-radius);
+  padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); }
+
+kbd {
+  background: var(--fore-color);
+  color: var(--back-color);
+  border-radius: var(--universal-border-radius);
+  padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); }
+
+pre {
+  overflow: auto;
+  background: var(--secondary-back-color);
+  padding: calc(1.5 * var(--universal-padding));
+  margin: var(--universal-margin);
+  border: 0.0714285714rem solid var(--secondary-border-color);
+  border-left: 0.2857142857rem solid var(--pre-color);
+  border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; }
+
+sup, sub, code, kbd {
+  line-height: 0;
+  position: relative;
+  vertical-align: baseline; }
+
+small, sup, sub, figcaption {
+  font-size: 0.75em; }
+
+sup {
+  top: -0.5em; }
+
+sub {
+  bottom: -0.25em; }
+
+figure {
+  margin: var(--universal-margin); }
+
+figcaption {
+  color: var(--secondary-fore-color); }
+
+a {
+  text-decoration: none; }
+  a:link {
+    color: var(--a-link-color); }
+  a:visited {
+    color: var(--a-visited-color); }
+  a:hover, a:focus {
+    text-decoration: underline; }
+
+/*
+  Definitions for the grid system, cards and containers.
+*/
+.container {
+  margin: 0 auto;
+  padding: 0 calc(1.5 * var(--universal-padding)); }
+
+.row {
+  box-sizing: border-box;
+  display: flex;
+  flex: 0 1 auto;
+  flex-flow: row wrap;
+  margin: 0 0 0 var(--background-margin); }
+
+.col-sm,
+[class^='col-sm-'],
+[class^='col-sm-offset-'],
+.row[class*='cols-sm-'] > * {
+  box-sizing: border-box;
+  flex: 0 0 auto;
+  padding: 0 calc(var(--universal-padding) / 2); }
+
+.col-sm,
+.row.cols-sm > * {
+  max-width: 100%;
+  flex-grow: 1;
+  flex-basis: 0; }
+
+.col-sm-1,
+.row.cols-sm-1 > * {
+  max-width: 8.3333333333%;
+  flex-basis: 8.3333333333%; }
+
+.col-sm-offset-0 {
+  margin-left: 0; }
+
+.col-sm-2,
+.row.cols-sm-2 > * {
+  max-width: 16.6666666667%;
+  flex-basis: 16.6666666667%; }
+
+.col-sm-offset-1 {
+  margin-left: 8.3333333333%; }
+
+.col-sm-3,
+.row.cols-sm-3 > * {
+  max-width: 25%;
+  flex-basis: 25%; }
+
+.col-sm-offset-2 {
+  margin-left: 16.6666666667%; }
+
+.col-sm-4,
+.row.cols-sm-4 > * {
+  max-width: 33.3333333333%;
+  flex-basis: 33.3333333333%; }
+
+.col-sm-offset-3 {
+  margin-left: 25%; }
+
+.col-sm-5,
+.row.cols-sm-5 > * {
+  max-width: 41.6666666667%;
+  flex-basis: 41.6666666667%; }
+
+.col-sm-offset-4 {
+  margin-left: 33.3333333333%; }
+
+.col-sm-6,
+.row.cols-sm-6 > * {
+  max-width: 50%;
+  flex-basis: 50%; }
+
+.col-sm-offset-5 {
+  margin-left: 41.6666666667%; }
+
+.col-sm-7,
+.row.cols-sm-7 > * {
+  max-width: 58.3333333333%;
+  flex-basis: 58.3333333333%; }
+
+.col-sm-offset-6 {
+  margin-left: 50%; }
+
+.col-sm-8,
+.row.cols-sm-8 > * {
+  max-width: 66.6666666667%;
+  flex-basis: 66.6666666667%; }
+
+.col-sm-offset-7 {
+  margin-left: 58.3333333333%; }
+
+.col-sm-9,
+.row.cols-sm-9 > * {
+  max-width: 75%;
+  flex-basis: 75%; }
+
+.col-sm-offset-8 {
+  margin-left: 66.6666666667%; }
+
+.col-sm-10,
+.row.cols-sm-10 > * {
+  max-width: 83.3333333333%;
+  flex-basis: 83.3333333333%; }
+
+.col-sm-offset-9 {
+  margin-left: 75%; }
+
+.col-sm-11,
+.row.cols-sm-11 > * {
+  max-width: 91.6666666667%;
+  flex-basis: 91.6666666667%; }
+
+.col-sm-offset-10 {
+  margin-left: 83.3333333333%; }
+
+.col-sm-12,
+.row.cols-sm-12 > * {
+  max-width: 100%;
+  flex-basis: 100%; }
+
+.col-sm-offset-11 {
+  margin-left: 91.6666666667%; }
+
+.col-sm-normal {
+  order: initial; }
+
+.col-sm-first {
+  order: -999; }
+
+.col-sm-last {
+  order: 999; }
+
+@media screen and (min-width: 500px) {
+  .col-md,
+  [class^='col-md-'],
+  [class^='col-md-offset-'],
+  .row[class*='cols-md-'] > * {
+    box-sizing: border-box;
+    flex: 0 0 auto;
+    padding: 0 calc(var(--universal-padding) / 2); }
+
+  .col-md,
+  .row.cols-md > * {
+    max-width: 100%;
+    flex-grow: 1;
+    flex-basis: 0; }
+
+  .col-md-1,
+  .row.cols-md-1 > * {
+    max-width: 8.3333333333%;
+    flex-basis: 8.3333333333%; }
+
+  .col-md-offset-0 {
+    margin-left: 0; }
+
+  .col-md-2,
+  .row.cols-md-2 > * {
+    max-width: 16.6666666667%;
+    flex-basis: 16.6666666667%; }
+
+  .col-md-offset-1 {
+    margin-left: 8.3333333333%; }
+
+  .col-md-3,
+  .row.cols-md-3 > * {
+    max-width: 25%;
+    flex-basis: 25%; }
+
+  .col-md-offset-2 {
+    margin-left: 16.6666666667%; }
+
+  .col-md-4,
+  .row.cols-md-4 > * {
+    max-width: 33.3333333333%;
+    flex-basis: 33.3333333333%; }
+
+  .col-md-offset-3 {
+    margin-left: 25%; }
+
+  .col-md-5,
+  .row.cols-md-5 > * {
+    max-width: 41.6666666667%;
+    flex-basis: 41.6666666667%; }
+
+  .col-md-offset-4 {
+    margin-left: 33.3333333333%; }
+
+  .col-md-6,
+  .row.cols-md-6 > * {
+    max-width: 50%;
+    flex-basis: 50%; }
+
+  .col-md-offset-5 {
+    margin-left: 41.6666666667%; }
+
+  .col-md-7,
+  .row.cols-md-7 > * {
+    max-width: 58.3333333333%;
+    flex-basis: 58.3333333333%; }
+
+  .col-md-offset-6 {
+    margin-left: 50%; }
+
+  .col-md-8,
+  .row.cols-md-8 > * {
+    max-width: 66.6666666667%;
+    flex-basis: 66.6666666667%; }
+
+  .col-md-offset-7 {
+    margin-left: 58.3333333333%; }
+
+  .col-md-9,
+  .row.cols-md-9 > * {
+    max-width: 75%;
+    flex-basis: 75%; }
+
+  .col-md-offset-8 {
+    margin-left: 66.6666666667%; }
+
+  .col-md-10,
+  .row.cols-md-10 > * {
+    max-width: 83.3333333333%;
+    flex-basis: 83.3333333333%; }
+
+  .col-md-offset-9 {
+    margin-left: 75%; }
+
+  .col-md-11,
+  .row.cols-md-11 > * {
+    max-width: 91.6666666667%;
+    flex-basis: 91.6666666667%; }
+
+  .col-md-offset-10 {
+    margin-left: 83.3333333333%; }
+
+  .col-md-12,
+  .row.cols-md-12 > * {
+    max-width: 100%;
+    flex-basis: 100%; }
+
+  .col-md-offset-11 {
+    margin-left: 91.6666666667%; }
+
+  .col-md-normal {
+    order: initial; }
+
+  .col-md-first {
+    order: -999; }
+
+  .col-md-last {
+    order: 999; } }
+@media screen and (min-width: 1280px) {
+  .col-lg,
+  [class^='col-lg-'],
+  [class^='col-lg-offset-'],
+  .row[class*='cols-lg-'] > * {
+    box-sizing: border-box;
+    flex: 0 0 auto;
+    padding: 0 calc(var(--universal-padding) / 2); }
+
+  .col-lg,
+  .row.cols-lg > * {
+    max-width: 100%;
+    flex-grow: 1;
+    flex-basis: 0; }
+
+  .col-lg-1,
+  .row.cols-lg-1 > * {
+    max-width: 8.3333333333%;
+    flex-basis: 8.3333333333%; }
+
+  .col-lg-offset-0 {
+    margin-left: 0; }
+
+  .col-lg-2,
+  .row.cols-lg-2 > * {
+    max-width: 16.6666666667%;
+    flex-basis: 16.6666666667%; }
+
+  .col-lg-offset-1 {
+    margin-left: 8.3333333333%; }
+
+  .col-lg-3,
+  .row.cols-lg-3 > * {
+    max-width: 25%;
+    flex-basis: 25%; }
+
+  .col-lg-offset-2 {
+    margin-left: 16.6666666667%; }
+
+  .col-lg-4,
+  .row.cols-lg-4 > * {
+    max-width: 33.3333333333%;
+    flex-basis: 33.3333333333%; }
+
+  .col-lg-offset-3 {
+    margin-left: 25%; }
+
+  .col-lg-5,
+  .row.cols-lg-5 > * {
+    max-width: 41.6666666667%;
+    flex-basis: 41.6666666667%; }
+
+  .col-lg-offset-4 {
+    margin-left: 33.3333333333%; }
+
+  .col-lg-6,
+  .row.cols-lg-6 > * {
+    max-width: 50%;
+    flex-basis: 50%; }
+
+  .col-lg-offset-5 {
+    margin-left: 41.6666666667%; }
+
+  .col-lg-7,
+  .row.cols-lg-7 > * {
+    max-width: 58.3333333333%;
+    flex-basis: 58.3333333333%; }
+
+  .col-lg-offset-6 {
+    margin-left: 50%; }
+
+  .col-lg-8,
+  .row.cols-lg-8 > * {
+    max-width: 66.6666666667%;
+    flex-basis: 66.6666666667%; }
+
+  .col-lg-offset-7 {
+    margin-left: 58.3333333333%; }
+
+  .col-lg-9,
+  .row.cols-lg-9 > * {
+    max-width: 75%;
+    flex-basis: 75%; }
+
+  .col-lg-offset-8 {
+    margin-left: 66.6666666667%; }
+
+  .col-lg-10,
+  .row.cols-lg-10 > * {
+    max-width: 83.3333333333%;
+    flex-basis: 83.3333333333%; }
+
+  .col-lg-offset-9 {
+    margin-left: 75%; }
+
+  .col-lg-11,
+  .row.cols-lg-11 > * {
+    max-width: 91.6666666667%;
+    flex-basis: 91.6666666667%; }
+
+  .col-lg-offset-10 {
+    margin-left: 83.3333333333%; }
+
+  .col-lg-12,
+  .row.cols-lg-12 > * {
+    max-width: 100%;
+    flex-basis: 100%; }
+
+  .col-lg-offset-11 {
+    margin-left: 91.6666666667%; }
+
+  .col-lg-normal {
+    order: initial; }
+
+  .col-lg-first {
+    order: -999; }
+
+  .col-lg-last {
+    order: 999; } }
+/* Card component CSS variable definitions */
+:root {
+  --card-back-color: #3cb4e6;
+  --card-fore-color: #03234b;
+  --card-border-color: #03234b; }
+
+.card {
+  display: flex;
+  flex-direction: column;
+  justify-content: space-between;
+  align-self: center;
+  position: relative;
+  width: 100%;
+  background: var(--card-back-color);
+  color: var(--card-fore-color);
+  border: 0.0714285714rem solid var(--card-border-color);
+  border-radius: var(--universal-border-radius);
+  margin: var(--universal-margin);
+  overflow: hidden; }
+  @media screen and (min-width: 320px) {
+    .card {
+      max-width: 320px; } }
+  .card > .sectione {
+    background: var(--card-back-color);
+    color: var(--card-fore-color);
+    box-sizing: border-box;
+    margin: 0;
+    border: 0;
+    border-radius: 0;
+    border-bottom: 0.0714285714rem solid var(--card-border-color);
+    padding: var(--universal-padding);
+    width: 100%; }
+    .card > .sectione.media {
+      height: 200px;
+      padding: 0;
+      -o-object-fit: cover;
+      object-fit: cover; }
+  .card > .sectione:last-child {
+    border-bottom: 0; }
+
+/*
+  Custom elements for card elements.
+*/
+@media screen and (min-width: 240px) {
+  .card.small {
+    max-width: 240px; } }
+@media screen and (min-width: 480px) {
+  .card.large {
+    max-width: 480px; } }
+.card.fluid {
+  max-width: 100%;
+  width: auto; }
+
+.card.warning {
+  --card-back-color: #e5b8b7;
+  --card-fore-color: #3b234b;
+  --card-border-color: #8c0078; }
+
+.card.error {
+  --card-back-color: #464650;
+  --card-fore-color: #ffffff;
+  --card-border-color: #8c0078; }
+
+.card > .sectione.dark {
+  --card-back-color: #3b234b;
+  --card-fore-color: #ffffff; }
+
+.card > .sectione.double-padded {
+  padding: calc(1.5 * var(--universal-padding)); }
+
+/*
+  Definitions for forms and input elements.
+*/
+/* Input_control module CSS variable definitions */
+:root {
+  --form-back-color: #ffe97f;
+  --form-fore-color: #03234b;
+  --form-border-color: #3cb4e6;
+  --input-back-color: #ffffff;
+  --input-fore-color: #03234b;
+  --input-border-color: #3cb4e6;
+  --input-focus-color: #0288d1;
+  --input-invalid-color: #d32f2f;
+  --button-back-color: #e2e2e2;
+  --button-hover-back-color: #dcdcdc;
+  --button-fore-color: #212121;
+  --button-border-color: transparent;
+  --button-hover-border-color: transparent;
+  --button-group-border-color: rgba(124, 124, 124, 0.54); }
+
+form {
+  background: var(--form-back-color);
+  color: var(--form-fore-color);
+  border: 0.0714285714rem solid var(--form-border-color);
+  border-radius: var(--universal-border-radius);
+  margin: var(--universal-margin);
+  padding: calc(2 * var(--universal-padding)) var(--universal-padding); }
+
+fieldset {
+  border: 0.0714285714rem solid var(--form-border-color);
+  border-radius: var(--universal-border-radius);
+  margin: calc(var(--universal-margin) / 4);
+  padding: var(--universal-padding); }
+
+legend {
+  box-sizing: border-box;
+  display: table;
+  max-width: 100%;
+  white-space: normal;
+  font-weight: 500;
+  padding: calc(var(--universal-padding) / 2); }
+
+label {
+  padding: calc(var(--universal-padding) / 2) var(--universal-padding); }
+
+.input-group {
+  display: inline-block; }
+  .input-group.fluid {
+    display: flex;
+    align-items: center;
+    justify-content: center; }
+    .input-group.fluid > input {
+      max-width: 100%;
+      flex-grow: 1;
+      flex-basis: 0px; }
+    @media screen and (max-width: 499px) {
+      .input-group.fluid {
+        align-items: stretch;
+        flex-direction: column; } }
+  .input-group.vertical {
+    display: flex;
+    align-items: stretch;
+    flex-direction: column; }
+    .input-group.vertical > input {
+      max-width: 100%;
+      flex-grow: 1;
+      flex-basis: 0px; }
+
+[type="number"]::-webkit-inner-spin-button, [type="number"]::-webkit-outer-spin-button {
+  height: auto; }
+
+[type="search"] {
+  -webkit-appearance: textfield;
+  outline-offset: -2px; }
+
+[type="search"]::-webkit-search-cancel-button,
+[type="search"]::-webkit-search-decoration {
+  -webkit-appearance: none; }
+
+input:not([type]), [type="text"], [type="email"], [type="number"], [type="search"],
+[type="password"], [type="url"], [type="tel"], [type="checkbox"], [type="radio"], textarea, select {
+  box-sizing: border-box;
+  background: var(--input-back-color);
+  color: var(--input-fore-color);
+  border: 0.0714285714rem solid var(--input-border-color);
+  border-radius: var(--universal-border-radius);
+  margin: calc(var(--universal-margin) / 2);
+  padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); }
+
+input:not([type="button"]):not([type="submit"]):not([type="reset"]):hover, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus, textarea:hover, textarea:focus, select:hover, select:focus {
+  border-color: var(--input-focus-color);
+  box-shadow: none; }
+input:not([type="button"]):not([type="submit"]):not([type="reset"]):invalid, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus:invalid, textarea:invalid, textarea:focus:invalid, select:invalid, select:focus:invalid {
+  border-color: var(--input-invalid-color);
+  box-shadow: none; }
+input:not([type="button"]):not([type="submit"]):not([type="reset"])[readonly], textarea[readonly], select[readonly] {
+  background: var(--secondary-back-color); }
+
+select {
+  max-width: 100%; }
+
+option {
+  overflow: hidden;
+  text-overflow: ellipsis; }
+
+[type="checkbox"], [type="radio"] {
+  -webkit-appearance: none;
+  -moz-appearance: none;
+  appearance: none;
+  position: relative;
+  height: calc(1rem + var(--universal-padding) / 2);
+  width: calc(1rem + var(--universal-padding) / 2);
+  vertical-align: text-bottom;
+  padding: 0;
+  flex-basis: calc(1rem + var(--universal-padding) / 2) !important;
+  flex-grow: 0 !important; }
+  [type="checkbox"]:checked:before, [type="radio"]:checked:before {
+    position: absolute; }
+
+[type="checkbox"]:checked:before {
+  content: '\2713';
+  font-family: sans-serif;
+  font-size: calc(1rem + var(--universal-padding) / 2);
+  top: calc(0rem - var(--universal-padding));
+  left: calc(var(--universal-padding) / 4); }
+
+[type="radio"] {
+  border-radius: 100%; }
+  [type="radio"]:checked:before {
+    border-radius: 100%;
+    content: '';
+    top: calc(0.0714285714rem + var(--universal-padding) / 2);
+    left: calc(0.0714285714rem + var(--universal-padding) / 2);
+    background: var(--input-fore-color);
+    width: 0.5rem;
+    height: 0.5rem; }
+
+:placeholder-shown {
+  color: var(--input-fore-color); }
+
+::-ms-placeholder {
+  color: var(--input-fore-color);
+  opacity: 0.54; }
+
+button::-moz-focus-inner, [type="button"]::-moz-focus-inner, [type="reset"]::-moz-focus-inner, [type="submit"]::-moz-focus-inner {
+  border-style: none;
+  padding: 0; }
+
+button, html [type="button"], [type="reset"], [type="submit"] {
+  -webkit-appearance: button; }
+
+button {
+  overflow: visible;
+  text-transform: none; }
+
+button, [type="button"], [type="submit"], [type="reset"],
+a.button, label.button, .button,
+a[role="button"], label[role="button"], [role="button"] {
+  display: inline-block;
+  background: var(--button-back-color);
+  color: var(--button-fore-color);
+  border: 0.0714285714rem solid var(--button-border-color);
+  border-radius: var(--universal-border-radius);
+  padding: var(--universal-padding) calc(1.5 * var(--universal-padding));
+  margin: var(--universal-margin);
+  text-decoration: none;
+  cursor: pointer;
+  transition: background 0.3s; }
+  button:hover, button:focus, [type="button"]:hover, [type="button"]:focus, [type="submit"]:hover, [type="submit"]:focus, [type="reset"]:hover, [type="reset"]:focus,
+  a.button:hover,
+  a.button:focus, label.button:hover, label.button:focus, .button:hover, .button:focus,
+  a[role="button"]:hover,
+  a[role="button"]:focus, label[role="button"]:hover, label[role="button"]:focus, [role="button"]:hover, [role="button"]:focus {
+    background: var(--button-hover-back-color);
+    border-color: var(--button-hover-border-color); }
+
+input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:disabled, select[disabled], button:disabled, button[disabled], .button:disabled, .button[disabled], [role="button"]:disabled, [role="button"][disabled] {
+  cursor: not-allowed;
+  opacity: 0.75; }
+
+.button-group {
+  display: flex;
+  border: 0.0714285714rem solid var(--button-group-border-color);
+  border-radius: var(--universal-border-radius);
+  margin: var(--universal-margin); }
+  .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] {
+    margin: 0;
+    max-width: 100%;
+    flex: 1 1 auto;
+    text-align: center;
+    border: 0;
+    border-radius: 0;
+    box-shadow: none; }
+  .button-group > :not(:first-child) {
+    border-left: 0.0714285714rem solid var(--button-group-border-color); }
+  @media screen and (max-width: 499px) {
+    .button-group {
+      flex-direction: column; }
+      .button-group > :not(:first-child) {
+        border: 0;
+        border-top: 0.0714285714rem solid var(--button-group-border-color); } }
+
+/*
+  Custom elements for forms and input elements.
+*/
+button.primary, [type="button"].primary, [type="submit"].primary, [type="reset"].primary, .button.primary, [role="button"].primary {
+  --button-back-color: #1976d2;
+  --button-fore-color: #f8f8f8; }
+  button.primary:hover, button.primary:focus, [type="button"].primary:hover, [type="button"].primary:focus, [type="submit"].primary:hover, [type="submit"].primary:focus, [type="reset"].primary:hover, [type="reset"].primary:focus, .button.primary:hover, .button.primary:focus, [role="button"].primary:hover, [role="button"].primary:focus {
+    --button-hover-back-color: #1565c0; }
+
+button.secondary, [type="button"].secondary, [type="submit"].secondary, [type="reset"].secondary, .button.secondary, [role="button"].secondary {
+  --button-back-color: #d32f2f;
+  --button-fore-color: #f8f8f8; }
+  button.secondary:hover, button.secondary:focus, [type="button"].secondary:hover, [type="button"].secondary:focus, [type="submit"].secondary:hover, [type="submit"].secondary:focus, [type="reset"].secondary:hover, [type="reset"].secondary:focus, .button.secondary:hover, .button.secondary:focus, [role="button"].secondary:hover, [role="button"].secondary:focus {
+    --button-hover-back-color: #c62828; }
+
+button.tertiary, [type="button"].tertiary, [type="submit"].tertiary, [type="reset"].tertiary, .button.tertiary, [role="button"].tertiary {
+  --button-back-color: #308732;
+  --button-fore-color: #f8f8f8; }
+  button.tertiary:hover, button.tertiary:focus, [type="button"].tertiary:hover, [type="button"].tertiary:focus, [type="submit"].tertiary:hover, [type="submit"].tertiary:focus, [type="reset"].tertiary:hover, [type="reset"].tertiary:focus, .button.tertiary:hover, .button.tertiary:focus, [role="button"].tertiary:hover, [role="button"].tertiary:focus {
+    --button-hover-back-color: #277529; }
+
+button.inverse, [type="button"].inverse, [type="submit"].inverse, [type="reset"].inverse, .button.inverse, [role="button"].inverse {
+  --button-back-color: #212121;
+  --button-fore-color: #f8f8f8; }
+  button.inverse:hover, button.inverse:focus, [type="button"].inverse:hover, [type="button"].inverse:focus, [type="submit"].inverse:hover, [type="submit"].inverse:focus, [type="reset"].inverse:hover, [type="reset"].inverse:focus, .button.inverse:hover, .button.inverse:focus, [role="button"].inverse:hover, [role="button"].inverse:focus {
+    --button-hover-back-color: #111; }
+
+button.small, [type="button"].small, [type="submit"].small, [type="reset"].small, .button.small, [role="button"].small {
+  padding: calc(0.5 * var(--universal-padding)) calc(0.75 * var(--universal-padding));
+  margin: var(--universal-margin); }
+
+button.large, [type="button"].large, [type="submit"].large, [type="reset"].large, .button.large, [role="button"].large {
+  padding: calc(1.5 * var(--universal-padding)) calc(2 * var(--universal-padding));
+  margin: var(--universal-margin); }
+
+/*
+  Definitions for navigation elements.
+*/
+/* Navigation module CSS variable definitions */
+:root {
+  --header-back-color: #03234b;
+  --header-hover-back-color: #ffd200;
+  --header-fore-color: #ffffff;
+  --header-border-color: #3cb4e6;
+  --nav-back-color: #ffffff;
+  --nav-hover-back-color: #ffe97f;
+  --nav-fore-color: #e6007e;
+  --nav-border-color: #3cb4e6;
+  --nav-link-color: #3cb4e6;
+  --footer-fore-color: #ffffff;
+  --footer-back-color: #03234b;
+  --footer-border-color: #3cb4e6;
+  --footer-link-color: #3cb4e6;
+  --drawer-back-color: #ffffff;
+  --drawer-hover-back-color: #ffe97f;
+  --drawer-border-color: #3cb4e6;
+  --drawer-close-color: #e6007e; }
+
+header {
+  height: 2.75rem;
+  background: var(--header-back-color);
+  color: var(--header-fore-color);
+  border-bottom: 0.0714285714rem solid var(--header-border-color);
+  padding: calc(var(--universal-padding) / 4) 0;
+  white-space: nowrap;
+  overflow-x: auto;
+  overflow-y: hidden; }
+  header.row {
+    box-sizing: content-box; }
+  header .logo {
+    color: var(--header-fore-color);
+    font-size: 1.75rem;
+    padding: var(--universal-padding) calc(2 * var(--universal-padding));
+    text-decoration: none; }
+  header button, header [type="button"], header .button, header [role="button"] {
+    box-sizing: border-box;
+    position: relative;
+    top: calc(0rem - var(--universal-padding) / 4);
+    height: calc(3.1875rem + var(--universal-padding) / 2);
+    background: var(--header-back-color);
+    line-height: calc(3.1875rem - var(--universal-padding) * 1.5);
+    text-align: center;
+    color: var(--header-fore-color);
+    border: 0;
+    border-radius: 0;
+    margin: 0;
+    text-transform: uppercase; }
+    header button:hover, header button:focus, header [type="button"]:hover, header [type="button"]:focus, header .button:hover, header .button:focus, header [role="button"]:hover, header [role="button"]:focus {
+      background: var(--header-hover-back-color); }
+
+nav {
+  background: var(--nav-back-color);
+  color: var(--nav-fore-color);
+  border: 0.0714285714rem solid var(--nav-border-color);
+  border-radius: var(--universal-border-radius);
+  margin: var(--universal-margin); }
+  nav * {
+    padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); }
+  nav a, nav a:visited {
+    display: block;
+    color: var(--nav-link-color);
+    border-radius: var(--universal-border-radius);
+    transition: background 0.3s; }
+    nav a:hover, nav a:focus, nav a:visited:hover, nav a:visited:focus {
+      text-decoration: none;
+      background: var(--nav-hover-back-color); }
+  nav .sublink-1 {
+    position: relative;
+    margin-left: calc(2 * var(--universal-padding)); }
+    nav .sublink-1:before {
+      position: absolute;
+      left: calc(var(--universal-padding) - 1 * var(--universal-padding));
+      top: -0.0714285714rem;
+      content: '';
+      height: 100%;
+      border: 0.0714285714rem solid var(--nav-border-color);
+      border-left: 0; }
+  nav .sublink-2 {
+    position: relative;
+    margin-left: calc(4 * var(--universal-padding)); }
+    nav .sublink-2:before {
+      position: absolute;
+      left: calc(var(--universal-padding) - 3 * var(--universal-padding));
+      top: -0.0714285714rem;
+      content: '';
+      height: 100%;
+      border: 0.0714285714rem solid var(--nav-border-color);
+      border-left: 0; }
+
+footer {
+  background: var(--footer-back-color);
+  color: var(--footer-fore-color);
+  border-top: 0.0714285714rem solid var(--footer-border-color);
+  padding: calc(2 * var(--universal-padding)) var(--universal-padding);
+  font-size: 0.875rem; }
+  footer a, footer a:visited {
+    color: var(--footer-link-color); }
+
+header.sticky {
+  position: -webkit-sticky;
+  position: sticky;
+  z-index: 1101;
+  top: 0; }
+
+footer.sticky {
+  position: -webkit-sticky;
+  position: sticky;
+  z-index: 1101;
+  bottom: 0; }
+
+.drawer-toggle:before {
+  display: inline-block;
+  position: relative;
+  vertical-align: bottom;
+  content: '\00a0\2261\00a0';
+  font-family: sans-serif;
+  font-size: 1.5em; }
+@media screen and (min-width: 500px) {
+  .drawer-toggle:not(.persistent) {
+    display: none; } }
+
+[type="checkbox"].drawer {
+  height: 1px;
+  width: 1px;
+  margin: -1px;
+  overflow: hidden;
+  position: absolute;
+  clip: rect(0 0 0 0);
+  -webkit-clip-path: inset(100%);
+  clip-path: inset(100%); }
+  [type="checkbox"].drawer + * {
+    display: block;
+    box-sizing: border-box;
+    position: fixed;
+    top: 0;
+    width: 320px;
+    height: 100vh;
+    overflow-y: auto;
+    background: var(--drawer-back-color);
+    border: 0.0714285714rem solid var(--drawer-border-color);
+    border-radius: 0;
+    margin: 0;
+    z-index: 1110;
+    right: -320px;
+    transition: right 0.3s; }
+    [type="checkbox"].drawer + * .drawer-close {
+      position: absolute;
+      top: var(--universal-margin);
+      right: var(--universal-margin);
+      z-index: 1111;
+      width: 2rem;
+      height: 2rem;
+      border-radius: var(--universal-border-radius);
+      padding: var(--universal-padding);
+      margin: 0;
+      cursor: pointer;
+      transition: background 0.3s; }
+      [type="checkbox"].drawer + * .drawer-close:before {
+        display: block;
+        content: '\00D7';
+        color: var(--drawer-close-color);
+        position: relative;
+        font-family: sans-serif;
+        font-size: 2rem;
+        line-height: 1;
+        text-align: center; }
+      [type="checkbox"].drawer + * .drawer-close:hover, [type="checkbox"].drawer + * .drawer-close:focus {
+        background: var(--drawer-hover-back-color); }
+    @media screen and (max-width: 320px) {
+      [type="checkbox"].drawer + * {
+        width: 100%; } }
+  [type="checkbox"].drawer:checked + * {
+    right: 0; }
+  @media screen and (min-width: 500px) {
+    [type="checkbox"].drawer:not(.persistent) + * {
+      position: static;
+      height: 100%;
+      z-index: 1100; }
+      [type="checkbox"].drawer:not(.persistent) + * .drawer-close {
+        display: none; } }
+
+/*
+  Definitions for the responsive table component.
+*/
+/* Table module CSS variable definitions. */
+:root {
+  --table-border-color: #03234b;
+  --table-border-separator-color: #03234b;
+  --table-head-back-color: #03234b;
+  --table-head-fore-color: #ffffff;
+  --table-body-back-color: #ffffff;
+  --table-body-fore-color: #03234b;
+  --table-body-alt-back-color: #f4f4f4; }
+
+table {
+  border-collapse: separate;
+  border-spacing: 0;
+  margin: 0;
+  display: flex;
+  flex: 0 1 auto;
+  flex-flow: row wrap;
+  padding: var(--universal-padding);
+  padding-top: 0; }
+  table caption {
+    font-size: 1rem;
+    margin: calc(2 * var(--universal-margin)) 0;
+    max-width: 100%;
+    flex: 0 0 100%; }
+  table thead, table tbody {
+    display: flex;
+    flex-flow: row wrap;
+    border: 0.0714285714rem solid var(--table-border-color); }
+  table thead {
+    z-index: 999;
+    border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0;
+    border-bottom: 0.0714285714rem solid var(--table-border-separator-color); }
+  table tbody {
+    border-top: 0;
+    margin-top: calc(0 - var(--universal-margin));
+    border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
+  table tr {
+    display: flex;
+    padding: 0; }
+  table th, table td {
+    padding: calc(0.5 * var(--universal-padding));
+		font-size: 0.9rem; }
+  table th {
+    text-align: left;
+    background: var(--table-head-back-color);
+    color: var(--table-head-fore-color); }
+  table td {
+    background: var(--table-body-back-color);
+    color: var(--table-body-fore-color);
+    border-top: 0.0714285714rem solid var(--table-border-color); }
+
+table:not(.horizontal) {
+  overflow: auto;
+  max-height: 100%; }
+  table:not(.horizontal) thead, table:not(.horizontal) tbody {
+    max-width: 100%;
+    flex: 0 0 100%; }
+  table:not(.horizontal) tr {
+    flex-flow: row wrap;
+    flex: 0 0 100%; }
+  table:not(.horizontal) th, table:not(.horizontal) td {
+    flex: 1 0 0%;
+    overflow: hidden;
+    text-overflow: ellipsis; }
+  table:not(.horizontal) thead {
+    position: sticky;
+    top: 0; }
+  table:not(.horizontal) tbody tr:first-child td {
+    border-top: 0; }
+
+table.horizontal {
+  border: 0; }
+  table.horizontal thead, table.horizontal tbody {
+    border: 0;
+    flex: .2 0 0;
+    flex-flow: row nowrap; }
+  table.horizontal tbody {
+    overflow: auto;
+    justify-content: space-between;
+    flex: .8 0 0;
+    margin-left: 0;
+    padding-bottom: calc(var(--universal-padding) / 4); }
+  table.horizontal tr {
+    flex-direction: column;
+    flex: 1 0 auto; }
+  table.horizontal th, table.horizontal td {
+    width: auto;
+    border: 0;
+    border-bottom: 0.0714285714rem solid var(--table-border-color); }
+    table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) {
+      border-top: 0; }
+  table.horizontal th {
+    text-align: right;
+    border-left: 0.0714285714rem solid var(--table-border-color);
+    border-right: 0.0714285714rem solid var(--table-border-separator-color); }
+  table.horizontal thead tr:first-child {
+    padding-left: 0; }
+  table.horizontal th:first-child, table.horizontal td:first-child {
+    border-top: 0.0714285714rem solid var(--table-border-color); }
+  table.horizontal tbody tr:last-child td {
+    border-right: 0.0714285714rem solid var(--table-border-color); }
+    table.horizontal tbody tr:last-child td:first-child {
+      border-top-right-radius: 0.25rem; }
+    table.horizontal tbody tr:last-child td:last-child {
+      border-bottom-right-radius: 0.25rem; }
+  table.horizontal thead tr:first-child th:first-child {
+    border-top-left-radius: 0.25rem; }
+  table.horizontal thead tr:first-child th:last-child {
+    border-bottom-left-radius: 0.25rem; }
+
+@media screen and (max-width: 499px) {
+  table, table.horizontal {
+    border-collapse: collapse;
+    border: 0;
+    width: 100%;
+    display: table; }
+    table thead, table th, table.horizontal thead, table.horizontal th {
+      border: 0;
+      height: 1px;
+      width: 1px;
+      margin: -1px;
+      overflow: hidden;
+      padding: 0;
+      position: absolute;
+      clip: rect(0 0 0 0);
+      -webkit-clip-path: inset(100%);
+      clip-path: inset(100%); }
+    table tbody, table.horizontal tbody {
+      border: 0;
+      display: table-row-group; }
+    table tr, table.horizontal tr {
+      display: block;
+      border: 0.0714285714rem solid var(--table-border-color);
+      border-radius: var(--universal-border-radius);
+      background: #ffffff;
+      padding: var(--universal-padding);
+      margin: var(--universal-margin);
+      margin-bottom: calc(1 * var(--universal-margin)); }
+    table th, table td, table.horizontal th, table.horizontal td {
+      width: auto; }
+    table td, table.horizontal td {
+      display: block;
+      border: 0;
+      text-align: right; }
+    table td:before, table.horizontal td:before {
+      content: attr(data-label);
+      float: left;
+      font-weight: 600; }
+    table th:first-child, table td:first-child, table.horizontal th:first-child, table.horizontal td:first-child {
+      border-top: 0; }
+    table tbody tr:last-child td, table.horizontal tbody tr:last-child td {
+      border-right: 0; } }
+table tr:nth-of-type(2n) > td {
+  background: var(--table-body-alt-back-color); }
+
+@media screen and (max-width: 500px) {
+  table tr:nth-of-type(2n) {
+    background: var(--table-body-alt-back-color); } }
+:root {
+  --table-body-hover-back-color: #90caf9; }
+
+table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td {
+  background: var(--table-body-hover-back-color); }
+
+@media screen and (max-width: 500px) {
+  table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td {
+    background: var(--table-body-hover-back-color); } }
+/*
+  Definitions for contextual background elements, toasts and tooltips.
+*/
+/* Contextual module CSS variable definitions */
+:root {
+  --mark-back-color: #3cb4e6;
+  --mark-fore-color: #ffffff; }
+
+mark {
+  background: var(--mark-back-color);
+  color: var(--mark-fore-color);
+  font-size: 0.95em;
+  line-height: 1em;
+  border-radius: var(--universal-border-radius);
+  padding: calc(var(--universal-padding) / 4) var(--universal-padding); }
+  mark.inline-block {
+    display: inline-block;
+    font-size: 1em;
+    line-height: 1.4;
+    padding: calc(var(--universal-padding) / 2) var(--universal-padding); }
+
+:root {
+  --toast-back-color: #424242;
+  --toast-fore-color: #fafafa; }
+
+.toast {
+  position: fixed;
+  bottom: calc(var(--universal-margin) * 3);
+  left: 50%;
+  transform: translate(-50%, -50%);
+  z-index: 1111;
+  color: var(--toast-fore-color);
+  background: var(--toast-back-color);
+  border-radius: calc(var(--universal-border-radius) * 16);
+  padding: var(--universal-padding) calc(var(--universal-padding) * 3); }
+
+:root {
+  --tooltip-back-color: #212121;
+  --tooltip-fore-color: #fafafa; }
+
+.tooltip {
+  position: relative;
+  display: inline-block; }
+  .tooltip:before, .tooltip:after {
+    position: absolute;
+    opacity: 0;
+    clip: rect(0 0 0 0);
+    -webkit-clip-path: inset(100%);
+    clip-path: inset(100%);
+    transition: all 0.3s;
+    z-index: 1010;
+    left: 50%; }
+  .tooltip:not(.bottom):before, .tooltip:not(.bottom):after {
+    bottom: 75%; }
+  .tooltip.bottom:before, .tooltip.bottom:after {
+    top: 75%; }
+  .tooltip:hover:before, .tooltip:hover:after, .tooltip:focus:before, .tooltip:focus:after {
+    opacity: 1;
+    clip: auto;
+    -webkit-clip-path: inset(0%);
+    clip-path: inset(0%); }
+  .tooltip:before {
+    content: '';
+    background: transparent;
+    border: var(--universal-margin) solid transparent;
+    left: calc(50% - var(--universal-margin)); }
+  .tooltip:not(.bottom):before {
+    border-top-color: #212121; }
+  .tooltip.bottom:before {
+    border-bottom-color: #212121; }
+  .tooltip:after {
+    content: attr(aria-label);
+    color: var(--tooltip-fore-color);
+    background: var(--tooltip-back-color);
+    border-radius: var(--universal-border-radius);
+    padding: var(--universal-padding);
+    white-space: nowrap;
+    transform: translateX(-50%); }
+  .tooltip:not(.bottom):after {
+    margin-bottom: calc(2 * var(--universal-margin)); }
+  .tooltip.bottom:after {
+    margin-top: calc(2 * var(--universal-margin)); }
+
+:root {
+  --modal-overlay-color: rgba(0, 0, 0, 0.45);
+  --modal-close-color: #e6007e;
+  --modal-close-hover-color: #ffe97f; }
+
+[type="checkbox"].modal {
+  height: 1px;
+  width: 1px;
+  margin: -1px;
+  overflow: hidden;
+  position: absolute;
+  clip: rect(0 0 0 0);
+  -webkit-clip-path: inset(100%);
+  clip-path: inset(100%); }
+  [type="checkbox"].modal + div {
+    position: fixed;
+    top: 0;
+    left: 0;
+    display: none;
+    width: 100vw;
+    height: 100vh;
+    background: var(--modal-overlay-color); }
+    [type="checkbox"].modal + div .card {
+      margin: 0 auto;
+      max-height: 50vh;
+      overflow: auto; }
+      [type="checkbox"].modal + div .card .modal-close {
+        position: absolute;
+        top: 0;
+        right: 0;
+        width: 1.75rem;
+        height: 1.75rem;
+        border-radius: var(--universal-border-radius);
+        padding: var(--universal-padding);
+        margin: 0;
+        cursor: pointer;
+        transition: background 0.3s; }
+        [type="checkbox"].modal + div .card .modal-close:before {
+          display: block;
+          content: '\00D7';
+          color: var(--modal-close-color);
+          position: relative;
+          font-family: sans-serif;
+          font-size: 1.75rem;
+          line-height: 1;
+          text-align: center; }
+        [type="checkbox"].modal + div .card .modal-close:hover, [type="checkbox"].modal + div .card .modal-close:focus {
+          background: var(--modal-close-hover-color); }
+  [type="checkbox"].modal:checked + div {
+    display: flex;
+    flex: 0 1 auto;
+    z-index: 1200; }
+    [type="checkbox"].modal:checked + div .card .modal-close {
+      z-index: 1211; }
+
+:root {
+  --collapse-label-back-color: #03234b;
+  --collapse-label-fore-color: #ffffff;
+  --collapse-label-hover-back-color: #3cb4e6;
+  --collapse-selected-label-back-color: #3cb4e6;
+  --collapse-border-color: var(--collapse-label-back-color);
+  --collapse-selected-border-color: #ceecf8;
+  --collapse-content-back-color: #ffffff;
+  --collapse-selected-label-border-color: #3cb4e6; }
+
+.collapse {
+  width: calc(100% - 2 * var(--universal-margin));
+  opacity: 1;
+  display: flex;
+  flex-direction: column;
+  margin: var(--universal-margin);
+  border-radius: var(--universal-border-radius); }
+  .collapse > [type="radio"], .collapse > [type="checkbox"] {
+    height: 1px;
+    width: 1px;
+    margin: -1px;
+    overflow: hidden;
+    position: absolute;
+    clip: rect(0 0 0 0);
+    -webkit-clip-path: inset(100%);
+    clip-path: inset(100%); }
+  .collapse > label {
+    flex-grow: 1;
+    display: inline-block;
+    height: 1.25rem;
+    cursor: pointer;
+    transition: background 0.2s;
+    color: var(--collapse-label-fore-color);
+    background: var(--collapse-label-back-color);
+    border: 0.0714285714rem solid var(--collapse-selected-border-color);
+    padding: calc(1.25 * var(--universal-padding)); }
+    .collapse > label:hover, .collapse > label:focus {
+      background: var(--collapse-label-hover-back-color); }
+    .collapse > label + div {
+      flex-basis: auto;
+      height: 1px;
+      width: 1px;
+      margin: -1px;
+      overflow: hidden;
+      position: absolute;
+      clip: rect(0 0 0 0);
+      -webkit-clip-path: inset(100%);
+      clip-path: inset(100%);
+      transition: max-height 0.3s;
+      max-height: 1px; }
+  .collapse > :checked + label {
+    background: var(--collapse-selected-label-back-color);
+    border-color: var(--collapse-selected-label-border-color); }
+    .collapse > :checked + label + div {
+      box-sizing: border-box;
+      position: relative;
+      width: 100%;
+      height: auto;
+      overflow: auto;
+      margin: 0;
+      background: var(--collapse-content-back-color);
+      border: 0.0714285714rem solid var(--collapse-selected-border-color);
+      border-top: 0;
+      padding: var(--universal-padding);
+      clip: auto;
+      -webkit-clip-path: inset(0%);
+      clip-path: inset(0%);
+      max-height: 100%; }
+  .collapse > label:not(:first-of-type) {
+    border-top: 0; }
+  .collapse > label:first-of-type {
+    border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; }
+  .collapse > label:last-of-type:not(:first-of-type) {
+    border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
+  .collapse > label:last-of-type:first-of-type {
+    border-radius: var(--universal-border-radius); }
+  .collapse > :checked:last-of-type:not(:first-of-type) + label {
+    border-radius: 0; }
+  .collapse > :checked:last-of-type + label + div {
+    border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
+
+/*
+  Custom elements for contextual background elements, toasts and tooltips.
+*/
+mark.tertiary {
+  --mark-back-color: #3cb4e6; }
+
+mark.tag {
+  padding: calc(var(--universal-padding)/2) var(--universal-padding);
+  border-radius: 1em; }
+
+/*
+  Definitions for progress elements and spinners.
+*/
+/* Progress module CSS variable definitions */
+:root {
+  --progress-back-color: #3cb4e6;
+  --progress-fore-color: #555; }
+
+progress {
+  display: block;
+  vertical-align: baseline;
+  -webkit-appearance: none;
+  -moz-appearance: none;
+  appearance: none;
+  height: 0.75rem;
+  width: calc(100% - 2 * var(--universal-margin));
+  margin: var(--universal-margin);
+  border: 0;
+  border-radius: calc(2 * var(--universal-border-radius));
+  background: var(--progress-back-color);
+  color: var(--progress-fore-color); }
+  progress::-webkit-progress-value {
+    background: var(--progress-fore-color);
+    border-top-left-radius: calc(2 * var(--universal-border-radius));
+    border-bottom-left-radius: calc(2 * var(--universal-border-radius)); }
+  progress::-webkit-progress-bar {
+    background: var(--progress-back-color); }
+  progress::-moz-progress-bar {
+    background: var(--progress-fore-color);
+    border-top-left-radius: calc(2 * var(--universal-border-radius));
+    border-bottom-left-radius: calc(2 * var(--universal-border-radius)); }
+  progress[value="1000"]::-webkit-progress-value {
+    border-radius: calc(2 * var(--universal-border-radius)); }
+  progress[value="1000"]::-moz-progress-bar {
+    border-radius: calc(2 * var(--universal-border-radius)); }
+  progress.inline {
+    display: inline-block;
+    vertical-align: middle;
+    width: 60%; }
+
+:root {
+  --spinner-back-color: #ddd;
+  --spinner-fore-color: #555; }
+
+@keyframes spinner-donut-anim {
+  0% {
+    transform: rotate(0deg); }
+  100% {
+    transform: rotate(360deg); } }
+.spinner {
+  display: inline-block;
+  margin: var(--universal-margin);
+  border: 0.25rem solid var(--spinner-back-color);
+  border-left: 0.25rem solid var(--spinner-fore-color);
+  border-radius: 50%;
+  width: 1.25rem;
+  height: 1.25rem;
+  animation: spinner-donut-anim 1.2s linear infinite; }
+
+/*
+  Custom elements for progress bars and spinners.
+*/
+progress.primary {
+  --progress-fore-color: #1976d2; }
+
+progress.secondary {
+  --progress-fore-color: #d32f2f; }
+
+progress.tertiary {
+  --progress-fore-color: #308732; }
+
+.spinner.primary {
+  --spinner-fore-color: #1976d2; }
+
+.spinner.secondary {
+  --spinner-fore-color: #d32f2f; }
+
+.spinner.tertiary {
+  --spinner-fore-color: #308732; }
+
+/*
+  Definitions for icons - powered by Feather (https://feathericons.com/).
+*/
+span[class^='icon-'] {
+  display: inline-block;
+  height: 1em;
+  width: 1em;
+  vertical-align: -0.125em;
+  background-size: contain;
+  margin: 0 calc(var(--universal-margin) / 4); }
+  span[class^='icon-'].secondary {
+    -webkit-filter: invert(25%);
+    filter: invert(25%); }
+  span[class^='icon-'].inverse {
+    -webkit-filter: invert(100%);
+    filter: invert(100%); }
+
+span.icon-alert {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-bookmark {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-calendar {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-credit {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-edit {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); }
+span.icon-link {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-help {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-home {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); }
+span.icon-info {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-lock {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-mail {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); }
+span.icon-location {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); }
+span.icon-phone {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-rss {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); }
+span.icon-search {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-settings {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-share {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-cart {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-upload {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-user {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); }
+
+/*
+  Definitions for STMicroelectronics icons (https://brandportal.st.com/document/26).
+*/
+span.icon-st-update {
+  background-image: url("Update.svg"); }
+span.icon-st-add {
+  background-image: url("Add button.svg"); }
+
+/*
+  Definitions for utilities and helper classes.
+*/
+/* Utility module CSS variable definitions */
+:root {
+  --generic-border-color: rgba(0, 0, 0, 0.3);
+  --generic-box-shadow: 0 0.2857142857rem 0.2857142857rem 0 rgba(0, 0, 0, 0.125), 0 0.1428571429rem 0.1428571429rem -0.1428571429rem rgba(0, 0, 0, 0.125); }
+
+.hidden {
+  display: none !important; }
+
+.visually-hidden {
+  position: absolute !important;
+  width: 1px !important;
+  height: 1px !important;
+  margin: -1px !important;
+  border: 0 !important;
+  padding: 0 !important;
+  clip: rect(0 0 0 0) !important;
+  -webkit-clip-path: inset(100%) !important;
+  clip-path: inset(100%) !important;
+  overflow: hidden !important; }
+
+.bordered {
+  border: 0.0714285714rem solid var(--generic-border-color) !important; }
+
+.rounded {
+  border-radius: var(--universal-border-radius) !important; }
+
+.circular {
+  border-radius: 50% !important; }
+
+.shadowed {
+  box-shadow: var(--generic-box-shadow) !important; }
+
+.responsive-margin {
+  margin: calc(var(--universal-margin) / 4) !important; }
+  @media screen and (min-width: 500px) {
+    .responsive-margin {
+      margin: calc(var(--universal-margin) / 2) !important; } }
+  @media screen and (min-width: 1280px) {
+    .responsive-margin {
+      margin: var(--universal-margin) !important; } }
+
+.responsive-padding {
+  padding: calc(var(--universal-padding) / 4) !important; }
+  @media screen and (min-width: 500px) {
+    .responsive-padding {
+      padding: calc(var(--universal-padding) / 2) !important; } }
+  @media screen and (min-width: 1280px) {
+    .responsive-padding {
+      padding: var(--universal-padding) !important; } }
+
+@media screen and (max-width: 499px) {
+  .hidden-sm {
+    display: none !important; } }
+@media screen and (min-width: 500px) and (max-width: 1279px) {
+  .hidden-md {
+    display: none !important; } }
+@media screen and (min-width: 1280px) {
+  .hidden-lg {
+    display: none !important; } }
+@media screen and (max-width: 499px) {
+  .visually-hidden-sm {
+    position: absolute !important;
+    width: 1px !important;
+    height: 1px !important;
+    margin: -1px !important;
+    border: 0 !important;
+    padding: 0 !important;
+    clip: rect(0 0 0 0) !important;
+    -webkit-clip-path: inset(100%) !important;
+    clip-path: inset(100%) !important;
+    overflow: hidden !important; } }
+@media screen and (min-width: 500px) and (max-width: 1279px) {
+  .visually-hidden-md {
+    position: absolute !important;
+    width: 1px !important;
+    height: 1px !important;
+    margin: -1px !important;
+    border: 0 !important;
+    padding: 0 !important;
+    clip: rect(0 0 0 0) !important;
+    -webkit-clip-path: inset(100%) !important;
+    clip-path: inset(100%) !important;
+    overflow: hidden !important; } }
+@media screen and (min-width: 1280px) {
+  .visually-hidden-lg {
+    position: absolute !important;
+    width: 1px !important;
+    height: 1px !important;
+    margin: -1px !important;
+    border: 0 !important;
+    padding: 0 !important;
+    clip: rect(0 0 0 0) !important;
+    -webkit-clip-path: inset(100%) !important;
+    clip-path: inset(100%) !important;
+    overflow: hidden !important; } }
+
+/*# sourceMappingURL=mini-custom.css.map */
+
+img[alt="ST logo"] { display: block; margin: auto; width: 75%; max-width: 250px; min-width: 71px; }
+img[alt="Cube logo"] { float: right; width: 30%; max-width: 10rem; min-width: 8rem; padding-right: 1rem;}
+
+.figure {
+  display: block;
+  margin-left: auto;
+  margin-right: auto;
+  text-align: center;
+}

airmouse/lib/lsm6dso-api/lsm6dso.c

@@ -0,0 +1,3909 @@
+/**
+  ******************************************************************************
+  * @file    lsm6dso.c
+  * @author  MEMS Software Solutions Team
+  * @brief   LSM6DSO driver file
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "lsm6dso.h"
+
+/** @addtogroup BSP BSP
+  * @{
+  */
+
+/** @addtogroup Component Component
+  * @{
+  */
+
+/** @defgroup LSM6DSO LSM6DSO
+  * @{
+  */
+
+/** @defgroup LSM6DSO_Exported_Variables LSM6DSO Exported Variables
+  * @{
+  */
+
+LSM6DSO_CommonDrv_t LSM6DSO_COMMON_Driver =
+{
+  LSM6DSO_Init,
+  LSM6DSO_DeInit,
+  LSM6DSO_ReadID,
+  LSM6DSO_GetCapabilities,
+};
+
+LSM6DSO_ACC_Drv_t LSM6DSO_ACC_Driver =
+{
+  LSM6DSO_ACC_Enable,
+  LSM6DSO_ACC_Disable,
+  LSM6DSO_ACC_GetSensitivity,
+  LSM6DSO_ACC_GetOutputDataRate,
+  LSM6DSO_ACC_SetOutputDataRate,
+  LSM6DSO_ACC_GetFullScale,
+  LSM6DSO_ACC_SetFullScale,
+  LSM6DSO_ACC_GetAxes,
+  LSM6DSO_ACC_GetAxesRaw,
+};
+
+LSM6DSO_GYRO_Drv_t LSM6DSO_GYRO_Driver =
+{
+  LSM6DSO_GYRO_Enable,
+  LSM6DSO_GYRO_Disable,
+  LSM6DSO_GYRO_GetSensitivity,
+  LSM6DSO_GYRO_GetOutputDataRate,
+  LSM6DSO_GYRO_SetOutputDataRate,
+  LSM6DSO_GYRO_GetFullScale,
+  LSM6DSO_GYRO_SetFullScale,
+  LSM6DSO_GYRO_GetAxes,
+  LSM6DSO_GYRO_GetAxesRaw,
+};
+
+/**
+  * @}
+  */
+
+/** @defgroup LSM6DSO_Private_Function_Prototypes LSM6DSO Private Function Prototypes
+  * @{
+  */
+
+static int32_t LSM6DSO_ACC_SetOutputDataRate_When_Enabled(LSM6DSO_Object_t *pObj, float_t Odr);
+static int32_t LSM6DSO_ACC_SetOutputDataRate_When_Disabled(LSM6DSO_Object_t *pObj, float_t Odr);
+static int32_t LSM6DSO_GYRO_SetOutputDataRate_When_Enabled(LSM6DSO_Object_t *pObj, float_t Odr);
+static int32_t LSM6DSO_GYRO_SetOutputDataRate_When_Disabled(LSM6DSO_Object_t *pObj, float_t Odr);
+static void LSM6DSO_Delay(LSM6DSO_Object_t *pObj, uint32_t msDelay);
+static int32_t ReadRegWrap(void *Handle, uint8_t Reg, uint8_t *pData, uint16_t Length);
+static int32_t WriteRegWrap(void *Handle, uint8_t Reg, uint8_t *pData, uint16_t Length);
+
+/**
+  * @}
+  */
+
+/** @defgroup LSM6DSO_Exported_Functions LSM6DSO Exported Functions
+  * @{
+  */
+
+/**
+  * @brief  Register Component Bus IO operations
+  * @param  pObj the device pObj
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_RegisterBusIO(LSM6DSO_Object_t *pObj, LSM6DSO_IO_t *pIO)
+{
+  int32_t ret = LSM6DSO_OK;
+
+  if (pObj == NULL)
+  {
+    ret = LSM6DSO_ERROR;
+  }
+  else
+  {
+    pObj->IO.Init      = pIO->Init;
+    pObj->IO.DeInit    = pIO->DeInit;
+    pObj->IO.BusType   = pIO->BusType;
+    pObj->IO.Address   = pIO->Address;
+    pObj->IO.WriteReg  = pIO->WriteReg;
+    pObj->IO.ReadReg   = pIO->ReadReg;
+    pObj->IO.GetTick   = pIO->GetTick;
+
+    pObj->Ctx.read_reg  = ReadRegWrap;
+    pObj->Ctx.write_reg = WriteRegWrap;
+    pObj->Ctx.mdelay    = pIO->Delay;
+    pObj->Ctx.handle   = pObj;
+
+    if (pObj->IO.Init == NULL)
+    {
+      ret = LSM6DSO_ERROR;
+    }
+    else if (pObj->IO.Init() != LSM6DSO_OK)
+    {
+      ret = LSM6DSO_ERROR;
+    }
+    else
+    {
+      if (pObj->IO.BusType == LSM6DSO_SPI_3WIRES_BUS) /* SPI 3-Wires */
+      {
+        /* Enable the SPI 3-Wires support only the first time */
+        if (pObj->is_initialized == 0U)
+        {
+          /* Enable SPI 3-Wires on the component */
+          uint8_t data = 0x0C;
+
+          if (LSM6DSO_Write_Reg(pObj, LSM6DSO_CTRL3_C, data) != LSM6DSO_OK)
+          {
+            ret = LSM6DSO_ERROR;
+          }
+        }
+      }
+    }
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Initialize the LSM6DSO sensor
+  * @param  pObj the device pObj
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_Init(LSM6DSO_Object_t *pObj)
+{
+  /* Disable I3C */
+  if (lsm6dso_i3c_disable_set(&(pObj->Ctx), LSM6DSO_I3C_DISABLE) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Enable register address automatically incremented during a multiple byte
+  access with a serial interface. */
+  if (lsm6dso_auto_increment_set(&(pObj->Ctx), PROPERTY_ENABLE) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Enable BDU */
+  if (lsm6dso_block_data_update_set(&(pObj->Ctx), PROPERTY_ENABLE) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* FIFO mode selection */
+  if (lsm6dso_fifo_mode_set(&(pObj->Ctx), LSM6DSO_BYPASS_MODE) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Select default output data rate. */
+  pObj->acc_odr = LSM6DSO_XL_ODR_104Hz;
+
+  /* Output data rate selection - power down. */
+  if (lsm6dso_xl_data_rate_set(&(pObj->Ctx), LSM6DSO_XL_ODR_OFF) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Full scale selection. */
+  if (lsm6dso_xl_full_scale_set(&(pObj->Ctx), LSM6DSO_2g) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Select default output data rate. */
+  pObj->gyro_odr = LSM6DSO_GY_ODR_104Hz;
+
+  /* Output data rate selection - power down. */
+  if (lsm6dso_gy_data_rate_set(&(pObj->Ctx), LSM6DSO_GY_ODR_OFF) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Full scale selection. */
+  if (lsm6dso_gy_full_scale_set(&(pObj->Ctx), LSM6DSO_2000dps) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  pObj->is_initialized = 1;
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Deinitialize the LSM6DSO sensor
+  * @param  pObj the device pObj
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_DeInit(LSM6DSO_Object_t *pObj)
+{
+  /* Disable the component */
+  if (LSM6DSO_ACC_Disable(pObj) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  if (LSM6DSO_GYRO_Disable(pObj) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Reset output data rate. */
+  pObj->acc_odr = LSM6DSO_XL_ODR_OFF;
+  pObj->gyro_odr = LSM6DSO_GY_ODR_OFF;
+
+  pObj->is_initialized = 0;
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Read component ID
+  * @param  pObj the device pObj
+  * @param  Id the WHO_AM_I value
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ReadID(LSM6DSO_Object_t *pObj, uint8_t *Id)
+{
+  if (lsm6dso_device_id_get(&(pObj->Ctx), Id) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Get LSM6DSO sensor capabilities
+  * @param  pObj Component object pointer
+  * @param  Capabilities pointer to LSM6DSO sensor capabilities
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_GetCapabilities(LSM6DSO_Object_t *pObj, LSM6DSO_Capabilities_t *Capabilities)
+{
+  /* Prevent unused argument(s) compilation warning */
+  (void)(pObj);
+
+  Capabilities->Acc          = 1;
+  Capabilities->Gyro         = 1;
+  Capabilities->Magneto      = 0;
+  Capabilities->LowPower     = 0;
+  Capabilities->GyroMaxFS    = 2000;
+  Capabilities->AccMaxFS     = 16;
+  Capabilities->MagMaxFS     = 0;
+  Capabilities->GyroMaxOdr   = 6660.0f;
+  Capabilities->AccMaxOdr    = 6660.0f;
+  Capabilities->MagMaxOdr    = 0.0f;
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Enable the LSM6DSO accelerometer sensor
+  * @param  pObj the device pObj
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Enable(LSM6DSO_Object_t *pObj)
+{
+  /* Check if the component is already enabled */
+  if (pObj->acc_is_enabled == 1U)
+  {
+    return LSM6DSO_OK;
+  }
+
+  /* Output data rate selection. */
+  if (lsm6dso_xl_data_rate_set(&(pObj->Ctx), pObj->acc_odr) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  pObj->acc_is_enabled = 1;
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Disable the LSM6DSO accelerometer sensor
+  * @param  pObj the device pObj
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Disable(LSM6DSO_Object_t *pObj)
+{
+  /* Check if the component is already disabled */
+  if (pObj->acc_is_enabled == 0U)
+  {
+    return LSM6DSO_OK;
+  }
+
+  /* Get current output data rate. */
+  if (lsm6dso_xl_data_rate_get(&(pObj->Ctx), &pObj->acc_odr) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Output data rate selection - power down. */
+  if (lsm6dso_xl_data_rate_set(&(pObj->Ctx), LSM6DSO_XL_ODR_OFF) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  pObj->acc_is_enabled = 0;
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Get the LSM6DSO accelerometer sensor sensitivity
+  * @param  pObj the device pObj
+  * @param  Sensitivity pointer
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_GetSensitivity(LSM6DSO_Object_t *pObj, float_t *Sensitivity)
+{
+  int32_t ret = LSM6DSO_OK;
+  lsm6dso_fs_xl_t full_scale;
+
+  /* Read actual full scale selection from sensor. */
+  if (lsm6dso_xl_full_scale_get(&(pObj->Ctx), &full_scale) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Store the Sensitivity based on actual full scale. */
+  switch (full_scale)
+  {
+    case LSM6DSO_2g:
+      *Sensitivity = LSM6DSO_ACC_SENSITIVITY_FS_2G;
+      break;
+
+    case LSM6DSO_4g:
+      *Sensitivity = LSM6DSO_ACC_SENSITIVITY_FS_4G;
+      break;
+
+    case LSM6DSO_8g:
+      *Sensitivity = LSM6DSO_ACC_SENSITIVITY_FS_8G;
+      break;
+
+    case LSM6DSO_16g:
+      *Sensitivity = LSM6DSO_ACC_SENSITIVITY_FS_16G;
+      break;
+
+    default:
+      ret = LSM6DSO_ERROR;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Get the LSM6DSO accelerometer sensor output data rate
+  * @param  pObj the device pObj
+  * @param  Odr pointer where the output data rate is written
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_GetOutputDataRate(LSM6DSO_Object_t *pObj, float_t *Odr)
+{
+  int32_t ret = LSM6DSO_OK;
+  lsm6dso_odr_xl_t odr_low_level;
+
+  /* Get current output data rate. */
+  if (lsm6dso_xl_data_rate_get(&(pObj->Ctx), &odr_low_level) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  switch (odr_low_level)
+  {
+    case LSM6DSO_XL_ODR_OFF:
+      *Odr = 0.0f;
+      break;
+
+    case LSM6DSO_XL_ODR_1Hz6:
+      *Odr = 1.6f;
+      break;
+
+    case LSM6DSO_XL_ODR_12Hz5:
+      *Odr = 12.5f;
+      break;
+
+    case LSM6DSO_XL_ODR_26Hz:
+      *Odr = 26.0f;
+      break;
+
+    case LSM6DSO_XL_ODR_52Hz:
+      *Odr = 52.0f;
+      break;
+
+    case LSM6DSO_XL_ODR_104Hz:
+      *Odr = 104.0f;
+      break;
+
+    case LSM6DSO_XL_ODR_208Hz:
+      *Odr = 208.0f;
+      break;
+
+    case LSM6DSO_XL_ODR_417Hz:
+      *Odr = 417.0f;
+      break;
+
+    case LSM6DSO_XL_ODR_833Hz:
+      *Odr = 833.0f;
+      break;
+
+    case LSM6DSO_XL_ODR_1667Hz:
+      *Odr = 1667.0f;
+      break;
+
+    case LSM6DSO_XL_ODR_3333Hz:
+      *Odr = 3333.0f;
+      break;
+
+    case LSM6DSO_XL_ODR_6667Hz:
+      *Odr = 6667.0f;
+      break;
+
+    default:
+      ret = LSM6DSO_ERROR;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Set the LSM6DSO accelerometer sensor output data rate
+  * @param  pObj the device pObj
+  * @param  Odr the output data rate value to be set
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_SetOutputDataRate(LSM6DSO_Object_t *pObj, float_t Odr)
+{
+  return LSM6DSO_ACC_SetOutputDataRate_With_Mode(pObj, Odr, LSM6DSO_ACC_HIGH_PERFORMANCE_MODE);
+}
+
+/**
+  * @brief  Set the LSM6DSO accelerometer sensor output data rate with operating mode
+  * @param  pObj the device pObj
+  * @param  Odr the output data rate value to be set
+  * @param  Mode the accelerometer operating mode
+  * @note   This function switches off the gyroscope if Ultra Low Power Mode is set
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_SetOutputDataRate_With_Mode(LSM6DSO_Object_t *pObj, float_t Odr, LSM6DSO_ACC_Operating_Mode_t Mode)
+{
+  int32_t ret = LSM6DSO_OK;
+  float_t newOdr = Odr;
+
+  switch (Mode)
+  {
+    case LSM6DSO_ACC_HIGH_PERFORMANCE_MODE:
+    {
+      /* We must uncheck Low Power and Ultra Low Power bits if they are enabled */
+      lsm6dso_ctrl5_c_t val1;
+      lsm6dso_ctrl6_c_t val2;
+
+      if (lsm6dso_read_reg(&(pObj->Ctx), LSM6DSO_CTRL5_C, (uint8_t *)&val1, 1) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+
+      if (val1.xl_ulp_en != 0U)
+      {
+        /* Power off the accelerometer */
+        if (pObj->acc_is_enabled == 1U)
+        {
+          if (lsm6dso_xl_data_rate_set(&(pObj->Ctx), LSM6DSO_XL_ODR_OFF) != LSM6DSO_OK)
+          {
+            return LSM6DSO_ERROR;
+          }
+        }
+
+        val1.xl_ulp_en = 0;
+        if (lsm6dso_write_reg(&(pObj->Ctx), LSM6DSO_CTRL5_C, (uint8_t *)&val1, 1) != LSM6DSO_OK)
+        {
+          return LSM6DSO_ERROR;
+        }
+      }
+
+      if (lsm6dso_read_reg(&(pObj->Ctx), LSM6DSO_CTRL6_C, (uint8_t *)&val2, 1) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+
+      if (val2.xl_hm_mode != 0U)
+      {
+        val2.xl_hm_mode = 0U;
+        if (lsm6dso_write_reg(&(pObj->Ctx), LSM6DSO_CTRL6_C, (uint8_t *)&val2, 1) != LSM6DSO_OK)
+        {
+          return LSM6DSO_ERROR;
+        }
+      }
+
+      /* ODR should be at least 12.5Hz */
+      if (newOdr < 12.5f)
+      {
+        newOdr = 12.5f;
+      }
+      break;
+    }
+    case LSM6DSO_ACC_LOW_POWER_NORMAL_MODE:
+    {
+      /* We must uncheck Ultra Low Power bit if it is enabled */
+      /* and check the Low Power bit if it is unchecked       */
+      lsm6dso_ctrl5_c_t val1;
+      lsm6dso_ctrl6_c_t val2;
+
+      if (lsm6dso_read_reg(&(pObj->Ctx), LSM6DSO_CTRL5_C, (uint8_t *)&val1, 1) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+
+      if (val1.xl_ulp_en != 0U)
+      {
+        /* Power off the accelerometer */
+        if (pObj->acc_is_enabled == 1U)
+        {
+          if (lsm6dso_xl_data_rate_set(&(pObj->Ctx), LSM6DSO_XL_ODR_OFF) != LSM6DSO_OK)
+          {
+            return LSM6DSO_ERROR;
+          }
+        }
+
+        val1.xl_ulp_en = 0;
+        if (lsm6dso_write_reg(&(pObj->Ctx), LSM6DSO_CTRL5_C, (uint8_t *)&val1, 1) != LSM6DSO_OK)
+        {
+          return LSM6DSO_ERROR;
+        }
+      }
+
+      if (lsm6dso_read_reg(&(pObj->Ctx), LSM6DSO_CTRL6_C, (uint8_t *)&val2, 1) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+
+      if (val2.xl_hm_mode == 0U)
+      {
+        val2.xl_hm_mode = 1U;
+        if (lsm6dso_write_reg(&(pObj->Ctx), LSM6DSO_CTRL6_C, (uint8_t *)&val2, 1) != LSM6DSO_OK)
+        {
+          return LSM6DSO_ERROR;
+        }
+      }
+
+      /* Now we need to limit the ODR to 208 Hz if it is higher */
+      if (newOdr > 208.0f)
+      {
+        newOdr = 208.0f;
+      }
+      break;
+    }
+    case LSM6DSO_ACC_ULTRA_LOW_POWER_MODE:
+    {
+      /* We must uncheck Low Power bit if it is enabled                   */
+      /* and check the Ultra Low Power bit if it is unchecked             */
+      /* We must switch off gyro otherwise Ultra Low Power does not work  */
+      lsm6dso_ctrl5_c_t val1;
+      lsm6dso_ctrl6_c_t val2;
+
+      if (lsm6dso_read_reg(&(pObj->Ctx), LSM6DSO_CTRL6_C, (uint8_t *)&val2, 1) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+
+      if (val2.xl_hm_mode != 0U)
+      {
+        val2.xl_hm_mode = 0U;
+        if (lsm6dso_write_reg(&(pObj->Ctx), LSM6DSO_CTRL6_C, (uint8_t *)&val2, 1) != LSM6DSO_OK)
+        {
+          return LSM6DSO_ERROR;
+        }
+      }
+
+      /* Disable Gyro */
+      if (pObj->gyro_is_enabled == 1U)
+      {
+        if (LSM6DSO_GYRO_Disable(pObj) != LSM6DSO_OK)
+        {
+          return LSM6DSO_ERROR;
+        }
+      }
+
+      if (lsm6dso_read_reg(&(pObj->Ctx), LSM6DSO_CTRL5_C, (uint8_t *)&val1, 1) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+
+      if (val1.xl_ulp_en == 0U)
+      {
+        /* Power off the accelerometer */
+        if (pObj->acc_is_enabled == 1U)
+        {
+          if (lsm6dso_xl_data_rate_set(&(pObj->Ctx), LSM6DSO_XL_ODR_OFF) != LSM6DSO_OK)
+          {
+            return LSM6DSO_ERROR;
+          }
+        }
+
+        val1.xl_ulp_en = 1U;
+        if (lsm6dso_write_reg(&(pObj->Ctx), LSM6DSO_CTRL5_C, (uint8_t *)&val1, 1) != LSM6DSO_OK)
+        {
+          return LSM6DSO_ERROR;
+        }
+      }
+
+      /* Now we need to limit the ODR to 208 Hz if it is higher */
+      if (newOdr > 208.0f)
+      {
+        newOdr = 208.0f;
+      }
+      break;
+    }
+    default:
+      ret = LSM6DSO_ERROR;
+      break;
+  }
+
+  if (ret == LSM6DSO_ERROR)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  if (pObj->acc_is_enabled == 1U)
+  {
+    ret = LSM6DSO_ACC_SetOutputDataRate_When_Enabled(pObj, newOdr);
+  }
+  else
+  {
+    ret = LSM6DSO_ACC_SetOutputDataRate_When_Disabled(pObj, newOdr);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Get the LSM6DSO accelerometer sensor full scale
+  * @param  pObj the device pObj
+  * @param  FullScale pointer where the full scale is written
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_GetFullScale(LSM6DSO_Object_t *pObj, int32_t *FullScale)
+{
+  int32_t ret = LSM6DSO_OK;
+  lsm6dso_fs_xl_t fs_low_level;
+
+  /* Read actual full scale selection from sensor. */
+  if (lsm6dso_xl_full_scale_get(&(pObj->Ctx), &fs_low_level) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  switch (fs_low_level)
+  {
+    case LSM6DSO_2g:
+      *FullScale =  2;
+      break;
+
+    case LSM6DSO_4g:
+      *FullScale =  4;
+      break;
+
+    case LSM6DSO_8g:
+      *FullScale =  8;
+      break;
+
+    case LSM6DSO_16g:
+      *FullScale = 16;
+      break;
+
+    default:
+      ret = LSM6DSO_ERROR;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Set the LSM6DSO accelerometer sensor full scale
+  * @param  pObj the device pObj
+  * @param  FullScale the functional full scale to be set
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_SetFullScale(LSM6DSO_Object_t *pObj, int32_t FullScale)
+{
+  lsm6dso_fs_xl_t new_fs;
+
+  /* Seems like MISRA C-2012 rule 14.3a violation but only from single file statical analysis point of view because
+     the parameter passed to the function is not known at the moment of analysis */
+  new_fs = (FullScale <= 2) ? LSM6DSO_2g
+           : (FullScale <= 4) ? LSM6DSO_4g
+           : (FullScale <= 8) ? LSM6DSO_8g
+           :                    LSM6DSO_16g;
+
+  if (lsm6dso_xl_full_scale_set(&(pObj->Ctx), new_fs) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Get the LSM6DSO accelerometer sensor raw axes
+  * @param  pObj the device pObj
+  * @param  Value pointer where the raw values of the axes are written
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_GetAxesRaw(LSM6DSO_Object_t *pObj, LSM6DSO_AxesRaw_t *Value)
+{
+  lsm6dso_axis3bit16_t data_raw;
+
+  /* Read raw data values. */
+  if (lsm6dso_acceleration_raw_get(&(pObj->Ctx), data_raw.i16bit) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Format the data. */
+  Value->x = data_raw.i16bit[0];
+  Value->y = data_raw.i16bit[1];
+  Value->z = data_raw.i16bit[2];
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Get the LSM6DSO accelerometer sensor axes
+  * @param  pObj the device pObj
+  * @param  Acceleration pointer where the values of the axes are written
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_GetAxes(LSM6DSO_Object_t *pObj, LSM6DSO_Axes_t *Acceleration)
+{
+  lsm6dso_axis3bit16_t data_raw;
+  float_t sensitivity = 0.0f;
+
+  /* Read raw data values. */
+  if (lsm6dso_acceleration_raw_get(&(pObj->Ctx), data_raw.i16bit) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Get LSM6DSO actual sensitivity. */
+  if (LSM6DSO_ACC_GetSensitivity(pObj, &sensitivity) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Calculate the data. */
+  Acceleration->x = (int32_t)((float_t)((float_t)data_raw.i16bit[0] * sensitivity));
+  Acceleration->y = (int32_t)((float_t)((float_t)data_raw.i16bit[1] * sensitivity));
+  Acceleration->z = (int32_t)((float_t)((float_t)data_raw.i16bit[2] * sensitivity));
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Enable the LSM6DSO gyroscope sensor
+  * @param  pObj the device pObj
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_GYRO_Enable(LSM6DSO_Object_t *pObj)
+{
+  /* Check if the component is already enabled */
+  if (pObj->gyro_is_enabled == 1U)
+  {
+    return LSM6DSO_OK;
+  }
+
+  /* Output data rate selection. */
+  if (lsm6dso_gy_data_rate_set(&(pObj->Ctx), pObj->gyro_odr) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  pObj->gyro_is_enabled = 1;
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Disable the LSM6DSO gyroscope sensor
+  * @param  pObj the device pObj
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_GYRO_Disable(LSM6DSO_Object_t *pObj)
+{
+  /* Check if the component is already disabled */
+  if (pObj->gyro_is_enabled == 0U)
+  {
+    return LSM6DSO_OK;
+  }
+
+  /* Get current output data rate. */
+  if (lsm6dso_gy_data_rate_get(&(pObj->Ctx), &pObj->gyro_odr) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Output data rate selection - power down. */
+  if (lsm6dso_gy_data_rate_set(&(pObj->Ctx), LSM6DSO_GY_ODR_OFF) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  pObj->gyro_is_enabled = 0;
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Get the LSM6DSO gyroscope sensor sensitivity
+  * @param  pObj the device pObj
+  * @param  Sensitivity pointer
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_GYRO_GetSensitivity(LSM6DSO_Object_t *pObj, float_t *Sensitivity)
+{
+  int32_t ret = LSM6DSO_OK;
+  lsm6dso_fs_g_t full_scale;
+
+  /* Read actual full scale selection from sensor. */
+  if (lsm6dso_gy_full_scale_get(&(pObj->Ctx), &full_scale) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Store the sensitivity based on actual full scale. */
+  switch (full_scale)
+  {
+    case LSM6DSO_125dps:
+      *Sensitivity = LSM6DSO_GYRO_SENSITIVITY_FS_125DPS;
+      break;
+
+    case LSM6DSO_250dps:
+      *Sensitivity = LSM6DSO_GYRO_SENSITIVITY_FS_250DPS;
+      break;
+
+    case LSM6DSO_500dps:
+      *Sensitivity = LSM6DSO_GYRO_SENSITIVITY_FS_500DPS;
+      break;
+
+    case LSM6DSO_1000dps:
+      *Sensitivity = LSM6DSO_GYRO_SENSITIVITY_FS_1000DPS;
+      break;
+
+    case LSM6DSO_2000dps:
+      *Sensitivity = LSM6DSO_GYRO_SENSITIVITY_FS_2000DPS;
+      break;
+
+    default:
+      ret = LSM6DSO_ERROR;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Get the LSM6DSO gyroscope sensor output data rate
+  * @param  pObj the device pObj
+  * @param  Odr pointer where the output data rate is written
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_GYRO_GetOutputDataRate(LSM6DSO_Object_t *pObj, float_t *Odr)
+{
+  int32_t ret = LSM6DSO_OK;
+  lsm6dso_odr_g_t odr_low_level;
+
+  /* Get current output data rate. */
+  if (lsm6dso_gy_data_rate_get(&(pObj->Ctx), &odr_low_level) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  switch (odr_low_level)
+  {
+    case LSM6DSO_GY_ODR_OFF:
+      *Odr = 0.0f;
+      break;
+
+    case LSM6DSO_GY_ODR_12Hz5:
+      *Odr = 12.5f;
+      break;
+
+    case LSM6DSO_GY_ODR_26Hz:
+      *Odr = 26.0f;
+      break;
+
+    case LSM6DSO_GY_ODR_52Hz:
+      *Odr = 52.0f;
+      break;
+
+    case LSM6DSO_GY_ODR_104Hz:
+      *Odr = 104.0f;
+      break;
+
+    case LSM6DSO_GY_ODR_208Hz:
+      *Odr = 208.0f;
+      break;
+
+    case LSM6DSO_GY_ODR_417Hz:
+      *Odr = 417.0f;
+      break;
+
+    case LSM6DSO_GY_ODR_833Hz:
+      *Odr = 833.0f;
+      break;
+
+    case LSM6DSO_GY_ODR_1667Hz:
+      *Odr = 1667.0f;
+      break;
+
+    case LSM6DSO_GY_ODR_3333Hz:
+      *Odr = 3333.0f;
+      break;
+
+    case LSM6DSO_GY_ODR_6667Hz:
+      *Odr = 6667.0f;
+      break;
+
+    default:
+      ret = LSM6DSO_ERROR;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Set the LSM6DSO gyroscope sensor output data rate
+  * @param  pObj the device pObj
+  * @param  Odr the output data rate value to be set
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_GYRO_SetOutputDataRate(LSM6DSO_Object_t *pObj, float_t Odr)
+{
+  return LSM6DSO_GYRO_SetOutputDataRate_With_Mode(pObj, Odr, LSM6DSO_GYRO_HIGH_PERFORMANCE_MODE);
+}
+
+/**
+  * @brief  Set the LSM6DSO gyroscope sensor output data rate with operating mode
+  * @param  pObj the device pObj
+  * @param  Odr the output data rate value to be set
+  * @param  Mode the gyroscope operating mode
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_GYRO_SetOutputDataRate_With_Mode(LSM6DSO_Object_t *pObj, float_t Odr,
+                                                 LSM6DSO_GYRO_Operating_Mode_t Mode)
+{
+  int32_t ret = LSM6DSO_OK;
+  float_t newOdr = Odr;
+
+  switch (Mode)
+  {
+    case LSM6DSO_GYRO_HIGH_PERFORMANCE_MODE:
+    {
+      /* We must uncheck Low Power bit if it is enabled */
+      lsm6dso_ctrl7_g_t val1;
+
+      if (lsm6dso_read_reg(&(pObj->Ctx), LSM6DSO_CTRL7_G, (uint8_t *)&val1, 1) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+
+      if (val1.g_hm_mode != 0U)
+      {
+        val1.g_hm_mode = 0U;
+        if (lsm6dso_write_reg(&(pObj->Ctx), LSM6DSO_CTRL7_G, (uint8_t *)&val1, 1) != LSM6DSO_OK)
+        {
+          return LSM6DSO_ERROR;
+        }
+      }
+      break;
+    }
+    case LSM6DSO_GYRO_LOW_POWER_NORMAL_MODE:
+    {
+      /* We must check the Low Power bit if it is unchecked */
+      lsm6dso_ctrl7_g_t val1;
+
+      if (lsm6dso_read_reg(&(pObj->Ctx), LSM6DSO_CTRL7_G, (uint8_t *)&val1, 1) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+
+      if (val1.g_hm_mode == 0U)
+      {
+        val1.g_hm_mode = 1U;
+        if (lsm6dso_write_reg(&(pObj->Ctx), LSM6DSO_CTRL7_G, (uint8_t *)&val1, 1) != LSM6DSO_OK)
+        {
+          return LSM6DSO_ERROR;
+        }
+      }
+
+      /* Now we need to limit the ODR to 208 Hz if it is higher */
+      if (newOdr > 208.0f)
+      {
+        newOdr = 208.0f;
+      }
+      break;
+    }
+    default:
+      ret = LSM6DSO_ERROR;
+      break;
+  }
+
+  if (ret == LSM6DSO_ERROR)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  if (pObj->gyro_is_enabled == 1U)
+  {
+    ret = LSM6DSO_GYRO_SetOutputDataRate_When_Enabled(pObj, newOdr);
+  }
+  else
+  {
+    ret = LSM6DSO_GYRO_SetOutputDataRate_When_Disabled(pObj, newOdr);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Get the LSM6DSO gyroscope sensor full scale
+  * @param  pObj the device pObj
+  * @param  FullScale pointer where the full scale is written
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_GYRO_GetFullScale(LSM6DSO_Object_t *pObj, int32_t  *FullScale)
+{
+  int32_t ret = LSM6DSO_OK;
+  lsm6dso_fs_g_t fs_low_level;
+
+  /* Read actual full scale selection from sensor. */
+  if (lsm6dso_gy_full_scale_get(&(pObj->Ctx), &fs_low_level) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  switch (fs_low_level)
+  {
+    case LSM6DSO_125dps:
+      *FullScale =  125;
+      break;
+
+    case LSM6DSO_250dps:
+      *FullScale =  250;
+      break;
+
+    case LSM6DSO_500dps:
+      *FullScale =  500;
+      break;
+
+    case LSM6DSO_1000dps:
+      *FullScale = 1000;
+      break;
+
+    case LSM6DSO_2000dps:
+      *FullScale = 2000;
+      break;
+
+    default:
+      ret = LSM6DSO_ERROR;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Set the LSM6DSO gyroscope sensor full scale
+  * @param  pObj the device pObj
+  * @param  FullScale the functional full scale to be set
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_GYRO_SetFullScale(LSM6DSO_Object_t *pObj, int32_t FullScale)
+{
+  lsm6dso_fs_g_t new_fs;
+
+  new_fs = (FullScale <= 125)  ? LSM6DSO_125dps
+           : (FullScale <= 250)  ? LSM6DSO_250dps
+           : (FullScale <= 500)  ? LSM6DSO_500dps
+           : (FullScale <= 1000) ? LSM6DSO_1000dps
+           :                       LSM6DSO_2000dps;
+
+  if (lsm6dso_gy_full_scale_set(&(pObj->Ctx), new_fs) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Get the LSM6DSO gyroscope sensor raw axes
+  * @param  pObj the device pObj
+  * @param  Value pointer where the raw values of the axes are written
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_GYRO_GetAxesRaw(LSM6DSO_Object_t *pObj, LSM6DSO_AxesRaw_t *Value)
+{
+  lsm6dso_axis3bit16_t data_raw;
+
+  /* Read raw data values. */
+  if (lsm6dso_angular_rate_raw_get(&(pObj->Ctx), data_raw.i16bit) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Format the data. */
+  Value->x = data_raw.i16bit[0];
+  Value->y = data_raw.i16bit[1];
+  Value->z = data_raw.i16bit[2];
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Get the LSM6DSO gyroscope sensor axes
+  * @param  pObj the device pObj
+  * @param  AngularRate pointer where the values of the axes are written
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_GYRO_GetAxes(LSM6DSO_Object_t *pObj, LSM6DSO_Axes_t *AngularRate)
+{
+  lsm6dso_axis3bit16_t data_raw;
+  float_t sensitivity;
+
+  /* Read raw data values. */
+  if (lsm6dso_angular_rate_raw_get(&(pObj->Ctx), data_raw.i16bit) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Get LSM6DSO actual sensitivity. */
+  if (LSM6DSO_GYRO_GetSensitivity(pObj, &sensitivity) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Calculate the data. */
+  AngularRate->x = (int32_t)((float_t)((float_t)data_raw.i16bit[0] * sensitivity));
+  AngularRate->y = (int32_t)((float_t)((float_t)data_raw.i16bit[1] * sensitivity));
+  AngularRate->z = (int32_t)((float_t)((float_t)data_raw.i16bit[2] * sensitivity));
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Get the LSM6DSO register value
+  * @param  pObj the device pObj
+  * @param  Reg address to be read
+  * @param  Data pointer where the value is written
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_Read_Reg(LSM6DSO_Object_t *pObj, uint8_t Reg, uint8_t *Data)
+{
+  if (lsm6dso_read_reg(&(pObj->Ctx), Reg, Data, 1) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Set the LSM6DSO register value
+  * @param  pObj the device pObj
+  * @param  Reg address to be written
+  * @param  Data value to be written
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_Write_Reg(LSM6DSO_Object_t *pObj, uint8_t Reg, uint8_t Data)
+{
+  if (lsm6dso_write_reg(&(pObj->Ctx), Reg, &Data, 1) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Set the interrupt latch
+  * @param  pObj the device pObj
+  * @param  Status value to be written
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_Set_Interrupt_Latch(LSM6DSO_Object_t *pObj, uint8_t Status)
+{
+  int32_t ret = LSM6DSO_OK;
+  lsm6dso_lir_t newStatus = LSM6DSO_ALL_INT_PULSED;
+
+  switch (Status)
+  {
+    case 0:
+      newStatus = LSM6DSO_ALL_INT_PULSED;
+      break;
+    case 1:
+      newStatus = LSM6DSO_BASE_LATCHED_EMB_PULSED;
+      break;
+    case 2:
+      newStatus = LSM6DSO_BASE_PULSED_EMB_LATCHED;
+      break;
+    case 3:
+      newStatus = LSM6DSO_ALL_INT_LATCHED;
+      break;
+    default:
+      ret = LSM6DSO_ERROR;
+      break;
+  }
+
+  if (ret == LSM6DSO_ERROR)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  if (Status > 1U)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  if (lsm6dso_int_notification_set(&(pObj->Ctx), newStatus) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Enable free fall detection
+  * @param  pObj the device pObj
+  * @param  IntPin interrupt pin line to be used
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Enable_Free_Fall_Detection(LSM6DSO_Object_t *pObj, LSM6DSO_SensorIntPin_t IntPin)
+{
+  int32_t ret = LSM6DSO_OK;
+  lsm6dso_pin_int1_route_t val1;
+  lsm6dso_pin_int2_route_t val2;
+
+  /* Output Data Rate selection */
+  if (LSM6DSO_ACC_SetOutputDataRate(pObj, 417.0f) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Full scale selection */
+  if (LSM6DSO_ACC_SetFullScale(pObj, 2) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* FF_DUR setting */
+  if (lsm6dso_ff_dur_set(&(pObj->Ctx), 0x06) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* WAKE_DUR setting */
+  if (lsm6dso_wkup_dur_set(&(pObj->Ctx), 0x00) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* SLEEP_DUR setting */
+  if (lsm6dso_act_sleep_dur_set(&(pObj->Ctx), 0x00) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* FF_THS setting */
+  if (lsm6dso_ff_threshold_set(&(pObj->Ctx), LSM6DSO_FF_TSH_312mg) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Enable free fall event on either INT1 or INT2 pin */
+  switch (IntPin)
+  {
+    case LSM6DSO_INT1_PIN:
+      if (lsm6dso_pin_int1_route_get(&(pObj->Ctx), &val1) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+
+      val1.free_fall = PROPERTY_ENABLE;
+
+      if (lsm6dso_pin_int1_route_set(&(pObj->Ctx), val1) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+      break;
+
+    case LSM6DSO_INT2_PIN:
+      if (lsm6dso_pin_int2_route_get(&(pObj->Ctx), NULL, &val2) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+
+      val2.free_fall = PROPERTY_ENABLE;
+
+      if (lsm6dso_pin_int2_route_set(&(pObj->Ctx), NULL, val2) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+      break;
+
+    default:
+      ret = LSM6DSO_ERROR;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Disable free fall detection
+  * @param  pObj the device pObj
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Disable_Free_Fall_Detection(LSM6DSO_Object_t *pObj)
+{
+  lsm6dso_pin_int1_route_t val1;
+  lsm6dso_pin_int2_route_t val2;
+
+  /* Disable free fall event on both INT1 and INT2 pins */
+  if (lsm6dso_pin_int1_route_get(&(pObj->Ctx), &val1) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  val1.free_fall = PROPERTY_DISABLE;
+
+  if (lsm6dso_pin_int1_route_set(&(pObj->Ctx), val1) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  if (lsm6dso_pin_int2_route_get(&(pObj->Ctx), NULL, &val2) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  val2.free_fall = PROPERTY_DISABLE;
+
+  if (lsm6dso_pin_int2_route_set(&(pObj->Ctx), NULL, val2) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* FF_DUR setting */
+  if (lsm6dso_ff_dur_set(&(pObj->Ctx), 0x00) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* FF_THS setting */
+  if (lsm6dso_ff_threshold_set(&(pObj->Ctx), LSM6DSO_FF_TSH_156mg) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Set free fall threshold
+  * @param  pObj the device pObj
+  * @param  Threshold free fall detection threshold
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Set_Free_Fall_Threshold(LSM6DSO_Object_t *pObj, uint8_t Threshold)
+{
+  int32_t ret = LSM6DSO_OK;
+  lsm6dso_ff_ths_t newThreshold = LSM6DSO_FF_TSH_156mg;
+
+  switch (Threshold)
+  {
+    case 0:
+      newThreshold = LSM6DSO_FF_TSH_156mg;
+      break;
+    case 1:
+      newThreshold = LSM6DSO_FF_TSH_219mg;
+      break;
+    case 2:
+      newThreshold = LSM6DSO_FF_TSH_250mg;
+      break;
+    case 3:
+      newThreshold = LSM6DSO_FF_TSH_312mg;
+      break;
+    case 4:
+      newThreshold = LSM6DSO_FF_TSH_344mg;
+      break;
+    case 5:
+      newThreshold = LSM6DSO_FF_TSH_406mg;
+      break;
+    case 6:
+      newThreshold = LSM6DSO_FF_TSH_469mg;
+      break;
+    case 7:
+      newThreshold = LSM6DSO_FF_TSH_500mg;
+      break;
+    default:
+      ret = LSM6DSO_ERROR;
+      break;
+  }
+
+  if (ret == LSM6DSO_ERROR)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  if (lsm6dso_ff_threshold_set(&(pObj->Ctx), newThreshold) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Set free fall duration
+  * @param  pObj the device pObj
+  * @param  Duration free fall detection duration
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Set_Free_Fall_Duration(LSM6DSO_Object_t *pObj, uint8_t Duration)
+{
+  if (lsm6dso_ff_dur_set(&(pObj->Ctx), Duration) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Enable pedometer
+  * @param  pObj the device pObj
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Enable_Pedometer(LSM6DSO_Object_t *pObj)
+{
+  lsm6dso_pin_int1_route_t val;
+  lsm6dso_emb_sens_t emb_sens;
+
+  /* Output Data Rate selection */
+  if (LSM6DSO_ACC_SetOutputDataRate(pObj, 26.0f) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Full scale selection */
+  if (LSM6DSO_ACC_SetFullScale(pObj, 2) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Save current embedded features */
+  if (lsm6dso_embedded_sens_get(&(pObj->Ctx), &emb_sens) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Turn off embedded features */
+  if (lsm6dso_embedded_sens_off(&(pObj->Ctx)) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Wait for 10 ms */
+  LSM6DSO_Delay(pObj, 10);
+
+  /* Enable pedometer algorithm. */
+  emb_sens.step = PROPERTY_ENABLE;
+
+  if (lsm6dso_pedo_sens_set(&(pObj->Ctx), LSM6DSO_PEDO_BASE_MODE) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Turn on embedded features */
+  if (lsm6dso_embedded_sens_set(&(pObj->Ctx), &emb_sens) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Enable step detector on INT1 pin */
+  if (lsm6dso_pin_int1_route_get(&(pObj->Ctx), &val) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  val.step_detector = PROPERTY_ENABLE;
+
+  if (lsm6dso_pin_int1_route_set(&(pObj->Ctx), val) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Disable pedometer
+  * @param  pObj the device pObj
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Disable_Pedometer(LSM6DSO_Object_t *pObj)
+{
+  lsm6dso_pin_int1_route_t val1;
+  lsm6dso_emb_sens_t emb_sens;
+
+  /* Disable step detector on INT1 pin */
+  if (lsm6dso_pin_int1_route_get(&(pObj->Ctx), &val1) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  val1.step_detector = PROPERTY_DISABLE;
+
+  if (lsm6dso_pin_int1_route_set(&(pObj->Ctx), val1) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Save current embedded features */
+  if (lsm6dso_embedded_sens_get(&(pObj->Ctx), &emb_sens) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Disable pedometer algorithm. */
+  emb_sens.step = PROPERTY_DISABLE;
+
+  if (lsm6dso_embedded_sens_set(&(pObj->Ctx), &emb_sens) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Get step count
+  * @param  pObj the device pObj
+  * @param  StepCount step counter
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Get_Step_Count(LSM6DSO_Object_t *pObj, uint16_t *StepCount)
+{
+  if (lsm6dso_number_of_steps_get(&(pObj->Ctx), StepCount) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Enable step counter reset
+  * @param  pObj the device pObj
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Step_Counter_Reset(LSM6DSO_Object_t *pObj)
+{
+  if (lsm6dso_steps_reset(&(pObj->Ctx)) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Enable tilt detection
+  * @param  pObj the device pObj
+  * @param  IntPin interrupt pin line to be used
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Enable_Tilt_Detection(LSM6DSO_Object_t *pObj, LSM6DSO_SensorIntPin_t IntPin)
+{
+  int32_t ret = LSM6DSO_OK;
+  lsm6dso_pin_int1_route_t val1;
+  lsm6dso_pin_int2_route_t val2;
+  lsm6dso_emb_sens_t emb_sens;
+
+  /* Output Data Rate selection */
+  if (LSM6DSO_ACC_SetOutputDataRate(pObj, 26.0f) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Full scale selection */
+  if (LSM6DSO_ACC_SetFullScale(pObj, 2) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Save current embedded features */
+  if (lsm6dso_embedded_sens_get(&(pObj->Ctx), &emb_sens) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Turn off embedded features */
+  if (lsm6dso_embedded_sens_off(&(pObj->Ctx)) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Wait for 10 ms */
+  LSM6DSO_Delay(pObj, 10);
+
+  /* Enable tilt algorithm. */
+  emb_sens.tilt = PROPERTY_ENABLE;
+
+  /* Turn on embedded features */
+  if (lsm6dso_embedded_sens_set(&(pObj->Ctx), &emb_sens) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Enable tilt event on either INT1 or INT2 pin */
+  switch (IntPin)
+  {
+    case LSM6DSO_INT1_PIN:
+      if (lsm6dso_pin_int1_route_get(&(pObj->Ctx), &val1) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+
+      val1.tilt = PROPERTY_ENABLE;
+
+      if (lsm6dso_pin_int1_route_set(&(pObj->Ctx), val1) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+      break;
+
+    case LSM6DSO_INT2_PIN:
+      if (lsm6dso_pin_int2_route_get(&(pObj->Ctx), NULL, &val2) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+
+      val2.tilt = PROPERTY_ENABLE;
+
+      if (lsm6dso_pin_int2_route_set(&(pObj->Ctx), NULL, val2) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+      break;
+
+    default:
+      ret = LSM6DSO_ERROR;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Disable tilt detection
+  * @param  pObj the device pObj
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Disable_Tilt_Detection(LSM6DSO_Object_t *pObj)
+{
+  lsm6dso_pin_int1_route_t val1;
+  lsm6dso_pin_int2_route_t val2;
+  lsm6dso_emb_sens_t emb_sens;
+
+  /* Disable tilt event on both INT1 and INT2 pins */
+  if (lsm6dso_pin_int1_route_get(&(pObj->Ctx), &val1) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  val1.tilt = PROPERTY_DISABLE;
+
+  if (lsm6dso_pin_int1_route_set(&(pObj->Ctx), val1) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  if (lsm6dso_pin_int2_route_get(&(pObj->Ctx), NULL, &val2) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  val2.tilt = PROPERTY_DISABLE;
+
+  if (lsm6dso_pin_int2_route_set(&(pObj->Ctx), NULL, val2) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Save current embedded features */
+  if (lsm6dso_embedded_sens_get(&(pObj->Ctx), &emb_sens) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Disable tilt algorithm. */
+  emb_sens.tilt = PROPERTY_DISABLE;
+
+  if (lsm6dso_embedded_sens_set(&(pObj->Ctx), &emb_sens) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Enable wake up detection
+  * @param  pObj the device pObj
+  * @param  IntPin interrupt pin line to be used
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Enable_Wake_Up_Detection(LSM6DSO_Object_t *pObj, LSM6DSO_SensorIntPin_t IntPin)
+{
+  int32_t ret = LSM6DSO_OK;
+  lsm6dso_pin_int1_route_t val1;
+  lsm6dso_pin_int2_route_t val2;
+
+  /* Output Data Rate selection */
+  if (LSM6DSO_ACC_SetOutputDataRate(pObj, 417.0f) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Full scale selection */
+  if (LSM6DSO_ACC_SetFullScale(pObj, 2) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* WAKE_DUR setting */
+  if (lsm6dso_wkup_dur_set(&(pObj->Ctx), 0x00) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Set wake up threshold. */
+  if (lsm6dso_wkup_threshold_set(&(pObj->Ctx), 0x02) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Enable wake up event on either INT1 or INT2 pin */
+  switch (IntPin)
+  {
+    case LSM6DSO_INT1_PIN:
+      if (lsm6dso_pin_int1_route_get(&(pObj->Ctx), &val1) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+
+      val1.wake_up = PROPERTY_ENABLE;
+
+      if (lsm6dso_pin_int1_route_set(&(pObj->Ctx), val1) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+      break;
+
+    case LSM6DSO_INT2_PIN:
+      if (lsm6dso_pin_int2_route_get(&(pObj->Ctx), NULL, &val2) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+
+      val2.wake_up = PROPERTY_ENABLE;
+
+      if (lsm6dso_pin_int2_route_set(&(pObj->Ctx), NULL, val2) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+      break;
+
+    default:
+      ret = LSM6DSO_ERROR;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Disable wake up detection
+  * @param  pObj the device pObj
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Disable_Wake_Up_Detection(LSM6DSO_Object_t *pObj)
+{
+  lsm6dso_pin_int1_route_t val1;
+  lsm6dso_pin_int2_route_t val2;
+
+  /* Disable wake up event on both INT1 and INT2 pins */
+  if (lsm6dso_pin_int1_route_get(&(pObj->Ctx), &val1) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  val1.wake_up = PROPERTY_DISABLE;
+
+  if (lsm6dso_pin_int1_route_set(&(pObj->Ctx), val1) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  if (lsm6dso_pin_int2_route_get(&(pObj->Ctx), NULL, &val2) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  val2.wake_up = PROPERTY_DISABLE;
+
+  if (lsm6dso_pin_int2_route_set(&(pObj->Ctx), NULL, val2) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Reset wake up threshold. */
+  if (lsm6dso_wkup_threshold_set(&(pObj->Ctx), 0x00) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* WAKE_DUR setting */
+  if (lsm6dso_wkup_dur_set(&(pObj->Ctx), 0x00) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Set wake up threshold
+  * @param  pObj the device pObj
+  * @param  Threshold wake up detection threshold
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Set_Wake_Up_Threshold(LSM6DSO_Object_t *pObj, uint8_t Threshold)
+{
+  /* Set wake up threshold. */
+  if (lsm6dso_wkup_threshold_set(&(pObj->Ctx), Threshold) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Set wake up duration
+  * @param  pObj the device pObj
+  * @param  Duration wake up detection duration
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Set_Wake_Up_Duration(LSM6DSO_Object_t *pObj, uint8_t Duration)
+{
+  /* Set wake up duration. */
+  if (lsm6dso_wkup_dur_set(&(pObj->Ctx), Duration) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Enable single tap detection
+  * @param  pObj the device pObj
+  * @param  IntPin interrupt pin line to be used
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Enable_Single_Tap_Detection(LSM6DSO_Object_t *pObj, LSM6DSO_SensorIntPin_t IntPin)
+{
+  int32_t ret = LSM6DSO_OK;
+  lsm6dso_pin_int1_route_t val1;
+  lsm6dso_pin_int2_route_t val2;
+
+  /* Output Data Rate selection */
+  if (LSM6DSO_ACC_SetOutputDataRate(pObj, 417.0f) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Full scale selection */
+  if (LSM6DSO_ACC_SetFullScale(pObj, 2) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Enable X direction in tap recognition. */
+  if (lsm6dso_tap_detection_on_x_set(&(pObj->Ctx), PROPERTY_ENABLE) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Enable Y direction in tap recognition. */
+  if (lsm6dso_tap_detection_on_y_set(&(pObj->Ctx), PROPERTY_ENABLE) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Enable Z direction in tap recognition. */
+  if (lsm6dso_tap_detection_on_z_set(&(pObj->Ctx), PROPERTY_ENABLE) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Set tap threshold. */
+  if (lsm6dso_tap_threshold_x_set(&(pObj->Ctx), 0x08) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Set tap shock time window. */
+  if (lsm6dso_tap_shock_set(&(pObj->Ctx), 0x02) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Set tap quiet time window. */
+  if (lsm6dso_tap_quiet_set(&(pObj->Ctx), 0x01) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* _NOTE_: Tap duration time window - don't care for single tap. */
+
+  /* _NOTE_: Single/Double Tap event - don't care of this flag for single tap. */
+
+  /* Enable single tap event on either INT1 or INT2 pin */
+  switch (IntPin)
+  {
+    case LSM6DSO_INT1_PIN:
+      if (lsm6dso_pin_int1_route_get(&(pObj->Ctx), &val1) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+
+      val1.single_tap = PROPERTY_ENABLE;
+
+      if (lsm6dso_pin_int1_route_set(&(pObj->Ctx), val1) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+      break;
+
+    case LSM6DSO_INT2_PIN:
+      if (lsm6dso_pin_int2_route_get(&(pObj->Ctx), NULL, &val2) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+
+      val2.single_tap = PROPERTY_ENABLE;
+
+      if (lsm6dso_pin_int2_route_set(&(pObj->Ctx), NULL, val2) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+      break;
+
+    default:
+      ret = LSM6DSO_ERROR;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Disable single tap detection
+  * @param  pObj the device pObj
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Disable_Single_Tap_Detection(LSM6DSO_Object_t *pObj)
+{
+  lsm6dso_pin_int1_route_t val1;
+  lsm6dso_pin_int2_route_t val2;
+
+  /* Disable single tap event on both INT1 and INT2 pins */
+  if (lsm6dso_pin_int1_route_get(&(pObj->Ctx), &val1) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  val1.single_tap = PROPERTY_DISABLE;
+
+  if (lsm6dso_pin_int1_route_set(&(pObj->Ctx), val1) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  if (lsm6dso_pin_int2_route_get(&(pObj->Ctx), NULL, &val2) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  val2.single_tap = PROPERTY_DISABLE;
+
+  if (lsm6dso_pin_int2_route_set(&(pObj->Ctx), NULL, val2) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Reset tap quiet time window. */
+  if (lsm6dso_tap_quiet_set(&(pObj->Ctx), 0x00) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Reset tap shock time window. */
+  if (lsm6dso_tap_shock_set(&(pObj->Ctx), 0x00) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Reset tap threshold. */
+  if (lsm6dso_tap_threshold_x_set(&(pObj->Ctx), 0x00) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Disable Z direction in tap recognition. */
+  if (lsm6dso_tap_detection_on_z_set(&(pObj->Ctx), PROPERTY_DISABLE) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Disable Y direction in tap recognition. */
+  if (lsm6dso_tap_detection_on_y_set(&(pObj->Ctx), PROPERTY_DISABLE) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Disable X direction in tap recognition. */
+  if (lsm6dso_tap_detection_on_x_set(&(pObj->Ctx), PROPERTY_DISABLE) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Enable double tap detection
+  * @param  pObj the device pObj
+  * @param  IntPin interrupt pin line to be used
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Enable_Double_Tap_Detection(LSM6DSO_Object_t *pObj, LSM6DSO_SensorIntPin_t IntPin)
+{
+  int32_t ret = LSM6DSO_OK;
+  lsm6dso_pin_int1_route_t val1;
+  lsm6dso_pin_int2_route_t val2;
+
+  /* Output Data Rate selection */
+  if (LSM6DSO_ACC_SetOutputDataRate(pObj, 417.0f) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Full scale selection */
+  if (LSM6DSO_ACC_SetFullScale(pObj, 2) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Enable X direction in tap recognition. */
+  if (lsm6dso_tap_detection_on_x_set(&(pObj->Ctx), PROPERTY_ENABLE) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Enable Y direction in tap recognition. */
+  if (lsm6dso_tap_detection_on_y_set(&(pObj->Ctx), PROPERTY_ENABLE) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Enable Z direction in tap recognition. */
+  if (lsm6dso_tap_detection_on_z_set(&(pObj->Ctx), PROPERTY_ENABLE) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Set tap threshold. */
+  if (lsm6dso_tap_threshold_x_set(&(pObj->Ctx), 0x08) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Set tap shock time window. */
+  if (lsm6dso_tap_shock_set(&(pObj->Ctx), 0x03) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Set tap quiet time window. */
+  if (lsm6dso_tap_quiet_set(&(pObj->Ctx), 0x03) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Set tap duration time window. */
+  if (lsm6dso_tap_dur_set(&(pObj->Ctx), 0x08) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Single and double tap enabled. */
+  if (lsm6dso_tap_mode_set(&(pObj->Ctx), LSM6DSO_BOTH_SINGLE_DOUBLE) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Enable double tap event on either INT1 or INT2 pin */
+  switch (IntPin)
+  {
+    case LSM6DSO_INT1_PIN:
+      if (lsm6dso_pin_int1_route_get(&(pObj->Ctx), &val1) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+
+      val1.double_tap = PROPERTY_ENABLE;
+
+      if (lsm6dso_pin_int1_route_set(&(pObj->Ctx), val1) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+      break;
+
+    case LSM6DSO_INT2_PIN:
+      if (lsm6dso_pin_int2_route_get(&(pObj->Ctx), NULL, &val2) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+
+      val2.double_tap = PROPERTY_ENABLE;
+
+      if (lsm6dso_pin_int2_route_set(&(pObj->Ctx), NULL, val2) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+      break;
+
+    default:
+      ret = LSM6DSO_ERROR;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Disable double tap detection
+  * @param  pObj the device pObj
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Disable_Double_Tap_Detection(LSM6DSO_Object_t *pObj)
+{
+  lsm6dso_pin_int1_route_t val1;
+  lsm6dso_pin_int2_route_t val2;
+
+  /* Disable double tap event on both INT1 and INT2 pins */
+  if (lsm6dso_pin_int1_route_get(&(pObj->Ctx), &val1) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  val1.double_tap = PROPERTY_DISABLE;
+
+  if (lsm6dso_pin_int1_route_set(&(pObj->Ctx), val1) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  if (lsm6dso_pin_int2_route_get(&(pObj->Ctx), NULL, &val2) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  val2.double_tap = PROPERTY_DISABLE;
+
+  if (lsm6dso_pin_int2_route_set(&(pObj->Ctx), NULL, val2) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Only single tap enabled. */
+  if (lsm6dso_tap_mode_set(&(pObj->Ctx), LSM6DSO_ONLY_SINGLE) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Reset tap duration time window. */
+  if (lsm6dso_tap_dur_set(&(pObj->Ctx), 0x00) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Reset tap quiet time window. */
+  if (lsm6dso_tap_quiet_set(&(pObj->Ctx), 0x00) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Reset tap shock time window. */
+  if (lsm6dso_tap_shock_set(&(pObj->Ctx), 0x00) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Reset tap threshold. */
+  if (lsm6dso_tap_threshold_x_set(&(pObj->Ctx), 0x00) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Disable Z direction in tap recognition. */
+  if (lsm6dso_tap_detection_on_z_set(&(pObj->Ctx), PROPERTY_DISABLE) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Disable Y direction in tap recognition. */
+  if (lsm6dso_tap_detection_on_y_set(&(pObj->Ctx), PROPERTY_DISABLE) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Disable X direction in tap recognition. */
+  if (lsm6dso_tap_detection_on_x_set(&(pObj->Ctx), PROPERTY_DISABLE) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Set tap threshold
+  * @param  pObj the device pObj
+  * @param  Threshold tap threshold
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Set_Tap_Threshold(LSM6DSO_Object_t *pObj, uint8_t Threshold)
+{
+  /* Set tap threshold. */
+  if (lsm6dso_tap_threshold_x_set(&(pObj->Ctx), Threshold) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Set tap shock time
+  * @param  pObj the device pObj
+  * @param  Time tap shock time
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Set_Tap_Shock_Time(LSM6DSO_Object_t *pObj, uint8_t Time)
+{
+  /* Set tap shock time window. */
+  if (lsm6dso_tap_shock_set(&(pObj->Ctx), Time) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Set tap quiet time
+  * @param  pObj the device pObj
+  * @param  Time tap quiet time
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Set_Tap_Quiet_Time(LSM6DSO_Object_t *pObj, uint8_t Time)
+{
+  /* Set tap quiet time window. */
+  if (lsm6dso_tap_quiet_set(&(pObj->Ctx), Time) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Set tap duration time
+  * @param  pObj the device pObj
+  * @param  Time tap duration time
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Set_Tap_Duration_Time(LSM6DSO_Object_t *pObj, uint8_t Time)
+{
+  /* Set tap duration time window. */
+  if (lsm6dso_tap_dur_set(&(pObj->Ctx), Time) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Enable 6D orientation detection
+  * @param  pObj the device pObj
+  * @param  IntPin interrupt pin line to be used
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Enable_6D_Orientation(LSM6DSO_Object_t *pObj, LSM6DSO_SensorIntPin_t IntPin)
+{
+  int32_t ret = LSM6DSO_OK;
+  lsm6dso_pin_int1_route_t val1;
+  lsm6dso_pin_int2_route_t val2;
+
+  /* Output Data Rate selection */
+  if (LSM6DSO_ACC_SetOutputDataRate(pObj, 417.0f) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Full scale selection */
+  if (LSM6DSO_ACC_SetFullScale(pObj, 2) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* 6D orientation enabled. */
+  if (lsm6dso_6d_threshold_set(&(pObj->Ctx), LSM6DSO_DEG_60) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Enable 6D orientation event on either INT1 or INT2 pin */
+  switch (IntPin)
+  {
+    case LSM6DSO_INT1_PIN:
+      if (lsm6dso_pin_int1_route_get(&(pObj->Ctx), &val1) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+
+      val1.six_d = PROPERTY_ENABLE;
+
+      if (lsm6dso_pin_int1_route_set(&(pObj->Ctx), val1) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+      break;
+
+    case LSM6DSO_INT2_PIN:
+      if (lsm6dso_pin_int2_route_get(&(pObj->Ctx), NULL, &val2) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+
+      val2.six_d = PROPERTY_ENABLE;
+
+      if (lsm6dso_pin_int2_route_set(&(pObj->Ctx), NULL, val2) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+      break;
+
+    default:
+      ret = LSM6DSO_ERROR;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Disable 6D orientation detection
+  * @param  pObj the device pObj
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Disable_6D_Orientation(LSM6DSO_Object_t *pObj)
+{
+  lsm6dso_pin_int1_route_t val1;
+  lsm6dso_pin_int2_route_t val2;
+
+  /* Disable 6D orientation event on both INT1 and INT2 pins */
+  if (lsm6dso_pin_int1_route_get(&(pObj->Ctx), &val1) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  val1.six_d = PROPERTY_DISABLE;
+
+  if (lsm6dso_pin_int1_route_set(&(pObj->Ctx), val1) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  if (lsm6dso_pin_int2_route_get(&(pObj->Ctx), NULL, &val2) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  val2.six_d = PROPERTY_DISABLE;
+
+  if (lsm6dso_pin_int2_route_set(&(pObj->Ctx), NULL, val2) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Reset 6D orientation. */
+  if (lsm6dso_6d_threshold_set(&(pObj->Ctx), LSM6DSO_DEG_80) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Set 6D orientation threshold
+  * @param  pObj the device pObj
+  * @param  Threshold 6D Orientation detection threshold
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Set_6D_Orientation_Threshold(LSM6DSO_Object_t *pObj, uint8_t Threshold)
+{
+  int32_t ret = LSM6DSO_OK;
+  lsm6dso_sixd_ths_t newThreshold = LSM6DSO_DEG_80;
+
+  switch (Threshold)
+  {
+    case 0:
+      newThreshold = LSM6DSO_DEG_80;
+      break;
+    case 1:
+      newThreshold = LSM6DSO_DEG_70;
+      break;
+    case 2:
+      newThreshold = LSM6DSO_DEG_60;
+      break;
+    case 3:
+      newThreshold = LSM6DSO_DEG_50;
+      break;
+    default:
+      ret = LSM6DSO_ERROR;
+      break;
+  }
+
+  if (ret == LSM6DSO_ERROR)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  if (lsm6dso_6d_threshold_set(&(pObj->Ctx), newThreshold) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Get the status of XLow orientation
+  * @param  pObj the device pObj
+  * @param  XLow the status of XLow orientation
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Get_6D_Orientation_XL(LSM6DSO_Object_t *pObj, uint8_t *XLow)
+{
+  lsm6dso_d6d_src_t data;
+
+  if (lsm6dso_read_reg(&(pObj->Ctx), LSM6DSO_D6D_SRC, (uint8_t *)&data, 1) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  *XLow = data.xl;
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Get the status of XHigh orientation
+  * @param  pObj the device pObj
+  * @param  XHigh the status of XHigh orientation
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Get_6D_Orientation_XH(LSM6DSO_Object_t *pObj, uint8_t *XHigh)
+{
+  lsm6dso_d6d_src_t data;
+
+  if (lsm6dso_read_reg(&(pObj->Ctx), LSM6DSO_D6D_SRC, (uint8_t *)&data, 1) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  *XHigh = data.xh;
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Get the status of YLow orientation
+  * @param  pObj the device pObj
+  * @param  YLow the status of YLow orientation
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Get_6D_Orientation_YL(LSM6DSO_Object_t *pObj, uint8_t *YLow)
+{
+  lsm6dso_d6d_src_t data;
+
+  if (lsm6dso_read_reg(&(pObj->Ctx), LSM6DSO_D6D_SRC, (uint8_t *)&data, 1) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  *YLow = data.yl;
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Get the status of YHigh orientation
+  * @param  pObj the device pObj
+  * @param  YHigh the status of YHigh orientation
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Get_6D_Orientation_YH(LSM6DSO_Object_t *pObj, uint8_t *YHigh)
+{
+  lsm6dso_d6d_src_t data;
+
+  if (lsm6dso_read_reg(&(pObj->Ctx), LSM6DSO_D6D_SRC, (uint8_t *)&data, 1) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  *YHigh = data.yh;
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Get the status of ZLow orientation
+  * @param  pObj the device pObj
+  * @param  ZLow the status of ZLow orientation
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Get_6D_Orientation_ZL(LSM6DSO_Object_t *pObj, uint8_t *ZLow)
+{
+  lsm6dso_d6d_src_t data;
+
+  if (lsm6dso_read_reg(&(pObj->Ctx), LSM6DSO_D6D_SRC, (uint8_t *)&data, 1) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  *ZLow = data.zl;
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Get the status of ZHigh orientation
+  * @param  pObj the device pObj
+  * @param  ZHigh the status of ZHigh orientation
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Get_6D_Orientation_ZH(LSM6DSO_Object_t *pObj, uint8_t *ZHigh)
+{
+  lsm6dso_d6d_src_t data;
+
+  if (lsm6dso_read_reg(&(pObj->Ctx), LSM6DSO_D6D_SRC, (uint8_t *)&data, 1) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  *ZHigh = data.zh;
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Get the LSM6DSO ACC data ready bit value
+  * @param  pObj the device pObj
+  * @param  Status the status of data ready bit
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Get_DRDY_Status(LSM6DSO_Object_t *pObj, uint8_t *Status)
+{
+  if (lsm6dso_xl_flag_data_ready_get(&(pObj->Ctx), Status) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Get the status of all hardware events
+  * @param  pObj the device pObj
+  * @param  Status the status of all hardware events
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Get_Event_Status(LSM6DSO_Object_t *pObj, LSM6DSO_Event_Status_t *Status)
+{
+  uint8_t tilt_ia;
+  lsm6dso_wake_up_src_t wake_up_src;
+  lsm6dso_tap_src_t tap_src;
+  lsm6dso_d6d_src_t d6d_src;
+  lsm6dso_emb_func_src_t func_src;
+  lsm6dso_md1_cfg_t md1_cfg;
+  lsm6dso_md2_cfg_t md2_cfg;
+  lsm6dso_emb_func_int1_t int1_ctrl;
+  lsm6dso_emb_func_int2_t int2_ctrl;
+
+  (void)memset((void *)Status, 0x0, sizeof(LSM6DSO_Event_Status_t));
+
+  if (lsm6dso_read_reg(&(pObj->Ctx), LSM6DSO_WAKE_UP_SRC, (uint8_t *)&wake_up_src, 1) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  if (lsm6dso_read_reg(&(pObj->Ctx), LSM6DSO_TAP_SRC, (uint8_t *)&tap_src, 1) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  if (lsm6dso_read_reg(&(pObj->Ctx), LSM6DSO_D6D_SRC, (uint8_t *)&d6d_src, 1) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  if (lsm6dso_mem_bank_set(&(pObj->Ctx), LSM6DSO_EMBEDDED_FUNC_BANK) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  if (lsm6dso_read_reg(&(pObj->Ctx), LSM6DSO_EMB_FUNC_SRC, (uint8_t *)&func_src, 1) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  if (lsm6dso_read_reg(&(pObj->Ctx), LSM6DSO_EMB_FUNC_INT1, (uint8_t *)&int1_ctrl, 1) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  if (lsm6dso_read_reg(&(pObj->Ctx), LSM6DSO_EMB_FUNC_INT2, (uint8_t *)&int2_ctrl, 1) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  if (lsm6dso_mem_bank_set(&(pObj->Ctx), LSM6DSO_USER_BANK) != 0)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  if (lsm6dso_read_reg(&(pObj->Ctx), LSM6DSO_MD1_CFG, (uint8_t *)&md1_cfg, 1) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  if (lsm6dso_read_reg(&(pObj->Ctx), LSM6DSO_MD2_CFG, (uint8_t *)&md2_cfg, 1) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  if (lsm6dso_tilt_flag_data_ready_get(&(pObj->Ctx), &tilt_ia) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  if ((md1_cfg.int1_ff == 1U) || (md2_cfg.int2_ff == 1U))
+  {
+    if (wake_up_src.ff_ia == 1U)
+    {
+      Status->FreeFallStatus = 1;
+    }
+  }
+
+  if ((md1_cfg.int1_wu == 1U) || (md2_cfg.int2_wu == 1U))
+  {
+    if (wake_up_src.wu_ia == 1U)
+    {
+      Status->WakeUpStatus = 1;
+    }
+  }
+
+  if ((md1_cfg.int1_single_tap == 1U) || (md2_cfg.int2_single_tap == 1U))
+  {
+    if (tap_src.single_tap == 1U)
+    {
+      Status->TapStatus = 1;
+    }
+  }
+
+  if ((md1_cfg.int1_double_tap == 1U) || (md2_cfg.int2_double_tap == 1U))
+  {
+    if (tap_src.double_tap == 1U)
+    {
+      Status->DoubleTapStatus = 1;
+    }
+  }
+
+  if ((md1_cfg.int1_6d == 1U) || (md2_cfg.int2_6d == 1U))
+  {
+    if (d6d_src.d6d_ia == 1U)
+    {
+      Status->D6DOrientationStatus = 1;
+    }
+  }
+
+  if (int1_ctrl.int1_step_detector == 1U)
+  {
+    if (func_src.step_detected == 1U)
+    {
+      Status->StepStatus = 1;
+    }
+  }
+
+  if ((int1_ctrl.int1_tilt == 1U) || (int2_ctrl.int2_tilt == 1U))
+  {
+    if (tilt_ia == 1U)
+    {
+      Status->TiltStatus = 1;
+    }
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Set self test
+  * @param  pObj the device pObj
+  * @param  val the value of st_xl in reg CTRL5_C
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Set_SelfTest(LSM6DSO_Object_t *pObj, uint8_t val)
+{
+  lsm6dso_st_xl_t reg;
+
+  reg = (val == 0U)  ? LSM6DSO_XL_ST_DISABLE
+        : (val == 1U)  ? LSM6DSO_XL_ST_POSITIVE
+        : (val == 2U)  ? LSM6DSO_XL_ST_NEGATIVE
+        :                LSM6DSO_XL_ST_DISABLE;
+
+  if (lsm6dso_xl_self_test_set(&(pObj->Ctx), reg) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Get the LSM6DSO GYRO data ready bit value
+  * @param  pObj the device pObj
+  * @param  Status the status of data ready bit
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_GYRO_Get_DRDY_Status(LSM6DSO_Object_t *pObj, uint8_t *Status)
+{
+  if (lsm6dso_gy_flag_data_ready_get(&(pObj->Ctx), Status) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Set self test
+  * @param  pObj the device pObj
+  * @param  val the value of st_xl in reg CTRL5_C
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_GYRO_Set_SelfTest(LSM6DSO_Object_t *pObj, uint8_t val)
+{
+  lsm6dso_st_g_t reg;
+
+  reg = (val == 0U)  ? LSM6DSO_GY_ST_DISABLE
+        : (val == 1U)  ? LSM6DSO_GY_ST_POSITIVE
+        : (val == 2U)  ? LSM6DSO_GY_ST_NEGATIVE
+        :                LSM6DSO_GY_ST_DISABLE;
+
+
+  if (lsm6dso_gy_self_test_set(&(pObj->Ctx), reg) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Get the LSM6DSO FIFO number of samples
+  * @param  pObj the device pObj
+  * @param  NumSamples number of samples
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_FIFO_Get_Num_Samples(LSM6DSO_Object_t *pObj, uint16_t *NumSamples)
+{
+  if (lsm6dso_fifo_data_level_get(&(pObj->Ctx), NumSamples) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Get the LSM6DSO FIFO full status
+  * @param  pObj the device pObj
+  * @param  Status FIFO full status
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_FIFO_Get_Full_Status(LSM6DSO_Object_t *pObj, uint8_t *Status)
+{
+  lsm6dso_reg_t reg;
+
+  if (lsm6dso_read_reg(&(pObj->Ctx), LSM6DSO_FIFO_STATUS2, &reg.byte, 1) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  *Status = reg.fifo_status2.fifo_full_ia;
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Set the LSM6DSO FIFO full interrupt on INT1 pin
+  * @param  pObj the device pObj
+  * @param  Status FIFO full interrupt on INT1 pin status
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_FIFO_Set_INT1_FIFO_Full(LSM6DSO_Object_t *pObj, uint8_t Status)
+{
+  lsm6dso_reg_t reg;
+
+  if (lsm6dso_read_reg(&(pObj->Ctx), LSM6DSO_INT1_CTRL, &reg.byte, 1) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  reg.int1_ctrl.int1_fifo_full = Status;
+
+  if (lsm6dso_write_reg(&(pObj->Ctx), LSM6DSO_INT1_CTRL, &reg.byte, 1) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Set the LSM6DSO FIFO watermark level
+  * @param  pObj the device pObj
+  * @param  Watermark FIFO watermark level
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_FIFO_Set_Watermark_Level(LSM6DSO_Object_t *pObj, uint16_t Watermark)
+{
+  if (lsm6dso_fifo_watermark_set(&(pObj->Ctx), Watermark) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Set the LSM6DSO FIFO stop on watermark
+  * @param  pObj the device pObj
+  * @param  Status FIFO stop on watermark status
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_FIFO_Set_Stop_On_Fth(LSM6DSO_Object_t *pObj, uint8_t Status)
+{
+  if (lsm6dso_fifo_stop_on_wtm_set(&(pObj->Ctx), Status) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Set the LSM6DSO FIFO mode
+  * @param  pObj the device pObj
+  * @param  Mode FIFO mode
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_FIFO_Set_Mode(LSM6DSO_Object_t *pObj, uint8_t Mode)
+{
+  int32_t ret = LSM6DSO_OK;
+  lsm6dso_fifo_mode_t newMode = LSM6DSO_BYPASS_MODE;
+
+  switch (Mode)
+  {
+    case 0:
+      newMode = LSM6DSO_BYPASS_MODE;
+      break;
+    case 1:
+      newMode = LSM6DSO_FIFO_MODE;
+      break;
+    case 3:
+      newMode = LSM6DSO_STREAM_TO_FIFO_MODE;
+      break;
+    case 4:
+      newMode = LSM6DSO_BYPASS_TO_STREAM_MODE;
+      break;
+    case 6:
+      newMode = LSM6DSO_STREAM_MODE;
+      break;
+    case 7:
+      newMode = LSM6DSO_BYPASS_TO_FIFO_MODE;
+      break;
+    default:
+      ret = LSM6DSO_ERROR;
+      break;
+  }
+
+  if (ret == LSM6DSO_ERROR)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  if (lsm6dso_fifo_mode_set(&(pObj->Ctx), newMode) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Get the LSM6DSO FIFO tag
+  * @param  pObj the device pObj
+  * @param  Tag FIFO tag
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_FIFO_Get_Tag(LSM6DSO_Object_t *pObj, uint8_t *Tag)
+{
+  lsm6dso_fifo_tag_t tag_local;
+
+  if (lsm6dso_fifo_sensor_tag_get(&(pObj->Ctx), &tag_local) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  *Tag = (uint8_t)tag_local;
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Get the LSM6DSO FIFO raw data
+  * @param  pObj the device pObj
+  * @param  Data FIFO raw data array [6]
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_FIFO_Get_Data(LSM6DSO_Object_t *pObj, uint8_t *Data)
+{
+  if (lsm6dso_read_reg(&(pObj->Ctx), LSM6DSO_FIFO_DATA_OUT_X_L, Data, 6) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Get the LSM6DSO FIFO accelero single sample (16-bit data per 3 axes) and calculate acceleration [mg]
+  * @param  pObj the device pObj
+  * @param  Acceleration FIFO accelero axes [mg]
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_FIFO_ACC_Get_Axes(LSM6DSO_Object_t *pObj, LSM6DSO_Axes_t *Acceleration)
+{
+  lsm6dso_axis3bit16_t data_raw;
+  float_t sensitivity = 0.0f;
+  float_t acceleration_float_t[3];
+
+  if (LSM6DSO_FIFO_Get_Data(pObj, data_raw.u8bit) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  if (LSM6DSO_ACC_GetSensitivity(pObj, &sensitivity) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  acceleration_float_t[0] = (float_t)data_raw.i16bit[0] * sensitivity;
+  acceleration_float_t[1] = (float_t)data_raw.i16bit[1] * sensitivity;
+  acceleration_float_t[2] = (float_t)data_raw.i16bit[2] * sensitivity;
+
+  Acceleration->x = (int32_t)acceleration_float_t[0];
+  Acceleration->y = (int32_t)acceleration_float_t[1];
+  Acceleration->z = (int32_t)acceleration_float_t[2];
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Set the LSM6DSO FIFO accelero BDR value
+  * @param  pObj the device pObj
+  * @param  Bdr FIFO accelero BDR value
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_FIFO_ACC_Set_BDR(LSM6DSO_Object_t *pObj, float_t Bdr)
+{
+  lsm6dso_bdr_xl_t new_bdr;
+
+  new_bdr = (Bdr <=    0.0f) ? LSM6DSO_XL_NOT_BATCHED
+            : (Bdr <=   12.5f) ? LSM6DSO_XL_BATCHED_AT_12Hz5
+            : (Bdr <=   26.0f) ? LSM6DSO_XL_BATCHED_AT_26Hz
+            : (Bdr <=   52.0f) ? LSM6DSO_XL_BATCHED_AT_52Hz
+            : (Bdr <=  104.0f) ? LSM6DSO_XL_BATCHED_AT_104Hz
+            : (Bdr <=  208.0f) ? LSM6DSO_XL_BATCHED_AT_208Hz
+            : (Bdr <=  417.0f) ? LSM6DSO_XL_BATCHED_AT_417Hz
+            : (Bdr <=  833.0f) ? LSM6DSO_XL_BATCHED_AT_833Hz
+            : (Bdr <= 1667.0f) ? LSM6DSO_XL_BATCHED_AT_1667Hz
+            : (Bdr <= 3333.0f) ? LSM6DSO_XL_BATCHED_AT_3333Hz
+            :                    LSM6DSO_XL_BATCHED_AT_6667Hz;
+
+  if (lsm6dso_fifo_xl_batch_set(&(pObj->Ctx), new_bdr) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Get the LSM6DSO FIFO gyro single sample (16-bit data per 3 axes) and calculate angular velocity [mDPS]
+  * @param  pObj the device pObj
+  * @param  AngularVelocity FIFO gyro axes [mDPS]
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_FIFO_GYRO_Get_Axes(LSM6DSO_Object_t *pObj, LSM6DSO_Axes_t *AngularVelocity)
+{
+  lsm6dso_axis3bit16_t data_raw;
+  float_t sensitivity = 0.0f;
+  float_t angular_velocity_float_t[3];
+
+  if (LSM6DSO_FIFO_Get_Data(pObj, data_raw.u8bit) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  if (LSM6DSO_GYRO_GetSensitivity(pObj, &sensitivity) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  angular_velocity_float_t[0] = (float_t)data_raw.i16bit[0] * sensitivity;
+  angular_velocity_float_t[1] = (float_t)data_raw.i16bit[1] * sensitivity;
+  angular_velocity_float_t[2] = (float_t)data_raw.i16bit[2] * sensitivity;
+
+  AngularVelocity->x = (int32_t)angular_velocity_float_t[0];
+  AngularVelocity->y = (int32_t)angular_velocity_float_t[1];
+  AngularVelocity->z = (int32_t)angular_velocity_float_t[2];
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Set the LSM6DSO FIFO gyro BDR value
+  * @param  pObj the device pObj
+  * @param  Bdr FIFO gyro BDR value
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_FIFO_GYRO_Set_BDR(LSM6DSO_Object_t *pObj, float_t Bdr)
+{
+  lsm6dso_bdr_gy_t new_bdr;
+
+  new_bdr = (Bdr <=    0.0f) ? LSM6DSO_GY_NOT_BATCHED
+            : (Bdr <=   12.5f) ? LSM6DSO_GY_BATCHED_AT_12Hz5
+            : (Bdr <=   26.0f) ? LSM6DSO_GY_BATCHED_AT_26Hz
+            : (Bdr <=   52.0f) ? LSM6DSO_GY_BATCHED_AT_52Hz
+            : (Bdr <=  104.0f) ? LSM6DSO_GY_BATCHED_AT_104Hz
+            : (Bdr <=  208.0f) ? LSM6DSO_GY_BATCHED_AT_208Hz
+            : (Bdr <=  417.0f) ? LSM6DSO_GY_BATCHED_AT_417Hz
+            : (Bdr <=  833.0f) ? LSM6DSO_GY_BATCHED_AT_833Hz
+            : (Bdr <= 1667.0f) ? LSM6DSO_GY_BATCHED_AT_1667Hz
+            : (Bdr <= 3333.0f) ? LSM6DSO_GY_BATCHED_AT_3333Hz
+            :                    LSM6DSO_GY_BATCHED_AT_6667Hz;
+
+  if (lsm6dso_fifo_gy_batch_set(&(pObj->Ctx), new_bdr) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Enable LSM6DSO accelerometer DRDY interrupt on INT1
+  * @param  pObj the device pObj
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Enable_DRDY_On_INT1(LSM6DSO_Object_t *pObj)
+{
+  lsm6dso_pin_int1_route_t pin_int1_route;
+
+  /* Enable accelerometer DRDY Interrupt on INT1 */
+  if (lsm6dso_pin_int1_route_get(&(pObj->Ctx), &pin_int1_route) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+  pin_int1_route.drdy_xl = 1;
+  pin_int1_route.drdy_g = 0;
+  if (lsm6dso_pin_int1_route_set(&(pObj->Ctx), pin_int1_route) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Disable LSM6DSO accelerometer DRDY interrupt on INT1
+  * @param  pObj the device pObj
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Disable_DRDY_On_INT1(LSM6DSO_Object_t *pObj)
+{
+  lsm6dso_pin_int1_route_t pin_int1_route;
+
+  /* Disable accelerometer DRDY Interrupt on INT1 */
+  if (lsm6dso_pin_int1_route_get(&(pObj->Ctx), &pin_int1_route) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+  pin_int1_route.drdy_xl = 0;
+  if (lsm6dso_pin_int1_route_set(&(pObj->Ctx), pin_int1_route) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Set the LSM6DSO accelerometer power mode
+  * @param  pObj the device pObj
+  * @param  PowerMode Value of the powerMode
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Set_Power_Mode(LSM6DSO_Object_t *pObj, uint8_t PowerMode)
+{
+  int32_t ret = LSM6DSO_OK;
+  lsm6dso_xl_hm_mode_t newPowerMode = LSM6DSO_HIGH_PERFORMANCE_MD;
+
+  switch (PowerMode)
+  {
+    case 0:
+      newPowerMode = LSM6DSO_HIGH_PERFORMANCE_MD;
+      break;
+    case 1:
+      newPowerMode = LSM6DSO_LOW_NORMAL_POWER_MD;
+      break;
+    case 2:
+      newPowerMode = LSM6DSO_ULTRA_LOW_POWER_MD;
+      break;
+    default:
+      ret = LSM6DSO_ERROR;
+      break;
+  }
+
+  if (ret == LSM6DSO_ERROR)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  if (lsm6dso_xl_power_mode_set(&(pObj->Ctx), newPowerMode) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Set the LSM6DSO accelerometer filter mode
+  * @param  pObj the device pObj
+  * @param  LowHighPassFlag 0/1 for setting low-pass/high-pass filter mode
+  * @param  FilterMode Value of the filter Mode
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Set_Filter_Mode(LSM6DSO_Object_t *pObj, uint8_t LowHighPassFlag, uint8_t FilterMode)
+{
+  int32_t ret = LSM6DSO_OK;
+  lsm6dso_hp_slope_xl_en_t newFilterMode = LSM6DSO_HP_PATH_DISABLE_ON_OUT;
+
+  switch (FilterMode)
+  {
+    case 0x00:
+      newFilterMode = LSM6DSO_HP_PATH_DISABLE_ON_OUT;
+      break;
+    case 0x01:
+      newFilterMode = LSM6DSO_LP_ODR_DIV_10;
+      break;
+    case 0x02:
+      newFilterMode = LSM6DSO_LP_ODR_DIV_20;
+      break;
+    case 0x03:
+      newFilterMode = LSM6DSO_LP_ODR_DIV_45;
+      break;
+    case 0x04:
+      newFilterMode = LSM6DSO_LP_ODR_DIV_100;
+      break;
+    case 0x05:
+      newFilterMode = LSM6DSO_LP_ODR_DIV_200;
+      break;
+    case 0x06:
+      newFilterMode = LSM6DSO_LP_ODR_DIV_400;
+      break;
+    case 0x07:
+      newFilterMode = LSM6DSO_LP_ODR_DIV_800;
+      break;
+    case 0x10:
+      newFilterMode = LSM6DSO_SLOPE_ODR_DIV_4;
+      break;
+    case 0x11:
+      newFilterMode = LSM6DSO_HP_ODR_DIV_10;
+      break;
+    case 0x12:
+      newFilterMode = LSM6DSO_HP_ODR_DIV_20;
+      break;
+    case 0x13:
+      newFilterMode = LSM6DSO_HP_ODR_DIV_45;
+      break;
+    case 0x14:
+      newFilterMode = LSM6DSO_HP_ODR_DIV_100;
+      break;
+    case 0x15:
+      newFilterMode = LSM6DSO_HP_ODR_DIV_200;
+      break;
+    case 0x16:
+      newFilterMode = LSM6DSO_HP_ODR_DIV_400;
+      break;
+    case 0x17:
+      newFilterMode = LSM6DSO_HP_ODR_DIV_800;
+      break;
+    case 0x31:
+      newFilterMode = LSM6DSO_HP_REF_MD_ODR_DIV_10;
+      break;
+    case 0x32:
+      newFilterMode = LSM6DSO_HP_REF_MD_ODR_DIV_20;
+      break;
+    case 0x33:
+      newFilterMode = LSM6DSO_HP_REF_MD_ODR_DIV_45;
+      break;
+    case 0x34:
+      newFilterMode = LSM6DSO_HP_REF_MD_ODR_DIV_100;
+      break;
+    case 0x35:
+      newFilterMode = LSM6DSO_HP_REF_MD_ODR_DIV_200;
+      break;
+    case 0x36:
+      newFilterMode = LSM6DSO_HP_REF_MD_ODR_DIV_400;
+      break;
+    case 0x37:
+      newFilterMode = LSM6DSO_HP_REF_MD_ODR_DIV_800;
+      break;
+    default:
+      ret = LSM6DSO_ERROR;
+      break;
+  }
+
+  if (ret == LSM6DSO_ERROR)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  if (LowHighPassFlag == 0U)
+  {
+    /*Set accelerometer low_pass filter-mode*/
+
+    /*Set to 1 LPF2 bit (CTRL8_XL)*/
+    if (lsm6dso_xl_filter_lp2_set(&(pObj->Ctx), 1) != LSM6DSO_OK)
+    {
+      return LSM6DSO_ERROR;
+    }
+    if (lsm6dso_xl_hp_path_on_out_set(&(pObj->Ctx), newFilterMode) != LSM6DSO_OK)
+    {
+      return LSM6DSO_ERROR;
+    }
+  }
+  else
+  {
+    /*Set accelerometer high_pass filter-mode*/
+    if (lsm6dso_xl_hp_path_on_out_set(&(pObj->Ctx), newFilterMode) != LSM6DSO_OK)
+    {
+      return LSM6DSO_ERROR;
+    }
+  }
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Enable LSM6DSO accelerometer inactivity detection
+  * @param  pObj the device pObj
+  * @param  InactMode inactivity detection mode
+  * @param  IntPin interrupt pin line to be used
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Enable_Inactivity_Detection(LSM6DSO_Object_t *pObj, lsm6dso_inact_en_t InactMode,
+                                                LSM6DSO_SensorIntPin_t IntPin)
+{
+  lsm6dso_pin_int1_route_t val1;
+  lsm6dso_pin_int2_route_t val2;
+  int32_t ret = LSM6DSO_OK;
+
+  /* Full scale selection */
+  if (LSM6DSO_ACC_SetFullScale(pObj, 2) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+  if (LSM6DSO_GYRO_SetFullScale(pObj, 250) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* SLEEP_DUR setting */
+  if (lsm6dso_act_sleep_dur_set(&(pObj->Ctx), 0x01) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Enable inactivity detection. */
+  switch (InactMode)
+  {
+    case LSM6DSO_XL_AND_GY_NOT_AFFECTED:
+    {
+      if (lsm6dso_act_mode_set(&(pObj->Ctx), LSM6DSO_XL_AND_GY_NOT_AFFECTED) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+      break;
+    }
+    case LSM6DSO_XL_12Hz5_GY_NOT_AFFECTED:
+    {
+      if (lsm6dso_act_mode_set(&(pObj->Ctx), LSM6DSO_XL_12Hz5_GY_NOT_AFFECTED) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+      break;
+    }
+    case LSM6DSO_XL_12Hz5_GY_SLEEP:
+    {
+      if (lsm6dso_act_mode_set(&(pObj->Ctx), LSM6DSO_XL_12Hz5_GY_SLEEP) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+      break;
+    }
+    case LSM6DSO_XL_12Hz5_GY_PD:
+    {
+      if (lsm6dso_act_mode_set(&(pObj->Ctx), LSM6DSO_XL_12Hz5_GY_PD) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+      break;
+    }
+    default:
+      ret = LSM6DSO_ERROR;
+      break;
+  }
+
+  if (ret == LSM6DSO_ERROR)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Enable Inactivity event on either INT1 or INT2 pin */
+  switch (IntPin)
+  {
+    case LSM6DSO_INT1_PIN:
+    {
+      if (lsm6dso_pin_int1_route_get(&(pObj->Ctx), &val1) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+
+      val1.sleep_change = PROPERTY_ENABLE;
+      if (lsm6dso_pin_int1_route_set(&(pObj->Ctx), val1) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+      break;
+    }
+    case LSM6DSO_INT2_PIN:
+    {
+      if (lsm6dso_pin_int2_route_get(&(pObj->Ctx), NULL, &val2) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+
+      val2.sleep_change = PROPERTY_ENABLE;
+      if (lsm6dso_pin_int2_route_set(&(pObj->Ctx), NULL, val2) != LSM6DSO_OK)
+      {
+        return LSM6DSO_ERROR;
+      }
+      break;
+    }
+    default:
+      ret = LSM6DSO_ERROR;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Disable LSM6DSO accelerometer inactivity detection
+  * @param  pObj the device pObj
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Disable_Inactivity_Detection(LSM6DSO_Object_t *pObj)
+{
+  lsm6dso_pin_int1_route_t val1;
+  lsm6dso_pin_int2_route_t val2;
+
+  /* Disable inactivity event on both INT1 and INT2 pins */
+  if (lsm6dso_pin_int1_route_get(&(pObj->Ctx), &val1) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  val1.sleep_change = PROPERTY_DISABLE;
+
+  if (lsm6dso_pin_int1_route_set(&(pObj->Ctx), val1) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  if (lsm6dso_pin_int2_route_get(&(pObj->Ctx), NULL, &val2) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  val2.sleep_change = PROPERTY_DISABLE;
+
+  if (lsm6dso_pin_int2_route_set(&(pObj->Ctx), NULL, val2) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Disable inactivity detection. */
+  if (lsm6dso_act_mode_set(&(pObj->Ctx), LSM6DSO_XL_AND_GY_NOT_AFFECTED) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* SLEEP_DUR reset */
+  if (lsm6dso_act_sleep_dur_set(&(pObj->Ctx), 0x00) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Set LSM6DSO accelerometer sleep duration
+  * @param  pObj the device pObj
+  * @param  Duration wake up detection duration
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_ACC_Set_Sleep_Duration(LSM6DSO_Object_t *pObj, uint8_t Duration)
+{
+  /* Set wake up duration. */
+  if (lsm6dso_act_sleep_dur_set(&(pObj->Ctx), Duration) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Enable LSM6DSO gyroscope DRDY interrupt on INT2
+  * @param  pObj the device pObj
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_GYRO_Enable_DRDY_On_INT2(LSM6DSO_Object_t *pObj)
+{
+  lsm6dso_pin_int2_route_t pin_int2_route;
+
+  /* Enable gyroscope DRDY Interrupts on INT2 */
+  if (lsm6dso_pin_int2_route_get(&(pObj->Ctx), NULL, &pin_int2_route) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+  pin_int2_route.drdy_xl = 0;
+  pin_int2_route.drdy_g = 1;
+  if (lsm6dso_pin_int2_route_set(&(pObj->Ctx), NULL, pin_int2_route) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Set the LSM6DSO gyroscope power mode
+  * @param  pObj the device pObj
+  * @param  PowerMode Value of the powerMode
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_GYRO_Set_Power_Mode(LSM6DSO_Object_t *pObj, uint8_t PowerMode)
+{
+  int32_t ret = LSM6DSO_OK;
+  lsm6dso_g_hm_mode_t newPowerMode = LSM6DSO_GY_HIGH_PERFORMANCE;
+
+  switch (PowerMode)
+  {
+    case 0:
+      newPowerMode = LSM6DSO_GY_HIGH_PERFORMANCE;
+      break;
+    case 1:
+      newPowerMode = LSM6DSO_GY_NORMAL;
+      break;
+    default:
+      ret = LSM6DSO_ERROR;
+      break;
+  }
+
+  if (ret == LSM6DSO_ERROR)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  if (lsm6dso_gy_power_mode_set(&(pObj->Ctx), newPowerMode) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Set the LSM6DSO gyroscope filter mode
+  * @param  pObj the device pObj
+  * @param  LowHighPassFlag 0/1 for setting low-pass/high-pass filter mode
+  * @param  FilterMode Value of the filter Mode
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_GYRO_Set_Filter_Mode(LSM6DSO_Object_t *pObj, uint8_t LowHighPassFlag, uint8_t FilterMode)
+{
+  int32_t ret = LSM6DSO_OK;
+
+  if (LowHighPassFlag == 0U)
+  {
+    lsm6dso_ftype_t newFilterMode = LSM6DSO_ULTRA_LIGHT;
+
+    switch (FilterMode)
+    {
+      case 0:
+        newFilterMode = LSM6DSO_ULTRA_LIGHT;
+        break;
+      case 1:
+        newFilterMode = LSM6DSO_VERY_LIGHT;
+        break;
+      case 2:
+        newFilterMode = LSM6DSO_LIGHT;
+        break;
+      case 3:
+        newFilterMode = LSM6DSO_MEDIUM;
+        break;
+      case 4:
+        newFilterMode = LSM6DSO_STRONG;
+        break;
+      case 5:
+        newFilterMode = LSM6DSO_VERY_STRONG;
+        break;
+      case 6:
+        newFilterMode = LSM6DSO_AGGRESSIVE;
+        break;
+      case 7:
+        newFilterMode = LSM6DSO_XTREME;
+        break;
+      default:
+        ret = LSM6DSO_ERROR;
+        break;
+    }
+
+    if (ret == LSM6DSO_ERROR)
+    {
+      return LSM6DSO_ERROR;
+    }
+    /*Set gyroscope low_pass 1 filter-mode*/
+    /* Enable low-pass filter */
+    if (lsm6dso_gy_filter_lp1_set(&(pObj->Ctx), 1) != LSM6DSO_OK)
+    {
+      return LSM6DSO_ERROR;
+    }
+    if (lsm6dso_gy_lp1_bandwidth_set(&(pObj->Ctx), newFilterMode) != LSM6DSO_OK)
+    {
+      return LSM6DSO_ERROR;
+    }
+  }
+  else
+  {
+    lsm6dso_hpm_g_t newFilterMode = LSM6DSO_HP_FILTER_NONE;
+
+    switch (FilterMode)
+    {
+      case 0x00:
+        newFilterMode = LSM6DSO_HP_FILTER_NONE;
+        break;
+      case 0x80:
+        newFilterMode = LSM6DSO_HP_FILTER_16mHz;
+        break;
+      case 0x81:
+        newFilterMode = LSM6DSO_HP_FILTER_65mHz;
+        break;
+      case 0x82:
+        newFilterMode = LSM6DSO_HP_FILTER_260mHz;
+        break;
+      case 0x83:
+        newFilterMode = LSM6DSO_HP_FILTER_1Hz04;
+        break;
+      default:
+        ret = LSM6DSO_ERROR;
+        break;
+    }
+
+    if (ret == LSM6DSO_ERROR)
+    {
+      return LSM6DSO_ERROR;
+    }
+
+    /*Set gyroscope high_pass filter-mode*/
+    /* Enable high-pass filter */
+    if (lsm6dso_gy_hp_path_internal_set(&(pObj->Ctx), newFilterMode) != LSM6DSO_OK)
+    {
+      return LSM6DSO_ERROR;
+    }
+  }
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Set LSM6DSO DRDY mode
+  * @param  pObj the device pObj
+  * @param  Mode DRDY mode
+  * @retval 0 in case of success, an error code otherwise
+  */
+int32_t LSM6DSO_DRDY_Set_Mode(LSM6DSO_Object_t *pObj, uint8_t Mode)
+{
+  int32_t ret = LSM6DSO_OK;
+  lsm6dso_dataready_pulsed_t newMode = LSM6DSO_DRDY_LATCHED;
+
+  switch (Mode)
+  {
+    case 0:
+      newMode = LSM6DSO_DRDY_LATCHED;
+      break;
+    case 1:
+      newMode = LSM6DSO_DRDY_PULSED;
+      break;
+    default:
+      ret = LSM6DSO_ERROR;
+      break;
+  }
+
+  if (ret == LSM6DSO_ERROR)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  /* Set DRDY mode */
+  if (lsm6dso_data_ready_mode_set(&(pObj->Ctx), newMode) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LSM6DSO_Private_Functions LSM6DSO Private Functions
+  * @{
+  */
+
+/**
+  * @brief  Set the LSM6DSO accelerometer sensor output data rate when enabled
+  * @param  pObj the device pObj
+  * @param  Odr the functional output data rate to be set
+  * @retval 0 in case of success, an error code otherwise
+  */
+static int32_t LSM6DSO_ACC_SetOutputDataRate_When_Enabled(LSM6DSO_Object_t *pObj, float_t Odr)
+{
+  lsm6dso_odr_xl_t new_odr;
+
+  new_odr = (Odr <=    1.6f) ? LSM6DSO_XL_ODR_1Hz6
+            : (Odr <=   12.5f) ? LSM6DSO_XL_ODR_12Hz5
+            : (Odr <=   26.0f) ? LSM6DSO_XL_ODR_26Hz
+            : (Odr <=   52.0f) ? LSM6DSO_XL_ODR_52Hz
+            : (Odr <=  104.0f) ? LSM6DSO_XL_ODR_104Hz
+            : (Odr <=  208.0f) ? LSM6DSO_XL_ODR_208Hz
+            : (Odr <=  417.0f) ? LSM6DSO_XL_ODR_417Hz
+            : (Odr <=  833.0f) ? LSM6DSO_XL_ODR_833Hz
+            : (Odr <= 1667.0f) ? LSM6DSO_XL_ODR_1667Hz
+            : (Odr <= 3333.0f) ? LSM6DSO_XL_ODR_3333Hz
+            :                    LSM6DSO_XL_ODR_6667Hz;
+
+  /* Output data rate selection. */
+  if (lsm6dso_xl_data_rate_set(&(pObj->Ctx), new_odr) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Set the LSM6DSO accelerometer sensor output data rate when disabled
+  * @param  pObj the device pObj
+  * @param  Odr the functional output data rate to be set
+  * @retval 0 in case of success, an error code otherwise
+  */
+static int32_t LSM6DSO_ACC_SetOutputDataRate_When_Disabled(LSM6DSO_Object_t *pObj, float_t Odr)
+{
+  pObj->acc_odr = (Odr <=    1.6f) ? LSM6DSO_XL_ODR_1Hz6
+                  : (Odr <=   12.5f) ? LSM6DSO_XL_ODR_12Hz5
+                  : (Odr <=   26.0f) ? LSM6DSO_XL_ODR_26Hz
+                  : (Odr <=   52.0f) ? LSM6DSO_XL_ODR_52Hz
+                  : (Odr <=  104.0f) ? LSM6DSO_XL_ODR_104Hz
+                  : (Odr <=  208.0f) ? LSM6DSO_XL_ODR_208Hz
+                  : (Odr <=  417.0f) ? LSM6DSO_XL_ODR_417Hz
+                  : (Odr <=  833.0f) ? LSM6DSO_XL_ODR_833Hz
+                  : (Odr <= 1667.0f) ? LSM6DSO_XL_ODR_1667Hz
+                  : (Odr <= 3333.0f) ? LSM6DSO_XL_ODR_3333Hz
+                  :                    LSM6DSO_XL_ODR_6667Hz;
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Set the LSM6DSO gyroscope sensor output data rate when enabled
+  * @param  pObj the device pObj
+  * @param  Odr the functional output data rate to be set
+  * @retval 0 in case of success, an error code otherwise
+  */
+static int32_t LSM6DSO_GYRO_SetOutputDataRate_When_Enabled(LSM6DSO_Object_t *pObj, float_t Odr)
+{
+  lsm6dso_odr_g_t new_odr;
+
+  new_odr = (Odr <=   12.5f) ? LSM6DSO_GY_ODR_12Hz5
+            : (Odr <=   26.0f) ? LSM6DSO_GY_ODR_26Hz
+            : (Odr <=   52.0f) ? LSM6DSO_GY_ODR_52Hz
+            : (Odr <=  104.0f) ? LSM6DSO_GY_ODR_104Hz
+            : (Odr <=  208.0f) ? LSM6DSO_GY_ODR_208Hz
+            : (Odr <=  417.0f) ? LSM6DSO_GY_ODR_417Hz
+            : (Odr <=  833.0f) ? LSM6DSO_GY_ODR_833Hz
+            : (Odr <= 1667.0f) ? LSM6DSO_GY_ODR_1667Hz
+            : (Odr <= 3333.0f) ? LSM6DSO_GY_ODR_3333Hz
+            :                    LSM6DSO_GY_ODR_6667Hz;
+
+  /* Output data rate selection. */
+  if (lsm6dso_gy_data_rate_set(&(pObj->Ctx), new_odr) != LSM6DSO_OK)
+  {
+    return LSM6DSO_ERROR;
+  }
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  Set the LSM6DSO gyroscope sensor output data rate when disabled
+  * @param  pObj the device pObj
+  * @param  Odr the functional output data rate to be set
+  * @retval 0 in case of success, an error code otherwise
+  */
+static int32_t LSM6DSO_GYRO_SetOutputDataRate_When_Disabled(LSM6DSO_Object_t *pObj, float_t Odr)
+{
+  pObj->gyro_odr = (Odr <=   12.5f) ? LSM6DSO_GY_ODR_12Hz5
+                   : (Odr <=   26.0f) ? LSM6DSO_GY_ODR_26Hz
+                   : (Odr <=   52.0f) ? LSM6DSO_GY_ODR_52Hz
+                   : (Odr <=  104.0f) ? LSM6DSO_GY_ODR_104Hz
+                   : (Odr <=  208.0f) ? LSM6DSO_GY_ODR_208Hz
+                   : (Odr <=  417.0f) ? LSM6DSO_GY_ODR_417Hz
+                   : (Odr <=  833.0f) ? LSM6DSO_GY_ODR_833Hz
+                   : (Odr <= 1667.0f) ? LSM6DSO_GY_ODR_1667Hz
+                   : (Odr <= 3333.0f) ? LSM6DSO_GY_ODR_3333Hz
+                   :                    LSM6DSO_GY_ODR_6667Hz;
+
+  return LSM6DSO_OK;
+}
+
+/**
+  * @brief  This function provides a minimum delay based on Tick counter
+  * @param  pObj the device pObj
+  * @param  msDelay delay expressed in ms
+  * @retval None
+  */
+static void LSM6DSO_Delay(LSM6DSO_Object_t *pObj, uint32_t msDelay)
+{
+  uint32_t tickstart = pObj->IO.GetTick();
+
+  while ((pObj->IO.GetTick() - tickstart) < msDelay)
+  {
+  }
+}
+
+/**
+  * @brief  Wrap Read register component function to Bus IO function
+  * @param  Handle the device handler
+  * @param  Reg the register address
+  * @param  pData the stored data pointer
+  * @param  Length the length
+  * @retval 0 in case of success, an error code otherwise
+  */
+static int32_t ReadRegWrap(void *Handle, uint8_t Reg, uint8_t *pData, uint16_t Length)
+{
+  LSM6DSO_Object_t *pObj = (LSM6DSO_Object_t *)Handle;
+
+  return pObj->IO.ReadReg(pObj->IO.Address, Reg, pData, Length);
+}
+
+/**
+  * @brief  Wrap Write register component function to Bus IO function
+  * @param  Handle the device handler
+  * @param  Reg the register address
+  * @param  pData the stored data pointer
+  * @param  Length the length
+  * @retval 0 in case of success, an error code otherwise
+  */
+static int32_t WriteRegWrap(void *Handle, uint8_t Reg, uint8_t *pData, uint16_t Length)
+{
+  LSM6DSO_Object_t *pObj = (LSM6DSO_Object_t *)Handle;
+
+  return pObj->IO.WriteReg(pObj->IO.Address, Reg, pData, Length);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

airmouse/lib/lsm6dso-api/lsm6dso.h

@@ -0,0 +1,369 @@
+/**
+  ******************************************************************************
+  * @file    lsm6dso.h
+  * @author  MEMS Software Solutions Team
+  * @brief   LSM6DSO header driver file
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef LSM6DSO_H
+#define LSM6DSO_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "lsm6dso_reg.h"
+#include <string.h>
+
+/** @addtogroup BSP BSP
+  * @{
+  */
+
+/** @addtogroup Component Component
+  * @{
+  */
+
+/** @addtogroup LSM6DSO LSM6DSO
+  * @{
+  */
+
+/** @defgroup LSM6DSO_Exported_Types LSM6DSO Exported Types
+  * @{
+  */
+
+typedef int32_t (*LSM6DSO_Init_Func)(void);
+typedef int32_t (*LSM6DSO_DeInit_Func)(void);
+typedef int32_t (*LSM6DSO_GetTick_Func)(void);
+typedef void    (*LSM6DSO_Delay_Func)(uint32_t);
+typedef int32_t (*LSM6DSO_WriteReg_Func)(uint16_t, uint16_t, uint8_t *, uint16_t);
+typedef int32_t (*LSM6DSO_ReadReg_Func)(uint16_t, uint16_t, uint8_t *, uint16_t);
+
+typedef enum
+{
+  LSM6DSO_INT1_PIN,
+  LSM6DSO_INT2_PIN,
+} LSM6DSO_SensorIntPin_t;
+
+typedef enum
+{
+  LSM6DSO_ACC_HIGH_PERFORMANCE_MODE,
+  LSM6DSO_ACC_LOW_POWER_NORMAL_MODE,
+  LSM6DSO_ACC_ULTRA_LOW_POWER_MODE
+} LSM6DSO_ACC_Operating_Mode_t;
+
+typedef enum
+{
+  LSM6DSO_GYRO_HIGH_PERFORMANCE_MODE,
+  LSM6DSO_GYRO_LOW_POWER_NORMAL_MODE
+} LSM6DSO_GYRO_Operating_Mode_t;
+
+typedef struct
+{
+  LSM6DSO_Init_Func          Init;
+  LSM6DSO_DeInit_Func        DeInit;
+  uint32_t                   BusType; /*0 means I2C, 1 means SPI 4-Wires, 2 means SPI-3-Wires */
+  uint8_t                    Address;
+  LSM6DSO_WriteReg_Func      WriteReg;
+  LSM6DSO_ReadReg_Func       ReadReg;
+  LSM6DSO_GetTick_Func       GetTick;
+  LSM6DSO_Delay_Func         Delay;
+} LSM6DSO_IO_t;
+
+
+typedef struct
+{
+  int16_t x;
+  int16_t y;
+  int16_t z;
+} LSM6DSO_AxesRaw_t;
+
+typedef struct
+{
+  int32_t x;
+  int32_t y;
+  int32_t z;
+} LSM6DSO_Axes_t;
+
+typedef struct
+{
+  unsigned int FreeFallStatus : 1;
+  unsigned int TapStatus : 1;
+  unsigned int DoubleTapStatus : 1;
+  unsigned int WakeUpStatus : 1;
+  unsigned int StepStatus : 1;
+  unsigned int TiltStatus : 1;
+  unsigned int D6DOrientationStatus : 1;
+  unsigned int SleepStatus : 1;
+} LSM6DSO_Event_Status_t;
+
+typedef struct
+{
+  LSM6DSO_IO_t        IO;
+  stmdev_ctx_t        Ctx;
+  uint8_t             is_initialized;
+  uint8_t             acc_is_enabled;
+  uint8_t             gyro_is_enabled;
+  lsm6dso_odr_xl_t    acc_odr;
+  lsm6dso_odr_g_t     gyro_odr;
+} LSM6DSO_Object_t;
+
+typedef struct
+{
+  uint8_t   Acc;
+  uint8_t   Gyro;
+  uint8_t   Magneto;
+  uint8_t   LowPower;
+  uint32_t  GyroMaxFS;
+  uint32_t  AccMaxFS;
+  uint32_t  MagMaxFS;
+  float_t     GyroMaxOdr;
+  float_t     AccMaxOdr;
+  float_t     MagMaxOdr;
+} LSM6DSO_Capabilities_t;
+
+typedef struct
+{
+  int32_t (*Init)(LSM6DSO_Object_t *);
+  int32_t (*DeInit)(LSM6DSO_Object_t *);
+  int32_t (*ReadID)(LSM6DSO_Object_t *, uint8_t *);
+  int32_t (*GetCapabilities)(LSM6DSO_Object_t *, LSM6DSO_Capabilities_t *);
+} LSM6DSO_CommonDrv_t;
+
+typedef struct
+{
+  int32_t (*Enable)(LSM6DSO_Object_t *);
+  int32_t (*Disable)(LSM6DSO_Object_t *);
+  int32_t (*GetSensitivity)(LSM6DSO_Object_t *, float_t *);
+  int32_t (*GetOutputDataRate)(LSM6DSO_Object_t *, float_t *);
+  int32_t (*SetOutputDataRate)(LSM6DSO_Object_t *, float_t);
+  int32_t (*GetFullScale)(LSM6DSO_Object_t *, int32_t *);
+  int32_t (*SetFullScale)(LSM6DSO_Object_t *, int32_t);
+  int32_t (*GetAxes)(LSM6DSO_Object_t *, LSM6DSO_Axes_t *);
+  int32_t (*GetAxesRaw)(LSM6DSO_Object_t *, LSM6DSO_AxesRaw_t *);
+} LSM6DSO_ACC_Drv_t;
+
+typedef struct
+{
+  int32_t (*Enable)(LSM6DSO_Object_t *);
+  int32_t (*Disable)(LSM6DSO_Object_t *);
+  int32_t (*GetSensitivity)(LSM6DSO_Object_t *, float_t *);
+  int32_t (*GetOutputDataRate)(LSM6DSO_Object_t *, float_t *);
+  int32_t (*SetOutputDataRate)(LSM6DSO_Object_t *, float_t);
+  int32_t (*GetFullScale)(LSM6DSO_Object_t *, int32_t *);
+  int32_t (*SetFullScale)(LSM6DSO_Object_t *, int32_t);
+  int32_t (*GetAxes)(LSM6DSO_Object_t *, LSM6DSO_Axes_t *);
+  int32_t (*GetAxesRaw)(LSM6DSO_Object_t *, LSM6DSO_AxesRaw_t *);
+} LSM6DSO_GYRO_Drv_t;
+
+typedef union
+{
+  int16_t i16bit[3];
+  uint8_t u8bit[6];
+} lsm6dso_axis3bit16_t;
+
+typedef union
+{
+  int16_t i16bit;
+  uint8_t u8bit[2];
+} lsm6dso_axis1bit16_t;
+
+typedef union
+{
+  int32_t i32bit[3];
+  uint8_t u8bit[12];
+} lsm6dso_axis3bit32_t;
+
+typedef union
+{
+  int32_t i32bit;
+  uint8_t u8bit[4];
+} lsm6dso_axis1bit32_t;
+
+/**
+  * @}
+  */
+
+/** @defgroup LSM6DSO_Exported_Constants LSM6DSO Exported Constants
+  * @{
+  */
+
+#define LSM6DSO_OK                       0
+#define LSM6DSO_ERROR                   -1
+
+#define LSM6DSO_I2C_BUS                 0U
+#define LSM6DSO_SPI_4WIRES_BUS          1U
+#define LSM6DSO_SPI_3WIRES_BUS          2U
+
+#define LSM6DSO_ACC_SENSITIVITY_FS_2G   0.061f
+#define LSM6DSO_ACC_SENSITIVITY_FS_4G   0.122f
+#define LSM6DSO_ACC_SENSITIVITY_FS_8G   0.244f
+#define LSM6DSO_ACC_SENSITIVITY_FS_16G  0.488f
+
+#define LSM6DSO_GYRO_SENSITIVITY_FS_125DPS    4.375f
+#define LSM6DSO_GYRO_SENSITIVITY_FS_250DPS    8.750f
+#define LSM6DSO_GYRO_SENSITIVITY_FS_500DPS   17.500f
+#define LSM6DSO_GYRO_SENSITIVITY_FS_1000DPS  35.000f
+#define LSM6DSO_GYRO_SENSITIVITY_FS_2000DPS  70.000f
+
+/**
+  * @}
+  */
+
+/** @addtogroup LSM6DSO_Exported_Functions LSM6DSO Exported Functions
+  * @{
+  */
+
+int32_t LSM6DSO_RegisterBusIO(LSM6DSO_Object_t *pObj, LSM6DSO_IO_t *pIO);
+int32_t LSM6DSO_Init(LSM6DSO_Object_t *pObj);
+int32_t LSM6DSO_DeInit(LSM6DSO_Object_t *pObj);
+int32_t LSM6DSO_ReadID(LSM6DSO_Object_t *pObj, uint8_t *Id);
+int32_t LSM6DSO_GetCapabilities(LSM6DSO_Object_t *pObj, LSM6DSO_Capabilities_t *Capabilities);
+
+int32_t LSM6DSO_ACC_Enable(LSM6DSO_Object_t *pObj);
+int32_t LSM6DSO_ACC_Disable(LSM6DSO_Object_t *pObj);
+int32_t LSM6DSO_ACC_GetSensitivity(LSM6DSO_Object_t *pObj, float_t *Sensitivity);
+int32_t LSM6DSO_ACC_GetOutputDataRate(LSM6DSO_Object_t *pObj, float_t *Odr);
+int32_t LSM6DSO_ACC_SetOutputDataRate(LSM6DSO_Object_t *pObj, float_t Odr);
+int32_t LSM6DSO_ACC_SetOutputDataRate_With_Mode(LSM6DSO_Object_t *pObj, float_t Odr, LSM6DSO_ACC_Operating_Mode_t Mode);
+int32_t LSM6DSO_ACC_GetFullScale(LSM6DSO_Object_t *pObj, int32_t *FullScale);
+int32_t LSM6DSO_ACC_SetFullScale(LSM6DSO_Object_t *pObj, int32_t FullScale);
+int32_t LSM6DSO_ACC_GetAxesRaw(LSM6DSO_Object_t *pObj, LSM6DSO_AxesRaw_t *Value);
+int32_t LSM6DSO_ACC_GetAxes(LSM6DSO_Object_t *pObj, LSM6DSO_Axes_t *Acceleration);
+
+int32_t LSM6DSO_GYRO_Enable(LSM6DSO_Object_t *pObj);
+int32_t LSM6DSO_GYRO_Disable(LSM6DSO_Object_t *pObj);
+int32_t LSM6DSO_GYRO_GetSensitivity(LSM6DSO_Object_t *pObj, float_t *Sensitivity);
+int32_t LSM6DSO_GYRO_GetOutputDataRate(LSM6DSO_Object_t *pObj, float_t *Odr);
+int32_t LSM6DSO_GYRO_SetOutputDataRate(LSM6DSO_Object_t *pObj, float_t Odr);
+int32_t LSM6DSO_GYRO_SetOutputDataRate_With_Mode(LSM6DSO_Object_t *pObj, float_t Odr,
+                                                 LSM6DSO_GYRO_Operating_Mode_t Mode);
+int32_t LSM6DSO_GYRO_GetFullScale(LSM6DSO_Object_t *pObj, int32_t *FullScale);
+int32_t LSM6DSO_GYRO_SetFullScale(LSM6DSO_Object_t *pObj, int32_t FullScale);
+int32_t LSM6DSO_GYRO_GetAxesRaw(LSM6DSO_Object_t *pObj, LSM6DSO_AxesRaw_t *Value);
+int32_t LSM6DSO_GYRO_GetAxes(LSM6DSO_Object_t *pObj, LSM6DSO_Axes_t *AngularRate);
+
+int32_t LSM6DSO_Read_Reg(LSM6DSO_Object_t *pObj, uint8_t reg, uint8_t *Data);
+int32_t LSM6DSO_Write_Reg(LSM6DSO_Object_t *pObj, uint8_t reg, uint8_t Data);
+int32_t LSM6DSO_Set_Interrupt_Latch(LSM6DSO_Object_t *pObj, uint8_t Status);
+
+int32_t LSM6DSO_ACC_Enable_Free_Fall_Detection(LSM6DSO_Object_t *pObj, LSM6DSO_SensorIntPin_t IntPin);
+int32_t LSM6DSO_ACC_Disable_Free_Fall_Detection(LSM6DSO_Object_t *pObj);
+int32_t LSM6DSO_ACC_Set_Free_Fall_Threshold(LSM6DSO_Object_t *pObj, uint8_t Threshold);
+int32_t LSM6DSO_ACC_Set_Free_Fall_Duration(LSM6DSO_Object_t *pObj, uint8_t Duration);
+
+int32_t LSM6DSO_ACC_Enable_Pedometer(LSM6DSO_Object_t *pObj);
+int32_t LSM6DSO_ACC_Disable_Pedometer(LSM6DSO_Object_t *pObj);
+int32_t LSM6DSO_ACC_Get_Step_Count(LSM6DSO_Object_t *pObj, uint16_t *StepCount);
+int32_t LSM6DSO_ACC_Step_Counter_Reset(LSM6DSO_Object_t *pObj);
+
+int32_t LSM6DSO_ACC_Enable_Tilt_Detection(LSM6DSO_Object_t *pObj, LSM6DSO_SensorIntPin_t IntPin);
+int32_t LSM6DSO_ACC_Disable_Tilt_Detection(LSM6DSO_Object_t *pObj);
+
+int32_t LSM6DSO_ACC_Enable_Wake_Up_Detection(LSM6DSO_Object_t *pObj, LSM6DSO_SensorIntPin_t IntPin);
+int32_t LSM6DSO_ACC_Disable_Wake_Up_Detection(LSM6DSO_Object_t *pObj);
+int32_t LSM6DSO_ACC_Set_Wake_Up_Threshold(LSM6DSO_Object_t *pObj, uint8_t Threshold);
+int32_t LSM6DSO_ACC_Set_Wake_Up_Duration(LSM6DSO_Object_t *pObj, uint8_t Duration);
+
+int32_t LSM6DSO_ACC_Enable_Single_Tap_Detection(LSM6DSO_Object_t *pObj, LSM6DSO_SensorIntPin_t IntPin);
+int32_t LSM6DSO_ACC_Disable_Single_Tap_Detection(LSM6DSO_Object_t *pObj);
+int32_t LSM6DSO_ACC_Enable_Double_Tap_Detection(LSM6DSO_Object_t *pObj, LSM6DSO_SensorIntPin_t IntPin);
+int32_t LSM6DSO_ACC_Disable_Double_Tap_Detection(LSM6DSO_Object_t *pObj);
+int32_t LSM6DSO_ACC_Set_Tap_Threshold(LSM6DSO_Object_t *pObj, uint8_t Threshold);
+int32_t LSM6DSO_ACC_Set_Tap_Shock_Time(LSM6DSO_Object_t *pObj, uint8_t Time);
+int32_t LSM6DSO_ACC_Set_Tap_Quiet_Time(LSM6DSO_Object_t *pObj, uint8_t Time);
+int32_t LSM6DSO_ACC_Set_Tap_Duration_Time(LSM6DSO_Object_t *pObj, uint8_t Time);
+
+int32_t LSM6DSO_ACC_Enable_6D_Orientation(LSM6DSO_Object_t *pObj, LSM6DSO_SensorIntPin_t IntPin);
+int32_t LSM6DSO_ACC_Disable_6D_Orientation(LSM6DSO_Object_t *pObj);
+int32_t LSM6DSO_ACC_Set_6D_Orientation_Threshold(LSM6DSO_Object_t *pObj, uint8_t Threshold);
+int32_t LSM6DSO_ACC_Get_6D_Orientation_XL(LSM6DSO_Object_t *pObj, uint8_t *XLow);
+int32_t LSM6DSO_ACC_Get_6D_Orientation_XH(LSM6DSO_Object_t *pObj, uint8_t *XHigh);
+int32_t LSM6DSO_ACC_Get_6D_Orientation_YL(LSM6DSO_Object_t *pObj, uint8_t *YLow);
+int32_t LSM6DSO_ACC_Get_6D_Orientation_YH(LSM6DSO_Object_t *pObj, uint8_t *YHigh);
+int32_t LSM6DSO_ACC_Get_6D_Orientation_ZL(LSM6DSO_Object_t *pObj, uint8_t *ZLow);
+int32_t LSM6DSO_ACC_Get_6D_Orientation_ZH(LSM6DSO_Object_t *pObj, uint8_t *ZHigh);
+
+int32_t LSM6DSO_ACC_Get_DRDY_Status(LSM6DSO_Object_t *pObj, uint8_t *Status);
+int32_t LSM6DSO_ACC_Get_Event_Status(LSM6DSO_Object_t *pObj, LSM6DSO_Event_Status_t *Status);
+int32_t LSM6DSO_ACC_Set_SelfTest(LSM6DSO_Object_t *pObj, uint8_t Status);
+
+int32_t LSM6DSO_GYRO_Get_DRDY_Status(LSM6DSO_Object_t *pObj, uint8_t *Status);
+int32_t LSM6DSO_GYRO_Set_SelfTest(LSM6DSO_Object_t *pObj, uint8_t Status);
+
+int32_t LSM6DSO_FIFO_Get_Num_Samples(LSM6DSO_Object_t *pObj, uint16_t *NumSamples);
+int32_t LSM6DSO_FIFO_Get_Full_Status(LSM6DSO_Object_t *pObj, uint8_t *Status);
+int32_t LSM6DSO_FIFO_Set_INT1_FIFO_Full(LSM6DSO_Object_t *pObj, uint8_t Status);
+int32_t LSM6DSO_FIFO_Set_Watermark_Level(LSM6DSO_Object_t *pObj, uint16_t Watermark);
+int32_t LSM6DSO_FIFO_Set_Stop_On_Fth(LSM6DSO_Object_t *pObj, uint8_t Status);
+int32_t LSM6DSO_FIFO_Set_Mode(LSM6DSO_Object_t *pObj, uint8_t Mode);
+int32_t LSM6DSO_FIFO_Get_Tag(LSM6DSO_Object_t *pObj, uint8_t *Tag);
+int32_t LSM6DSO_FIFO_Get_Data(LSM6DSO_Object_t *pObj, uint8_t *Data);
+int32_t LSM6DSO_FIFO_Get_Empty_Status(LSM6DSO_Object_t *pObj, uint8_t *Status);
+int32_t LSM6DSO_FIFO_Get_Overrun_Status(LSM6DSO_Object_t *pObj, uint8_t *Status);
+int32_t LSM6DSO_FIFO_ACC_Get_Axes(LSM6DSO_Object_t *pObj, LSM6DSO_Axes_t *Acceleration);
+int32_t LSM6DSO_FIFO_ACC_Set_BDR(LSM6DSO_Object_t *pObj, float_t Bdr);
+int32_t LSM6DSO_FIFO_GYRO_Get_Axes(LSM6DSO_Object_t *pObj, LSM6DSO_Axes_t *AngularVelocity);
+int32_t LSM6DSO_FIFO_GYRO_Set_BDR(LSM6DSO_Object_t *pObj, float_t Bdr);
+
+int32_t LSM6DSO_ACC_Enable_DRDY_On_INT1(LSM6DSO_Object_t *pObj);
+int32_t LSM6DSO_ACC_Disable_DRDY_On_INT1(LSM6DSO_Object_t *pObj);
+int32_t LSM6DSO_ACC_Set_Power_Mode(LSM6DSO_Object_t *pObj, uint8_t PowerMode);
+int32_t LSM6DSO_ACC_Set_Filter_Mode(LSM6DSO_Object_t *pObj, uint8_t LowHighPassFlag, uint8_t FilterMode);
+int32_t LSM6DSO_ACC_Enable_Inactivity_Detection(LSM6DSO_Object_t *pObj, lsm6dso_inact_en_t InactMode,
+                                                LSM6DSO_SensorIntPin_t IntPin);
+int32_t LSM6DSO_ACC_Disable_Inactivity_Detection(LSM6DSO_Object_t *pObj);
+int32_t LSM6DSO_ACC_Set_Sleep_Duration(LSM6DSO_Object_t *pObj, uint8_t Duration);
+
+int32_t LSM6DSO_GYRO_Enable_DRDY_On_INT2(LSM6DSO_Object_t *pObj);
+int32_t LSM6DSO_GYRO_Set_Power_Mode(LSM6DSO_Object_t *pObj, uint8_t PowerMode);
+int32_t LSM6DSO_GYRO_Set_Filter_Mode(LSM6DSO_Object_t *pObj, uint8_t LowHighPassFlag, uint8_t FilterMode);
+
+int32_t LSM6DSO_DRDY_Set_Mode(LSM6DSO_Object_t *pObj, uint8_t Mode);
+
+/**
+  * @}
+  */
+
+/** @addtogroup LSM6DSO_Exported_Variables LSM6DSO Exported Variables
+  * @{
+  */
+
+extern LSM6DSO_CommonDrv_t LSM6DSO_COMMON_Driver;
+extern LSM6DSO_ACC_Drv_t LSM6DSO_ACC_Driver;
+extern LSM6DSO_GYRO_Drv_t LSM6DSO_GYRO_Driver;
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

airmouse/lib/lsm6dso-api/lsm6dso_reg.c

@@ -0,0 +1,13139 @@
+/**
+  ******************************************************************************
+  * @file    lsm6dso_reg.c
+  * @author  Sensors Software Solution Team
+  * @brief   LSM6DSO driver file
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+#include "lsm6dso_reg.h"
+#include <stddef.h>
+
+/**
+  * @defgroup  LSM6DSO
+  * @brief     This file provides a set of functions needed to drive the
+  *            lsm6dso enhanced inertial module.
+  * @{
+  *
+  */
+
+/**
+  * @defgroup  LSM6DSO_Interfaces_Functions
+  * @brief     This section provide a set of functions used to read and
+  *            write a generic register of the device.
+  *            MANDATORY: return 0 -> no Error.
+  * @{
+  *
+  */
+
+/**
+  * @brief  Read generic device register
+  *
+  * @param  ctx   read / write interface definitions(ptr)
+  * @param  reg   register to read
+  * @param  data  pointer to buffer that store the data read(ptr)
+  * @param  len   number of consecutive register to read
+  * @retval          interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t __weak lsm6dso_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+                                uint8_t *data,
+                                uint16_t len)
+{
+  int32_t ret;
+
+  ret = ctx->read_reg(ctx->handle, reg, data, len);
+
+  return ret;
+}
+
+/**
+  * @brief  Write generic device register
+  *
+  * @param  ctx   read / write interface definitions(ptr)
+  * @param  reg   register to write
+  * @param  data  pointer to data to write in register reg(ptr)
+  * @param  len   number of consecutive register to write
+  * @retval          interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t __weak lsm6dso_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+                                 uint8_t *data,
+                                 uint16_t len)
+{
+  int32_t ret;
+
+  ret = ctx->write_reg(ctx->handle, reg, data, len);
+
+  return ret;
+}
+
+/**
+  * @}
+  *
+  */
+
+/**
+  * @defgroup  LSM6DSOX_Private_functions
+  * @brief     Section collect all the utility functions needed by APIs.
+  * @{
+  *
+  */
+
+static void bytecpy(uint8_t *target, uint8_t *source)
+{
+  if ((target != NULL) && (source != NULL))
+  {
+    *target = *source;
+  }
+}
+
+/**
+  * @defgroup  LSM6DSO_Sensitivity
+  * @brief     These functions convert raw-data into engineering units.
+  * @{
+  *
+  */
+float_t lsm6dso_from_fs2_to_mg(int16_t lsb)
+{
+  return ((float_t)lsb) * 0.061f;
+}
+
+float_t lsm6dso_from_fs4_to_mg(int16_t lsb)
+{
+  return ((float_t)lsb) * 0.122f;
+}
+
+float_t lsm6dso_from_fs8_to_mg(int16_t lsb)
+{
+  return ((float_t)lsb) * 0.244f;
+}
+
+float_t lsm6dso_from_fs16_to_mg(int16_t lsb)
+{
+  return ((float_t)lsb) * 0.488f;
+}
+
+float_t lsm6dso_from_fs125_to_mdps(int16_t lsb)
+{
+  return ((float_t)lsb) * 4.375f;
+}
+
+float_t lsm6dso_from_fs500_to_mdps(int16_t lsb)
+{
+  return ((float_t)lsb) * 17.50f;
+}
+
+float_t lsm6dso_from_fs250_to_mdps(int16_t lsb)
+{
+  return ((float_t)lsb) * 8.750f;
+}
+
+float_t lsm6dso_from_fs1000_to_mdps(int16_t lsb)
+{
+  return ((float_t)lsb) * 35.0f;
+}
+
+float_t lsm6dso_from_fs2000_to_mdps(int16_t lsb)
+{
+  return ((float_t)lsb) * 70.0f;
+}
+
+float_t lsm6dso_from_lsb_to_celsius(int16_t lsb)
+{
+  return (((float_t)lsb / 256.0f) + 25.0f);
+}
+
+float_t lsm6dso_from_lsb_to_nsec(int16_t lsb)
+{
+  return ((float_t)lsb * 25000.0f);
+}
+
+/**
+  * @}
+  *
+  */
+
+/**
+  * @defgroup  LSM6DSO_Data_Generation
+  * @brief     This section groups all the functions concerning
+  *            data generation.
+  *
+  */
+
+/**
+  * @brief  Accelerometer full-scale selection.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of fs_xl in reg CTRL1_XL
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_xl_full_scale_set(stmdev_ctx_t *ctx,
+                                  lsm6dso_fs_xl_t val)
+{
+  lsm6dso_ctrl1_xl_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.fs_xl = (uint8_t) val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Accelerometer full-scale selection.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of fs_xl in reg CTRL1_XL
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_xl_full_scale_get(stmdev_ctx_t *ctx,
+                                  lsm6dso_fs_xl_t *val)
+{
+  lsm6dso_ctrl1_xl_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)&reg, 1);
+
+  switch (reg.fs_xl)
+  {
+    case LSM6DSO_2g:
+      *val = LSM6DSO_2g;
+      break;
+
+    case LSM6DSO_16g:
+      *val = LSM6DSO_16g;
+      break;
+
+    case LSM6DSO_4g:
+      *val = LSM6DSO_4g;
+      break;
+
+    case LSM6DSO_8g:
+      *val = LSM6DSO_8g;
+      break;
+
+    default:
+      *val = LSM6DSO_2g;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Accelerometer UI data rate selection.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of odr_xl in reg CTRL1_XL
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_xl_data_rate_set(stmdev_ctx_t *ctx,
+                                 lsm6dso_odr_xl_t val)
+{
+  lsm6dso_odr_xl_t odr_xl =  val;
+  lsm6dso_emb_fsm_enable_t fsm_enable;
+  lsm6dso_fsm_odr_t fsm_odr;
+  lsm6dso_ctrl1_xl_t reg;
+  int32_t ret;
+
+  /* Check the Finite State Machine data rate constraints */
+  ret =  lsm6dso_fsm_enable_get(ctx, &fsm_enable);
+
+  if (ret == 0)
+  {
+    if ((fsm_enable.fsm_enable_a.fsm1_en  |
+         fsm_enable.fsm_enable_a.fsm2_en  |
+         fsm_enable.fsm_enable_a.fsm3_en  |
+         fsm_enable.fsm_enable_a.fsm4_en  |
+         fsm_enable.fsm_enable_a.fsm5_en  |
+         fsm_enable.fsm_enable_a.fsm6_en  |
+         fsm_enable.fsm_enable_a.fsm7_en  |
+         fsm_enable.fsm_enable_a.fsm8_en  |
+         fsm_enable.fsm_enable_b.fsm9_en  |
+         fsm_enable.fsm_enable_b.fsm10_en |
+         fsm_enable.fsm_enable_b.fsm11_en |
+         fsm_enable.fsm_enable_b.fsm12_en |
+         fsm_enable.fsm_enable_b.fsm13_en |
+         fsm_enable.fsm_enable_b.fsm14_en |
+         fsm_enable.fsm_enable_b.fsm15_en |
+         fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
+    {
+      ret =  lsm6dso_fsm_data_rate_get(ctx, &fsm_odr);
+
+      if (ret == 0)
+      {
+        switch (fsm_odr)
+        {
+          case LSM6DSO_ODR_FSM_12Hz5:
+            if (val == LSM6DSO_XL_ODR_OFF)
+            {
+              odr_xl = LSM6DSO_XL_ODR_12Hz5;
+            }
+
+            else
+            {
+              odr_xl = val;
+            }
+
+            break;
+
+          case LSM6DSO_ODR_FSM_26Hz:
+            if (val == LSM6DSO_XL_ODR_OFF)
+            {
+              odr_xl = LSM6DSO_XL_ODR_26Hz;
+            }
+
+            else if (val == LSM6DSO_XL_ODR_12Hz5)
+            {
+              odr_xl = LSM6DSO_XL_ODR_26Hz;
+            }
+
+            else
+            {
+              odr_xl = val;
+            }
+
+            break;
+
+          case LSM6DSO_ODR_FSM_52Hz:
+            if (val == LSM6DSO_XL_ODR_OFF)
+            {
+              odr_xl = LSM6DSO_XL_ODR_52Hz;
+            }
+
+            else if (val == LSM6DSO_XL_ODR_12Hz5)
+            {
+              odr_xl = LSM6DSO_XL_ODR_52Hz;
+            }
+
+            else if (val == LSM6DSO_XL_ODR_26Hz)
+            {
+              odr_xl = LSM6DSO_XL_ODR_52Hz;
+            }
+
+            else
+            {
+              odr_xl = val;
+            }
+
+            break;
+
+          case LSM6DSO_ODR_FSM_104Hz:
+            if (val == LSM6DSO_XL_ODR_OFF)
+            {
+              odr_xl = LSM6DSO_XL_ODR_104Hz;
+            }
+
+            else if (val == LSM6DSO_XL_ODR_12Hz5)
+            {
+              odr_xl = LSM6DSO_XL_ODR_104Hz;
+            }
+
+            else if (val == LSM6DSO_XL_ODR_26Hz)
+            {
+              odr_xl = LSM6DSO_XL_ODR_104Hz;
+            }
+
+            else if (val == LSM6DSO_XL_ODR_52Hz)
+            {
+              odr_xl = LSM6DSO_XL_ODR_104Hz;
+            }
+
+            else
+            {
+              odr_xl = val;
+            }
+
+            break;
+
+          default:
+            odr_xl = val;
+            break;
+        }
+      }
+    }
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    reg.odr_xl = (uint8_t) odr_xl;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Accelerometer UI data rate selection.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of odr_xl in reg CTRL1_XL
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_xl_data_rate_get(stmdev_ctx_t *ctx,
+                                 lsm6dso_odr_xl_t *val)
+{
+  lsm6dso_ctrl1_xl_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)&reg, 1);
+
+  switch (reg.odr_xl)
+  {
+    case LSM6DSO_XL_ODR_OFF:
+      *val = LSM6DSO_XL_ODR_OFF;
+      break;
+
+    case LSM6DSO_XL_ODR_12Hz5:
+      *val = LSM6DSO_XL_ODR_12Hz5;
+      break;
+
+    case LSM6DSO_XL_ODR_26Hz:
+      *val = LSM6DSO_XL_ODR_26Hz;
+      break;
+
+    case LSM6DSO_XL_ODR_52Hz:
+      *val = LSM6DSO_XL_ODR_52Hz;
+      break;
+
+    case LSM6DSO_XL_ODR_104Hz:
+      *val = LSM6DSO_XL_ODR_104Hz;
+      break;
+
+    case LSM6DSO_XL_ODR_208Hz:
+      *val = LSM6DSO_XL_ODR_208Hz;
+      break;
+
+    case LSM6DSO_XL_ODR_417Hz:
+      *val = LSM6DSO_XL_ODR_417Hz;
+      break;
+
+    case LSM6DSO_XL_ODR_833Hz:
+      *val = LSM6DSO_XL_ODR_833Hz;
+      break;
+
+    case LSM6DSO_XL_ODR_1667Hz:
+      *val = LSM6DSO_XL_ODR_1667Hz;
+      break;
+
+    case LSM6DSO_XL_ODR_3333Hz:
+      *val = LSM6DSO_XL_ODR_3333Hz;
+      break;
+
+    case LSM6DSO_XL_ODR_6667Hz:
+      *val = LSM6DSO_XL_ODR_6667Hz;
+      break;
+
+    case LSM6DSO_XL_ODR_1Hz6:
+      *val = LSM6DSO_XL_ODR_1Hz6;
+      break;
+
+    default:
+      *val = LSM6DSO_XL_ODR_OFF;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Gyroscope UI chain full-scale selection.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of fs_g in reg CTRL2_G
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_gy_full_scale_set(stmdev_ctx_t *ctx,
+                                  lsm6dso_fs_g_t val)
+{
+  lsm6dso_ctrl2_g_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.fs_g = (uint8_t) val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Gyroscope UI chain full-scale selection.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of fs_g in reg CTRL2_G
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_gy_full_scale_get(stmdev_ctx_t *ctx,
+                                  lsm6dso_fs_g_t *val)
+{
+  lsm6dso_ctrl2_g_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t *)&reg, 1);
+
+  switch (reg.fs_g)
+  {
+    case LSM6DSO_250dps:
+      *val = LSM6DSO_250dps;
+      break;
+
+    case LSM6DSO_125dps:
+      *val = LSM6DSO_125dps;
+      break;
+
+    case LSM6DSO_500dps:
+      *val = LSM6DSO_500dps;
+      break;
+
+    case LSM6DSO_1000dps:
+      *val = LSM6DSO_1000dps;
+      break;
+
+    case LSM6DSO_2000dps:
+      *val = LSM6DSO_2000dps;
+      break;
+
+    default:
+      *val = LSM6DSO_250dps;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Gyroscope UI data rate selection.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of odr_g in reg CTRL2_G
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_gy_data_rate_set(stmdev_ctx_t *ctx,
+                                 lsm6dso_odr_g_t val)
+{
+  lsm6dso_odr_g_t odr_gy =  val;
+  lsm6dso_emb_fsm_enable_t fsm_enable;
+  lsm6dso_fsm_odr_t fsm_odr;
+  lsm6dso_ctrl2_g_t reg;
+  int32_t ret;
+
+  /* Check the Finite State Machine data rate constraints */
+  ret =  lsm6dso_fsm_enable_get(ctx, &fsm_enable);
+
+  if (ret == 0)
+  {
+    if ((fsm_enable.fsm_enable_a.fsm1_en  |
+         fsm_enable.fsm_enable_a.fsm2_en  |
+         fsm_enable.fsm_enable_a.fsm3_en  |
+         fsm_enable.fsm_enable_a.fsm4_en  |
+         fsm_enable.fsm_enable_a.fsm5_en  |
+         fsm_enable.fsm_enable_a.fsm6_en  |
+         fsm_enable.fsm_enable_a.fsm7_en  |
+         fsm_enable.fsm_enable_a.fsm8_en  |
+         fsm_enable.fsm_enable_b.fsm9_en  |
+         fsm_enable.fsm_enable_b.fsm10_en |
+         fsm_enable.fsm_enable_b.fsm11_en |
+         fsm_enable.fsm_enable_b.fsm12_en |
+         fsm_enable.fsm_enable_b.fsm13_en |
+         fsm_enable.fsm_enable_b.fsm14_en |
+         fsm_enable.fsm_enable_b.fsm15_en |
+         fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
+    {
+      ret =  lsm6dso_fsm_data_rate_get(ctx, &fsm_odr);
+
+      if (ret == 0)
+      {
+        switch (fsm_odr)
+        {
+          case LSM6DSO_ODR_FSM_12Hz5:
+            if (val == LSM6DSO_GY_ODR_OFF)
+            {
+              odr_gy = LSM6DSO_GY_ODR_12Hz5;
+            }
+
+            else
+            {
+              odr_gy = val;
+            }
+
+            break;
+
+          case LSM6DSO_ODR_FSM_26Hz:
+            if (val == LSM6DSO_GY_ODR_OFF)
+            {
+              odr_gy = LSM6DSO_GY_ODR_26Hz;
+            }
+
+            else if (val == LSM6DSO_GY_ODR_12Hz5)
+            {
+              odr_gy = LSM6DSO_GY_ODR_26Hz;
+            }
+
+            else
+            {
+              odr_gy = val;
+            }
+
+            break;
+
+          case LSM6DSO_ODR_FSM_52Hz:
+            if (val == LSM6DSO_GY_ODR_OFF)
+            {
+              odr_gy = LSM6DSO_GY_ODR_52Hz;
+            }
+
+            else if (val == LSM6DSO_GY_ODR_12Hz5)
+            {
+              odr_gy = LSM6DSO_GY_ODR_52Hz;
+            }
+
+            else if (val == LSM6DSO_GY_ODR_26Hz)
+            {
+              odr_gy = LSM6DSO_GY_ODR_52Hz;
+            }
+
+            else
+            {
+              odr_gy = val;
+            }
+
+            break;
+
+          case LSM6DSO_ODR_FSM_104Hz:
+            if (val == LSM6DSO_GY_ODR_OFF)
+            {
+              odr_gy = LSM6DSO_GY_ODR_104Hz;
+            }
+
+            else if (val == LSM6DSO_GY_ODR_12Hz5)
+            {
+              odr_gy = LSM6DSO_GY_ODR_104Hz;
+            }
+
+            else if (val == LSM6DSO_GY_ODR_26Hz)
+            {
+              odr_gy = LSM6DSO_GY_ODR_104Hz;
+            }
+
+            else if (val == LSM6DSO_GY_ODR_52Hz)
+            {
+              odr_gy = LSM6DSO_GY_ODR_104Hz;
+            }
+
+            else
+            {
+              odr_gy = val;
+            }
+
+            break;
+
+          default:
+            odr_gy = val;
+            break;
+        }
+      }
+    }
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    reg.odr_g = (uint8_t) odr_gy;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Gyroscope UI data rate selection.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of odr_g in reg CTRL2_G
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_gy_data_rate_get(stmdev_ctx_t *ctx,
+                                 lsm6dso_odr_g_t *val)
+{
+  lsm6dso_ctrl2_g_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t *)&reg, 1);
+
+  switch (reg.odr_g)
+  {
+    case LSM6DSO_GY_ODR_OFF:
+      *val = LSM6DSO_GY_ODR_OFF;
+      break;
+
+    case LSM6DSO_GY_ODR_12Hz5:
+      *val = LSM6DSO_GY_ODR_12Hz5;
+      break;
+
+    case LSM6DSO_GY_ODR_26Hz:
+      *val = LSM6DSO_GY_ODR_26Hz;
+      break;
+
+    case LSM6DSO_GY_ODR_52Hz:
+      *val = LSM6DSO_GY_ODR_52Hz;
+      break;
+
+    case LSM6DSO_GY_ODR_104Hz:
+      *val = LSM6DSO_GY_ODR_104Hz;
+      break;
+
+    case LSM6DSO_GY_ODR_208Hz:
+      *val = LSM6DSO_GY_ODR_208Hz;
+      break;
+
+    case LSM6DSO_GY_ODR_417Hz:
+      *val = LSM6DSO_GY_ODR_417Hz;
+      break;
+
+    case LSM6DSO_GY_ODR_833Hz:
+      *val = LSM6DSO_GY_ODR_833Hz;
+      break;
+
+    case LSM6DSO_GY_ODR_1667Hz:
+      *val = LSM6DSO_GY_ODR_1667Hz;
+      break;
+
+    case LSM6DSO_GY_ODR_3333Hz:
+      *val = LSM6DSO_GY_ODR_3333Hz;
+      break;
+
+    case LSM6DSO_GY_ODR_6667Hz:
+      *val = LSM6DSO_GY_ODR_6667Hz;
+      break;
+
+    default:
+      *val = LSM6DSO_GY_ODR_OFF;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Block data update.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of bdu in reg CTRL3_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_ctrl3_c_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.bdu = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Block data update.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of bdu in reg CTRL3_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_ctrl3_c_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
+  *val = reg.bdu;
+
+  return ret;
+}
+
+/**
+  * @brief  Weight of XL user offset bits of registers X_OFS_USR (73h),
+  *         Y_OFS_USR (74h), Z_OFS_USR (75h).[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of usr_off_w in reg CTRL6_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_xl_offset_weight_set(stmdev_ctx_t *ctx,
+                                     lsm6dso_usr_off_w_t val)
+{
+  lsm6dso_ctrl6_c_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.usr_off_w = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief    Weight of XL user offset bits of registers X_OFS_USR (73h),
+  *           Y_OFS_USR (74h), Z_OFS_USR (75h).[get]
+  *
+  * @param    ctx      read / write interface definitions
+  * @param    val      Get the values of usr_off_w in reg CTRL6_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_xl_offset_weight_get(stmdev_ctx_t *ctx,
+                                     lsm6dso_usr_off_w_t *val)
+{
+  lsm6dso_ctrl6_c_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)&reg, 1);
+
+  switch (reg.usr_off_w)
+  {
+    case LSM6DSO_LSb_1mg:
+      *val = LSM6DSO_LSb_1mg;
+      break;
+
+    case LSM6DSO_LSb_16mg:
+      *val = LSM6DSO_LSb_16mg;
+      break;
+
+    default:
+      *val = LSM6DSO_LSb_1mg;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Accelerometer power mode.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of xl_hm_mode in
+  *                               reg CTRL6_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_xl_power_mode_set(stmdev_ctx_t *ctx,
+                                  lsm6dso_xl_hm_mode_t val)
+{
+  lsm6dso_ctrl5_c_t ctrl5_c;
+  lsm6dso_ctrl6_c_t ctrl6_c;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *) &ctrl5_c, 1);
+
+  if (ret == 0)
+  {
+    ctrl5_c.xl_ulp_en = ((uint8_t)val & 0x02U) >> 1;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *) &ctrl5_c, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *) &ctrl6_c, 1);
+  }
+
+  if (ret == 0)
+  {
+    ctrl6_c.xl_hm_mode = (uint8_t)val & 0x01U;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *) &ctrl6_c, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Accelerometer power mode.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of xl_hm_mode in reg CTRL6_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_xl_power_mode_get(stmdev_ctx_t *ctx,
+                                  lsm6dso_xl_hm_mode_t *val)
+{
+  lsm6dso_ctrl5_c_t ctrl5_c;
+  lsm6dso_ctrl6_c_t ctrl6_c;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *) &ctrl5_c, 1);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *) &ctrl6_c, 1);
+
+    switch ((ctrl5_c.xl_ulp_en << 1) | ctrl6_c.xl_hm_mode)
+    {
+      case LSM6DSO_HIGH_PERFORMANCE_MD:
+        *val = LSM6DSO_HIGH_PERFORMANCE_MD;
+        break;
+
+      case LSM6DSO_LOW_NORMAL_POWER_MD:
+        *val = LSM6DSO_LOW_NORMAL_POWER_MD;
+        break;
+
+      case LSM6DSO_ULTRA_LOW_POWER_MD:
+        *val = LSM6DSO_ULTRA_LOW_POWER_MD;
+        break;
+
+      default:
+        *val = LSM6DSO_HIGH_PERFORMANCE_MD;
+        break;
+    }
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Operating mode for gyroscope.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of g_hm_mode in reg CTRL7_G
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_gy_power_mode_set(stmdev_ctx_t *ctx,
+                                  lsm6dso_g_hm_mode_t val)
+{
+  lsm6dso_ctrl7_g_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.g_hm_mode = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Operating mode for gyroscope.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of g_hm_mode in reg CTRL7_G
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_gy_power_mode_get(stmdev_ctx_t *ctx,
+                                  lsm6dso_g_hm_mode_t *val)
+{
+  lsm6dso_ctrl7_g_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)&reg, 1);
+
+  switch (reg.g_hm_mode)
+  {
+    case LSM6DSO_GY_HIGH_PERFORMANCE:
+      *val = LSM6DSO_GY_HIGH_PERFORMANCE;
+      break;
+
+    case LSM6DSO_GY_NORMAL:
+      *val = LSM6DSO_GY_NORMAL;
+      break;
+
+    default:
+      *val = LSM6DSO_GY_HIGH_PERFORMANCE;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  The STATUS_REG register is read by the primary interface.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      register STATUS_REG
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_status_reg_get(stmdev_ctx_t *ctx,
+                               lsm6dso_status_reg_t *val)
+{
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t *) val, 1);
+
+  return ret;
+}
+
+/**
+  * @brief  Accelerometer new data available.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of xlda in reg STATUS_REG
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+                                       uint8_t *val)
+{
+  lsm6dso_status_reg_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t *)&reg, 1);
+  *val = reg.xlda;
+
+  return ret;
+}
+
+/**
+  * @brief  Gyroscope new data available.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of gda in reg STATUS_REG
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+                                       uint8_t *val)
+{
+  lsm6dso_status_reg_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t *)&reg, 1);
+  *val = reg.gda;
+
+  return ret;
+}
+
+/**
+  * @brief  Temperature new data available.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of tda in reg STATUS_REG
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+                                         uint8_t *val)
+{
+  lsm6dso_status_reg_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t *)&reg, 1);
+  *val = reg.tda;
+
+  return ret;
+}
+
+/**
+  * @brief  Accelerometer X-axis user offset correction expressed in
+  *         two's complement, weight depends on USR_OFF_W in CTRL6_C (15h).
+  *         The value must be in the range [-127 127].[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  buff     buffer that contains data to write
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff)
+{
+  int32_t ret;
+
+  ret = lsm6dso_write_reg(ctx, LSM6DSO_X_OFS_USR, buff, 1);
+
+  return ret;
+}
+
+/**
+  * @brief  Accelerometer X-axis user offset correction expressed in two's
+  *         complement, weight depends on USR_OFF_W in CTRL6_C (15h).
+  *         The value must be in the range [-127 127].[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  buff     buffer that stores data read
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff)
+{
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_X_OFS_USR, buff, 1);
+
+  return ret;
+}
+
+/**
+  * @brief  Accelerometer Y-axis user offset correction expressed in two's
+  *         complement, weight depends on USR_OFF_W in CTRL6_C (15h).
+  *         The value must be in the range [-127 127].[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  buff     buffer that contains data to write
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff)
+{
+  int32_t ret;
+
+  ret = lsm6dso_write_reg(ctx, LSM6DSO_Y_OFS_USR, buff, 1);
+
+  return ret;
+}
+
+/**
+  * @brief  Accelerometer Y-axis user offset correction expressed in two's
+  *         complement, weight depends on USR_OFF_W in CTRL6_C (15h).
+  *         The value must be in the range [-127 127].[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  buff     buffer that stores data read
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff)
+{
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_Y_OFS_USR, buff, 1);
+
+  return ret;
+}
+
+/**
+  * @brief  Accelerometer Z-axis user offset correction expressed in two's
+  *         complement, weight depends on USR_OFF_W in CTRL6_C (15h).
+  *         The value must be in the range [-127 127].[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  buff     buffer that contains data to write
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff)
+{
+  int32_t ret;
+
+  ret = lsm6dso_write_reg(ctx, LSM6DSO_Z_OFS_USR, buff, 1);
+
+  return ret;
+}
+
+/**
+  * @brief  Accelerometer Z-axis user offset correction expressed in two's
+  *         complement, weight depends on USR_OFF_W in CTRL6_C (15h).
+  *         The value must be in the range [-127 127].[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  buff     buffer that stores data read
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff)
+{
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_Z_OFS_USR, buff, 1);
+
+  return ret;
+}
+
+/**
+  * @brief  Enables user offset on out.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of usr_off_on_out in reg CTRL7_G
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_ctrl7_g_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.usr_off_on_out = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  User offset on out flag.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      values of usr_off_on_out in reg CTRL7_G
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_ctrl7_g_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)&reg, 1);
+  *val = reg.usr_off_on_out;
+
+  return ret;
+}
+
+/**
+  * @}
+  *
+  */
+
+/**
+  * @defgroup  LSM6DSO_Timestamp
+  * @brief     This section groups all the functions that manage the
+  *            timestamp generation.
+  * @{
+  *
+  */
+
+/**
+  * @brief  Reset timestamp counter.[set]
+  *
+  * @param  ctx    Read / write interface definitions.(ptr)
+  * @retval        Interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_timestamp_rst(stmdev_ctx_t *ctx)
+{
+  uint8_t rst_val = 0xAA;
+  return lsm6dso_write_reg(ctx, LSM6DSO_TIMESTAMP2, &rst_val, 1);
+}
+
+/**
+  * @brief  Enables timestamp counter.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of timestamp_en in reg CTRL10_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_timestamp_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_ctrl10_c_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL10_C, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.timestamp_en = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL10_C, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Enables timestamp counter.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of timestamp_en in reg CTRL10_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_ctrl10_c_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL10_C, (uint8_t *)&reg, 1);
+  *val = reg.timestamp_en;
+
+  return ret;
+}
+
+/**
+  * @brief  Timestamp first data output register (r).
+  *         The value is expressed as a 32-bit word and the bit
+  *         resolution is 25 us.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  buff     buffer that stores data read
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val)
+{
+  uint8_t buff[4];
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_TIMESTAMP0, buff, 4);
+  *val = buff[3];
+  *val = (*val * 256U) +  buff[2];
+  *val = (*val * 256U) +  buff[1];
+  *val = (*val * 256U) +  buff[0];
+
+  return ret;
+}
+
+/**
+  * @}
+  *
+  */
+
+/**
+  * @defgroup  LSM6DSO_Data output
+  * @brief     This section groups all the data output functions.
+  * @{
+  *
+  */
+
+/**
+  * @brief  Circular burst-mode (rounding) read of the output
+  *         registers.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of rounding in reg CTRL5_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_rounding_mode_set(stmdev_ctx_t *ctx,
+                                  lsm6dso_rounding_t val)
+{
+  lsm6dso_ctrl5_c_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.rounding = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Gyroscope UI chain full-scale selection.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of rounding in reg CTRL5_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_rounding_mode_get(stmdev_ctx_t *ctx,
+                                  lsm6dso_rounding_t *val)
+{
+  lsm6dso_ctrl5_c_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)&reg, 1);
+
+  switch (reg.rounding)
+  {
+    case LSM6DSO_NO_ROUND:
+      *val = LSM6DSO_NO_ROUND;
+      break;
+
+    case LSM6DSO_ROUND_XL:
+      *val = LSM6DSO_ROUND_XL;
+      break;
+
+    case LSM6DSO_ROUND_GY:
+      *val = LSM6DSO_ROUND_GY;
+      break;
+
+    case LSM6DSO_ROUND_GY_XL:
+      *val = LSM6DSO_ROUND_GY_XL;
+      break;
+
+    default:
+      *val = LSM6DSO_NO_ROUND;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Temperature data output register (r).
+  *         L and H registers together express a 16-bit word in two's
+  *         complement.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  buff     buffer that stores data read
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
+{
+  uint8_t buff[2];
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_OUT_TEMP_L, buff, 2);
+  val[0] = (int16_t)buff[1];
+  val[0] = (val[0] * 256) + (int16_t)buff[0];
+
+  return ret;
+}
+
+/**
+  * @brief  Angular rate sensor. The value is expressed as a 16-bit
+  *         word in two's complement.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  buff     buffer that stores data read
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val)
+{
+  uint8_t buff[6];
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_OUTX_L_G, buff, 6);
+  val[0] = (int16_t)buff[1];
+  val[0] = (val[0] * 256) + (int16_t)buff[0];
+  val[1] = (int16_t)buff[3];
+  val[1] = (val[1] * 256) + (int16_t)buff[2];
+  val[2] = (int16_t)buff[5];
+  val[2] = (val[2] * 256) + (int16_t)buff[4];
+
+  return ret;
+}
+
+/**
+  * @brief  Linear acceleration output register.
+  *         The value is expressed as a 16-bit word in two's complement.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  buff     buffer that stores data read
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
+{
+  uint8_t buff[6];
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_OUTX_L_A, buff, 6);
+  val[0] = (int16_t)buff[1];
+  val[0] = (val[0] * 256) + (int16_t)buff[0];
+  val[1] = (int16_t)buff[3];
+  val[1] = (val[1] * 256) + (int16_t)buff[2];
+  val[2] = (int16_t)buff[5];
+  val[2] = (val[2] * 256) + (int16_t)buff[4];
+
+  return ret;
+}
+
+/**
+  * @brief  FIFO data output [get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  buff     buffer that stores data read
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
+{
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_DATA_OUT_X_L, buff, 6);
+
+  return ret;
+}
+
+/**
+  * @brief  Step counter output register.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  buff     buffer that stores data read
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_number_of_steps_get(stmdev_ctx_t *ctx, uint16_t *val)
+{
+  uint8_t buff[2];
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_STEP_COUNTER_L, buff, 2);
+  }
+
+  if (ret == 0)
+  {
+    *val = buff[1];
+    *val = (*val * 256U) +  buff[0];
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Reset step counter register.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_steps_reset(stmdev_ctx_t *ctx)
+{
+  lsm6dso_emb_func_src_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_SRC, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    reg.pedo_rst_step = PROPERTY_ENABLE;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_SRC, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @}
+  *
+  */
+
+/**
+  * @defgroup  LSM6DSO_common
+  * @brief   This section groups common useful functions.
+  * @{
+  *
+  */
+
+/**
+  * @brief  Difference in percentage of the effective ODR(and timestamp rate)
+  *         with respect to the typical.
+  *         Step:  0.15%. 8-bit format, 2's complement.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of freq_fine in reg
+  *                      INTERNAL_FREQ_FINE
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_internal_freq_fine_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_INTERNAL_FREQ_FINE,
+                         (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.freq_fine = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_INTERNAL_FREQ_FINE,
+                            (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Difference in percentage of the effective ODR(and timestamp rate)
+  *         with respect to the typical.
+  *         Step:  0.15%. 8-bit format, 2's complement.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of freq_fine in reg INTERNAL_FREQ_FINE
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_internal_freq_fine_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_INTERNAL_FREQ_FINE,
+                         (uint8_t *)&reg, 1);
+  *val = reg.freq_fine;
+
+  return ret;
+}
+
+
+/**
+  * @brief  Enable access to the embedded functions/sensor
+  *         hub configuration registers.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of reg_access in
+  *                               reg FUNC_CFG_ACCESS
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_mem_bank_set(stmdev_ctx_t *ctx,
+                             lsm6dso_reg_access_t val)
+{
+  lsm6dso_func_cfg_access_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.reg_access = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Enable access to the embedded functions/sensor
+  *         hub configuration registers.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of reg_access in
+  *                               reg FUNC_CFG_ACCESS
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_mem_bank_get(stmdev_ctx_t *ctx,
+                             lsm6dso_reg_access_t *val)
+{
+  lsm6dso_func_cfg_access_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS, (uint8_t *)&reg, 1);
+
+  switch (reg.reg_access)
+  {
+    case LSM6DSO_USER_BANK:
+      *val = LSM6DSO_USER_BANK;
+      break;
+
+    case LSM6DSO_SENSOR_HUB_BANK:
+      *val = LSM6DSO_SENSOR_HUB_BANK;
+      break;
+
+    case LSM6DSO_EMBEDDED_FUNC_BANK:
+      *val = LSM6DSO_EMBEDDED_FUNC_BANK;
+      break;
+
+    default:
+      *val = LSM6DSO_USER_BANK;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Write a line(byte) in a page.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  uint8_t address: page line address
+  * @param  val      value to write
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t address,
+                                 uint8_t *val)
+{
+  lsm6dso_page_rw_t page_rw;
+  lsm6dso_page_sel_t page_sel;
+  lsm6dso_page_address_t page_address;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
+  }
+
+  if (ret == 0)
+  {
+    page_rw.page_rw = 0x02; /* page_write enable */
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1);
+  }
+
+  if (ret == 0)
+  {
+    page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU);
+    page_sel.not_used_01 = 1;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1);
+  }
+
+  if (ret == 0)
+  {
+    page_address.page_addr = (uint8_t)address & 0xFFU;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_ADDRESS,
+                            (uint8_t *)&page_address, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_VALUE, val, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
+  }
+
+  if (ret == 0)
+  {
+    page_rw.page_rw = 0x00; /* page_write disable */
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Write buffer in a page.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  uint8_t address: page line address
+  * @param  uint8_t *buf: buffer to write
+  * @param  uint8_t len: buffer len
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address,
+                            uint8_t *buf, uint8_t len)
+{
+  lsm6dso_page_rw_t page_rw;
+  lsm6dso_page_sel_t page_sel;
+  lsm6dso_page_address_t  page_address;
+  uint16_t addr_pointed;
+  int32_t ret;
+
+  uint8_t i ;
+  addr_pointed = address;
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
+  }
+
+  if (ret == 0)
+  {
+    page_rw.page_rw = 0x02; /* page_write enable*/
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1);
+  }
+
+  if (ret == 0)
+  {
+    page_sel.page_sel = ((uint8_t)(addr_pointed >> 8) & 0x0FU);
+    page_sel.not_used_01 = 1;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1);
+  }
+
+  if (ret == 0)
+  {
+    page_address.page_addr = (uint8_t)(addr_pointed & 0x00FFU);
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_ADDRESS,
+                            (uint8_t *)&page_address, 1);
+  }
+
+  if (ret == 0)
+  {
+    for (i = 0; ((i < len) && (ret == 0)); i++)
+    {
+      ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_VALUE, &buf[i], 1);
+      addr_pointed++;
+
+      /* Check if page wrap */
+      if (((addr_pointed % 0x0100U) == 0x00U) && (ret == 0))
+      {
+        ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *)&page_sel, 1);
+
+        if (ret == 0)
+        {
+          page_sel.page_sel = ((uint8_t)(addr_pointed >> 8) & 0x0FU);
+          page_sel.not_used_01 = 1;
+          ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL,
+                                  (uint8_t *)&page_sel, 1);
+        }
+      }
+    }
+
+    page_sel.page_sel = 0;
+    page_sel.not_used_01 = 1;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
+  }
+
+  if (ret == 0)
+  {
+    page_rw.page_rw = 0x00; /* page_write disable */
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Read a line(byte) in a page.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  uint8_t address: page line address
+  * @param  val      read value
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t address,
+                                uint8_t *val)
+{
+  lsm6dso_page_rw_t page_rw;
+  lsm6dso_page_sel_t page_sel;
+  lsm6dso_page_address_t  page_address;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
+  }
+
+  if (ret == 0)
+  {
+    page_rw.page_rw = 0x01; /* page_read enable*/
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1);
+  }
+
+  if (ret == 0)
+  {
+    page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU);
+    page_sel.not_used_01 = 1;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1);
+  }
+
+  if (ret == 0)
+  {
+    page_address.page_addr = (uint8_t)address & 0x00FFU;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_ADDRESS,
+                            (uint8_t *)&page_address, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_VALUE, val, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
+  }
+
+  if (ret == 0)
+  {
+    page_rw.page_rw = 0x00; /* page_read disable */
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Data-ready pulsed / letched mode.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of
+  *                                     dataready_pulsed in
+  *                                     reg COUNTER_BDR_REG1
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_data_ready_mode_set(stmdev_ctx_t *ctx,
+                                    lsm6dso_dataready_pulsed_t val)
+{
+  lsm6dso_counter_bdr_reg1_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.dataready_pulsed = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1,
+                            (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Data-ready pulsed / letched mode.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of
+  *                                     dataready_pulsed in
+  *                                     reg COUNTER_BDR_REG1
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_data_ready_mode_get(stmdev_ctx_t *ctx,
+                                    lsm6dso_dataready_pulsed_t *val)
+{
+  lsm6dso_counter_bdr_reg1_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)&reg, 1);
+
+  switch (reg.dataready_pulsed)
+  {
+    case LSM6DSO_DRDY_LATCHED:
+      *val = LSM6DSO_DRDY_LATCHED;
+      break;
+
+    case LSM6DSO_DRDY_PULSED:
+      *val = LSM6DSO_DRDY_PULSED;
+      break;
+
+    default:
+      *val = LSM6DSO_DRDY_LATCHED;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Device "Who am I".[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  buff     buffer that stores data read
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
+{
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_WHO_AM_I, buff, 1);
+
+  return ret;
+}
+
+/**
+  * @brief  Software reset. Restore the default values
+  *         in user registers[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of sw_reset in reg CTRL3_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_reset_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_ctrl3_c_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.sw_reset = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Software reset. Restore the default values in user registers.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of sw_reset in reg CTRL3_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_ctrl3_c_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
+  *val = reg.sw_reset;
+
+  return ret;
+}
+
+/**
+  * @brief  Register address automatically incremented during a multiple byte
+  *         access with a serial interface.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of if_inc in reg CTRL3_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_ctrl3_c_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.if_inc = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Register address automatically incremented during a multiple byte
+  *         access with a serial interface.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of if_inc in reg CTRL3_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_ctrl3_c_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
+  *val = reg.if_inc;
+
+  return ret;
+}
+
+/**
+  * @brief  Reboot memory content. Reload the calibration parameters.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of boot in reg CTRL3_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_boot_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_ctrl3_c_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.boot = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Reboot memory content. Reload the calibration parameters.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of boot in reg CTRL3_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_ctrl3_c_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
+  *val = reg.boot;
+
+  return ret;
+}
+
+/**
+  * @brief  Linear acceleration sensor self-test enable.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of st_xl in reg CTRL5_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_xl_self_test_set(stmdev_ctx_t *ctx,
+                                 lsm6dso_st_xl_t val)
+{
+  lsm6dso_ctrl5_c_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.st_xl = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Linear acceleration sensor self-test enable.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of st_xl in reg CTRL5_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_xl_self_test_get(stmdev_ctx_t *ctx,
+                                 lsm6dso_st_xl_t *val)
+{
+  lsm6dso_ctrl5_c_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)&reg, 1);
+
+  switch (reg.st_xl)
+  {
+    case LSM6DSO_XL_ST_DISABLE:
+      *val = LSM6DSO_XL_ST_DISABLE;
+      break;
+
+    case LSM6DSO_XL_ST_POSITIVE:
+      *val = LSM6DSO_XL_ST_POSITIVE;
+      break;
+
+    case LSM6DSO_XL_ST_NEGATIVE:
+      *val = LSM6DSO_XL_ST_NEGATIVE;
+      break;
+
+    default:
+      *val = LSM6DSO_XL_ST_DISABLE;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Angular rate sensor self-test enable.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of st_g in reg CTRL5_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_gy_self_test_set(stmdev_ctx_t *ctx,
+                                 lsm6dso_st_g_t val)
+{
+  lsm6dso_ctrl5_c_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.st_g = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Angular rate sensor self-test enable.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of st_g in reg CTRL5_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_gy_self_test_get(stmdev_ctx_t *ctx,
+                                 lsm6dso_st_g_t *val)
+{
+  lsm6dso_ctrl5_c_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)&reg, 1);
+
+  switch (reg.st_g)
+  {
+    case LSM6DSO_GY_ST_DISABLE:
+      *val = LSM6DSO_GY_ST_DISABLE;
+      break;
+
+    case LSM6DSO_GY_ST_POSITIVE:
+      *val = LSM6DSO_GY_ST_POSITIVE;
+      break;
+
+    case LSM6DSO_GY_ST_NEGATIVE:
+      *val = LSM6DSO_GY_ST_NEGATIVE;
+      break;
+
+    default:
+      *val = LSM6DSO_GY_ST_DISABLE;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @}
+  *
+  */
+
+/**
+  * @defgroup  LSM6DSO_filters
+  * @brief     This section group all the functions concerning the
+  *            filters configuration
+  * @{
+  *
+  */
+
+/**
+  * @brief  Accelerometer output from LPF2 filtering stage selection.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of lpf2_xl_en in reg CTRL1_XL
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_ctrl1_xl_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.lpf2_xl_en = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Accelerometer output from LPF2 filtering stage selection.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of lpf2_xl_en in reg CTRL1_XL
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_ctrl1_xl_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)&reg, 1);
+  *val = reg.lpf2_xl_en;
+
+  return ret;
+}
+
+/**
+  * @brief  Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
+  *         the bandwidth can be selected through FTYPE [2:0]
+  *         in CTRL6_C (15h).[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of lpf1_sel_g in reg CTRL4_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_ctrl4_c_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.lpf1_sel_g = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
+  *         the bandwidth can be selected through FTYPE [2:0]
+  *         in CTRL6_C (15h).[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of lpf1_sel_g in reg CTRL4_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_ctrl4_c_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&reg, 1);
+  *val = reg.lpf1_sel_g;
+
+  return ret;
+}
+
+/**
+  * @brief  Mask DRDY on pin (both XL & Gyro) until filter settling ends
+  *         (XL and Gyro independently masked).[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of drdy_mask in reg CTRL4_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_filter_settling_mask_set(stmdev_ctx_t *ctx,
+                                         uint8_t val)
+{
+  lsm6dso_ctrl4_c_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.drdy_mask = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Mask DRDY on pin (both XL & Gyro) until filter settling ends
+  *         (XL and Gyro independently masked).[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of drdy_mask in reg CTRL4_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_filter_settling_mask_get(stmdev_ctx_t *ctx,
+                                         uint8_t *val)
+{
+  lsm6dso_ctrl4_c_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&reg, 1);
+  *val = reg.drdy_mask;
+
+  return ret;
+}
+
+/**
+  * @brief  Gyroscope lp1 bandwidth.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of ftype in reg CTRL6_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
+                                     lsm6dso_ftype_t val)
+{
+  lsm6dso_ctrl6_c_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.ftype = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Gyroscope lp1 bandwidth.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val       Get the values of ftype in reg CTRL6_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
+                                     lsm6dso_ftype_t *val)
+{
+  lsm6dso_ctrl6_c_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)&reg, 1);
+
+  switch (reg.ftype)
+  {
+    case LSM6DSO_ULTRA_LIGHT:
+      *val = LSM6DSO_ULTRA_LIGHT;
+      break;
+
+    case LSM6DSO_VERY_LIGHT:
+      *val = LSM6DSO_VERY_LIGHT;
+      break;
+
+    case LSM6DSO_LIGHT:
+      *val = LSM6DSO_LIGHT;
+      break;
+
+    case LSM6DSO_MEDIUM:
+      *val = LSM6DSO_MEDIUM;
+      break;
+
+    case LSM6DSO_STRONG:
+      *val = LSM6DSO_STRONG;
+      break;
+
+    case LSM6DSO_VERY_STRONG:
+      *val = LSM6DSO_VERY_STRONG;
+      break;
+
+    case LSM6DSO_AGGRESSIVE:
+      *val = LSM6DSO_AGGRESSIVE;
+      break;
+
+    case LSM6DSO_XTREME:
+      *val = LSM6DSO_XTREME;
+      break;
+
+    default:
+      *val = LSM6DSO_ULTRA_LIGHT;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Low pass filter 2 on 6D function selection.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of low_pass_on_6d in reg CTRL8_XL
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_ctrl8_xl_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.low_pass_on_6d = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Low pass filter 2 on 6D function selection.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of low_pass_on_6d in reg CTRL8_XL
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_ctrl8_xl_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)&reg, 1);
+  *val = reg.low_pass_on_6d;
+
+  return ret;
+}
+
+/**
+  * @brief  Accelerometer slope filter / high-pass filter selection
+  *         on output.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of hp_slope_xl_en
+  *                                   in reg CTRL8_XL
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_xl_hp_path_on_out_set(stmdev_ctx_t *ctx,
+                                      lsm6dso_hp_slope_xl_en_t val)
+{
+  lsm6dso_ctrl8_xl_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.hp_slope_xl_en = ((uint8_t)val & 0x10U) >> 4;
+    reg.hp_ref_mode_xl = ((uint8_t)val & 0x20U) >> 5;
+    reg.hpcf_xl = (uint8_t)val & 0x07U;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Accelerometer slope filter / high-pass filter selection
+  *         on output.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of hp_slope_xl_en
+  *                                   in reg CTRL8_XL
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_xl_hp_path_on_out_get(stmdev_ctx_t *ctx,
+                                      lsm6dso_hp_slope_xl_en_t *val)
+{
+  lsm6dso_ctrl8_xl_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)&reg, 1);
+
+  switch ((reg.hp_ref_mode_xl << 5) | (reg.hp_slope_xl_en << 4) |
+          reg.hpcf_xl)
+  {
+    case LSM6DSO_HP_PATH_DISABLE_ON_OUT:
+      *val = LSM6DSO_HP_PATH_DISABLE_ON_OUT;
+      break;
+
+    case LSM6DSO_SLOPE_ODR_DIV_4:
+      *val = LSM6DSO_SLOPE_ODR_DIV_4;
+      break;
+
+    case LSM6DSO_HP_ODR_DIV_10:
+      *val = LSM6DSO_HP_ODR_DIV_10;
+      break;
+
+    case LSM6DSO_HP_ODR_DIV_20:
+      *val = LSM6DSO_HP_ODR_DIV_20;
+      break;
+
+    case LSM6DSO_HP_ODR_DIV_45:
+      *val = LSM6DSO_HP_ODR_DIV_45;
+      break;
+
+    case LSM6DSO_HP_ODR_DIV_100:
+      *val = LSM6DSO_HP_ODR_DIV_100;
+      break;
+
+    case LSM6DSO_HP_ODR_DIV_200:
+      *val = LSM6DSO_HP_ODR_DIV_200;
+      break;
+
+    case LSM6DSO_HP_ODR_DIV_400:
+      *val = LSM6DSO_HP_ODR_DIV_400;
+      break;
+
+    case LSM6DSO_HP_ODR_DIV_800:
+      *val = LSM6DSO_HP_ODR_DIV_800;
+      break;
+
+    case LSM6DSO_HP_REF_MD_ODR_DIV_10:
+      *val = LSM6DSO_HP_REF_MD_ODR_DIV_10;
+      break;
+
+    case LSM6DSO_HP_REF_MD_ODR_DIV_20:
+      *val = LSM6DSO_HP_REF_MD_ODR_DIV_20;
+      break;
+
+    case LSM6DSO_HP_REF_MD_ODR_DIV_45:
+      *val = LSM6DSO_HP_REF_MD_ODR_DIV_45;
+      break;
+
+    case LSM6DSO_HP_REF_MD_ODR_DIV_100:
+      *val = LSM6DSO_HP_REF_MD_ODR_DIV_100;
+      break;
+
+    case LSM6DSO_HP_REF_MD_ODR_DIV_200:
+      *val = LSM6DSO_HP_REF_MD_ODR_DIV_200;
+      break;
+
+    case LSM6DSO_HP_REF_MD_ODR_DIV_400:
+      *val = LSM6DSO_HP_REF_MD_ODR_DIV_400;
+      break;
+
+    case LSM6DSO_HP_REF_MD_ODR_DIV_800:
+      *val = LSM6DSO_HP_REF_MD_ODR_DIV_800;
+      break;
+
+    case LSM6DSO_LP_ODR_DIV_10:
+      *val = LSM6DSO_LP_ODR_DIV_10;
+      break;
+
+    case LSM6DSO_LP_ODR_DIV_20:
+      *val = LSM6DSO_LP_ODR_DIV_20;
+      break;
+
+    case LSM6DSO_LP_ODR_DIV_45:
+      *val = LSM6DSO_LP_ODR_DIV_45;
+      break;
+
+    case LSM6DSO_LP_ODR_DIV_100:
+      *val = LSM6DSO_LP_ODR_DIV_100;
+      break;
+
+    case LSM6DSO_LP_ODR_DIV_200:
+      *val = LSM6DSO_LP_ODR_DIV_200;
+      break;
+
+    case LSM6DSO_LP_ODR_DIV_400:
+      *val = LSM6DSO_LP_ODR_DIV_400;
+      break;
+
+    case LSM6DSO_LP_ODR_DIV_800:
+      *val = LSM6DSO_LP_ODR_DIV_800;
+      break;
+
+    default:
+      *val = LSM6DSO_HP_PATH_DISABLE_ON_OUT;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Enables accelerometer LPF2 and HPF fast-settling mode.
+  *         The filter sets the second samples after writing this bit.
+  *         Active only during device exit from power-down mode.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of fastsettl_mode_xl in
+  *                  reg CTRL8_XL
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_ctrl8_xl_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.fastsettl_mode_xl = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Enables accelerometer LPF2 and HPF fast-settling mode.
+  *         The filter sets the second samples after writing this bit.
+  *         Active only during device exit from power-down mode.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of fastsettl_mode_xl in reg CTRL8_XL
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_ctrl8_xl_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)&reg, 1);
+  *val = reg.fastsettl_mode_xl;
+
+  return ret;
+}
+
+/**
+  * @brief  HPF or SLOPE filter selection on wake-up and Activity/Inactivity
+  *         functions.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of slope_fds in reg TAP_CFG0
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
+                                        lsm6dso_slope_fds_t val)
+{
+  lsm6dso_tap_cfg0_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.slope_fds = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  HPF or SLOPE filter selection on wake-up and Activity/Inactivity
+  *         functions.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of slope_fds in reg TAP_CFG0
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
+                                        lsm6dso_slope_fds_t *val)
+{
+  lsm6dso_tap_cfg0_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)&reg, 1);
+
+  switch (reg.slope_fds)
+  {
+    case LSM6DSO_USE_SLOPE:
+      *val = LSM6DSO_USE_SLOPE;
+      break;
+
+    case LSM6DSO_USE_HPF:
+      *val = LSM6DSO_USE_HPF;
+      break;
+
+    default:
+      *val = LSM6DSO_USE_SLOPE;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Enables gyroscope digital high-pass filter. The filter is
+  *         enabled only if the gyro is in HP mode.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of hp_en_g and hp_en_g
+  *                            in reg CTRL7_G
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_gy_hp_path_internal_set(stmdev_ctx_t *ctx,
+                                        lsm6dso_hpm_g_t val)
+{
+  lsm6dso_ctrl7_g_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.hp_en_g = ((uint8_t)val & 0x80U) >> 7;
+    reg.hpm_g = (uint8_t)val & 0x03U;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Enables gyroscope digital high-pass filter. The filter is
+  *         enabled only if the gyro is in HP mode.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of hp_en_g and hp_en_g
+  *                            in reg CTRL7_G
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_gy_hp_path_internal_get(stmdev_ctx_t *ctx,
+                                        lsm6dso_hpm_g_t *val)
+{
+  lsm6dso_ctrl7_g_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)&reg, 1);
+
+  switch ((reg.hp_en_g << 7) + reg.hpm_g)
+  {
+    case LSM6DSO_HP_FILTER_NONE:
+      *val = LSM6DSO_HP_FILTER_NONE;
+      break;
+
+    case LSM6DSO_HP_FILTER_16mHz:
+      *val = LSM6DSO_HP_FILTER_16mHz;
+      break;
+
+    case LSM6DSO_HP_FILTER_65mHz:
+      *val = LSM6DSO_HP_FILTER_65mHz;
+      break;
+
+    case LSM6DSO_HP_FILTER_260mHz:
+      *val = LSM6DSO_HP_FILTER_260mHz;
+      break;
+
+    case LSM6DSO_HP_FILTER_1Hz04:
+      *val = LSM6DSO_HP_FILTER_1Hz04;
+      break;
+
+    default:
+      *val = LSM6DSO_HP_FILTER_NONE;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @}
+  *
+  */
+
+/**
+  * @defgroup  LSM6DSO_ Auxiliary_interface
+  * @brief     This section groups all the functions concerning
+  *            auxiliary interface.
+  * @{
+  *
+  */
+
+/**
+  * @brief  aOn auxiliary interface connect/disconnect SDO and OCS
+  *         internal pull-up.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of ois_pu_dis in
+  *                               reg PIN_CTRL
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx,
+                                     lsm6dso_ois_pu_dis_t val)
+{
+  lsm6dso_pin_ctrl_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.ois_pu_dis = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  On auxiliary interface connect/disconnect SDO and OCS
+  *         internal pull-up.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of ois_pu_dis in reg PIN_CTRL
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx,
+                                     lsm6dso_ois_pu_dis_t *val)
+{
+  lsm6dso_pin_ctrl_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)&reg, 1);
+
+  switch (reg.ois_pu_dis)
+  {
+    case LSM6DSO_AUX_PULL_UP_DISC:
+      *val = LSM6DSO_AUX_PULL_UP_DISC;
+      break;
+
+    case LSM6DSO_AUX_PULL_UP_CONNECT:
+      *val = LSM6DSO_AUX_PULL_UP_CONNECT;
+      break;
+
+    default:
+      *val = LSM6DSO_AUX_PULL_UP_DISC;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  OIS chain on aux interface power on mode.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of ois_on in reg CTRL7_G
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx,
+                                   lsm6dso_ois_on_t val)
+{
+  lsm6dso_ctrl7_g_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.ois_on_en = (uint8_t)val & 0x01U;
+    reg.ois_on = (uint8_t)val & 0x01U;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  aux_pw_on_ctrl: [get]  OIS chain on aux interface power on mode
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of ois_on in reg CTRL7_G
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx,
+                                   lsm6dso_ois_on_t *val)
+{
+  lsm6dso_ctrl7_g_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)&reg, 1);
+
+  switch (reg.ois_on)
+  {
+    case LSM6DSO_AUX_ON:
+      *val = LSM6DSO_AUX_ON;
+      break;
+
+    case LSM6DSO_AUX_ON_BY_AUX_INTERFACE:
+      *val = LSM6DSO_AUX_ON_BY_AUX_INTERFACE;
+      break;
+
+    default:
+      *val = LSM6DSO_AUX_ON;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Accelerometer full-scale management between UI chain and
+  *         OIS chain. When XL UI is on, the full scale is the same
+  *         between UI/OIS and is chosen by the UI CTRL registers;
+  *         when XL UI is in PD, the OIS can choose the FS.
+  *         Full scales are independent between the UI/OIS chain
+  *         but both bound to 8 g.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of xl_fs_mode in
+  *                               reg CTRL8_XL
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_aux_xl_fs_mode_set(stmdev_ctx_t *ctx,
+                                   lsm6dso_xl_fs_mode_t val)
+{
+  lsm6dso_ctrl8_xl_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.xl_fs_mode = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Accelerometer full-scale management between UI chain and
+  *         OIS chain. When XL UI is on, the full scale is the same
+  *         between UI/OIS and is chosen by the UI CTRL registers;
+  *         when XL UI is in PD, the OIS can choose the FS.
+  *         Full scales are independent between the UI/OIS chain
+  *         but both bound to 8 g.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of xl_fs_mode in reg CTRL8_XL
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_aux_xl_fs_mode_get(stmdev_ctx_t *ctx,
+                                   lsm6dso_xl_fs_mode_t *val)
+{
+  lsm6dso_ctrl8_xl_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)&reg, 1);
+
+  switch (reg.xl_fs_mode)
+  {
+    case LSM6DSO_USE_SAME_XL_FS:
+      *val = LSM6DSO_USE_SAME_XL_FS;
+      break;
+
+    case LSM6DSO_USE_DIFFERENT_XL_FS:
+      *val = LSM6DSO_USE_DIFFERENT_XL_FS;
+      break;
+
+    default:
+      *val = LSM6DSO_USE_SAME_XL_FS;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  The STATUS_SPIAux register is read by the auxiliary SPI.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  lsm6dso_status_spiaux_t: registers STATUS_SPIAUX
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_aux_status_reg_get(stmdev_ctx_t *ctx,
+                                   lsm6dso_status_spiaux_t *val)
+{
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t *) val, 1);
+
+  return ret;
+}
+
+/**
+  * @brief  aux_xl_flag_data_ready: [get]  AUX accelerometer data available
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of xlda in reg STATUS_SPIAUX
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+                                           uint8_t *val)
+{
+  lsm6dso_status_spiaux_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t *)&reg, 1);
+  *val = reg.xlda;
+
+  return ret;
+}
+
+/**
+  * @brief  aux_gy_flag_data_ready: [get]  AUX gyroscope data available.
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of gda in reg STATUS_SPIAUX
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+                                           uint8_t *val)
+{
+  lsm6dso_status_spiaux_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t *)&reg, 1);
+  *val = reg.gda;
+
+  return ret;
+}
+
+/**
+  * @brief  High when the gyroscope output is in the settling phase.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of gyro_settling in reg STATUS_SPIAUX
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_aux_gy_flag_settling_get(stmdev_ctx_t *ctx,
+                                         uint8_t *val)
+{
+  lsm6dso_status_spiaux_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t *)&reg, 1);
+  *val = reg.gyro_settling;
+
+  return ret;
+}
+
+/**
+  * @brief  Selects accelerometer self-test. Effective only if XL OIS
+  *         chain is enabled.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of st_xl_ois in reg INT_OIS
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_aux_xl_self_test_set(stmdev_ctx_t *ctx,
+                                     lsm6dso_st_xl_ois_t val)
+{
+  lsm6dso_int_ois_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.st_xl_ois = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Selects accelerometer self-test. Effective only if XL OIS
+  *         chain is enabled.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of st_xl_ois in reg INT_OIS
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_aux_xl_self_test_get(stmdev_ctx_t *ctx,
+                                     lsm6dso_st_xl_ois_t *val)
+{
+  lsm6dso_int_ois_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)&reg, 1);
+
+  switch (reg.st_xl_ois)
+  {
+    case LSM6DSO_AUX_XL_DISABLE:
+      *val = LSM6DSO_AUX_XL_DISABLE;
+      break;
+
+    case LSM6DSO_AUX_XL_POS:
+      *val = LSM6DSO_AUX_XL_POS;
+      break;
+
+    case LSM6DSO_AUX_XL_NEG:
+      *val = LSM6DSO_AUX_XL_NEG;
+      break;
+
+    default:
+      *val = LSM6DSO_AUX_XL_DISABLE;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Indicates polarity of DEN signal on OIS chain.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of den_lh_ois in
+  *                  reg INT_OIS
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_aux_den_polarity_set(stmdev_ctx_t *ctx,
+                                     lsm6dso_den_lh_ois_t val)
+{
+  lsm6dso_int_ois_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.den_lh_ois = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Indicates polarity of DEN signal on OIS chain.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of den_lh_ois in reg INT_OIS
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_aux_den_polarity_get(stmdev_ctx_t *ctx,
+                                     lsm6dso_den_lh_ois_t *val)
+{
+  lsm6dso_int_ois_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)&reg, 1);
+
+  switch (reg.den_lh_ois)
+  {
+    case LSM6DSO_AUX_DEN_ACTIVE_LOW:
+      *val = LSM6DSO_AUX_DEN_ACTIVE_LOW;
+      break;
+
+    case LSM6DSO_AUX_DEN_ACTIVE_HIGH:
+      *val = LSM6DSO_AUX_DEN_ACTIVE_HIGH;
+      break;
+
+    default:
+      *val = LSM6DSO_AUX_DEN_ACTIVE_LOW;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Configure DEN mode on the OIS chain.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of lvl2_ois in reg INT_OIS
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_aux_den_mode_set(stmdev_ctx_t *ctx,
+                                 lsm6dso_lvl2_ois_t val)
+{
+  lsm6dso_ctrl1_ois_t ctrl1_ois;
+  lsm6dso_int_ois_t int_ois;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *) &int_ois, 1);
+
+  if (ret == 0)
+  {
+    int_ois.lvl2_ois = (uint8_t)val & 0x01U;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *) &int_ois, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *) &ctrl1_ois, 1);
+  }
+
+  if (ret == 0)
+  {
+    ctrl1_ois.lvl1_ois = ((uint8_t)val & 0x02U) >> 1;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS,
+                            (uint8_t *) &ctrl1_ois, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Configure DEN mode on the OIS chain.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of lvl2_ois in reg INT_OIS
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_aux_den_mode_get(stmdev_ctx_t *ctx,
+                                 lsm6dso_lvl2_ois_t *val)
+{
+  lsm6dso_ctrl1_ois_t ctrl1_ois;
+  lsm6dso_int_ois_t int_ois;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *) &int_ois, 1);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *) &ctrl1_ois, 1);
+
+    switch ((ctrl1_ois.lvl1_ois << 1) + int_ois.lvl2_ois)
+    {
+      case LSM6DSO_AUX_DEN_DISABLE:
+        *val = LSM6DSO_AUX_DEN_DISABLE;
+        break;
+
+      case LSM6DSO_AUX_DEN_LEVEL_LATCH:
+        *val = LSM6DSO_AUX_DEN_LEVEL_LATCH;
+        break;
+
+      case LSM6DSO_AUX_DEN_LEVEL_TRIG:
+        *val = LSM6DSO_AUX_DEN_LEVEL_TRIG;
+        break;
+
+      default:
+        *val = LSM6DSO_AUX_DEN_DISABLE;
+        break;
+    }
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Enables/Disable OIS chain DRDY on INT2 pin.
+  *         This setting has priority over all other INT2 settings.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of int2_drdy_ois in reg INT_OIS
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_int_ois_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.int2_drdy_ois = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Enables/Disable OIS chain DRDY on INT2 pin.
+  *         This setting has priority over all other INT2 settings.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of int2_drdy_ois in reg INT_OIS
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_int_ois_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)&reg, 1);
+  *val = reg.int2_drdy_ois;
+
+  return ret;
+}
+
+/**
+  * @brief  Enables OIS chain data processing for gyro in Mode 3 and Mode 4
+  *         (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1).
+  *         When the OIS chain is enabled, the OIS outputs are available
+  *         through the SPI2 in registers OUTX_L_G (22h) through
+  *         OUTZ_H_G (27h) and STATUS_REG (1Eh) / STATUS_SPIAux, and
+  *         LPF1 is dedicated to this chain.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of ois_en_spi2 in
+  *                                reg CTRL1_OIS
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_aux_mode_set(stmdev_ctx_t *ctx,
+                             lsm6dso_ois_en_spi2_t val)
+{
+  lsm6dso_ctrl1_ois_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.ois_en_spi2 = (uint8_t)val & 0x01U;
+    reg.mode4_en = ((uint8_t)val & 0x02U) >> 1;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Enables OIS chain data processing for gyro in Mode 3 and Mode 4
+  *         (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1).
+  *         When the OIS chain is enabled, the OIS outputs are available
+  *         through the SPI2 in registers OUTX_L_G (22h) through
+  *         OUTZ_H_G (27h) and STATUS_REG (1Eh) / STATUS_SPIAux, and
+  *         LPF1 is dedicated to this chain.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of ois_en_spi2 in
+  *                                reg CTRL1_OIS
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_aux_mode_get(stmdev_ctx_t *ctx,
+                             lsm6dso_ois_en_spi2_t *val)
+{
+  lsm6dso_ctrl1_ois_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)&reg, 1);
+
+  switch ((reg.mode4_en << 1) | reg.ois_en_spi2)
+  {
+    case LSM6DSO_AUX_DISABLE:
+      *val = LSM6DSO_AUX_DISABLE;
+      break;
+
+    case LSM6DSO_MODE_3_GY:
+      *val = LSM6DSO_MODE_3_GY;
+      break;
+
+    case LSM6DSO_MODE_4_GY_XL:
+      *val = LSM6DSO_MODE_4_GY_XL;
+      break;
+
+    default:
+      *val = LSM6DSO_AUX_DISABLE;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Selects gyroscope OIS chain full-scale.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of fs_g_ois in reg CTRL1_OIS
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_aux_gy_full_scale_set(stmdev_ctx_t *ctx,
+                                      lsm6dso_fs_g_ois_t val)
+{
+  lsm6dso_ctrl1_ois_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.fs_g_ois = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Selects gyroscope OIS chain full-scale.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of fs_g_ois in reg CTRL1_OIS
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_aux_gy_full_scale_get(stmdev_ctx_t *ctx,
+                                      lsm6dso_fs_g_ois_t *val)
+{
+  lsm6dso_ctrl1_ois_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)&reg, 1);
+
+  switch (reg.fs_g_ois)
+  {
+    case LSM6DSO_250dps_AUX:
+      *val = LSM6DSO_250dps_AUX;
+      break;
+
+    case LSM6DSO_125dps_AUX:
+      *val = LSM6DSO_125dps_AUX;
+      break;
+
+    case LSM6DSO_500dps_AUX:
+      *val = LSM6DSO_500dps_AUX;
+      break;
+
+    case LSM6DSO_1000dps_AUX:
+      *val = LSM6DSO_1000dps_AUX;
+      break;
+
+    case LSM6DSO_2000dps_AUX:
+      *val = LSM6DSO_2000dps_AUX;
+      break;
+
+    default:
+      *val = LSM6DSO_250dps_AUX;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  SPI2 3- or 4-wire interface.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of sim_ois in reg CTRL1_OIS
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_aux_spi_mode_set(stmdev_ctx_t *ctx,
+                                 lsm6dso_sim_ois_t val)
+{
+  lsm6dso_ctrl1_ois_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.sim_ois = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  SPI2 3- or 4-wire interface.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of sim_ois in reg CTRL1_OIS
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_aux_spi_mode_get(stmdev_ctx_t *ctx,
+                                 lsm6dso_sim_ois_t *val)
+{
+  lsm6dso_ctrl1_ois_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)&reg, 1);
+
+  switch (reg.sim_ois)
+  {
+    case LSM6DSO_AUX_SPI_4_WIRE:
+      *val = LSM6DSO_AUX_SPI_4_WIRE;
+      break;
+
+    case LSM6DSO_AUX_SPI_3_WIRE:
+      *val = LSM6DSO_AUX_SPI_3_WIRE;
+      break;
+
+    default:
+      *val = LSM6DSO_AUX_SPI_4_WIRE;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Selects gyroscope digital LPF1 filter bandwidth.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of ftype_ois in
+  *                              reg CTRL2_OIS
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
+                                         lsm6dso_ftype_ois_t val)
+{
+  lsm6dso_ctrl2_ois_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.ftype_ois = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Selects gyroscope digital LPF1 filter bandwidth.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of ftype_ois in reg CTRL2_OIS
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
+                                         lsm6dso_ftype_ois_t *val)
+{
+  lsm6dso_ctrl2_ois_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t *)&reg, 1);
+
+  switch (reg.ftype_ois)
+  {
+    case LSM6DSO_351Hz39:
+      *val = LSM6DSO_351Hz39;
+      break;
+
+    case LSM6DSO_236Hz63:
+      *val = LSM6DSO_236Hz63;
+      break;
+
+    case LSM6DSO_172Hz70:
+      *val = LSM6DSO_172Hz70;
+      break;
+
+    case LSM6DSO_937Hz91:
+      *val = LSM6DSO_937Hz91;
+      break;
+
+    default:
+      *val = LSM6DSO_351Hz39;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Selects gyroscope OIS chain digital high-pass filter cutoff.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of hpm_ois in reg CTRL2_OIS
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx,
+                                        lsm6dso_hpm_ois_t val)
+{
+  lsm6dso_ctrl2_ois_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.hpm_ois = (uint8_t)val & 0x03U;
+    reg.hp_en_ois = ((uint8_t)val & 0x10U) >> 4;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Selects gyroscope OIS chain digital high-pass filter cutoff.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of hpm_ois in reg CTRL2_OIS
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx,
+                                        lsm6dso_hpm_ois_t *val)
+{
+  lsm6dso_ctrl2_ois_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t *)&reg, 1);
+
+  switch ((reg.hp_en_ois << 4) | reg.hpm_ois)
+  {
+    case LSM6DSO_AUX_HP_DISABLE:
+      *val = LSM6DSO_AUX_HP_DISABLE;
+      break;
+
+    case LSM6DSO_AUX_HP_Hz016:
+      *val = LSM6DSO_AUX_HP_Hz016;
+      break;
+
+    case LSM6DSO_AUX_HP_Hz065:
+      *val = LSM6DSO_AUX_HP_Hz065;
+      break;
+
+    case LSM6DSO_AUX_HP_Hz260:
+      *val = LSM6DSO_AUX_HP_Hz260;
+      break;
+
+    case LSM6DSO_AUX_HP_1Hz040:
+      *val = LSM6DSO_AUX_HP_1Hz040;
+      break;
+
+    default:
+      *val = LSM6DSO_AUX_HP_DISABLE;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Enable / Disables OIS chain clamp.
+  *         Enable: All OIS chain outputs = 8000h
+  *         during self-test; Disable: OIS chain self-test
+  *         outputs dependent from the aux gyro full
+  *         scale selected.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of st_ois_clampdis in
+  *                                    reg CTRL3_OIS
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_aux_gy_clamp_set(stmdev_ctx_t *ctx,
+                                 lsm6dso_st_ois_clampdis_t val)
+{
+  lsm6dso_ctrl3_ois_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.st_ois_clampdis = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Enable / Disables OIS chain clamp.
+  *         Enable: All OIS chain outputs = 8000h
+  *         during self-test; Disable: OIS chain self-test
+  *         outputs dependent from the aux gyro full
+  *         scale selected.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of st_ois_clampdis in
+  *                                    reg CTRL3_OIS
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_aux_gy_clamp_get(stmdev_ctx_t *ctx,
+                                 lsm6dso_st_ois_clampdis_t *val)
+{
+  lsm6dso_ctrl3_ois_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)&reg, 1);
+
+  switch (reg.st_ois_clampdis)
+  {
+    case LSM6DSO_ENABLE_CLAMP:
+      *val = LSM6DSO_ENABLE_CLAMP;
+      break;
+
+    case LSM6DSO_DISABLE_CLAMP:
+      *val = LSM6DSO_DISABLE_CLAMP;
+      break;
+
+    default:
+      *val = LSM6DSO_ENABLE_CLAMP;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Selects gyroscope OIS chain self-test.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of st_ois in reg CTRL3_OIS
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_aux_gy_self_test_set(stmdev_ctx_t *ctx,
+                                     lsm6dso_st_ois_t val)
+{
+  lsm6dso_ctrl3_ois_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.st_ois = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Selects gyroscope OIS chain self-test.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of st_ois in reg CTRL3_OIS
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_aux_gy_self_test_get(stmdev_ctx_t *ctx,
+                                     lsm6dso_st_ois_t *val)
+{
+  lsm6dso_ctrl3_ois_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)&reg, 1);
+
+  switch (reg.st_ois)
+  {
+    case LSM6DSO_AUX_GY_DISABLE:
+      *val = LSM6DSO_AUX_GY_DISABLE;
+      break;
+
+    case LSM6DSO_AUX_GY_POS:
+      *val = LSM6DSO_AUX_GY_POS;
+      break;
+
+    case LSM6DSO_AUX_GY_NEG:
+      *val = LSM6DSO_AUX_GY_NEG;
+      break;
+
+    default:
+      *val = LSM6DSO_AUX_GY_DISABLE;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Selects accelerometer OIS channel bandwidth.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of
+  *                                       filter_xl_conf_ois in reg CTRL3_OIS
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_aux_xl_bandwidth_set(stmdev_ctx_t *ctx,
+                                     lsm6dso_filter_xl_conf_ois_t val)
+{
+  lsm6dso_ctrl3_ois_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.filter_xl_conf_ois = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Selects accelerometer OIS channel bandwidth.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of
+  *                                       filter_xl_conf_ois in reg CTRL3_OIS
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_aux_xl_bandwidth_get(stmdev_ctx_t *ctx,
+                                     lsm6dso_filter_xl_conf_ois_t *val)
+{
+  lsm6dso_ctrl3_ois_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)&reg, 1);
+
+  switch (reg.filter_xl_conf_ois)
+  {
+    case LSM6DSO_289Hz:
+      *val = LSM6DSO_289Hz;
+      break;
+
+    case LSM6DSO_258Hz:
+      *val = LSM6DSO_258Hz;
+      break;
+
+    case LSM6DSO_120Hz:
+      *val = LSM6DSO_120Hz;
+      break;
+
+    case LSM6DSO_65Hz2:
+      *val = LSM6DSO_65Hz2;
+      break;
+
+    case LSM6DSO_33Hz2:
+      *val = LSM6DSO_33Hz2;
+      break;
+
+    case LSM6DSO_16Hz6:
+      *val = LSM6DSO_16Hz6;
+      break;
+
+    case LSM6DSO_8Hz30:
+      *val = LSM6DSO_8Hz30;
+      break;
+
+    case LSM6DSO_4Hz15:
+      *val = LSM6DSO_4Hz15;
+      break;
+
+    default:
+      *val = LSM6DSO_289Hz;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Selects accelerometer OIS channel full-scale.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of fs_xl_ois in
+  *                              reg CTRL3_OIS
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_aux_xl_full_scale_set(stmdev_ctx_t *ctx,
+                                      lsm6dso_fs_xl_ois_t val)
+{
+  lsm6dso_ctrl3_ois_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.fs_xl_ois = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Selects accelerometer OIS channel full-scale.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of fs_xl_ois in reg CTRL3_OIS
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_aux_xl_full_scale_get(stmdev_ctx_t *ctx,
+                                      lsm6dso_fs_xl_ois_t *val)
+{
+  lsm6dso_ctrl3_ois_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)&reg, 1);
+
+  switch (reg.fs_xl_ois)
+  {
+    case LSM6DSO_AUX_2g:
+      *val = LSM6DSO_AUX_2g;
+      break;
+
+    case LSM6DSO_AUX_16g:
+      *val = LSM6DSO_AUX_16g;
+      break;
+
+    case LSM6DSO_AUX_4g:
+      *val = LSM6DSO_AUX_4g;
+      break;
+
+    case LSM6DSO_AUX_8g:
+      *val = LSM6DSO_AUX_8g;
+      break;
+
+    default:
+      *val = LSM6DSO_AUX_2g;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @}
+  *
+  */
+
+/**
+  * @defgroup  LSM6DSO_ main_serial_interface
+  * @brief     This section groups all the functions concerning main
+  *            serial interface management (not auxiliary)
+  * @{
+  *
+  */
+
+/**
+  * @brief  Connect/Disconnect SDO/SA0 internal pull-up.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of sdo_pu_en in
+  *                              reg PIN_CTRL
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
+                                 lsm6dso_sdo_pu_en_t val)
+{
+  lsm6dso_pin_ctrl_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.sdo_pu_en = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Connect/Disconnect SDO/SA0 internal pull-up.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of sdo_pu_en in reg PIN_CTRL
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
+                                 lsm6dso_sdo_pu_en_t *val)
+{
+  lsm6dso_pin_ctrl_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)&reg, 1);
+
+  switch (reg.sdo_pu_en)
+  {
+    case LSM6DSO_PULL_UP_DISC:
+      *val = LSM6DSO_PULL_UP_DISC;
+      break;
+
+    case LSM6DSO_PULL_UP_CONNECT:
+      *val = LSM6DSO_PULL_UP_CONNECT;
+      break;
+
+    default:
+      *val = LSM6DSO_PULL_UP_DISC;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  SPI Serial Interface Mode selection.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of sim in reg CTRL3_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_spi_mode_set(stmdev_ctx_t *ctx, lsm6dso_sim_t val)
+{
+  lsm6dso_ctrl3_c_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.sim = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  SPI Serial Interface Mode selection.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of sim in reg CTRL3_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_spi_mode_get(stmdev_ctx_t *ctx, lsm6dso_sim_t *val)
+{
+  lsm6dso_ctrl3_c_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
+
+  switch (reg.sim)
+  {
+    case LSM6DSO_SPI_4_WIRE:
+      *val = LSM6DSO_SPI_4_WIRE;
+      break;
+
+    case LSM6DSO_SPI_3_WIRE:
+      *val = LSM6DSO_SPI_3_WIRE;
+      break;
+
+    default:
+      *val = LSM6DSO_SPI_4_WIRE;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Disable / Enable I2C interface.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of i2c_disable in
+  *                                reg CTRL4_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_i2c_interface_set(stmdev_ctx_t *ctx,
+                                  lsm6dso_i2c_disable_t val)
+{
+  lsm6dso_ctrl4_c_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.i2c_disable = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Disable / Enable I2C interface.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of i2c_disable in
+  *                                reg CTRL4_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_i2c_interface_get(stmdev_ctx_t *ctx,
+                                  lsm6dso_i2c_disable_t *val)
+{
+  lsm6dso_ctrl4_c_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&reg, 1);
+
+  switch (reg.i2c_disable)
+  {
+    case LSM6DSO_I2C_ENABLE:
+      *val = LSM6DSO_I2C_ENABLE;
+      break;
+
+    case LSM6DSO_I2C_DISABLE:
+      *val = LSM6DSO_I2C_DISABLE;
+      break;
+
+    default:
+      *val = LSM6DSO_I2C_ENABLE;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  I3C Enable/Disable communication protocol[.set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of i3c_disable
+  *                                    in reg CTRL9_XL
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_i3c_disable_set(stmdev_ctx_t *ctx,
+                                lsm6dso_i3c_disable_t val)
+{
+  lsm6dso_i3c_bus_avb_t i3c_bus_avb;
+  lsm6dso_ctrl9_xl_t ctrl9_xl;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+  if (ret == 0)
+  {
+    ctrl9_xl.i3c_disable = ((uint8_t)val & 0x80U) >> 7;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB,
+                           (uint8_t *)&i3c_bus_avb, 1);
+  }
+
+  if (ret == 0)
+  {
+    i3c_bus_avb.i3c_bus_avb_sel = (uint8_t)val & 0x03U;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_I3C_BUS_AVB,
+                            (uint8_t *)&i3c_bus_avb, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  I3C Enable/Disable communication protocol.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of i3c_disable in
+  *                                reg CTRL9_XL
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_i3c_disable_get(stmdev_ctx_t *ctx,
+                                lsm6dso_i3c_disable_t *val)
+{
+  lsm6dso_ctrl9_xl_t ctrl9_xl;
+  lsm6dso_i3c_bus_avb_t i3c_bus_avb;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB,
+                           (uint8_t *)&i3c_bus_avb, 1);
+
+    switch ((ctrl9_xl.i3c_disable << 7) | i3c_bus_avb.i3c_bus_avb_sel)
+    {
+      case LSM6DSO_I3C_DISABLE:
+        *val = LSM6DSO_I3C_DISABLE;
+        break;
+
+      case LSM6DSO_I3C_ENABLE_T_50us:
+        *val = LSM6DSO_I3C_ENABLE_T_50us;
+        break;
+
+      case LSM6DSO_I3C_ENABLE_T_2us:
+        *val = LSM6DSO_I3C_ENABLE_T_2us;
+        break;
+
+      case LSM6DSO_I3C_ENABLE_T_1ms:
+        *val = LSM6DSO_I3C_ENABLE_T_1ms;
+        break;
+
+      case LSM6DSO_I3C_ENABLE_T_25ms:
+        *val = LSM6DSO_I3C_ENABLE_T_25ms;
+        break;
+
+      default:
+        *val = LSM6DSO_I3C_DISABLE;
+        break;
+    }
+  }
+
+  return ret;
+}
+
+/**
+  * @}
+  *
+  */
+
+/**
+  * @defgroup  LSM6DSO_interrupt_pins
+  * @brief     This section groups all the functions that manage interrupt pins
+  * @{
+  *
+  */
+
+/**
+  * @brief  Connect/Disconnect INT1 internal pull-down.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of pd_dis_int1 in reg I3C_BUS_AVB
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_int1_mode_set(stmdev_ctx_t *ctx,
+                              lsm6dso_int1_pd_en_t val)
+{
+  lsm6dso_i3c_bus_avb_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.pd_dis_int1 = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_I3C_BUS_AVB, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Connect/Disconnect INT1 internal pull-down.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of pd_dis_int1 in reg I3C_BUS_AVB
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_int1_mode_get(stmdev_ctx_t *ctx,
+                              lsm6dso_int1_pd_en_t *val)
+{
+  lsm6dso_i3c_bus_avb_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB, (uint8_t *)&reg, 1);
+
+  switch (reg.pd_dis_int1)
+  {
+    case LSM6DSO_PULL_DOWN_DISC:
+      *val = LSM6DSO_PULL_DOWN_DISC;
+      break;
+
+    case LSM6DSO_PULL_DOWN_CONNECT:
+      *val = LSM6DSO_PULL_DOWN_CONNECT;
+      break;
+
+    default:
+      *val = LSM6DSO_PULL_DOWN_DISC;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Push-pull/open drain selection on interrupt pads.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of pp_od in reg CTRL3_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_pin_mode_set(stmdev_ctx_t *ctx, lsm6dso_pp_od_t val)
+{
+  lsm6dso_ctrl3_c_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.pp_od = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Push-pull/open drain selection on interrupt pads.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of pp_od in reg CTRL3_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_pin_mode_get(stmdev_ctx_t *ctx, lsm6dso_pp_od_t *val)
+{
+  lsm6dso_ctrl3_c_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
+
+  switch (reg.pp_od)
+  {
+    case LSM6DSO_PUSH_PULL:
+      *val = LSM6DSO_PUSH_PULL;
+      break;
+
+    case LSM6DSO_OPEN_DRAIN:
+      *val = LSM6DSO_OPEN_DRAIN;
+      break;
+
+    default:
+      *val = LSM6DSO_PUSH_PULL;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Interrupt active-high/low.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of h_lactive in reg CTRL3_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_pin_polarity_set(stmdev_ctx_t *ctx,
+                                 lsm6dso_h_lactive_t val)
+{
+  lsm6dso_ctrl3_c_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.h_lactive = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Interrupt active-high/low.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of h_lactive in reg CTRL3_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_pin_polarity_get(stmdev_ctx_t *ctx,
+                                 lsm6dso_h_lactive_t *val)
+{
+  lsm6dso_ctrl3_c_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&reg, 1);
+
+  switch (reg.h_lactive)
+  {
+    case LSM6DSO_ACTIVE_HIGH:
+      *val = LSM6DSO_ACTIVE_HIGH;
+      break;
+
+    case LSM6DSO_ACTIVE_LOW:
+      *val = LSM6DSO_ACTIVE_LOW;
+      break;
+
+    default:
+      *val = LSM6DSO_ACTIVE_HIGH;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  All interrupt signals become available on INT1 pin.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of int2_on_int1 in reg CTRL4_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_ctrl4_c_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.int2_on_int1 = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  All interrupt signals become available on INT1 pin.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of int2_on_int1 in reg CTRL4_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_ctrl4_c_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&reg, 1);
+  *val = reg.int2_on_int1;
+
+  return ret;
+}
+
+/**
+  * @brief  Interrupt notification mode.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of lir in reg TAP_CFG0
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_int_notification_set(stmdev_ctx_t *ctx,
+                                     lsm6dso_lir_t val)
+{
+  lsm6dso_tap_cfg0_t tap_cfg0;
+  lsm6dso_page_rw_t page_rw;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *) &tap_cfg0, 1);
+
+  if (ret == 0)
+  {
+    tap_cfg0.lir = (uint8_t)val & 0x01U;
+    tap_cfg0.int_clr_on_read = (uint8_t)val & 0x01U;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *) &tap_cfg0, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
+  }
+
+  if (ret == 0)
+  {
+    page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Interrupt notification mode.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of lir in reg TAP_CFG0
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_int_notification_get(stmdev_ctx_t *ctx,
+                                     lsm6dso_lir_t *val)
+{
+  lsm6dso_tap_cfg0_t tap_cfg0;
+  lsm6dso_page_rw_t page_rw;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *) &tap_cfg0, 1);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  if (ret == 0)
+  {
+    switch ((page_rw.emb_func_lir << 1) | tap_cfg0.lir)
+    {
+      case LSM6DSO_ALL_INT_PULSED:
+        *val = LSM6DSO_ALL_INT_PULSED;
+        break;
+
+      case LSM6DSO_BASE_LATCHED_EMB_PULSED:
+        *val = LSM6DSO_BASE_LATCHED_EMB_PULSED;
+        break;
+
+      case LSM6DSO_BASE_PULSED_EMB_LATCHED:
+        *val = LSM6DSO_BASE_PULSED_EMB_LATCHED;
+        break;
+
+      case LSM6DSO_ALL_INT_LATCHED:
+        *val = LSM6DSO_ALL_INT_LATCHED;
+        break;
+
+      default:
+        *val = LSM6DSO_ALL_INT_PULSED;
+        break;
+    }
+
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @}
+  *
+  */
+
+/**
+  * @defgroup  LSM6DSO_Wake_Up_event
+  * @brief     This section groups all the functions that manage the Wake Up
+  *            event generation.
+  * @{
+  *
+  */
+
+/**
+  * @brief  Weight of 1 LSB of wakeup threshold.[set]
+  *         0: 1 LSB =FS_XL  /  64
+  *         1: 1 LSB = FS_XL / 256
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of wake_ths_w in
+  *                                 reg WAKE_UP_DUR
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_wkup_ths_weight_set(stmdev_ctx_t *ctx,
+                                    lsm6dso_wake_ths_w_t val)
+{
+  lsm6dso_wake_up_dur_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.wake_ths_w = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Weight of 1 LSB of wakeup threshold.[get]
+  *         0: 1 LSB =FS_XL  /  64
+  *         1: 1 LSB = FS_XL / 256
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of wake_ths_w in
+  *                                 reg WAKE_UP_DUR
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_wkup_ths_weight_get(stmdev_ctx_t *ctx,
+                                    lsm6dso_wake_ths_w_t *val)
+{
+  lsm6dso_wake_up_dur_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)&reg, 1);
+
+  switch (reg.wake_ths_w)
+  {
+    case LSM6DSO_LSb_FS_DIV_64:
+      *val = LSM6DSO_LSb_FS_DIV_64;
+      break;
+
+    case LSM6DSO_LSb_FS_DIV_256:
+      *val = LSM6DSO_LSb_FS_DIV_256;
+      break;
+
+    default:
+      *val = LSM6DSO_LSb_FS_DIV_64;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
+  *         WAKE_UP_DUR.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of wk_ths in reg WAKE_UP_THS
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_wake_up_ths_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.wk_ths = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
+  *         WAKE_UP_DUR.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of wk_ths in reg WAKE_UP_THS
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_wake_up_ths_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)&reg, 1);
+  *val = reg.wk_ths;
+
+  return ret;
+}
+
+/**
+  * @brief  Wake up duration event.[set]
+  *         1LSb = 1 / ODR
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of usr_off_on_wu in reg WAKE_UP_THS
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx,
+                                          uint8_t val)
+{
+  lsm6dso_wake_up_ths_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.usr_off_on_wu = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Wake up duration event.[get]
+  *         1LSb = 1 / ODR
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of usr_off_on_wu in reg WAKE_UP_THS
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx,
+                                          uint8_t *val)
+{
+  lsm6dso_wake_up_ths_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)&reg, 1);
+  *val = reg.usr_off_on_wu;
+
+  return ret;
+}
+
+/**
+  * @brief  Wake up duration event.[set]
+  *         1LSb = 1 / ODR
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of wake_dur in reg WAKE_UP_DUR
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_wake_up_dur_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.wake_dur = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Wake up duration event.[get]
+  *         1LSb = 1 / ODR
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of wake_dur in reg WAKE_UP_DUR
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_wake_up_dur_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)&reg, 1);
+  *val = reg.wake_dur;
+
+  return ret;
+}
+
+/**
+  * @}
+  *
+  */
+
+/**
+  * @defgroup  LSM6DSO_ Activity/Inactivity_detection
+  * @brief     This section groups all the functions concerning
+  *            activity/inactivity detection.
+  * @{
+  *
+  */
+
+/**
+  * @brief  Enables gyroscope Sleep mode.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of sleep_g in reg CTRL4_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_ctrl4_c_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.sleep_g = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Enables gyroscope Sleep mode.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of sleep_g in reg CTRL4_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_ctrl4_c_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&reg, 1);
+  *val = reg.sleep_g;
+
+  return ret;
+}
+
+/**
+  * @brief  Drives the sleep status instead of
+  *         sleep change on INT pins
+  *         (only if INT1_SLEEP_CHANGE or
+  *         INT2_SLEEP_CHANGE bits are enabled).[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of sleep_status_on_int in reg TAP_CFG0
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_act_pin_notification_set(stmdev_ctx_t *ctx,
+                                         lsm6dso_sleep_status_on_int_t val)
+{
+  lsm6dso_tap_cfg0_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.sleep_status_on_int = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Drives the sleep status instead of
+  *         sleep change on INT pins (only if
+  *         INT1_SLEEP_CHANGE or
+  *         INT2_SLEEP_CHANGE bits are enabled).[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of sleep_status_on_int in reg TAP_CFG0
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_act_pin_notification_get(stmdev_ctx_t *ctx,
+                                         lsm6dso_sleep_status_on_int_t *val)
+{
+  lsm6dso_tap_cfg0_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)&reg, 1);
+
+  switch (reg.sleep_status_on_int)
+  {
+    case LSM6DSO_DRIVE_SLEEP_CHG_EVENT:
+      *val = LSM6DSO_DRIVE_SLEEP_CHG_EVENT;
+      break;
+
+    case LSM6DSO_DRIVE_SLEEP_STATUS:
+      *val = LSM6DSO_DRIVE_SLEEP_STATUS;
+      break;
+
+    default:
+      *val = LSM6DSO_DRIVE_SLEEP_CHG_EVENT;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Enable inactivity function.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of inact_en in reg TAP_CFG2
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_act_mode_set(stmdev_ctx_t *ctx,
+                             lsm6dso_inact_en_t val)
+{
+  lsm6dso_tap_cfg2_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.inact_en = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Enable inactivity function.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of inact_en in reg TAP_CFG2
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_act_mode_get(stmdev_ctx_t *ctx,
+                             lsm6dso_inact_en_t *val)
+{
+  lsm6dso_tap_cfg2_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *)&reg, 1);
+
+  switch (reg.inact_en)
+  {
+    case LSM6DSO_XL_AND_GY_NOT_AFFECTED:
+      *val = LSM6DSO_XL_AND_GY_NOT_AFFECTED;
+      break;
+
+    case LSM6DSO_XL_12Hz5_GY_NOT_AFFECTED:
+      *val = LSM6DSO_XL_12Hz5_GY_NOT_AFFECTED;
+      break;
+
+    case LSM6DSO_XL_12Hz5_GY_SLEEP:
+      *val = LSM6DSO_XL_12Hz5_GY_SLEEP;
+      break;
+
+    case LSM6DSO_XL_12Hz5_GY_PD:
+      *val = LSM6DSO_XL_12Hz5_GY_PD;
+      break;
+
+    default:
+      *val = LSM6DSO_XL_AND_GY_NOT_AFFECTED;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Duration to go in sleep mode.[set]
+  *         1 LSb = 512 / ODR
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of sleep_dur in reg WAKE_UP_DUR
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_wake_up_dur_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.sleep_dur = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Duration to go in sleep mode.[get]
+  *         1 LSb = 512 / ODR
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of sleep_dur in reg WAKE_UP_DUR
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_wake_up_dur_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)&reg, 1);
+  *val = reg.sleep_dur;
+
+  return ret;
+}
+
+/**
+  * @}
+  *
+  */
+
+/**
+  * @defgroup  LSM6DSO_tap_generator
+  * @brief     This section groups all the functions that manage the
+  *            tap and double tap event generation.
+  * @{
+  *
+  */
+
+/**
+  * @brief  Enable Z direction in tap recognition.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of tap_z_en in reg TAP_CFG0
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_tap_cfg0_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.tap_z_en = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Enable Z direction in tap recognition.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of tap_z_en in reg TAP_CFG0
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_tap_detection_on_z_get(stmdev_ctx_t *ctx,
+                                       uint8_t *val)
+{
+  lsm6dso_tap_cfg0_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)&reg, 1);
+  *val = reg.tap_z_en;
+
+  return ret;
+}
+
+/**
+  * @brief  Enable Y direction in tap recognition.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of tap_y_en in reg TAP_CFG0
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_tap_cfg0_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.tap_y_en = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Enable Y direction in tap recognition.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of tap_y_en in reg TAP_CFG0
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+                                       uint8_t *val)
+{
+  lsm6dso_tap_cfg0_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)&reg, 1);
+  *val = reg.tap_y_en;
+
+  return ret;
+}
+
+/**
+  * @brief  Enable X direction in tap recognition.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of tap_x_en in reg TAP_CFG0
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_tap_cfg0_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.tap_x_en = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Enable X direction in tap recognition.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of tap_x_en in reg TAP_CFG0
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+                                       uint8_t *val)
+{
+  lsm6dso_tap_cfg0_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)&reg, 1);
+  *val = reg.tap_x_en;
+
+  return ret;
+}
+
+/**
+  * @brief  X-axis tap recognition threshold.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of tap_ths_x in reg TAP_CFG1
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_tap_cfg1_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.tap_ths_x = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  X-axis tap recognition threshold.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of tap_ths_x in reg TAP_CFG1
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_tap_cfg1_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t *)&reg, 1);
+  *val = reg.tap_ths_x;
+
+  return ret;
+}
+
+/**
+  * @brief  Selection of axis priority for TAP detection.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of tap_priority in
+  *                                 reg TAP_CFG1
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_tap_axis_priority_set(stmdev_ctx_t *ctx,
+                                      lsm6dso_tap_priority_t val)
+{
+  lsm6dso_tap_cfg1_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.tap_priority = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Selection of axis priority for TAP detection.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of tap_priority in
+  *                                 reg TAP_CFG1
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_tap_axis_priority_get(stmdev_ctx_t *ctx,
+                                      lsm6dso_tap_priority_t *val)
+{
+  lsm6dso_tap_cfg1_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t *)&reg, 1);
+
+  switch (reg.tap_priority)
+  {
+    case LSM6DSO_XYZ:
+      *val = LSM6DSO_XYZ;
+      break;
+
+    case LSM6DSO_YXZ:
+      *val = LSM6DSO_YXZ;
+      break;
+
+    case LSM6DSO_XZY:
+      *val = LSM6DSO_XZY;
+      break;
+
+    case LSM6DSO_ZYX:
+      *val = LSM6DSO_ZYX;
+      break;
+
+    case LSM6DSO_YZX:
+      *val = LSM6DSO_YZX;
+      break;
+
+    case LSM6DSO_ZXY:
+      *val = LSM6DSO_ZXY;
+      break;
+
+    default:
+      *val = LSM6DSO_XYZ;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Y-axis tap recognition threshold.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of tap_ths_y in reg TAP_CFG2
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_tap_cfg2_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.tap_ths_y = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Y-axis tap recognition threshold.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of tap_ths_y in reg TAP_CFG2
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_tap_cfg2_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *)&reg, 1);
+  *val = reg.tap_ths_y;
+
+  return ret;
+}
+
+/**
+  * @brief  Z-axis recognition threshold.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of tap_ths_z in reg TAP_THS_6D
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_tap_ths_6d_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.tap_ths_z = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Z-axis recognition threshold.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of tap_ths_z in reg TAP_THS_6D
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_tap_ths_6d_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)&reg, 1);
+  *val = reg.tap_ths_z;
+
+  return ret;
+}
+
+/**
+  * @brief  Maximum duration is the maximum time of an
+  *         over threshold signal detection to be recognized
+  *         as a tap event. The default value of these bits
+  *         is 00b which corresponds to 4*ODR_XL time.
+  *         If the SHOCK[1:0] bits are set to a different
+  *         value, 1LSB corresponds to 8*ODR_XL time.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of shock in reg INT_DUR2
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_int_dur2_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.shock = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Maximum duration is the maximum time of an
+  *         over threshold signal detection to be recognized
+  *         as a tap event. The default value of these bits
+  *         is 00b which corresponds to 4*ODR_XL time.
+  *         If the SHOCK[1:0] bits are set to a different
+  *         value, 1LSB corresponds to 8*ODR_XL time.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of shock in reg INT_DUR2
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_int_dur2_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)&reg, 1);
+  *val = reg.shock;
+
+  return ret;
+}
+
+/**
+  * @brief   Quiet time is the time after the first detected
+  *          tap in which there must not be any over threshold
+  *          event.
+  *          The default value of these bits is 00b which
+  *          corresponds to 2*ODR_XL time. If the QUIET[1:0]
+  *          bits are set to a different value,
+  *          1LSB corresponds to 4*ODR_XL time.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of quiet in reg INT_DUR2
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_int_dur2_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.quiet = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Quiet time is the time after the first detected
+  *         tap in which there must not be any over threshold
+  *         event.
+  *         The default value of these bits is 00b which
+  *         corresponds to 2*ODR_XL time.
+  *         If the QUIET[1:0] bits are set to a different
+  *         value, 1LSB corresponds to 4*ODR_XL time.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of quiet in reg INT_DUR2
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_int_dur2_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)&reg, 1);
+  *val = reg.quiet;
+
+  return ret;
+}
+
+/**
+  * @brief  When double tap recognition is enabled,
+  *         this register expresses the maximum time
+  *         between two consecutive detected taps to
+  *         determine a double tap event.
+  *         The default value of these bits is 0000b which
+  *         corresponds to 16*ODR_XL time.
+  *         If the DUR[3:0] bits are set to a different value,
+  *         1LSB corresponds to 32*ODR_XL time.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of dur in reg INT_DUR2
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_int_dur2_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.dur = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  When double tap recognition is enabled,
+  *         this register expresses the maximum time
+  *         between two consecutive detected taps to
+  *         determine a double tap event.
+  *         The default value of these bits is 0000b which
+  *         corresponds to 16*ODR_XL time. If the DUR[3:0]
+  *         bits are set to a different value,
+  *         1LSB corresponds to 32*ODR_XL time.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of dur in reg INT_DUR2
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_int_dur2_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)&reg, 1);
+  *val = reg.dur;
+
+  return ret;
+}
+
+/**
+  * @brief  Single/double-tap event enable.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of single_double_tap in reg WAKE_UP_THS
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_tap_mode_set(stmdev_ctx_t *ctx,
+                             lsm6dso_single_double_tap_t val)
+{
+  lsm6dso_wake_up_ths_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.single_double_tap = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Single/double-tap event enable.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of single_double_tap in reg WAKE_UP_THS
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_tap_mode_get(stmdev_ctx_t *ctx,
+                             lsm6dso_single_double_tap_t *val)
+{
+  lsm6dso_wake_up_ths_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)&reg, 1);
+
+  switch (reg.single_double_tap)
+  {
+    case LSM6DSO_ONLY_SINGLE:
+      *val = LSM6DSO_ONLY_SINGLE;
+      break;
+
+    case LSM6DSO_BOTH_SINGLE_DOUBLE:
+      *val = LSM6DSO_BOTH_SINGLE_DOUBLE;
+      break;
+
+    default:
+      *val = LSM6DSO_ONLY_SINGLE;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @}
+  *
+  */
+
+/**
+  * @defgroup  LSM6DSO_ Six_position_detection(6D/4D)
+  * @brief   This section groups all the functions concerning six position
+  *          detection (6D).
+  * @{
+  *
+  */
+
+/**
+  * @brief  Threshold for 4D/6D function.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of sixd_ths in reg TAP_THS_6D
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_6d_threshold_set(stmdev_ctx_t *ctx,
+                                 lsm6dso_sixd_ths_t val)
+{
+  lsm6dso_tap_ths_6d_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.sixd_ths = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Threshold for 4D/6D function.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of sixd_ths in reg TAP_THS_6D
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_6d_threshold_get(stmdev_ctx_t *ctx,
+                                 lsm6dso_sixd_ths_t *val)
+{
+  lsm6dso_tap_ths_6d_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)&reg, 1);
+
+  switch (reg.sixd_ths)
+  {
+    case LSM6DSO_DEG_80:
+      *val = LSM6DSO_DEG_80;
+      break;
+
+    case LSM6DSO_DEG_70:
+      *val = LSM6DSO_DEG_70;
+      break;
+
+    case LSM6DSO_DEG_60:
+      *val = LSM6DSO_DEG_60;
+      break;
+
+    case LSM6DSO_DEG_50:
+      *val = LSM6DSO_DEG_50;
+      break;
+
+    default:
+      *val = LSM6DSO_DEG_80;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  4D orientation detection enable.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of d4d_en in reg TAP_THS_6D
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_tap_ths_6d_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.d4d_en = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  4D orientation detection enable.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of d4d_en in reg TAP_THS_6D
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_tap_ths_6d_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)&reg, 1);
+  *val = reg.d4d_en;
+
+  return ret;
+}
+
+/**
+  * @}
+  *
+  */
+
+/**
+  * @defgroup  LSM6DSO_free_fall
+  * @brief   This section group all the functions concerning the free
+  *          fall detection.
+  * @{
+  *
+  */
+/**
+  * @brief  Free fall threshold setting.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of ff_ths in reg FREE_FALL
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_ff_threshold_set(stmdev_ctx_t *ctx,
+                                 lsm6dso_ff_ths_t val)
+{
+  lsm6dso_free_fall_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.ff_ths = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Free fall threshold setting.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of ff_ths in reg FREE_FALL
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_ff_threshold_get(stmdev_ctx_t *ctx,
+                                 lsm6dso_ff_ths_t *val)
+{
+  lsm6dso_free_fall_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t *)&reg, 1);
+
+  switch (reg.ff_ths)
+  {
+    case LSM6DSO_FF_TSH_156mg:
+      *val = LSM6DSO_FF_TSH_156mg;
+      break;
+
+    case LSM6DSO_FF_TSH_219mg:
+      *val = LSM6DSO_FF_TSH_219mg;
+      break;
+
+    case LSM6DSO_FF_TSH_250mg:
+      *val = LSM6DSO_FF_TSH_250mg;
+      break;
+
+    case LSM6DSO_FF_TSH_312mg:
+      *val = LSM6DSO_FF_TSH_312mg;
+      break;
+
+    case LSM6DSO_FF_TSH_344mg:
+      *val = LSM6DSO_FF_TSH_344mg;
+      break;
+
+    case LSM6DSO_FF_TSH_406mg:
+      *val = LSM6DSO_FF_TSH_406mg;
+      break;
+
+    case LSM6DSO_FF_TSH_469mg:
+      *val = LSM6DSO_FF_TSH_469mg;
+      break;
+
+    case LSM6DSO_FF_TSH_500mg:
+      *val = LSM6DSO_FF_TSH_500mg;
+      break;
+
+    default:
+      *val = LSM6DSO_FF_TSH_156mg;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Free-fall duration event.[set]
+  *         1LSb = 1 / ODR
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of ff_dur in reg FREE_FALL
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_wake_up_dur_t wake_up_dur;
+  lsm6dso_free_fall_t free_fall;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR,
+                         (uint8_t *)&wake_up_dur, 1);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t *)&free_fall, 1);
+  }
+
+  if (ret == 0)
+  {
+    wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5;
+    free_fall.ff_dur = (uint8_t)val & 0x1FU;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR,
+                            (uint8_t *)&wake_up_dur, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t *)&free_fall, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Free-fall duration event.[get]
+  *         1LSb = 1 / ODR
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of ff_dur in reg FREE_FALL
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_wake_up_dur_t wake_up_dur;
+  lsm6dso_free_fall_t free_fall;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR,
+                         (uint8_t *)&wake_up_dur, 1);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t *)&free_fall, 1);
+    *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
+  }
+
+  return ret;
+}
+
+/**
+  * @}
+  *
+  */
+
+/**
+  * @defgroup  LSM6DSO_fifo
+  * @brief   This section group all the functions concerning the fifo usage
+  * @{
+  *
+  */
+
+/**
+  * @brief  FIFO watermark level selection.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of wtm in reg FIFO_CTRL1
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val)
+{
+  lsm6dso_fifo_ctrl1_t fifo_ctrl1;
+  lsm6dso_fifo_ctrl2_t fifo_ctrl2;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2,
+                         (uint8_t *)&fifo_ctrl2, 1);
+
+  if (ret == 0)
+  {
+    fifo_ctrl1.wtm = 0x00FFU & (uint8_t)val;
+    fifo_ctrl2.wtm = (uint8_t)((0x0100U & val) >> 8);
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL1,
+                            (uint8_t *)&fifo_ctrl1, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2,
+                            (uint8_t *)&fifo_ctrl2, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  FIFO watermark level selection.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of wtm in reg FIFO_CTRL1
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val)
+{
+  lsm6dso_fifo_ctrl1_t fifo_ctrl1;
+  lsm6dso_fifo_ctrl2_t fifo_ctrl2;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL1,
+                         (uint8_t *)&fifo_ctrl1, 1);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2,
+                           (uint8_t *)&fifo_ctrl2, 1);
+    *val = ((uint16_t)fifo_ctrl2.wtm << 8) + (uint16_t)fifo_ctrl1.wtm;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  FIFO compression feature initialization request [set].
+  *
+  * @param  ctx       read / write interface definitions
+  * @param  val       change the values of FIFO_COMPR_INIT in
+  *                   reg EMB_FUNC_INIT_B
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_compression_algo_init_set(stmdev_ctx_t *ctx,
+                                          uint8_t val)
+{
+  lsm6dso_emb_func_init_b_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    reg.fifo_compr_init = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  FIFO compression feature initialization request [get].
+  *
+  * @param  ctx    read / write interface definitions
+  * @param  val    change the values of FIFO_COMPR_INIT in
+  *                reg EMB_FUNC_INIT_B
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_compression_algo_init_get(stmdev_ctx_t *ctx,
+                                          uint8_t *val)
+{
+  lsm6dso_emb_func_init_b_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    *val = reg.fifo_compr_init;
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Enable and configure compression algo.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of uncoptr_rate in
+  *                  reg FIFO_CTRL2
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_compression_algo_set(stmdev_ctx_t *ctx,
+                                     lsm6dso_uncoptr_rate_t val)
+{
+  lsm6dso_fifo_ctrl2_t fifo_ctrl2;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2,
+                         (uint8_t *)&fifo_ctrl2, 1);
+
+  if (ret == 0)
+  {
+    fifo_ctrl2.fifo_compr_rt_en = ((uint8_t)val & 0x04U) >> 2;
+    fifo_ctrl2.uncoptr_rate = (uint8_t)val & 0x03U;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2,
+                            (uint8_t *)&fifo_ctrl2, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Enable and configure compression algo.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of uncoptr_rate in
+  *                  reg FIFO_CTRL2
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_compression_algo_get(stmdev_ctx_t *ctx,
+                                     lsm6dso_uncoptr_rate_t *val)
+{
+  lsm6dso_fifo_ctrl2_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)&reg, 1);
+
+  switch ((reg.fifo_compr_rt_en << 2) | reg.uncoptr_rate)
+  {
+    case LSM6DSO_CMP_DISABLE:
+      *val = LSM6DSO_CMP_DISABLE;
+      break;
+
+    case LSM6DSO_CMP_ALWAYS:
+      *val = LSM6DSO_CMP_ALWAYS;
+      break;
+
+    case LSM6DSO_CMP_8_TO_1:
+      *val = LSM6DSO_CMP_8_TO_1;
+      break;
+
+    case LSM6DSO_CMP_16_TO_1:
+      *val = LSM6DSO_CMP_16_TO_1;
+      break;
+
+    case LSM6DSO_CMP_32_TO_1:
+      *val = LSM6DSO_CMP_32_TO_1;
+      break;
+
+    default:
+      *val = LSM6DSO_CMP_DISABLE;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Enables ODR CHANGE virtual sensor to be batched in FIFO.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of odrchg_en in reg FIFO_CTRL2
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx,
+                                              uint8_t val)
+{
+  lsm6dso_fifo_ctrl2_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.odrchg_en = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Enables ODR CHANGE virtual sensor to be batched in FIFO.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of odrchg_en in reg FIFO_CTRL2
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx,
+                                              uint8_t *val)
+{
+  lsm6dso_fifo_ctrl2_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)&reg, 1);
+  *val = reg.odrchg_en;
+
+  return ret;
+}
+
+/**
+  * @brief  Enables/Disables compression algorithm runtime.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of fifo_compr_rt_en in
+  *                  reg FIFO_CTRL2
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_compression_algo_real_time_set(stmdev_ctx_t *ctx,
+                                               uint8_t val)
+{
+  lsm6dso_fifo_ctrl2_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.fifo_compr_rt_en = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief   Enables/Disables compression algorithm runtime. [get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of fifo_compr_rt_en in reg FIFO_CTRL2
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_compression_algo_real_time_get(stmdev_ctx_t *ctx,
+                                               uint8_t *val)
+{
+  lsm6dso_fifo_ctrl2_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)&reg, 1);
+  *val = reg.fifo_compr_rt_en;
+
+  return ret;
+}
+
+/**
+  * @brief  Sensing chain FIFO stop values memorization at
+  *         threshold level.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of stop_on_wtm in reg FIFO_CTRL2
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_fifo_ctrl2_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.stop_on_wtm = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Sensing chain FIFO stop values memorization at
+  *         threshold level.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of stop_on_wtm in reg FIFO_CTRL2
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_fifo_ctrl2_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)&reg, 1);
+  *val = reg.stop_on_wtm;
+
+  return ret;
+}
+
+/**
+  * @brief  Selects Batching Data Rate (writing frequency in FIFO)
+  *         for accelerometer data.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of bdr_xl in reg FIFO_CTRL3
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_fifo_xl_batch_set(stmdev_ctx_t *ctx,
+                                  lsm6dso_bdr_xl_t val)
+{
+  lsm6dso_fifo_ctrl3_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.bdr_xl = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Selects Batching Data Rate (writing frequency in FIFO)
+  *         for accelerometer data.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of bdr_xl in reg FIFO_CTRL3
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_fifo_xl_batch_get(stmdev_ctx_t *ctx,
+                                  lsm6dso_bdr_xl_t *val)
+{
+  lsm6dso_fifo_ctrl3_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t *)&reg, 1);
+
+  switch (reg.bdr_xl)
+  {
+    case LSM6DSO_XL_NOT_BATCHED:
+      *val = LSM6DSO_XL_NOT_BATCHED;
+      break;
+
+    case LSM6DSO_XL_BATCHED_AT_12Hz5:
+      *val = LSM6DSO_XL_BATCHED_AT_12Hz5;
+      break;
+
+    case LSM6DSO_XL_BATCHED_AT_26Hz:
+      *val = LSM6DSO_XL_BATCHED_AT_26Hz;
+      break;
+
+    case LSM6DSO_XL_BATCHED_AT_52Hz:
+      *val = LSM6DSO_XL_BATCHED_AT_52Hz;
+      break;
+
+    case LSM6DSO_XL_BATCHED_AT_104Hz:
+      *val = LSM6DSO_XL_BATCHED_AT_104Hz;
+      break;
+
+    case LSM6DSO_XL_BATCHED_AT_208Hz:
+      *val = LSM6DSO_XL_BATCHED_AT_208Hz;
+      break;
+
+    case LSM6DSO_XL_BATCHED_AT_417Hz:
+      *val = LSM6DSO_XL_BATCHED_AT_417Hz;
+      break;
+
+    case LSM6DSO_XL_BATCHED_AT_833Hz:
+      *val = LSM6DSO_XL_BATCHED_AT_833Hz;
+      break;
+
+    case LSM6DSO_XL_BATCHED_AT_1667Hz:
+      *val = LSM6DSO_XL_BATCHED_AT_1667Hz;
+      break;
+
+    case LSM6DSO_XL_BATCHED_AT_3333Hz:
+      *val = LSM6DSO_XL_BATCHED_AT_3333Hz;
+      break;
+
+    case LSM6DSO_XL_BATCHED_AT_6667Hz:
+      *val = LSM6DSO_XL_BATCHED_AT_6667Hz;
+      break;
+
+    case LSM6DSO_XL_BATCHED_AT_6Hz5:
+      *val = LSM6DSO_XL_BATCHED_AT_6Hz5;
+      break;
+
+    default:
+      *val = LSM6DSO_XL_NOT_BATCHED;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Selects Batching Data Rate (writing frequency in FIFO)
+  *         for gyroscope data.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of bdr_gy in reg FIFO_CTRL3
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_fifo_gy_batch_set(stmdev_ctx_t *ctx,
+                                  lsm6dso_bdr_gy_t val)
+{
+  lsm6dso_fifo_ctrl3_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.bdr_gy = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Selects Batching Data Rate (writing frequency in FIFO)
+  *         for gyroscope data.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of bdr_gy in reg FIFO_CTRL3
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_fifo_gy_batch_get(stmdev_ctx_t *ctx,
+                                  lsm6dso_bdr_gy_t *val)
+{
+  lsm6dso_fifo_ctrl3_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t *)&reg, 1);
+
+  switch (reg.bdr_gy)
+  {
+    case LSM6DSO_GY_NOT_BATCHED:
+      *val = LSM6DSO_GY_NOT_BATCHED;
+      break;
+
+    case LSM6DSO_GY_BATCHED_AT_12Hz5:
+      *val = LSM6DSO_GY_BATCHED_AT_12Hz5;
+      break;
+
+    case LSM6DSO_GY_BATCHED_AT_26Hz:
+      *val = LSM6DSO_GY_BATCHED_AT_26Hz;
+      break;
+
+    case LSM6DSO_GY_BATCHED_AT_52Hz:
+      *val = LSM6DSO_GY_BATCHED_AT_52Hz;
+      break;
+
+    case LSM6DSO_GY_BATCHED_AT_104Hz:
+      *val = LSM6DSO_GY_BATCHED_AT_104Hz;
+      break;
+
+    case LSM6DSO_GY_BATCHED_AT_208Hz:
+      *val = LSM6DSO_GY_BATCHED_AT_208Hz;
+      break;
+
+    case LSM6DSO_GY_BATCHED_AT_417Hz:
+      *val = LSM6DSO_GY_BATCHED_AT_417Hz;
+      break;
+
+    case LSM6DSO_GY_BATCHED_AT_833Hz:
+      *val = LSM6DSO_GY_BATCHED_AT_833Hz;
+      break;
+
+    case LSM6DSO_GY_BATCHED_AT_1667Hz:
+      *val = LSM6DSO_GY_BATCHED_AT_1667Hz;
+      break;
+
+    case LSM6DSO_GY_BATCHED_AT_3333Hz:
+      *val = LSM6DSO_GY_BATCHED_AT_3333Hz;
+      break;
+
+    case LSM6DSO_GY_BATCHED_AT_6667Hz:
+      *val = LSM6DSO_GY_BATCHED_AT_6667Hz;
+      break;
+
+    case LSM6DSO_GY_BATCHED_AT_6Hz5:
+      *val = LSM6DSO_GY_BATCHED_AT_6Hz5;
+      break;
+
+    default:
+      *val = LSM6DSO_GY_NOT_BATCHED;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  FIFO mode selection.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of fifo_mode in reg FIFO_CTRL4
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_fifo_mode_set(stmdev_ctx_t *ctx,
+                              lsm6dso_fifo_mode_t val)
+{
+  lsm6dso_fifo_ctrl4_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.fifo_mode = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  FIFO mode selection.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of fifo_mode in reg FIFO_CTRL4
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_fifo_mode_get(stmdev_ctx_t *ctx,
+                              lsm6dso_fifo_mode_t *val)
+{
+  lsm6dso_fifo_ctrl4_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)&reg, 1);
+
+  switch (reg.fifo_mode)
+  {
+    case LSM6DSO_BYPASS_MODE:
+      *val = LSM6DSO_BYPASS_MODE;
+      break;
+
+    case LSM6DSO_FIFO_MODE:
+      *val = LSM6DSO_FIFO_MODE;
+      break;
+
+    case LSM6DSO_STREAM_TO_FIFO_MODE:
+      *val = LSM6DSO_STREAM_TO_FIFO_MODE;
+      break;
+
+    case LSM6DSO_BYPASS_TO_STREAM_MODE:
+      *val = LSM6DSO_BYPASS_TO_STREAM_MODE;
+      break;
+
+    case LSM6DSO_STREAM_MODE:
+      *val = LSM6DSO_STREAM_MODE;
+      break;
+
+    case LSM6DSO_BYPASS_TO_FIFO_MODE:
+      *val = LSM6DSO_BYPASS_TO_FIFO_MODE;
+      break;
+
+    default:
+      *val = LSM6DSO_BYPASS_MODE;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Selects Batching Data Rate (writing frequency in FIFO)
+  *         for temperature data.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of odr_t_batch in reg FIFO_CTRL4
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_fifo_temp_batch_set(stmdev_ctx_t *ctx,
+                                    lsm6dso_odr_t_batch_t val)
+{
+  lsm6dso_fifo_ctrl4_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.odr_t_batch = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Selects Batching Data Rate (writing frequency in FIFO)
+  *         for temperature data.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of odr_t_batch in reg FIFO_CTRL4
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_fifo_temp_batch_get(stmdev_ctx_t *ctx,
+                                    lsm6dso_odr_t_batch_t *val)
+{
+  lsm6dso_fifo_ctrl4_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)&reg, 1);
+
+  switch (reg.odr_t_batch)
+  {
+    case LSM6DSO_TEMP_NOT_BATCHED:
+      *val = LSM6DSO_TEMP_NOT_BATCHED;
+      break;
+
+    case LSM6DSO_TEMP_BATCHED_AT_1Hz6:
+      *val = LSM6DSO_TEMP_BATCHED_AT_1Hz6;
+      break;
+
+    case LSM6DSO_TEMP_BATCHED_AT_12Hz5:
+      *val = LSM6DSO_TEMP_BATCHED_AT_12Hz5;
+      break;
+
+    case LSM6DSO_TEMP_BATCHED_AT_52Hz:
+      *val = LSM6DSO_TEMP_BATCHED_AT_52Hz;
+      break;
+
+    default:
+      *val = LSM6DSO_TEMP_NOT_BATCHED;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Selects decimation for timestamp batching in FIFO.
+  *         Writing rate will be the maximum rate between XL and
+  *         GYRO BDR divided by decimation decoder.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of odr_ts_batch in reg FIFO_CTRL4
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
+                                              lsm6dso_odr_ts_batch_t val)
+{
+  lsm6dso_fifo_ctrl4_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.odr_ts_batch = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief   Selects decimation for timestamp batching in FIFO.
+  *          Writing rate will be the maximum rate between XL and
+  *          GYRO BDR divided by decimation decoder.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of odr_ts_batch in reg FIFO_CTRL4
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
+                                              lsm6dso_odr_ts_batch_t *val)
+{
+  lsm6dso_fifo_ctrl4_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)&reg, 1);
+
+  switch (reg.odr_ts_batch)
+  {
+    case LSM6DSO_NO_DECIMATION:
+      *val = LSM6DSO_NO_DECIMATION;
+      break;
+
+    case LSM6DSO_DEC_1:
+      *val = LSM6DSO_DEC_1;
+      break;
+
+    case LSM6DSO_DEC_8:
+      *val = LSM6DSO_DEC_8;
+      break;
+
+    case LSM6DSO_DEC_32:
+      *val = LSM6DSO_DEC_32;
+      break;
+
+    default:
+      *val = LSM6DSO_NO_DECIMATION;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Selects the trigger for the internal counter of batching events
+  *         between XL and gyro.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of trig_counter_bdr
+  *                  in reg COUNTER_BDR_REG1
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx,
+                                         lsm6dso_trig_counter_bdr_t val)
+{
+  lsm6dso_counter_bdr_reg1_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.trig_counter_bdr = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1,
+                            (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Selects the trigger for the internal counter of batching events
+  *         between XL and gyro.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of trig_counter_bdr
+  *                                     in reg COUNTER_BDR_REG1
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx,
+                                         lsm6dso_trig_counter_bdr_t *val)
+{
+  lsm6dso_counter_bdr_reg1_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)&reg, 1);
+
+  switch (reg.trig_counter_bdr)
+  {
+    case LSM6DSO_XL_BATCH_EVENT:
+      *val = LSM6DSO_XL_BATCH_EVENT;
+      break;
+
+    case LSM6DSO_GYRO_BATCH_EVENT:
+      *val = LSM6DSO_GYRO_BATCH_EVENT;
+      break;
+
+    default:
+      *val = LSM6DSO_XL_BATCH_EVENT;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Resets the internal counter of batching vents for a single sensor.
+  *         This bit is automatically reset to zero if it was set to '1'.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of rst_counter_bdr in
+  *                      reg COUNTER_BDR_REG1
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_counter_bdr_reg1_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.rst_counter_bdr = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1,
+                            (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Resets the internal counter of batching events for a single sensor.
+  *         This bit is automatically reset to zero if it was set to '1'.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of rst_counter_bdr in
+  *                  reg COUNTER_BDR_REG1
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_counter_bdr_reg1_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)&reg, 1);
+  *val = reg.rst_counter_bdr;
+
+  return ret;
+}
+
+/**
+  * @brief  Batch data rate counter.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of cnt_bdr_th in
+  *                  reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1.
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_batch_counter_threshold_set(stmdev_ctx_t *ctx,
+                                            uint16_t val)
+{
+  lsm6dso_counter_bdr_reg1_t counter_bdr_reg1;
+  lsm6dso_counter_bdr_reg2_t counter_bdr_reg2;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1,
+                         (uint8_t *)&counter_bdr_reg1, 1);
+
+  if (ret == 0)
+  {
+    counter_bdr_reg2.cnt_bdr_th =  0x00FFU & (uint8_t)val;
+    counter_bdr_reg1.cnt_bdr_th = (uint8_t)(0x0700U & val) >> 8;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1,
+                            (uint8_t *)&counter_bdr_reg1, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG2,
+                            (uint8_t *)&counter_bdr_reg2, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Batch data rate counter.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of cnt_bdr_th in
+  *                  reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1.
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_batch_counter_threshold_get(stmdev_ctx_t *ctx,
+                                            uint16_t *val)
+{
+  lsm6dso_counter_bdr_reg1_t counter_bdr_reg1;
+  lsm6dso_counter_bdr_reg2_t counter_bdr_reg2;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1,
+                         (uint8_t *)&counter_bdr_reg1, 1);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG2,
+                           (uint8_t *)&counter_bdr_reg2, 1);
+    *val = ((uint16_t)counter_bdr_reg1.cnt_bdr_th << 8)
+           + (uint16_t)counter_bdr_reg2.cnt_bdr_th;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Number of unread sensor data(TAG + 6 bytes) stored in FIFO.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of diff_fifo in reg FIFO_STATUS1
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
+{
+  lsm6dso_fifo_status1_t fifo_status1;
+  lsm6dso_fifo_status2_t fifo_status2;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS1,
+                         (uint8_t *)&fifo_status1, 1);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2,
+                           (uint8_t *)&fifo_status2, 1);
+    *val = ((uint16_t)fifo_status2.diff_fifo << 8) +
+           (uint16_t)fifo_status1.diff_fifo;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  FIFO status.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      registers FIFO_STATUS2
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_fifo_status_get(stmdev_ctx_t *ctx,
+                                lsm6dso_fifo_status2_t *val)
+{
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2, (uint8_t *) val, 1);
+
+  return ret;
+}
+
+/**
+  * @brief  Smart FIFO full status.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of fifo_full_ia in reg FIFO_STATUS2
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_fifo_status2_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2, (uint8_t *)&reg, 1);
+  *val = reg.fifo_full_ia;
+
+  return ret;
+}
+
+/**
+  * @brief  FIFO overrun status.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of  fifo_over_run_latched in
+  *                  reg FIFO_STATUS2
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_fifo_status2_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2, (uint8_t *)&reg, 1);
+  *val = reg.fifo_ovr_ia;
+
+  return ret;
+}
+
+/**
+  * @brief  FIFO watermark status.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of fifo_wtm_ia in reg FIFO_STATUS2
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_fifo_status2_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2, (uint8_t *)&reg, 1);
+  *val = reg.fifo_wtm_ia;
+
+  return ret;
+}
+
+/**
+  * @brief  Identifies the sensor in FIFO_DATA_OUT.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of tag_sensor in reg FIFO_DATA_OUT_TAG
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_fifo_sensor_tag_get(stmdev_ctx_t *ctx,
+                                    lsm6dso_fifo_tag_t *val)
+{
+  lsm6dso_fifo_data_out_tag_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_DATA_OUT_TAG,
+                         (uint8_t *)&reg, 1);
+
+  switch (reg.tag_sensor)
+  {
+    case LSM6DSO_GYRO_NC_TAG:
+      *val = LSM6DSO_GYRO_NC_TAG;
+      break;
+
+    case LSM6DSO_XL_NC_TAG:
+      *val = LSM6DSO_XL_NC_TAG;
+      break;
+
+    case LSM6DSO_TEMPERATURE_TAG:
+      *val = LSM6DSO_TEMPERATURE_TAG;
+      break;
+
+    case LSM6DSO_CFG_CHANGE_TAG:
+      *val = LSM6DSO_CFG_CHANGE_TAG;
+      break;
+
+    case LSM6DSO_XL_NC_T_2_TAG:
+      *val = LSM6DSO_XL_NC_T_2_TAG;
+      break;
+
+    case LSM6DSO_XL_NC_T_1_TAG:
+      *val = LSM6DSO_XL_NC_T_1_TAG;
+      break;
+
+    case LSM6DSO_XL_2XC_TAG:
+      *val = LSM6DSO_XL_2XC_TAG;
+      break;
+
+    case LSM6DSO_XL_3XC_TAG:
+      *val = LSM6DSO_XL_3XC_TAG;
+      break;
+
+    case LSM6DSO_GYRO_NC_T_2_TAG:
+      *val = LSM6DSO_GYRO_NC_T_2_TAG;
+      break;
+
+    case LSM6DSO_GYRO_NC_T_1_TAG:
+      *val = LSM6DSO_GYRO_NC_T_1_TAG;
+      break;
+
+    case LSM6DSO_GYRO_2XC_TAG:
+      *val = LSM6DSO_GYRO_2XC_TAG;
+      break;
+
+    case LSM6DSO_GYRO_3XC_TAG:
+      *val = LSM6DSO_GYRO_3XC_TAG;
+      break;
+
+    case LSM6DSO_SENSORHUB_SLAVE0_TAG:
+      *val = LSM6DSO_SENSORHUB_SLAVE0_TAG;
+      break;
+
+    case LSM6DSO_SENSORHUB_SLAVE1_TAG:
+      *val = LSM6DSO_SENSORHUB_SLAVE1_TAG;
+      break;
+
+    case LSM6DSO_SENSORHUB_SLAVE2_TAG:
+      *val = LSM6DSO_SENSORHUB_SLAVE2_TAG;
+      break;
+
+    case LSM6DSO_SENSORHUB_SLAVE3_TAG:
+      *val = LSM6DSO_SENSORHUB_SLAVE3_TAG;
+      break;
+
+    case LSM6DSO_STEP_CPUNTER_TAG:
+      *val = LSM6DSO_STEP_CPUNTER_TAG;
+      break;
+
+    case LSM6DSO_GAME_ROTATION_TAG:
+      *val = LSM6DSO_GAME_ROTATION_TAG;
+      break;
+
+    case LSM6DSO_GEOMAG_ROTATION_TAG:
+      *val = LSM6DSO_GEOMAG_ROTATION_TAG;
+      break;
+
+    case LSM6DSO_ROTATION_TAG:
+      *val = LSM6DSO_ROTATION_TAG;
+      break;
+
+    case LSM6DSO_SENSORHUB_NACK_TAG:
+      *val = LSM6DSO_SENSORHUB_NACK_TAG;
+      break;
+
+    default:
+      *val = LSM6DSO_GYRO_NC_TAG;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  :  Enable FIFO batching of pedometer embedded
+  *            function values.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of gbias_fifo_en in
+  *                  reg LSM6DSO_EMB_FUNC_FIFO_CFG
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_emb_func_fifo_cfg_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_FIFO_CFG,
+                           (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    reg.pedo_fifo_en = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_FIFO_CFG,
+                            (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Enable FIFO batching of pedometer embedded function values.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of pedo_fifo_en in
+  *                  reg LSM6DSO_EMB_FUNC_FIFO_CFG
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_emb_func_fifo_cfg_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_FIFO_CFG,
+                           (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    *val = reg.pedo_fifo_en;
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief   Enable FIFO batching data of first slave.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of  batch_ext_sens_0_en in
+  *                  reg SLV0_CONFIG
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_slv0_config_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    reg.batch_ext_sens_0_en = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Enable FIFO batching data of first slave.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of  batch_ext_sens_0_en in
+  *                  reg SLV0_CONFIG
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_slv0_config_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    *val = reg.batch_ext_sens_0_en;
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Enable FIFO batching data of second slave.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of  batch_ext_sens_1_en in
+  *                  reg SLV1_CONFIG
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_slv1_config_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    reg.batch_ext_sens_1_en = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief   Enable FIFO batching data of second slave.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of  batch_ext_sens_1_en in
+  *                  reg SLV1_CONFIG
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_slv1_config_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t *)&reg, 1);
+    *val = reg.batch_ext_sens_1_en;
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Enable FIFO batching data of third slave.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of  batch_ext_sens_2_en in
+  *                  reg SLV2_CONFIG
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_slv2_config_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV2_CONFIG, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    reg.batch_ext_sens_2_en = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV2_CONFIG, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Enable FIFO batching data of third slave.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of  batch_ext_sens_2_en in
+  *                  reg SLV2_CONFIG
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_slv2_config_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV2_CONFIG, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    *val = reg.batch_ext_sens_2_en;
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief   Enable FIFO batching data of fourth slave.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of  batch_ext_sens_3_en
+  *                  in reg SLV3_CONFIG
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_slv3_config_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV3_CONFIG, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    reg.batch_ext_sens_3_en = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV3_CONFIG, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Enable FIFO batching data of fourth slave.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of  batch_ext_sens_3_en in
+  *                  reg SLV3_CONFIG
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_slv3_config_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV3_CONFIG, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    *val = reg.batch_ext_sens_3_en;
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @}
+  *
+  */
+
+/**
+  * @defgroup  LSM6DSO_DEN_functionality
+  * @brief     This section groups all the functions concerning
+  *            DEN functionality.
+  * @{
+  *
+  */
+
+/**
+  * @brief  DEN functionality marking mode.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of den_mode in reg CTRL6_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_den_mode_set(stmdev_ctx_t *ctx,
+                             lsm6dso_den_mode_t val)
+{
+  lsm6dso_ctrl6_c_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.den_mode = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  DEN functionality marking mode.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of den_mode in reg CTRL6_C
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_den_mode_get(stmdev_ctx_t *ctx,
+                             lsm6dso_den_mode_t *val)
+{
+  lsm6dso_ctrl6_c_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)&reg, 1);
+
+  switch (reg.den_mode)
+  {
+    case LSM6DSO_DEN_DISABLE:
+      *val = LSM6DSO_DEN_DISABLE;
+      break;
+
+    case LSM6DSO_LEVEL_FIFO:
+      *val = LSM6DSO_LEVEL_FIFO;
+      break;
+
+    case LSM6DSO_LEVEL_LETCHED:
+      *val = LSM6DSO_LEVEL_LETCHED;
+      break;
+
+    case LSM6DSO_LEVEL_TRIGGER:
+      *val = LSM6DSO_LEVEL_TRIGGER;
+      break;
+
+    case LSM6DSO_EDGE_TRIGGER:
+      *val = LSM6DSO_EDGE_TRIGGER;
+      break;
+
+    default:
+      *val = LSM6DSO_DEN_DISABLE;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  DEN active level configuration.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of den_lh in reg CTRL9_XL
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_den_polarity_set(stmdev_ctx_t *ctx,
+                                 lsm6dso_den_lh_t val)
+{
+  lsm6dso_ctrl9_xl_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.den_lh = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  DEN active level configuration.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of den_lh in reg CTRL9_XL
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_den_polarity_get(stmdev_ctx_t *ctx,
+                                 lsm6dso_den_lh_t *val)
+{
+  lsm6dso_ctrl9_xl_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&reg, 1);
+
+  switch (reg.den_lh)
+  {
+    case LSM6DSO_DEN_ACT_LOW:
+      *val = LSM6DSO_DEN_ACT_LOW;
+      break;
+
+    case LSM6DSO_DEN_ACT_HIGH:
+      *val = LSM6DSO_DEN_ACT_HIGH;
+      break;
+
+    default:
+      *val = LSM6DSO_DEN_ACT_LOW;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  DEN enable.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of den_xl_g in reg CTRL9_XL
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_den_enable_set(stmdev_ctx_t *ctx,
+                               lsm6dso_den_xl_g_t val)
+{
+  lsm6dso_ctrl9_xl_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.den_xl_g = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  DEN enable.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of den_xl_g in reg CTRL9_XL
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_den_enable_get(stmdev_ctx_t *ctx,
+                               lsm6dso_den_xl_g_t *val)
+{
+  lsm6dso_ctrl9_xl_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&reg, 1);
+
+  switch (reg.den_xl_g)
+  {
+    case LSM6DSO_STAMP_IN_GY_DATA:
+      *val = LSM6DSO_STAMP_IN_GY_DATA;
+      break;
+
+    case LSM6DSO_STAMP_IN_XL_DATA:
+      *val = LSM6DSO_STAMP_IN_XL_DATA;
+      break;
+
+    case LSM6DSO_STAMP_IN_GY_XL_DATA:
+      *val = LSM6DSO_STAMP_IN_GY_XL_DATA;
+      break;
+
+    default:
+      *val = LSM6DSO_STAMP_IN_GY_DATA;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  DEN value stored in LSB of X-axis.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of den_z in reg CTRL9_XL
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_ctrl9_xl_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.den_z = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  DEN value stored in LSB of X-axis.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of den_z in reg CTRL9_XL
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_ctrl9_xl_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&reg, 1);
+  *val = reg.den_z;
+
+  return ret;
+}
+
+/**
+  * @brief  DEN value stored in LSB of Y-axis.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of den_y in reg CTRL9_XL
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_ctrl9_xl_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.den_y = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  DEN value stored in LSB of Y-axis.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of den_y in reg CTRL9_XL
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_ctrl9_xl_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&reg, 1);
+  *val = reg.den_y;
+
+  return ret;
+}
+
+/**
+  * @brief  DEN value stored in LSB of Z-axis.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of den_x in reg CTRL9_XL
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_ctrl9_xl_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&reg, 1);
+
+  if (ret == 0)
+  {
+    reg.den_x = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&reg, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  DEN value stored in LSB of Z-axis.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of den_x in reg CTRL9_XL
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_ctrl9_xl_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&reg, 1);
+  *val = reg.den_x;
+
+  return ret;
+}
+
+/**
+  * @}
+  *
+  */
+
+/**
+  * @defgroup  LSM6DSO_Pedometer
+  * @brief     This section groups all the functions that manage pedometer.
+  * @{
+  *
+  */
+
+/**
+  * @brief  Enable pedometer algorithm.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      turn on and configure pedometer
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_pedo_sens_set(stmdev_ctx_t *ctx,
+                              lsm6dso_pedo_md_t val)
+{
+  lsm6dso_pedo_cmd_reg_t pedo_cmd_reg;
+  int32_t ret;
+
+  ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_CMD_REG,
+                                (uint8_t *)&pedo_cmd_reg);
+
+  if (ret == 0)
+  {
+    pedo_cmd_reg.fp_rejection_en = ((uint8_t)val & 0x10U) >> 4;
+    pedo_cmd_reg.ad_det_en = ((uint8_t)val & 0x20U) >> 5;
+    ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_CMD_REG,
+                                   (uint8_t *)&pedo_cmd_reg);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Enable pedometer algorithm.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      turn on and configure pedometer
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_pedo_sens_get(stmdev_ctx_t *ctx,
+                              lsm6dso_pedo_md_t *val)
+{
+  lsm6dso_pedo_cmd_reg_t pedo_cmd_reg;
+  int32_t ret;
+
+  ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_CMD_REG,
+                                (uint8_t *)&pedo_cmd_reg);
+
+  switch ((pedo_cmd_reg.ad_det_en << 5) | (pedo_cmd_reg.fp_rejection_en
+                                           << 4))
+  {
+    case LSM6DSO_PEDO_BASE_MODE:
+      *val = LSM6DSO_PEDO_BASE_MODE;
+      break;
+
+    case LSM6DSO_FALSE_STEP_REJ:
+      *val = LSM6DSO_FALSE_STEP_REJ;
+      break;
+
+    case LSM6DSO_FALSE_STEP_REJ_ADV_MODE:
+      *val = LSM6DSO_FALSE_STEP_REJ_ADV_MODE;
+      break;
+
+    default:
+      *val = LSM6DSO_PEDO_BASE_MODE;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Interrupt status bit for step detection.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of is_step_det in reg EMB_FUNC_STATUS
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_emb_func_status_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    *val = reg.is_step_det;
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Pedometer debounce configuration register (r/w).[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  buff     buffer that contains data to write
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_pedo_debounce_steps_set(stmdev_ctx_t *ctx,
+                                        uint8_t *buff)
+{
+  int32_t ret;
+
+  ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_DEB_STEPS_CONF,
+                                 buff);
+
+  return ret;
+}
+
+/**
+  * @brief  Pedometer debounce configuration register (r/w).[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  buff     buffer that stores data read
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_pedo_debounce_steps_get(stmdev_ctx_t *ctx,
+                                        uint8_t *buff)
+{
+  int32_t ret;
+
+  ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_DEB_STEPS_CONF, buff);
+
+  return ret;
+}
+
+/**
+  * @brief  Time period register for step detection on delta time (r/w).[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  buff     buffer that contains data to write
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_pedo_steps_period_set(stmdev_ctx_t *ctx, uint16_t val)
+{
+  uint8_t buff[2];
+  int32_t ret;
+
+  buff[1] = (uint8_t)(val / 256U);
+  buff[0] = (uint8_t)(val - (buff[1] * 256U));
+  ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_SC_DELTAT_L,
+                                 &buff[0]);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_SC_DELTAT_H,
+                                   &buff[1]);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief   Time period register for step detection on delta time (r/w).[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  buff     buffer that stores data read
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_pedo_steps_period_get(stmdev_ctx_t *ctx,
+                                      uint16_t *val)
+{
+  uint8_t buff[2];
+  int32_t ret;
+
+  ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_SC_DELTAT_L,
+                                &buff[0]);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_SC_DELTAT_H,
+                                  &buff[1]);
+    *val = buff[1];
+    *val = (*val * 256U) +  buff[0];
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Set when user wants to generate interrupt on count overflow
+  *         event/every step.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of carry_count_en in reg PEDO_CMD_REG
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_pedo_int_mode_set(stmdev_ctx_t *ctx,
+                                  lsm6dso_carry_count_en_t val)
+{
+  lsm6dso_pedo_cmd_reg_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_CMD_REG,
+                                (uint8_t *)&reg);
+
+  if (ret == 0)
+  {
+    reg.carry_count_en = (uint8_t)val;
+    ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_CMD_REG,
+                                   (uint8_t *)&reg);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Set when user wants to generate interrupt on count overflow
+  *         event/every step.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of carry_count_en in reg PEDO_CMD_REG
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_pedo_int_mode_get(stmdev_ctx_t *ctx,
+                                  lsm6dso_carry_count_en_t *val)
+{
+  lsm6dso_pedo_cmd_reg_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_CMD_REG,
+                                (uint8_t *)&reg);
+
+  switch (reg.carry_count_en)
+  {
+    case LSM6DSO_EVERY_STEP:
+      *val = LSM6DSO_EVERY_STEP;
+      break;
+
+    case LSM6DSO_COUNT_OVERFLOW:
+      *val = LSM6DSO_COUNT_OVERFLOW;
+      break;
+
+    default:
+      *val = LSM6DSO_EVERY_STEP;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @}
+  *
+  */
+
+/**
+  * @defgroup  LSM6DSO_significant_motion
+  * @brief   This section groups all the functions that manage the
+  *          significant motion detection.
+  * @{
+  *
+  */
+
+/**
+  * @brief   Interrupt status bit for significant motion detection.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of is_sigmot in reg EMB_FUNC_STATUS
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_motion_flag_data_ready_get(stmdev_ctx_t *ctx,
+                                           uint8_t *val)
+{
+  lsm6dso_emb_func_status_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    *val = reg.is_sigmot;
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @}
+  *
+  */
+
+/**
+  * @defgroup  LSM6DSO_tilt_detection
+  * @brief     This section groups all the functions that manage the tilt
+  *            event detection.
+  * @{
+  *
+  */
+
+/**
+  * @brief  Interrupt status bit for tilt detection.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of is_tilt in reg EMB_FUNC_STATUS
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_tilt_flag_data_ready_get(stmdev_ctx_t *ctx,
+                                         uint8_t *val)
+{
+  lsm6dso_emb_func_status_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    *val = reg.is_tilt;
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @}
+  *
+  */
+
+/**
+  * @defgroup  LSM6DSO_ magnetometer_sensor
+  * @brief     This section groups all the functions that manage additional
+  *            magnetometer sensor.
+  * @{
+  *
+  */
+
+/**
+  * @brief  External magnetometer sensitivity value register.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  buff     buffer that contains data to write
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val)
+{
+  uint8_t buff[2];
+  int32_t ret;
+
+  buff[1] = (uint8_t)(val / 256U);
+  buff[0] = (uint8_t)(val - (buff[1] * 256U));
+  ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SENSITIVITY_L,
+                                 &buff[0]);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SENSITIVITY_H,
+                                   &buff[1]);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  External magnetometer sensitivity value register.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  buff     buffer that stores data read
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val)
+{
+  uint8_t buff[2];
+  int32_t ret;
+
+  ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SENSITIVITY_L,
+                                &buff[0]);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SENSITIVITY_H,
+                                  &buff[1]);
+    *val = buff[1];
+    *val = (*val * 256U) +  buff[0];
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Offset for hard-iron compensation register (r/w).[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  buff     buffer that contains data to write
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val)
+{
+  uint8_t buff[6];
+  int32_t ret;
+
+  buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
+  buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
+  buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
+  buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
+  buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
+  buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
+  ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFX_L, &buff[0]);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFX_H, &buff[1]);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFY_L, &buff[2]);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFY_H, &buff[3]);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFZ_L, &buff[4]);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFZ_H, &buff[5]);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Offset for hard-iron compensation register (r/w).[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  buff     buffer that stores data read
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val)
+{
+  uint8_t buff[6];
+  int32_t ret;
+
+  ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFX_L, &buff[0]);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFX_H, &buff[1]);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFY_L, &buff[2]);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFY_H, &buff[3]);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFZ_L, &buff[4]);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFZ_H, &buff[5]);
+    val[0] = (int16_t)buff[1];
+    val[0] = (val[0] * 256) + (int16_t)buff[0];
+    val[1] = (int16_t)buff[3];
+    val[1] = (val[1] * 256) + (int16_t)buff[2];
+    val[2] = (int16_t)buff[5];
+    val[2] = (val[2] * 256) + (int16_t)buff[4];
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Soft-iron (3x3 symmetric) matrix correction
+  *         register (r/w). The value is expressed as
+  *         half-precision floating-point format:
+  *         SEEEEEFFFFFFFFFF
+  *         S: 1 sign bit;
+  *         E: 5 exponent bits;
+  *         F: 10 fraction bits).[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  buff     buffer that contains data to write
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_mag_soft_iron_set(stmdev_ctx_t *ctx, int16_t *val)
+{
+  uint8_t buff[12];
+  int32_t ret;
+
+  uint8_t index;
+  buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
+  buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
+  buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
+  buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
+  buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
+  buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
+  buff[7] = (uint8_t)((uint16_t)val[3] / 256U);
+  buff[6] = (uint8_t)((uint16_t)val[3] - (buff[7] * 256U));
+  buff[9] = (uint8_t)((uint16_t)val[4] / 256U);
+  buff[8] = (uint8_t)((uint16_t)val[4] - (buff[9] * 256U));
+  buff[11] = (uint8_t)((uint16_t)val[5] / 256U);
+  buff[10] = (uint8_t)((uint16_t)val[5] - (buff[11] * 256U));
+  index = 0x00U;
+  ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XX_L,
+                                 &buff[index]);
+
+  if (ret == 0)
+  {
+    index++;
+    ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XX_H,
+                                   &buff[index]);
+  }
+
+  if (ret == 0)
+  {
+    index++;
+    ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XY_L,
+                                   &buff[index]);
+  }
+
+  if (ret == 0)
+  {
+    index++;
+    ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XY_H,
+                                   &buff[index]);
+  }
+
+  if (ret == 0)
+  {
+    index++;
+    ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XZ_L,
+                                   &buff[index]);
+  }
+
+  if (ret == 0)
+  {
+    index++;
+    ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XZ_H,
+                                   &buff[index]);
+  }
+
+  if (ret == 0)
+  {
+    index++;
+    ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_YY_L,
+                                   &buff[index]);
+  }
+
+  if (ret == 0)
+  {
+    index++;
+    ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_YY_H,
+                                   &buff[index]);
+  }
+
+  if (ret == 0)
+  {
+    index++;
+    ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_YZ_L,
+                                   &buff[index]);
+  }
+
+  if (ret == 0)
+  {
+    index++;
+    ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_YZ_H,
+                                   &buff[index]);
+  }
+
+  if (ret == 0)
+  {
+    index++;
+    ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_ZZ_L,
+                                   &buff[index]);
+  }
+
+  if (ret == 0)
+  {
+    index++;
+    ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_ZZ_H,
+                                   &buff[index]);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Soft-iron (3x3 symmetric) matrix
+  *         correction register (r/w).
+  *         The value is expressed as half-precision
+  *         floating-point format:
+  *         SEEEEEFFFFFFFFFF
+  *         S: 1 sign bit;
+  *         E: 5 exponent bits;
+  *         F: 10 fraction bits.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  buff     buffer that stores data read
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_mag_soft_iron_get(stmdev_ctx_t *ctx, int16_t *val)
+{
+  uint8_t buff[12];
+  int32_t ret;
+
+  uint8_t index;
+  index = 0x00U;
+  ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XX_L, &buff[index]);
+
+  if (ret == 0)
+  {
+    index++;
+    ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XX_H, &buff[index]);
+  }
+
+  if (ret == 0)
+  {
+    index++;
+    ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XY_L, &buff[index]);
+  }
+
+  if (ret == 0)
+  {
+    index++;
+    ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XY_H, &buff[index]);
+  }
+
+  if (ret == 0)
+  {
+    index++;
+    ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XZ_L, &buff[index]);
+  }
+
+  if (ret == 0)
+  {
+    index++;
+    ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XZ_H, &buff[index]);
+  }
+
+  if (ret == 0)
+  {
+    index++;
+    ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_YY_L, &buff[index]);
+  }
+
+  if (ret == 0)
+  {
+    index++;
+    ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_YY_H, &buff[index]);
+  }
+
+  if (ret == 0)
+  {
+    index++;
+    ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_YZ_L, &buff[index]);
+  }
+
+  if (ret == 0)
+  {
+    index++;
+    ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_YZ_H, &buff[index]);
+  }
+
+  if (ret == 0)
+  {
+    index++;
+    ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_ZZ_L, &buff[index]);
+  }
+
+  if (ret == 0)
+  {
+    index++;
+    ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_ZZ_H, &buff[index]);
+  }
+
+  val[0] = (int16_t)buff[1];
+  val[0] = (val[0] * 256) + (int16_t)buff[0];
+  val[1] = (int16_t)buff[3];
+  val[1] = (val[1] * 256) + (int16_t)buff[2];
+  val[2] = (int16_t)buff[5];
+  val[2] = (val[2] * 256) + (int16_t)buff[4];
+  val[3] = (int16_t)buff[7];
+  val[3] = (val[3] * 256) + (int16_t)buff[6];
+  val[4] = (int16_t)buff[9];
+  val[4] = (val[4] * 256) + (int16_t)buff[8];
+  val[5] = (int16_t)buff[11];
+  val[5] = (val[5] * 256) + (int16_t)buff[10];
+
+  return ret;
+}
+
+/**
+  * @brief  Magnetometer Z-axis coordinates
+  *         rotation (to be aligned to
+  *         accelerometer/gyroscope axes
+  *         orientation).[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of mag_z_axis in reg MAG_CFG_A
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_mag_z_orient_set(stmdev_ctx_t *ctx,
+                                 lsm6dso_mag_z_axis_t val)
+{
+  lsm6dso_mag_cfg_a_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A,
+                                (uint8_t *)&reg);
+
+  if (ret == 0)
+  {
+    reg.mag_z_axis = (uint8_t) val;
+    ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_CFG_A,
+                                   (uint8_t *)&reg);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Magnetometer Z-axis coordinates
+  *         rotation (to be aligned to
+  *         accelerometer/gyroscope axes
+  *         orientation).[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of mag_z_axis in reg MAG_CFG_A
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_mag_z_orient_get(stmdev_ctx_t *ctx,
+                                 lsm6dso_mag_z_axis_t *val)
+{
+  lsm6dso_mag_cfg_a_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A,
+                                (uint8_t *)&reg);
+
+  switch (reg.mag_z_axis)
+  {
+    case LSM6DSO_Z_EQ_Y:
+      *val = LSM6DSO_Z_EQ_Y;
+      break;
+
+    case LSM6DSO_Z_EQ_MIN_Y:
+      *val = LSM6DSO_Z_EQ_MIN_Y;
+      break;
+
+    case LSM6DSO_Z_EQ_X:
+      *val = LSM6DSO_Z_EQ_X;
+      break;
+
+    case LSM6DSO_Z_EQ_MIN_X:
+      *val = LSM6DSO_Z_EQ_MIN_X;
+      break;
+
+    case LSM6DSO_Z_EQ_MIN_Z:
+      *val = LSM6DSO_Z_EQ_MIN_Z;
+      break;
+
+    case LSM6DSO_Z_EQ_Z:
+      *val = LSM6DSO_Z_EQ_Z;
+      break;
+
+    default:
+      *val = LSM6DSO_Z_EQ_Y;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief   Magnetometer Y-axis coordinates
+  *          rotation (to be aligned to
+  *          accelerometer/gyroscope axes
+  *          orientation).[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of mag_y_axis in reg MAG_CFG_A
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_mag_y_orient_set(stmdev_ctx_t *ctx,
+                                 lsm6dso_mag_y_axis_t val)
+{
+  lsm6dso_mag_cfg_a_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A,
+                                (uint8_t *)&reg);
+
+  if (ret == 0)
+  {
+    reg.mag_y_axis = (uint8_t)val;
+    ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_CFG_A,
+                                   (uint8_t *) &reg);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Magnetometer Y-axis coordinates
+  *         rotation (to be aligned to
+  *         accelerometer/gyroscope axes
+  *         orientation).[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of mag_y_axis in reg MAG_CFG_A
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_mag_y_orient_get(stmdev_ctx_t *ctx,
+                                 lsm6dso_mag_y_axis_t *val)
+{
+  lsm6dso_mag_cfg_a_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A,
+                                (uint8_t *)&reg);
+
+  switch (reg.mag_y_axis)
+  {
+    case LSM6DSO_Y_EQ_Y:
+      *val = LSM6DSO_Y_EQ_Y;
+      break;
+
+    case LSM6DSO_Y_EQ_MIN_Y:
+      *val = LSM6DSO_Y_EQ_MIN_Y;
+      break;
+
+    case LSM6DSO_Y_EQ_X:
+      *val = LSM6DSO_Y_EQ_X;
+      break;
+
+    case LSM6DSO_Y_EQ_MIN_X:
+      *val = LSM6DSO_Y_EQ_MIN_X;
+      break;
+
+    case LSM6DSO_Y_EQ_MIN_Z:
+      *val = LSM6DSO_Y_EQ_MIN_Z;
+      break;
+
+    case LSM6DSO_Y_EQ_Z:
+      *val = LSM6DSO_Y_EQ_Z;
+      break;
+
+    default:
+      *val = LSM6DSO_Y_EQ_Y;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Magnetometer X-axis coordinates
+  *         rotation (to be aligned to
+  *         accelerometer/gyroscope axes
+  *         orientation).[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of mag_x_axis in reg MAG_CFG_B
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_mag_x_orient_set(stmdev_ctx_t *ctx,
+                                 lsm6dso_mag_x_axis_t val)
+{
+  lsm6dso_mag_cfg_b_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_B,
+                                (uint8_t *)&reg);
+
+  if (ret == 0)
+  {
+    reg.mag_x_axis = (uint8_t)val;
+    ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_CFG_B,
+                                   (uint8_t *)&reg);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief   Magnetometer X-axis coordinates
+  *          rotation (to be aligned to
+  *          accelerometer/gyroscope axes
+  *          orientation).[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of mag_x_axis in reg MAG_CFG_B
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_mag_x_orient_get(stmdev_ctx_t *ctx,
+                                 lsm6dso_mag_x_axis_t *val)
+{
+  lsm6dso_mag_cfg_b_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_B,
+                                (uint8_t *)&reg);
+
+  switch (reg.mag_x_axis)
+  {
+    case LSM6DSO_X_EQ_Y:
+      *val = LSM6DSO_X_EQ_Y;
+      break;
+
+    case LSM6DSO_X_EQ_MIN_Y:
+      *val = LSM6DSO_X_EQ_MIN_Y;
+      break;
+
+    case LSM6DSO_X_EQ_X:
+      *val = LSM6DSO_X_EQ_X;
+      break;
+
+    case LSM6DSO_X_EQ_MIN_X:
+      *val = LSM6DSO_X_EQ_MIN_X;
+      break;
+
+    case LSM6DSO_X_EQ_MIN_Z:
+      *val = LSM6DSO_X_EQ_MIN_Z;
+      break;
+
+    case LSM6DSO_X_EQ_Z:
+      *val = LSM6DSO_X_EQ_Z;
+      break;
+
+    default:
+      *val = LSM6DSO_X_EQ_Y;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @}
+  *
+  */
+
+/**
+  * @defgroup  LSM6DSO_finite_state_machine
+  * @brief     This section groups all the functions that manage the
+  *            state_machine.
+  * @{
+  *
+  */
+
+/**
+  * @brief   Interrupt status bit for FSM long counter
+  *          timeout interrupt event.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of is_fsm_lc in reg EMB_FUNC_STATUS
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx,
+                                             uint8_t *val)
+{
+  lsm6dso_emb_func_status_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    *val = reg.is_fsm_lc;
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Final State Machine enable.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      union of registers from FSM_ENABLE_A to FSM_ENABLE_B
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_fsm_enable_set(stmdev_ctx_t *ctx,
+                               lsm6dso_emb_fsm_enable_t *val)
+{
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_ENABLE_A,
+                            (uint8_t *)&val->fsm_enable_a, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_ENABLE_B,
+                            (uint8_t *)&val->fsm_enable_b, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Final State Machine enable.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      union of registers from FSM_ENABLE_A to FSM_ENABLE_B
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_fsm_enable_get(stmdev_ctx_t *ctx,
+                               lsm6dso_emb_fsm_enable_t *val)
+{
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_ENABLE_A, (uint8_t *) val, 2);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  FSM long counter status register. Long counter value is an
+  *         unsigned integer value (16-bit format).[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  buff     buffer that contains data to write
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val)
+{
+  uint8_t buff[2];
+  int32_t ret;
+
+  buff[1] = (uint8_t)(val / 256U);
+  buff[0] = (uint8_t)(val - (buff[1] * 256U));
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_L, buff, 2);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  FSM long counter status register. Long counter value is an
+  *         unsigned integer value (16-bit format).[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  buff     buffer that stores data read
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val)
+{
+  uint8_t buff[2];
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_L, buff, 2);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+    *val = buff[1];
+    *val = (*val * 256U) +  buff[0];
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Clear FSM long counter value.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of fsm_lc_clr in
+  *                  reg FSM_LONG_COUNTER_CLEAR
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_long_clr_set(stmdev_ctx_t *ctx,
+                             lsm6dso_fsm_lc_clr_t val)
+{
+  lsm6dso_fsm_long_counter_clear_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_CLEAR,
+                           (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    reg. fsm_lc_clr = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_CLEAR,
+                            (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Clear FSM long counter value.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of fsm_lc_clr in
+  *                  reg FSM_LONG_COUNTER_CLEAR
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_long_clr_get(stmdev_ctx_t *ctx,
+                             lsm6dso_fsm_lc_clr_t *val)
+{
+  lsm6dso_fsm_long_counter_clear_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_CLEAR,
+                           (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    switch (reg.fsm_lc_clr)
+    {
+      case LSM6DSO_LC_NORMAL:
+        *val = LSM6DSO_LC_NORMAL;
+        break;
+
+      case LSM6DSO_LC_CLEAR:
+        *val = LSM6DSO_LC_CLEAR;
+        break;
+
+      case LSM6DSO_LC_CLEAR_DONE:
+        *val = LSM6DSO_LC_CLEAR_DONE;
+        break;
+
+      default:
+        *val = LSM6DSO_LC_NORMAL;
+        break;
+    }
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  FSM output registers[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      struct of registers from FSM_OUTS1 to FSM_OUTS16
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_fsm_out_get(stmdev_ctx_t *ctx, lsm6dso_fsm_out_t *val)
+{
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_OUTS1, (uint8_t *)val, 16);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Finite State Machine ODR configuration.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_fsm_data_rate_set(stmdev_ctx_t *ctx,
+                                  lsm6dso_fsm_odr_t val)
+{
+  lsm6dso_emb_func_odr_cfg_b_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_ODR_CFG_B,
+                           (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    reg.not_used_01 = 3; /* set default values */
+    reg.not_used_02 = 2; /* set default values */
+    reg.fsm_odr = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_ODR_CFG_B,
+                            (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Finite State Machine ODR configuration.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_fsm_data_rate_get(stmdev_ctx_t *ctx,
+                                  lsm6dso_fsm_odr_t *val)
+{
+  lsm6dso_emb_func_odr_cfg_b_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_ODR_CFG_B,
+                           (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    switch (reg.fsm_odr)
+    {
+      case LSM6DSO_ODR_FSM_12Hz5:
+        *val = LSM6DSO_ODR_FSM_12Hz5;
+        break;
+
+      case LSM6DSO_ODR_FSM_26Hz:
+        *val = LSM6DSO_ODR_FSM_26Hz;
+        break;
+
+      case LSM6DSO_ODR_FSM_52Hz:
+        *val = LSM6DSO_ODR_FSM_52Hz;
+        break;
+
+      case LSM6DSO_ODR_FSM_104Hz:
+        *val = LSM6DSO_ODR_FSM_104Hz;
+        break;
+
+      default:
+        *val = LSM6DSO_ODR_FSM_12Hz5;
+        break;
+    }
+
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  FSM initialization request.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of fsm_init in reg FSM_INIT
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_emb_func_init_b_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    reg.fsm_init = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  FSM initialization request.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of fsm_init in reg FSM_INIT
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_emb_func_init_b_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    *val = reg.fsm_init;
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  FSM long counter timeout register (r/w). The long counter
+  *         timeout value is an unsigned integer value (16-bit format).
+  *         When the long counter value reached this value,
+  *         the FSM generates an interrupt.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      the value of long counter
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_long_cnt_int_value_set(stmdev_ctx_t *ctx,
+                                       uint16_t val)
+{
+  uint8_t buff[2];
+  int32_t ret;
+
+  buff[1] = (uint8_t)(val / 256U);
+  buff[0] = (uint8_t)(val - (buff[1] * 256U));
+  ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_L,
+                                 &buff[0]);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_H,
+                                   &buff[1]);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  FSM long counter timeout register (r/w). The long counter
+  *         timeout value is an unsigned integer value (16-bit format).
+  *         When the long counter value reached this value,
+  *         the FSM generates an interrupt.[get]
+  *
+  * @param  ctx     read / write interface definitions
+  * @param  val     buffer that stores the value of long counter
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_long_cnt_int_value_get(stmdev_ctx_t *ctx,
+                                       uint16_t *val)
+{
+  uint8_t buff[2];
+  int32_t ret;
+
+  ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_L,
+                                &buff[0]);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_H,
+                                  &buff[1]);
+    *val = buff[1];
+    *val = (*val * 256U) +  buff[0];
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  FSM number of programs register.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      value to write
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_fsm_number_of_programs_set(stmdev_ctx_t *ctx,
+                                           uint8_t val)
+{
+  int32_t ret;
+
+  ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_PROGRAMS, &val);
+
+  return ret;
+}
+
+/**
+  * @brief  FSM number of programs register.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      buffer that stores data read.
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_fsm_number_of_programs_get(stmdev_ctx_t *ctx,
+                                           uint8_t *val)
+{
+  int32_t ret;
+
+  ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_PROGRAMS, val);
+
+  return ret;
+}
+
+/**
+  * @brief  FSM start address register (r/w).
+  *         First available address is 0x033C.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      the value of start address
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val)
+{
+  uint8_t buff[2];
+  int32_t ret;
+
+  buff[1] = (uint8_t)(val / 256U);
+  buff[0] = (uint8_t)(val - (buff[1] * 256U));
+  ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_START_ADD_L,
+                                 &buff[0]);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_START_ADD_H,
+                                   &buff[1]);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  FSM start address register (r/w).
+  *         First available address is 0x033C.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      buffer the value of start address.
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_fsm_start_address_get(stmdev_ctx_t *ctx,
+                                      uint16_t *val)
+{
+  uint8_t buff[2];
+  int32_t ret;
+
+  ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_START_ADD_L, &buff[0]);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_START_ADD_H, &buff[1]);
+    *val = buff[1];
+    *val = (*val * 256U) +  buff[0];
+  }
+
+  return ret;
+}
+
+/**
+  * @}
+  *
+  */
+
+/**
+  * @defgroup  LSM6DSO_Sensor_hub
+  * @brief     This section groups all the functions that manage the
+  *            sensor hub.
+  * @{
+  *
+  */
+
+/**
+  * @brief  Sensor hub output registers.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      values read from registers SENSOR_HUB_1 to SENSOR_HUB_18
+  * @param  len      number of consecutive register to read (max 18)
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_sh_read_data_raw_get(stmdev_ctx_t *ctx, uint8_t *val,
+                                     uint8_t len)
+{
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_SENSOR_HUB_1, (uint8_t *) val,
+                           len);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Number of external sensors to be read by the sensor hub.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of aux_sens_on in reg MASTER_CONFIG
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_sh_slave_connected_set(stmdev_ctx_t *ctx,
+                                       lsm6dso_aux_sens_on_t val)
+{
+  lsm6dso_master_config_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    reg.aux_sens_on = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Number of external sensors to be read by the sensor hub.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of aux_sens_on in reg MASTER_CONFIG
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_sh_slave_connected_get(stmdev_ctx_t *ctx,
+                                       lsm6dso_aux_sens_on_t *val)
+{
+  lsm6dso_master_config_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    switch (reg.aux_sens_on)
+    {
+      case LSM6DSO_SLV_0:
+        *val = LSM6DSO_SLV_0;
+        break;
+
+      case LSM6DSO_SLV_0_1:
+        *val = LSM6DSO_SLV_0_1;
+        break;
+
+      case LSM6DSO_SLV_0_1_2:
+        *val = LSM6DSO_SLV_0_1_2;
+        break;
+
+      case LSM6DSO_SLV_0_1_2_3:
+        *val = LSM6DSO_SLV_0_1_2_3;
+        break;
+
+      default:
+        *val = LSM6DSO_SLV_0;
+        break;
+    }
+
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Sensor hub I2C master enable.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of master_on in reg MASTER_CONFIG
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_sh_master_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_master_config_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    reg.master_on = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Sensor hub I2C master enable.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of master_on in reg MASTER_CONFIG
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_master_config_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    *val = reg.master_on;
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Master I2C pull-up enable.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of shub_pu_en in reg MASTER_CONFIG
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_sh_pin_mode_set(stmdev_ctx_t *ctx,
+                                lsm6dso_shub_pu_en_t val)
+{
+  lsm6dso_master_config_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    reg.shub_pu_en = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Master I2C pull-up enable.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of shub_pu_en in reg MASTER_CONFIG
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_sh_pin_mode_get(stmdev_ctx_t *ctx,
+                                lsm6dso_shub_pu_en_t *val)
+{
+  lsm6dso_master_config_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    switch (reg.shub_pu_en)
+    {
+      case LSM6DSO_EXT_PULL_UP:
+        *val = LSM6DSO_EXT_PULL_UP;
+        break;
+
+      case LSM6DSO_INTERNAL_PULL_UP:
+        *val = LSM6DSO_INTERNAL_PULL_UP;
+        break;
+
+      default:
+        *val = LSM6DSO_EXT_PULL_UP;
+        break;
+    }
+
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  I2C interface pass-through.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of pass_through_mode in
+  *                  reg MASTER_CONFIG
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val)
+{
+  lsm6dso_master_config_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    reg.pass_through_mode = val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  I2C interface pass-through.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of pass_through_mode in
+  *                  reg MASTER_CONFIG
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_master_config_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    *val = reg.pass_through_mode;
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Sensor hub trigger signal selection.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of start_config in reg MASTER_CONFIG
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_sh_syncro_mode_set(stmdev_ctx_t *ctx,
+                                   lsm6dso_start_config_t val)
+{
+  lsm6dso_master_config_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    reg.start_config = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Sensor hub trigger signal selection.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of start_config in reg MASTER_CONFIG
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_sh_syncro_mode_get(stmdev_ctx_t *ctx,
+                                   lsm6dso_start_config_t *val)
+{
+  lsm6dso_master_config_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    switch (reg.start_config)
+    {
+      case LSM6DSO_EXT_ON_INT2_PIN:
+        *val = LSM6DSO_EXT_ON_INT2_PIN;
+        break;
+
+      case LSM6DSO_XL_GY_DRDY:
+        *val = LSM6DSO_XL_GY_DRDY;
+        break;
+
+      default:
+        *val = LSM6DSO_EXT_ON_INT2_PIN;
+        break;
+    }
+
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Slave 0 write operation is performed only at the first
+  *         sensor hub cycle.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of write_once in reg MASTER_CONFIG
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_sh_write_mode_set(stmdev_ctx_t *ctx,
+                                  lsm6dso_write_once_t val)
+{
+  lsm6dso_master_config_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    reg.write_once = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Slave 0 write operation is performed only at the first sensor
+  *         hub cycle.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of write_once in reg MASTER_CONFIG
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_sh_write_mode_get(stmdev_ctx_t *ctx,
+                                  lsm6dso_write_once_t *val)
+{
+  lsm6dso_master_config_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    switch (reg.write_once)
+    {
+      case LSM6DSO_EACH_SH_CYCLE:
+        *val = LSM6DSO_EACH_SH_CYCLE;
+        break;
+
+      case LSM6DSO_ONLY_FIRST_CYCLE:
+        *val = LSM6DSO_ONLY_FIRST_CYCLE;
+        break;
+
+      default:
+        *val = LSM6DSO_EACH_SH_CYCLE;
+        break;
+    }
+
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Reset Master logic and output registers.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_sh_reset_set(stmdev_ctx_t *ctx)
+{
+  lsm6dso_master_config_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    reg.rst_master_regs = PROPERTY_ENABLE;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    reg.rst_master_regs = PROPERTY_DISABLE;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Reset Master logic and output registers.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of rst_master_regs in reg MASTER_CONFIG
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
+{
+  lsm6dso_master_config_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    *val = reg.rst_master_regs;
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Rate at which the master communicates.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of shub_odr in reg slv1_CONFIG
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_sh_data_rate_set(stmdev_ctx_t *ctx,
+                                 lsm6dso_shub_odr_t val)
+{
+  lsm6dso_slv0_config_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    reg.shub_odr = (uint8_t)val;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Rate at which the master communicates.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Get the values of shub_odr in reg slv1_CONFIG
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_sh_data_rate_get(stmdev_ctx_t *ctx,
+                                 lsm6dso_shub_odr_t *val)
+{
+  lsm6dso_slv0_config_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    switch (reg.shub_odr)
+    {
+      case LSM6DSO_SH_ODR_104Hz:
+        *val = LSM6DSO_SH_ODR_104Hz;
+        break;
+
+      case LSM6DSO_SH_ODR_52Hz:
+        *val = LSM6DSO_SH_ODR_52Hz;
+        break;
+
+      case LSM6DSO_SH_ODR_26Hz:
+        *val = LSM6DSO_SH_ODR_26Hz;
+        break;
+
+      case LSM6DSO_SH_ODR_13Hz:
+        *val = LSM6DSO_SH_ODR_13Hz;
+        break;
+
+      default:
+        *val = LSM6DSO_SH_ODR_104Hz;
+        break;
+    }
+
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Configure slave 0 for perform a write.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      a structure that contain
+  *                      - uint8_t slv1_add;    8 bit i2c device address
+  *                      - uint8_t slv1_subadd; 8 bit register device address
+  *                      - uint8_t slv1_data;   8 bit data to write
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_sh_cfg_write(stmdev_ctx_t *ctx,
+                             lsm6dso_sh_cfg_write_t *val)
+{
+  lsm6dso_slv0_add_t reg;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
+
+  if (ret == 0)
+  {
+    reg.slave0 = val->slv0_add;
+    reg.rw_0 = 0;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_ADD, (uint8_t *)&reg, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_SUBADD,
+                            &(val->slv0_subadd), 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_DATAWRITE_SLV0,
+                            &(val->slv0_data), 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Configure slave 0 for perform a read.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Structure that contain
+  *                      - uint8_t slv1_add;    8 bit i2c device address
+  *                      - uint8_t slv1_subadd; 8 bit register device address
+  *                      - uint8_t slv1_len;    num of bit to read
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
+                                 lsm6dso_sh_cfg_read_t *val)
+{
+  lsm6dso_slv0_add_t slv0_add;
+  lsm6dso_slv0_config_t slv0_config;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
+
+  if (ret == 0)
+  {
+    slv0_add.slave0 = val->slv_add;
+    slv0_add.rw_0 = 1;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_ADD, (uint8_t *)&slv0_add, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_SUBADD,
+                            &(val->slv_subadd), 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV0_CONFIG,
+                           (uint8_t *)&slv0_config, 1);
+  }
+
+  if (ret == 0)
+  {
+    slv0_config.slave0_numop = val->slv_len;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_CONFIG,
+                            (uint8_t *)&slv0_config, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Configure slave 0 for perform a write/read.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Structure that contain
+  *                      - uint8_t slv1_add;    8 bit i2c device address
+  *                      - uint8_t slv1_subadd; 8 bit register device address
+  *                      - uint8_t slv1_len;    num of bit to read
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
+                                 lsm6dso_sh_cfg_read_t *val)
+{
+  lsm6dso_slv1_add_t slv1_add;
+  lsm6dso_slv1_config_t slv1_config;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
+
+  if (ret == 0)
+  {
+    slv1_add.slave1_add = val->slv_add;
+    slv1_add.r_1 = 1;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_ADD, (uint8_t *)&slv1_add, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_SUBADD,
+                            &(val->slv_subadd), 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV1_CONFIG,
+                           (uint8_t *)&slv1_config, 1);
+  }
+
+  if (ret == 0)
+  {
+    slv1_config.slave1_numop = val->slv_len;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_CONFIG,
+                            (uint8_t *)&slv1_config, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Configure slave 0 for perform a write/read.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Structure that contain
+  *                      - uint8_t slv2_add;    8 bit i2c device address
+  *                      - uint8_t slv2_subadd; 8 bit register device address
+  *                      - uint8_t slv2_len;    num of bit to read
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
+                                 lsm6dso_sh_cfg_read_t *val)
+{
+  lsm6dso_slv2_add_t slv2_add;
+  lsm6dso_slv2_config_t slv2_config;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
+
+  if (ret == 0)
+  {
+    slv2_add.slave2_add = val->slv_add;
+    slv2_add.r_2 = 1;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV2_ADD, (uint8_t *)&slv2_add, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV2_SUBADD,
+                            &(val->slv_subadd), 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV2_CONFIG,
+                           (uint8_t *)&slv2_config, 1);
+  }
+
+  if (ret == 0)
+  {
+    slv2_config.slave2_numop = val->slv_len;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV2_CONFIG,
+                            (uint8_t *)&slv2_config, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief Configure slave 0 for perform a write/read.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      Structure that contain
+  *                      - uint8_t slv3_add;    8 bit i2c device address
+  *                      - uint8_t slv3_subadd; 8 bit register device address
+  *                      - uint8_t slv3_len;    num of bit to read
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
+                                 lsm6dso_sh_cfg_read_t *val)
+{
+  lsm6dso_slv3_add_t slv3_add;
+  lsm6dso_slv3_config_t slv3_config;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
+
+  if (ret == 0)
+  {
+    slv3_add.slave3_add = val->slv_add;
+    slv3_add.r_3 = 1;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV3_ADD, (uint8_t *)&slv3_add, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV3_SUBADD,
+                            &(val->slv_subadd), 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV3_CONFIG,
+                           (uint8_t *)&slv3_config, 1);
+  }
+
+  if (ret == 0)
+  {
+    slv3_config.slave3_numop = val->slv_len;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV3_CONFIG,
+                            (uint8_t *)&slv3_config, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Sensor hub source register.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      union of registers from STATUS_MASTER to
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_sh_status_get(stmdev_ctx_t *ctx,
+                              lsm6dso_status_master_t *val)
+{
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_MASTER, (uint8_t *) val, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @}
+  *
+  */
+
+/**
+  * @defgroup  Basic configuration
+  * @brief     This section groups all the functions concerning
+  *            device basic configuration.
+  * @{
+  *
+  */
+
+/**
+  * @brief  Device "Who am I".[get]
+  *
+  * @param  ctx          communication interface handler. Use NULL to ignore
+  *                      this interface.(ptr)
+  * @param  aux_ctx      auxiliary communication interface handler. Use NULL
+  *                      to ignore this interface.(ptr)
+  * @param  val          ID values read from the two interfaces. ID values
+  *                      will be the same.(ptr)
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_id_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
+                       lsm6dso_id_t *val)
+{
+  int32_t ret = 0;
+
+  if (ctx != NULL)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_WHO_AM_I,
+                           (uint8_t *) & (val->ui), 1);
+  }
+
+  if (aux_ctx != NULL)
+  {
+    if (ret == 0)
+    {
+      ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_WHO_AM_I,
+                             (uint8_t *) & (val->aux), 1);
+    }
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Re-initialize the device.[set]
+  *
+  * @param  ctx          communication interface handler.(ptr)
+  * @param  val          re-initialization mode. Refer to datasheet
+  *                      and application note for more information
+  *                      about differencies between boot and sw_reset
+  *                      procedure.
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_init_set(stmdev_ctx_t *ctx, lsm6dso_init_t val)
+{
+  lsm6dso_emb_func_init_a_t emb_func_init_a;
+  lsm6dso_emb_func_init_b_t emb_func_init_b;
+  lsm6dso_ctrl3_c_t ctrl3_c;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B,
+                           (uint8_t *)&emb_func_init_b, 1);
+  }
+
+  if (ret == 0)
+  {
+    emb_func_init_b.fifo_compr_init = (uint8_t)val
+                                      & ((uint8_t)LSM6DSO_FIFO_COMP >> 2);
+    emb_func_init_b.fsm_init = (uint8_t)val
+                               & ((uint8_t)LSM6DSO_FSM >> 3);
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B,
+                            (uint8_t *)&emb_func_init_b, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_A,
+                           (uint8_t *)&emb_func_init_a, 1);
+  }
+
+  if (ret == 0)
+  {
+    emb_func_init_a.step_det_init = ((uint8_t)val
+                                     & (uint8_t)LSM6DSO_PEDO) >> 5;
+    emb_func_init_a.tilt_init = ((uint8_t)val
+                                 & (uint8_t)LSM6DSO_TILT) >> 6;
+    emb_func_init_a.sig_mot_init = ((uint8_t)val
+                                    & (uint8_t)LSM6DSO_SMOTION) >> 7;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INIT_A,
+                            (uint8_t *)&emb_func_init_a, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+  }
+
+  if (((val == LSM6DSO_BOOT) || (val == LSM6DSO_RESET)) &&
+      (ret == 0))
+  {
+    ctrl3_c.boot = (uint8_t)val & (uint8_t)LSM6DSO_BOOT;
+    ctrl3_c.sw_reset = ((uint8_t)val & (uint8_t)LSM6DSO_RESET) >> 1;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+  }
+
+  if ((val == LSM6DSO_DRV_RDY)
+      && ((ctrl3_c.bdu == PROPERTY_DISABLE)
+          || (ctrl3_c.if_inc == PROPERTY_DISABLE)) && (ret == 0))
+  {
+    ctrl3_c.bdu = PROPERTY_ENABLE;
+    ctrl3_c.if_inc = PROPERTY_ENABLE;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Configures the bus operating mode.[set]
+  *
+  * @param  ctx          communication interface handler. Use NULL to ignore
+  *                      this interface.(ptr)
+  * @param  aux_ctx      auxiliary communication interface handler. Use NULL
+  *                      to ignore this interface.(ptr)
+  * @param  val          configures the bus operating mode for both the
+  *                      main and the auxiliary interface.
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_bus_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
+                             lsm6dso_bus_mode_t val)
+{
+  lsm6dso_ctrl1_ois_t ctrl1_ois;
+  lsm6dso_i3c_bus_avb_t i3c_bus_avb;
+  lsm6dso_ctrl9_xl_t ctrl9_xl;
+  lsm6dso_ctrl3_c_t ctrl3_c;
+  lsm6dso_ctrl4_c_t ctrl4_c;
+  uint8_t bit_val;
+  int32_t ret;
+
+  ret = 0;
+
+  if (aux_ctx != NULL)
+  {
+    ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_CTRL1_OIS,
+                           (uint8_t *)&ctrl1_ois, 1);
+    bit_val = ((uint8_t)val.aux_bus_md & 0x04U) >> 2;
+
+    if ((ret == 0) && (ctrl1_ois.sim_ois != bit_val))
+    {
+      ctrl1_ois.sim_ois = bit_val;
+      ret = lsm6dso_write_reg(aux_ctx, LSM6DSO_CTRL1_OIS,
+                              (uint8_t *)&ctrl1_ois, 1);
+    }
+  }
+
+  if (ctx != NULL)
+  {
+    if (ret == 0)
+    {
+      ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL,
+                             (uint8_t *)&ctrl9_xl, 1);
+    }
+
+    bit_val = ((uint8_t)val.ui_bus_md & 0x04U) >> 2;
+
+    if ((ret == 0) && (ctrl9_xl.i3c_disable != bit_val))
+    {
+      ctrl9_xl.i3c_disable = bit_val;
+      ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL,
+                              (uint8_t *)&ctrl9_xl, 1);
+    }
+
+    if (ret == 0)
+    {
+      ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB,
+                             (uint8_t *)&i3c_bus_avb, 1);
+    }
+
+    bit_val = ((uint8_t)val.ui_bus_md & 0x30U) >> 4;
+
+    if ((ret == 0) && (i3c_bus_avb.i3c_bus_avb_sel != bit_val))
+    {
+      i3c_bus_avb.i3c_bus_avb_sel = bit_val;
+      ret = lsm6dso_write_reg(ctx, LSM6DSO_I3C_BUS_AVB,
+                              (uint8_t *)&i3c_bus_avb, 1);
+    }
+
+    if (ret == 0)
+    {
+      ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C,
+                             (uint8_t *)&ctrl4_c, 1);
+    }
+
+    bit_val = ((uint8_t)val.ui_bus_md & 0x02U) >> 1;
+
+    if ((ret == 0) && (ctrl4_c.i2c_disable != bit_val))
+    {
+      ctrl4_c.i2c_disable = bit_val;
+      ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C,
+                              (uint8_t *)&ctrl4_c, 1);
+    }
+
+    if (ret == 0)
+    {
+      ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C,
+                             (uint8_t *)&ctrl3_c, 1);
+    }
+
+    bit_val = (uint8_t)val.ui_bus_md & 0x01U;
+
+    if ((ret == 0) && (ctrl3_c.sim != bit_val))
+    {
+      ctrl3_c.sim = bit_val;
+      ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C,
+                              (uint8_t *)&ctrl3_c, 1);
+    }
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Get the bus operating mode.[get]
+  *
+  * @param  ctx          communication interface handler. Use NULL to ignore
+  *                      this interface.(ptr)
+  * @param  aux_ctx      auxiliary communication interface handler. Use NULL
+  *                      to ignore this interface.(ptr)
+  * @param  val          retrieves the bus operating mode for both the main
+  *                      and the auxiliary interface.(ptr)
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_bus_mode_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
+                             lsm6dso_bus_mode_t *val)
+{
+  lsm6dso_ctrl1_ois_t ctrl1_ois;
+  lsm6dso_i3c_bus_avb_t i3c_bus_avb;
+  lsm6dso_ctrl9_xl_t ctrl9_xl;
+  lsm6dso_ctrl3_c_t ctrl3_c;
+  lsm6dso_ctrl4_c_t ctrl4_c;
+  int32_t ret = 0;
+
+  if (aux_ctx != NULL)
+  {
+    ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_CTRL1_OIS,
+                           (uint8_t *)&ctrl1_ois, 1);
+
+    switch (ctrl1_ois.sim_ois)
+    {
+      case LSM6DSO_SPI_4W_AUX:
+        val->aux_bus_md = LSM6DSO_SPI_4W_AUX;
+        break;
+
+      case LSM6DSO_SPI_3W_AUX:
+        val->aux_bus_md = LSM6DSO_SPI_3W_AUX;
+        break;
+
+      default:
+        val->aux_bus_md = LSM6DSO_SPI_4W_AUX;
+        break;
+    }
+  }
+
+  if (ctx != NULL)
+  {
+    if (ret == 0)
+    {
+      ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL,
+                             (uint8_t *)&ctrl9_xl, 1);
+    }
+
+    if (ret == 0)
+    {
+      ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB,
+                             (uint8_t *)&i3c_bus_avb, 1);
+    }
+
+    if (ret == 0)
+    {
+      ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C,
+                             (uint8_t *)&ctrl4_c, 1);
+    }
+
+    if (ret == 0)
+    {
+      ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C,
+                             (uint8_t *)&ctrl3_c, 1);
+
+      switch ((i3c_bus_avb.i3c_bus_avb_sel << 4) &
+              (ctrl9_xl.i3c_disable << 2) &
+              (ctrl4_c.i2c_disable << 1) & ctrl3_c.sim)
+      {
+        case LSM6DSO_SEL_BY_HW:
+          val->ui_bus_md = LSM6DSO_SEL_BY_HW;
+          break;
+
+        case LSM6DSO_SPI_4W:
+          val->ui_bus_md = LSM6DSO_SPI_4W;
+          break;
+
+        case LSM6DSO_SPI_3W:
+          val->ui_bus_md = LSM6DSO_SPI_3W;
+          break;
+
+        case LSM6DSO_I2C:
+          val->ui_bus_md = LSM6DSO_I2C;
+          break;
+
+        case LSM6DSO_I3C_T_50us:
+          val->ui_bus_md = LSM6DSO_I3C_T_50us;
+          break;
+
+        case LSM6DSO_I3C_T_2us:
+          val->ui_bus_md = LSM6DSO_I3C_T_2us;
+          break;
+
+        case LSM6DSO_I3C_T_1ms:
+          val->ui_bus_md = LSM6DSO_I3C_T_1ms;
+          break;
+
+        case LSM6DSO_I3C_T_25ms:
+          val->ui_bus_md = LSM6DSO_I3C_T_25ms;
+          break;
+
+        default:
+          val->ui_bus_md = LSM6DSO_SEL_BY_HW;
+          break;
+      }
+    }
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Get the status of the device.[get]
+  *
+  * @param  ctx          communication interface handler. Use NULL to ignore
+  *                      this interface.(ptr)
+  * @param  aux_ctx      auxiliary communication interface handler. Use NULL
+  *                      to ignore this interface.(ptr)
+  * @param  val          the status of the device.(ptr)
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_status_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
+                           lsm6dso_status_t *val)
+{
+  lsm6dso_status_spiaux_t       status_spiaux;
+  lsm6dso_status_reg_t          status_reg;
+  lsm6dso_ctrl3_c_t             ctrl3_c;
+  int32_t                       ret;
+  ret = 0;
+
+  if (aux_ctx != NULL)
+  {
+    ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_STATUS_SPIAUX,
+                           (uint8_t *)&status_spiaux, 1);
+    val->ois_drdy_xl        = status_spiaux.xlda;
+    val->ois_drdy_g         = status_spiaux.gda;
+    val->ois_gyro_settling  = status_spiaux.gyro_settling;
+  }
+
+  if (ctx != NULL)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+    val->sw_reset = ctrl3_c.sw_reset;
+    val->boot = ctrl3_c.boot;
+
+    if ((ret == 0) && (ctrl3_c.sw_reset == PROPERTY_DISABLE) &&
+        (ctrl3_c.boot == PROPERTY_DISABLE))
+    {
+      ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG,
+                             (uint8_t *)&status_reg, 1);
+      val->drdy_xl   = status_reg.xlda;
+      val->drdy_g    = status_reg.gda;
+      val->drdy_temp = status_reg.tda;
+    }
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Electrical pin configuration.[set]
+  *
+  * @param  ctx          communication interface handler.(ptr)
+  * @param  val          the electrical settings for the configurable
+  *                      pins.
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_pin_conf_set(stmdev_ctx_t *ctx,
+                             lsm6dso_pin_conf_t val)
+{
+  lsm6dso_i3c_bus_avb_t i3c_bus_avb;
+  lsm6dso_pin_ctrl_t pin_ctrl;
+  lsm6dso_ctrl3_c_t ctrl3_c;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
+
+  if (ret == 0)
+  {
+    pin_ctrl.ois_pu_dis = ~val.aux_sdo_ocs_pull_up;
+    pin_ctrl.sdo_pu_en  = val.sdo_sa0_pull_up;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+  }
+
+  if (ret == 0)
+  {
+    ctrl3_c.pp_od = ~val.int1_int2_push_pull;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB,
+                           (uint8_t *)&i3c_bus_avb, 1);
+  }
+
+  if (ret == 0)
+  {
+    i3c_bus_avb.pd_dis_int1 = ~val.int1_pull_down;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_I3C_BUS_AVB,
+                            (uint8_t *)&i3c_bus_avb, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Electrical pin configuration.[get]
+  *
+  * @param  ctx          communication interface handler.(ptr)
+  * @param  val          the electrical settings for the configurable
+  *                      pins.(ptr)
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_pin_conf_get(stmdev_ctx_t *ctx,
+                             lsm6dso_pin_conf_t *val)
+{
+  lsm6dso_i3c_bus_avb_t i3c_bus_avb;
+  lsm6dso_pin_ctrl_t pin_ctrl;
+  lsm6dso_ctrl3_c_t ctrl3_c;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
+
+  if (ret == 0)
+  {
+    val->aux_sdo_ocs_pull_up = ~pin_ctrl.ois_pu_dis;
+    val->aux_sdo_ocs_pull_up =  pin_ctrl.sdo_pu_en;
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+  }
+
+  if (ret == 0)
+  {
+    val->int1_int2_push_pull = ~ctrl3_c.pp_od;
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB,
+                           (uint8_t *)&i3c_bus_avb, 1);
+  }
+
+  if (ret == 0)
+  {
+    val->int1_pull_down = ~i3c_bus_avb.pd_dis_int1;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Interrupt pins hardware signal configuration.[set]
+  *
+  * @param  ctx          communication interface handler.(ptr)
+  * @param  val          the pins hardware signal settings.
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_interrupt_mode_set(stmdev_ctx_t *ctx,
+                                   lsm6dso_int_mode_t val)
+{
+  lsm6dso_tap_cfg0_t tap_cfg0;
+  lsm6dso_page_rw_t page_rw;
+  lsm6dso_ctrl3_c_t ctrl3_c;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+  if (ret == 0)
+  {
+    ctrl3_c.h_lactive = val.active_low;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *) &tap_cfg0, 1);
+  }
+
+  if (ret == 0)
+  {
+    tap_cfg0.lir = val.base_latched;
+    tap_cfg0.int_clr_on_read = val.base_latched | val.emb_latched;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *) &tap_cfg0, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
+  }
+
+  if (ret == 0)
+  {
+    page_rw.emb_func_lir = val.emb_latched;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Interrupt pins hardware signal configuration.[get]
+  *
+  * @param  ctx          communication interface handler.(ptr)
+  * @param  val          the pins hardware signal settings.(ptr)
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_interrupt_mode_get(stmdev_ctx_t *ctx,
+                                   lsm6dso_int_mode_t *val)
+{
+  lsm6dso_tap_cfg0_t tap_cfg0;
+  lsm6dso_page_rw_t page_rw;
+  lsm6dso_ctrl3_c_t ctrl3_c;
+  int32_t ret;
+
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
+
+  if (ret == 0)
+  {
+    ctrl3_c.h_lactive = val->active_low;
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *) &tap_cfg0, 1);
+  }
+
+  if (ret == 0)
+  {
+    tap_cfg0.lir = val->base_latched;
+    tap_cfg0.int_clr_on_read = val->base_latched | val->emb_latched;
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
+  }
+
+  if (ret == 0)
+  {
+    page_rw.emb_func_lir = val->emb_latched;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Route interrupt signals on int1 pin.[set]
+  *
+  * @param  ctx          communication interface handler.(ptr)
+  * @param  val          the signals to route on int1 pin.
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_pin_int1_route_set(stmdev_ctx_t *ctx,
+                                   lsm6dso_pin_int1_route_t val)
+{
+  lsm6dso_pin_int2_route_t  pin_int2_route;
+  lsm6dso_emb_func_int1_t   emb_func_int1;
+  lsm6dso_fsm_int1_a_t      fsm_int1_a;
+  lsm6dso_fsm_int1_b_t      fsm_int1_b;
+  lsm6dso_int1_ctrl_t       int1_ctrl;
+  lsm6dso_int2_ctrl_t       int2_ctrl;
+  lsm6dso_tap_cfg2_t        tap_cfg2;
+  lsm6dso_md2_cfg_t         md2_cfg;
+  lsm6dso_md1_cfg_t         md1_cfg;
+  lsm6dso_ctrl4_c_t         ctrl4_c;
+  int32_t                    ret;
+  int1_ctrl.int1_drdy_xl   = val.drdy_xl;
+  int1_ctrl.int1_drdy_g    = val.drdy_g;
+  int1_ctrl.int1_boot      = val.boot;
+  int1_ctrl.int1_fifo_th   = val.fifo_th;
+  int1_ctrl.int1_fifo_ovr  = val.fifo_ovr;
+  int1_ctrl.int1_fifo_full = val.fifo_full;
+  int1_ctrl.int1_cnt_bdr   = val.fifo_bdr;
+  int1_ctrl.den_drdy_flag  = val.den_flag;
+  md1_cfg.int1_shub         = val.sh_endop;
+  md1_cfg.int1_6d           = val.six_d;
+  md1_cfg.int1_double_tap   = val.double_tap;
+  md1_cfg.int1_ff           = val.free_fall;
+  md1_cfg.int1_wu           = val.wake_up;
+  md1_cfg.int1_single_tap   = val.single_tap;
+  md1_cfg.int1_sleep_change = val.sleep_change;
+  emb_func_int1.not_used_01 = 0;
+  emb_func_int1.int1_step_detector = val.step_detector;
+  emb_func_int1.int1_tilt          = val.tilt;
+  emb_func_int1.int1_sig_mot       = val.sig_mot;
+  emb_func_int1.not_used_02 = 0;
+  emb_func_int1.int1_fsm_lc        = val.fsm_lc;
+  fsm_int1_a.int1_fsm1 = val.fsm1;
+  fsm_int1_a.int1_fsm2 = val.fsm2;
+  fsm_int1_a.int1_fsm3 = val.fsm3;
+  fsm_int1_a.int1_fsm4 = val.fsm4;
+  fsm_int1_a.int1_fsm5 = val.fsm5;
+  fsm_int1_a.int1_fsm6 = val.fsm6;
+  fsm_int1_a.int1_fsm7 = val.fsm7;
+  fsm_int1_a.int1_fsm8 = val.fsm8;
+  fsm_int1_b.int1_fsm9  = val.fsm9 ;
+  fsm_int1_b.int1_fsm10 = val.fsm10;
+  fsm_int1_b.int1_fsm11 = val.fsm11;
+  fsm_int1_b.int1_fsm12 = val.fsm12;
+  fsm_int1_b.int1_fsm13 = val.fsm13;
+  fsm_int1_b.int1_fsm14 = val.fsm14;
+  fsm_int1_b.int1_fsm15 = val.fsm15;
+  fsm_int1_b.int1_fsm16 = val.fsm16;
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+  if (ret == 0)
+  {
+    if ((val.drdy_temp | val.timestamp) != PROPERTY_DISABLE)
+    {
+      ctrl4_c.int2_on_int1 = PROPERTY_ENABLE;
+    }
+
+    else
+    {
+      ctrl4_c.int2_on_int1 = PROPERTY_DISABLE;
+    }
+
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INT1,
+                            (uint8_t *)&emb_func_int1, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_INT1_A,
+                            (uint8_t *)&fsm_int1_a, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_INT1_B,
+                            (uint8_t *)&fsm_int1_b, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  if (ret == 0)
+  {
+    if ((emb_func_int1.int1_fsm_lc
+         | emb_func_int1.int1_sig_mot
+         | emb_func_int1.int1_step_detector
+         | emb_func_int1.int1_tilt
+         | fsm_int1_a.int1_fsm1
+         | fsm_int1_a.int1_fsm2
+         | fsm_int1_a.int1_fsm3
+         | fsm_int1_a.int1_fsm4
+         | fsm_int1_a.int1_fsm5
+         | fsm_int1_a.int1_fsm6
+         | fsm_int1_a.int1_fsm7
+         | fsm_int1_a.int1_fsm8
+         | fsm_int1_b.int1_fsm9
+         | fsm_int1_b.int1_fsm10
+         | fsm_int1_b.int1_fsm11
+         | fsm_int1_b.int1_fsm12
+         | fsm_int1_b.int1_fsm13
+         | fsm_int1_b.int1_fsm14
+         | fsm_int1_b.int1_fsm15
+         | fsm_int1_b.int1_fsm16) != PROPERTY_DISABLE)
+    {
+      md1_cfg.int1_emb_func = PROPERTY_ENABLE;
+    }
+
+    else
+    {
+      md1_cfg.int1_emb_func = PROPERTY_DISABLE;
+    }
+
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_INT1_CTRL,
+                            (uint8_t *)&int1_ctrl, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_MD1_CFG, (uint8_t *)&md1_cfg, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
+  }
+
+  if (ret == 0)
+  {
+    int2_ctrl.int2_drdy_temp = val.drdy_temp;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t *)&md2_cfg, 1);
+  }
+
+  if (ret == 0)
+  {
+    md2_cfg.int2_timestamp = val.timestamp;
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t *)&md2_cfg, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *) &tap_cfg2, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_pin_int2_route_get(ctx, NULL, &pin_int2_route);
+  }
+
+  if (ret == 0)
+  {
+    if ((pin_int2_route.fifo_bdr
+         | pin_int2_route.drdy_g
+         | pin_int2_route.drdy_temp
+         | pin_int2_route.drdy_xl
+         | pin_int2_route.fifo_full
+         | pin_int2_route.fifo_ovr
+         | pin_int2_route.fifo_th
+         | pin_int2_route.six_d
+         | pin_int2_route.double_tap
+         | pin_int2_route.free_fall
+         | pin_int2_route.wake_up
+         | pin_int2_route.single_tap
+         | pin_int2_route.sleep_change
+         | int1_ctrl.den_drdy_flag
+         | int1_ctrl.int1_boot
+         | int1_ctrl.int1_cnt_bdr
+         | int1_ctrl.int1_drdy_g
+         | int1_ctrl.int1_drdy_xl
+         | int1_ctrl.int1_fifo_full
+         | int1_ctrl.int1_fifo_ovr
+         | int1_ctrl.int1_fifo_th
+         | md1_cfg.int1_shub
+         | md1_cfg.int1_6d
+         | md1_cfg.int1_double_tap
+         | md1_cfg.int1_ff
+         | md1_cfg.int1_wu
+         | md1_cfg.int1_single_tap
+         | md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
+    {
+      tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
+    }
+
+    else
+    {
+      tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
+    }
+
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *) &tap_cfg2, 1);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Route interrupt signals on int1 pin.[get]
+  *
+  * @param  ctx          communication interface handler.(ptr)
+  * @param  val          the signals that are routed on int1 pin.(ptr)
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_pin_int1_route_get(stmdev_ctx_t *ctx,
+                                   lsm6dso_pin_int1_route_t *val)
+{
+  lsm6dso_emb_func_int1_t   emb_func_int1;
+  lsm6dso_fsm_int1_a_t      fsm_int1_a;
+  lsm6dso_fsm_int1_b_t      fsm_int1_b;
+  lsm6dso_int1_ctrl_t       int1_ctrl;
+  lsm6dso_int2_ctrl_t       int2_ctrl;
+  lsm6dso_md2_cfg_t         md2_cfg;
+  lsm6dso_md1_cfg_t         md1_cfg;
+  lsm6dso_ctrl4_c_t         ctrl4_c;
+  int32_t                    ret;
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INT1,
+                           (uint8_t *)&emb_func_int1, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_INT1_A,
+                           (uint8_t *)&fsm_int1_a, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_INT1_B,
+                           (uint8_t *)&fsm_int1_b, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_INT1_CTRL,
+                           (uint8_t *)&int1_ctrl, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_MD1_CFG, (uint8_t *)&md1_cfg, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+  }
+
+  if (ctrl4_c.int2_on_int1 == PROPERTY_ENABLE)
+  {
+    if (ret == 0)
+    {
+      ret = lsm6dso_read_reg(ctx, LSM6DSO_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
+      val->drdy_temp = int2_ctrl.int2_drdy_temp;
+    }
+
+    if (ret == 0)
+    {
+      ret = lsm6dso_read_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t *)&md2_cfg, 1);
+      val->timestamp = md2_cfg.int2_timestamp;
+    }
+  }
+
+  else
+  {
+    val->drdy_temp = PROPERTY_DISABLE;
+    val->timestamp = PROPERTY_DISABLE;
+  }
+
+  val->drdy_xl   = int1_ctrl.int1_drdy_xl;
+  val->drdy_g    = int1_ctrl.int1_drdy_g;
+  val->boot      = int1_ctrl.int1_boot;
+  val->fifo_th   = int1_ctrl.int1_fifo_th;
+  val->fifo_ovr  = int1_ctrl.int1_fifo_ovr;
+  val->fifo_full = int1_ctrl.int1_fifo_full;
+  val->fifo_bdr  = int1_ctrl.int1_cnt_bdr;
+  val->den_flag  = int1_ctrl.den_drdy_flag;
+  val->sh_endop     = md1_cfg.int1_shub;
+  val->six_d        = md1_cfg.int1_6d;
+  val->double_tap   = md1_cfg.int1_double_tap;
+  val->free_fall    = md1_cfg.int1_ff;
+  val->wake_up      = md1_cfg.int1_wu;
+  val->single_tap   = md1_cfg.int1_single_tap;
+  val->sleep_change = md1_cfg.int1_sleep_change;
+  val->step_detector = emb_func_int1.int1_step_detector;
+  val->tilt          = emb_func_int1.int1_tilt;
+  val->sig_mot       = emb_func_int1.int1_sig_mot;
+  val->fsm_lc        = emb_func_int1.int1_fsm_lc;
+  val->fsm1 = fsm_int1_a.int1_fsm1;
+  val->fsm2 = fsm_int1_a.int1_fsm2;
+  val->fsm3 = fsm_int1_a.int1_fsm3;
+  val->fsm4 = fsm_int1_a.int1_fsm4;
+  val->fsm5 = fsm_int1_a.int1_fsm5;
+  val->fsm6 = fsm_int1_a.int1_fsm6;
+  val->fsm7 = fsm_int1_a.int1_fsm7;
+  val->fsm8 = fsm_int1_a.int1_fsm8;
+  val->fsm9  = fsm_int1_b.int1_fsm9;
+  val->fsm10 = fsm_int1_b.int1_fsm10;
+  val->fsm11 = fsm_int1_b.int1_fsm11;
+  val->fsm12 = fsm_int1_b.int1_fsm12;
+  val->fsm13 = fsm_int1_b.int1_fsm13;
+  val->fsm14 = fsm_int1_b.int1_fsm14;
+  val->fsm15 = fsm_int1_b.int1_fsm15;
+  val->fsm16 = fsm_int1_b.int1_fsm16;
+
+  return ret;
+}
+
+/**
+  * @brief  Route interrupt signals on int2 pin.[set]
+  *
+  * @param  ctx          communication interface handler. Use NULL to ignore
+  *                      this interface.(ptr)
+  * @param  aux_ctx      auxiliary communication interface handler. Use NULL
+  *                      to ignore this interface.(ptr)
+  * @param  val          the signals to route on int2 pin.
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_pin_int2_route_set(stmdev_ctx_t *ctx,
+                                   stmdev_ctx_t *aux_ctx,
+                                   lsm6dso_pin_int2_route_t val)
+{
+  lsm6dso_pin_int1_route_t pin_int1_route;
+  lsm6dso_emb_func_int2_t  emb_func_int2;
+  lsm6dso_fsm_int2_a_t     fsm_int2_a;
+  lsm6dso_fsm_int2_b_t     fsm_int2_b;
+  lsm6dso_int2_ctrl_t      int2_ctrl;
+  lsm6dso_tap_cfg2_t       tap_cfg2;
+  lsm6dso_md2_cfg_t        md2_cfg;
+  lsm6dso_ctrl4_c_t        ctrl4_c;
+  lsm6dso_int_ois_t        int_ois;
+  int32_t                  ret;
+  ret = 0;
+
+  if (aux_ctx != NULL)
+  {
+    ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_INT_OIS,
+                           (uint8_t *)&int_ois, 1);
+
+    if (ret == 0)
+    {
+      int_ois.int2_drdy_ois = val.drdy_ois;
+      ret = lsm6dso_write_reg(aux_ctx, LSM6DSO_INT_OIS,
+                              (uint8_t *)&int_ois, 1);
+    }
+  }
+
+  if (ctx != NULL)
+  {
+    int2_ctrl.int2_drdy_xl   = val.drdy_xl;
+    int2_ctrl.int2_drdy_g    = val.drdy_g;
+    int2_ctrl.int2_drdy_temp = val.drdy_temp;
+    int2_ctrl.int2_fifo_th   = val.fifo_th;
+    int2_ctrl.int2_fifo_ovr  = val.fifo_ovr;
+    int2_ctrl.int2_fifo_full = val.fifo_full;
+    int2_ctrl.int2_cnt_bdr   = val.fifo_bdr;
+    int2_ctrl.not_used_01    = 0;
+    md2_cfg.int2_timestamp    = val.timestamp;
+    md2_cfg.int2_6d           = val.six_d;
+    md2_cfg.int2_double_tap   = val.double_tap;
+    md2_cfg.int2_ff           = val.free_fall;
+    md2_cfg.int2_wu           = val.wake_up;
+    md2_cfg.int2_single_tap   = val.single_tap;
+    md2_cfg.int2_sleep_change = val.sleep_change;
+    emb_func_int2.not_used_01 = 0;
+    emb_func_int2. int2_step_detector = val.step_detector;
+    emb_func_int2.int2_tilt           = val.tilt;
+    emb_func_int2.int2_sig_mot        = val.sig_mot;
+    emb_func_int2.not_used_02 = 0;
+    emb_func_int2.int2_fsm_lc         = val.fsm_lc;
+    fsm_int2_a.int2_fsm1 = val.fsm1;
+    fsm_int2_a.int2_fsm2 = val.fsm2;
+    fsm_int2_a.int2_fsm3 = val.fsm3;
+    fsm_int2_a.int2_fsm4 = val.fsm4;
+    fsm_int2_a.int2_fsm5 = val.fsm5;
+    fsm_int2_a.int2_fsm6 = val.fsm6;
+    fsm_int2_a.int2_fsm7 = val.fsm7;
+    fsm_int2_a.int2_fsm8 = val.fsm8;
+    fsm_int2_b.int2_fsm9  = val.fsm9 ;
+    fsm_int2_b.int2_fsm10 = val.fsm10;
+    fsm_int2_b.int2_fsm11 = val.fsm11;
+    fsm_int2_b.int2_fsm12 = val.fsm12;
+    fsm_int2_b.int2_fsm13 = val.fsm13;
+    fsm_int2_b.int2_fsm14 = val.fsm14;
+    fsm_int2_b.int2_fsm15 = val.fsm15;
+    fsm_int2_b.int2_fsm16 = val.fsm16;
+
+    if (ret == 0)
+    {
+      ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+
+      if (ret == 0)
+      {
+        if ((val.drdy_temp | val.timestamp) != PROPERTY_DISABLE)
+        {
+          ctrl4_c.int2_on_int1 = PROPERTY_DISABLE;
+        }
+
+        ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+      }
+    }
+
+    if (ret == 0)
+    {
+      ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+    }
+
+    if (ret == 0)
+    {
+      ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INT2,
+                              (uint8_t *)&emb_func_int2, 1);
+    }
+
+    if (ret == 0)
+    {
+      ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_INT2_A,
+                              (uint8_t *)&fsm_int2_a, 1);
+    }
+
+    if (ret == 0)
+    {
+      ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_INT2_B,
+                              (uint8_t *)&fsm_int2_b, 1);
+    }
+
+    if (ret == 0)
+    {
+      ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+    }
+
+    if (ret == 0)
+    {
+      if ((emb_func_int2.int2_fsm_lc
+           | emb_func_int2.int2_sig_mot
+           | emb_func_int2.int2_step_detector
+           | emb_func_int2.int2_tilt
+           | fsm_int2_a.int2_fsm1
+           | fsm_int2_a.int2_fsm2
+           | fsm_int2_a.int2_fsm3
+           | fsm_int2_a.int2_fsm4
+           | fsm_int2_a.int2_fsm5
+           | fsm_int2_a.int2_fsm6
+           | fsm_int2_a.int2_fsm7
+           | fsm_int2_a.int2_fsm8
+           | fsm_int2_b.int2_fsm9
+           | fsm_int2_b.int2_fsm10
+           | fsm_int2_b.int2_fsm11
+           | fsm_int2_b.int2_fsm12
+           | fsm_int2_b.int2_fsm13
+           | fsm_int2_b.int2_fsm14
+           | fsm_int2_b.int2_fsm15
+           | fsm_int2_b.int2_fsm16) != PROPERTY_DISABLE)
+      {
+        md2_cfg.int2_emb_func = PROPERTY_ENABLE;
+      }
+
+      else
+      {
+        md2_cfg.int2_emb_func = PROPERTY_DISABLE;
+      }
+
+      ret = lsm6dso_write_reg(ctx, LSM6DSO_INT2_CTRL,
+                              (uint8_t *)&int2_ctrl, 1);
+    }
+
+    if (ret == 0)
+    {
+      ret = lsm6dso_write_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t *)&md2_cfg, 1);
+    }
+
+    if (ret == 0)
+    {
+      ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *) &tap_cfg2, 1);
+    }
+
+    if (ret == 0)
+    {
+      ret = lsm6dso_pin_int1_route_get(ctx, &pin_int1_route);
+    }
+
+    if (ret == 0)
+    {
+      if ((val.fifo_bdr
+           | val.drdy_g
+           | val.drdy_temp
+           | val.drdy_xl
+           | val.fifo_full
+           | val.fifo_ovr
+           | val.fifo_th
+           | val.six_d
+           | val.double_tap
+           | val.free_fall
+           | val.wake_up
+           | val.single_tap
+           | val.sleep_change
+           | pin_int1_route.den_flag
+           | pin_int1_route.boot
+           | pin_int1_route.fifo_bdr
+           | pin_int1_route.drdy_g
+           | pin_int1_route.drdy_xl
+           | pin_int1_route.fifo_full
+           | pin_int1_route.fifo_ovr
+           | pin_int1_route.fifo_th
+           | pin_int1_route.six_d
+           | pin_int1_route.double_tap
+           | pin_int1_route.free_fall
+           | pin_int1_route.wake_up
+           | pin_int1_route.single_tap
+           | pin_int1_route.sleep_change) != PROPERTY_DISABLE)
+      {
+        tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
+      }
+
+      else
+      {
+        tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
+      }
+
+      ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *) &tap_cfg2, 1);
+    }
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Route interrupt signals on int2 pin.[get]
+  *
+  * @param  ctx          communication interface handler. Use NULL to ignore
+  *                      this interface.(ptr)
+  * @param  aux_ctx      auxiliary communication interface handler. Use NULL
+  *                      to ignore this interface.(ptr)
+  * @param  val          the signals that are routed on int2 pin.(ptr)
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_pin_int2_route_get(stmdev_ctx_t *ctx,
+                                   stmdev_ctx_t *aux_ctx,
+                                   lsm6dso_pin_int2_route_t *val)
+{
+  lsm6dso_emb_func_int2_t  emb_func_int2;
+  lsm6dso_fsm_int2_a_t     fsm_int2_a;
+  lsm6dso_fsm_int2_b_t     fsm_int2_b;
+  lsm6dso_int2_ctrl_t      int2_ctrl;
+  lsm6dso_md2_cfg_t        md2_cfg;
+  lsm6dso_ctrl4_c_t        ctrl4_c;
+  lsm6dso_int_ois_t        int_ois;
+  int32_t                   ret;
+  ret = 0;
+
+  if (aux_ctx != NULL)
+  {
+    ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_INT_OIS,
+                           (uint8_t *)&int_ois, 1);
+    val->drdy_ois = int_ois.int2_drdy_ois;
+  }
+
+  if (ctx != NULL)
+  {
+    if (ret == 0)
+    {
+      ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+    }
+
+    if (ret == 0)
+    {
+      ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INT2,
+                             (uint8_t *)&emb_func_int2, 1);
+    }
+
+    if (ret == 0)
+    {
+      ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_INT2_A,
+                             (uint8_t *)&fsm_int2_a, 1);
+    }
+
+    if (ret == 0)
+    {
+      ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_INT2_B,
+                             (uint8_t *)&fsm_int2_b, 1);
+    }
+
+    if (ret == 0)
+    {
+      ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+    }
+
+    if (ret == 0)
+    {
+      ret = lsm6dso_read_reg(ctx, LSM6DSO_INT2_CTRL,
+                             (uint8_t *)&int2_ctrl, 1);
+    }
+
+    if (ret == 0)
+    {
+      ret = lsm6dso_read_reg(ctx, LSM6DSO_MD2_CFG,
+                             (uint8_t *)&md2_cfg, 1);
+    }
+
+    if (ret == 0)
+    {
+      ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
+    }
+
+    if (ctrl4_c.int2_on_int1 == PROPERTY_DISABLE)
+    {
+      if (ret == 0)
+      {
+        ret = lsm6dso_read_reg(ctx, LSM6DSO_INT2_CTRL,
+                               (uint8_t *)&int2_ctrl, 1);
+        val->drdy_temp = int2_ctrl.int2_drdy_temp;
+      }
+
+      if (ret == 0)
+      {
+        ret = lsm6dso_read_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t *)&md2_cfg, 1);
+        val->timestamp = md2_cfg.int2_timestamp;
+      }
+    }
+
+    else
+    {
+      val->drdy_temp = PROPERTY_DISABLE;
+      val->timestamp = PROPERTY_DISABLE;
+    }
+
+    val->drdy_xl   = int2_ctrl.int2_drdy_xl;
+    val->drdy_g    = int2_ctrl.int2_drdy_g;
+    val->drdy_temp = int2_ctrl.int2_drdy_temp;
+    val->fifo_th   = int2_ctrl.int2_fifo_th;
+    val->fifo_ovr  = int2_ctrl.int2_fifo_ovr;
+    val->fifo_full = int2_ctrl.int2_fifo_full;
+    val->fifo_bdr   = int2_ctrl.int2_cnt_bdr;
+    val->timestamp    = md2_cfg.int2_timestamp;
+    val->six_d        = md2_cfg.int2_6d;
+    val->double_tap   = md2_cfg.int2_double_tap;
+    val->free_fall    = md2_cfg.int2_ff;
+    val->wake_up      = md2_cfg.int2_wu;
+    val->single_tap   = md2_cfg.int2_single_tap;
+    val->sleep_change = md2_cfg.int2_sleep_change;
+    val->step_detector = emb_func_int2. int2_step_detector;
+    val->tilt          = emb_func_int2.int2_tilt;
+    val->fsm_lc        = emb_func_int2.int2_fsm_lc;
+    val->fsm1 = fsm_int2_a.int2_fsm1;
+    val->fsm2 = fsm_int2_a.int2_fsm2;
+    val->fsm3 = fsm_int2_a.int2_fsm3;
+    val->fsm4 = fsm_int2_a.int2_fsm4;
+    val->fsm5 = fsm_int2_a.int2_fsm5;
+    val->fsm6 = fsm_int2_a.int2_fsm6;
+    val->fsm7 = fsm_int2_a.int2_fsm7;
+    val->fsm8 = fsm_int2_a.int2_fsm8;
+    val->fsm9  = fsm_int2_b.int2_fsm9;
+    val->fsm10 = fsm_int2_b.int2_fsm10;
+    val->fsm11 = fsm_int2_b.int2_fsm11;
+    val->fsm12 = fsm_int2_b.int2_fsm12;
+    val->fsm13 = fsm_int2_b.int2_fsm13;
+    val->fsm14 = fsm_int2_b.int2_fsm14;
+    val->fsm15 = fsm_int2_b.int2_fsm15;
+    val->fsm16 = fsm_int2_b.int2_fsm16;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Get the status of all the interrupt sources.[get]
+  *
+  * @param  ctx          communication interface handler.(ptr)
+  * @param  val          the status of all the interrupt sources.(ptr)
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_all_sources_get(stmdev_ctx_t *ctx,
+                                lsm6dso_all_sources_t *val)
+{
+  lsm6dso_emb_func_status_mainpage_t emb_func_status_mainpage;
+  lsm6dso_status_master_mainpage_t   status_master_mainpage;
+  lsm6dso_fsm_status_a_mainpage_t    fsm_status_a_mainpage;
+  lsm6dso_fsm_status_b_mainpage_t    fsm_status_b_mainpage;
+  lsm6dso_fifo_status1_t             fifo_status1;
+  lsm6dso_fifo_status2_t             fifo_status2;
+  lsm6dso_all_int_src_t              all_int_src;
+  lsm6dso_wake_up_src_t              wake_up_src;
+  lsm6dso_status_reg_t               status_reg;
+  lsm6dso_tap_src_t                  tap_src;
+  lsm6dso_d6d_src_t                  d6d_src;
+  uint8_t                            reg[5];
+  int32_t                            ret;
+  ret = lsm6dso_read_reg(ctx, LSM6DSO_ALL_INT_SRC, reg, 5);
+
+  if (ret == 0)
+  {
+    bytecpy((uint8_t *)&all_int_src, &reg[0]);
+    bytecpy((uint8_t *)&wake_up_src, &reg[1]);
+    bytecpy((uint8_t *)&tap_src, &reg[2]);
+    bytecpy((uint8_t *)&d6d_src, &reg[3]);
+    bytecpy((uint8_t *)&status_reg, &reg[4]);
+    val->timestamp = all_int_src.timestamp_endcount;
+    val->wake_up_z    = wake_up_src.z_wu;
+    val->wake_up_y    = wake_up_src.y_wu;
+    val->wake_up_x    = wake_up_src.x_wu;
+    val->wake_up      = wake_up_src.wu_ia;
+    val->sleep_state  = wake_up_src.sleep_state;
+    val->free_fall    = wake_up_src.ff_ia;
+    val->sleep_change = wake_up_src.sleep_change_ia;
+    val->tap_x      = tap_src.x_tap;
+    val->tap_y      = tap_src.y_tap;
+    val->tap_z      = tap_src.z_tap;
+    val->tap_sign   = tap_src.tap_sign;
+    val->double_tap = tap_src.double_tap;
+    val->single_tap = tap_src.single_tap;
+    val->six_d_xl = d6d_src.xl;
+    val->six_d_xh = d6d_src.xh;
+    val->six_d_yl = d6d_src.yl;
+    val->six_d_yh = d6d_src.yh;
+    val->six_d_zl = d6d_src.zl;
+    val->six_d_zh = d6d_src.zh;
+    val->six_d    = d6d_src.d6d_ia;
+    val->den_flag = d6d_src.den_drdy;
+    val->drdy_xl   = status_reg.xlda;
+    val->drdy_g    = status_reg.gda;
+    val->drdy_temp = status_reg.tda;
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS_MAINPAGE, reg, 3);
+  }
+
+  if (ret == 0)
+  {
+    bytecpy((uint8_t *)&emb_func_status_mainpage, &reg[0]);
+    bytecpy((uint8_t *)&fsm_status_a_mainpage, &reg[1]);
+    bytecpy((uint8_t *)&fsm_status_b_mainpage, &reg[2]);
+    val->step_detector = emb_func_status_mainpage.is_step_det;
+    val->tilt          = emb_func_status_mainpage.is_tilt;
+    val->sig_mot       = emb_func_status_mainpage.is_sigmot;
+    val->fsm_lc        = emb_func_status_mainpage.is_fsm_lc;
+    val->fsm1 = fsm_status_a_mainpage.is_fsm1;
+    val->fsm2 = fsm_status_a_mainpage.is_fsm2;
+    val->fsm3 = fsm_status_a_mainpage.is_fsm3;
+    val->fsm4 = fsm_status_a_mainpage.is_fsm4;
+    val->fsm5 = fsm_status_a_mainpage.is_fsm5;
+    val->fsm6 = fsm_status_a_mainpage.is_fsm6;
+    val->fsm7 = fsm_status_a_mainpage.is_fsm7;
+    val->fsm8 = fsm_status_a_mainpage.is_fsm8;
+    val->fsm9  = fsm_status_b_mainpage.is_fsm9;
+    val->fsm10 = fsm_status_b_mainpage.is_fsm10;
+    val->fsm11 = fsm_status_b_mainpage.is_fsm11;
+    val->fsm12 = fsm_status_b_mainpage.is_fsm12;
+    val->fsm13 = fsm_status_b_mainpage.is_fsm13;
+    val->fsm14 = fsm_status_b_mainpage.is_fsm14;
+    val->fsm15 = fsm_status_b_mainpage.is_fsm15;
+    val->fsm16 = fsm_status_b_mainpage.is_fsm16;
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_MASTER_MAINPAGE, reg, 3);
+  }
+
+  if (ret == 0)
+  {
+    bytecpy((uint8_t *)&status_master_mainpage, &reg[0]);
+    bytecpy((uint8_t *)&fifo_status1, &reg[1]);
+    bytecpy((uint8_t *)&fifo_status2, &reg[2]);
+    val->sh_endop       = status_master_mainpage.sens_hub_endop;
+    val->sh_slave0_nack = status_master_mainpage.slave0_nack;
+    val->sh_slave1_nack = status_master_mainpage.slave1_nack;
+    val->sh_slave2_nack = status_master_mainpage.slave2_nack;
+    val->sh_slave3_nack = status_master_mainpage.slave3_nack;
+    val->sh_wr_once     = status_master_mainpage.wr_once_done;
+    val->fifo_diff = (256U * fifo_status2.diff_fifo) +
+                     fifo_status1.diff_fifo;
+    val->fifo_ovr_latched = fifo_status2.over_run_latched;
+    val->fifo_bdr         = fifo_status2.counter_bdr_ia;
+    val->fifo_full        = fifo_status2.fifo_full_ia;
+    val->fifo_ovr         = fifo_status2.fifo_ovr_ia;
+    val->fifo_th          = fifo_status2.fifo_wtm_ia;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Sensor conversion parameters selection.[set]
+  *
+  * @param  ctx          communication interface handler. Use NULL to ignore
+  *                      this interface.(ptr)
+  * @param  aux_ctx      auxiliary communication interface handler. Use NULL
+  *                      to ignore this interface.(ptr)
+  * @param  val          set the sensor conversion parameters by checking
+  *                      the constraints of the device.(ptr)
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
+                         lsm6dso_md_t *val)
+{
+  lsm6dso_func_cfg_access_t func_cfg_access;
+  lsm6dso_ctrl1_ois_t ctrl1_ois;
+  lsm6dso_ctrl2_ois_t ctrl2_ois;
+  lsm6dso_ctrl3_ois_t ctrl3_ois;
+  lsm6dso_ctrl1_xl_t ctrl1_xl;
+  lsm6dso_ctrl8_xl_t ctrl8_xl;
+  lsm6dso_ctrl2_g_t ctrl2_g;
+  lsm6dso_ctrl3_c_t ctrl3_c;
+  lsm6dso_ctrl4_c_t ctrl4_c;
+  lsm6dso_ctrl5_c_t ctrl5_c;
+  lsm6dso_ctrl6_c_t ctrl6_c;
+  lsm6dso_ctrl7_g_t ctrl7_g;
+  uint8_t xl_hm_mode;
+  uint8_t g_hm_mode;
+  uint8_t xl_ulp_en;
+  uint8_t odr_gy;
+  uint8_t odr_xl;
+  uint8_t reg[8];
+  int32_t ret;
+
+  ret = 0;
+  /* FIXME: Remove warnings with STM32CubeIDE */
+  ctrl3_c.not_used_01 = 0;
+  ctrl4_c.not_used_01 = 0;
+  ctrl5_c.xl_ulp_en = 0;
+  /* reading input configuration */
+  xl_hm_mode = ((uint8_t)val->ui.xl.odr & 0x10U) >> 4;
+  xl_ulp_en = ((uint8_t)val->ui.xl.odr & 0x20U) >> 5;
+  odr_xl = (uint8_t)val->ui.xl.odr & 0x0FU;
+
+  /* if enable xl ultra low power mode disable gy and OIS chain */
+  if (xl_ulp_en == PROPERTY_ENABLE)
+  {
+    val->ois.xl.odr = LSM6DSO_XL_OIS_OFF;
+    val->ois.gy.odr = LSM6DSO_GY_OIS_OFF;
+    val->ui.gy.odr  = LSM6DSO_GY_UI_OFF;
+  }
+
+  /* if OIS xl is enabled also gyro OIS is enabled */
+  if (val->ois.xl.odr == LSM6DSO_XL_OIS_6667Hz_HP)
+  {
+    val->ois.gy.odr = LSM6DSO_GY_OIS_6667Hz_HP;
+  }
+
+  g_hm_mode = ((uint8_t)val->ui.gy.odr & 0x10U) >> 4;
+  odr_gy = (uint8_t)val->ui.gy.odr & 0x0FU;
+
+  /* reading registers to be configured */
+  if (ctx != NULL)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, reg, 8);
+    bytecpy((uint8_t *)&ctrl1_xl, &reg[0]);
+    bytecpy((uint8_t *)&ctrl2_g,  &reg[1]);
+    bytecpy((uint8_t *)&ctrl3_c,  &reg[2]);
+    bytecpy((uint8_t *)&ctrl4_c,  &reg[3]);
+    bytecpy((uint8_t *)&ctrl5_c,  &reg[4]);
+    bytecpy((uint8_t *)&ctrl6_c,  &reg[5]);
+    bytecpy((uint8_t *)&ctrl7_g,  &reg[6]);
+    bytecpy((uint8_t *)&ctrl8_xl, &reg[7]);
+
+    if (ret == 0)
+    {
+      ret = lsm6dso_read_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS,
+                             (uint8_t *)&func_cfg_access, 1);
+    }
+
+    /* if toggle xl ultra low power mode, turn off xl before reconfigure */
+    if (ctrl5_c.xl_ulp_en != xl_ulp_en)
+    {
+      ctrl1_xl.odr_xl = (uint8_t) 0x00U;
+      ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL,
+                              (uint8_t *)&ctrl1_xl, 1);
+    }
+  }
+
+  /* reading OIS registers to be configured */
+  if (aux_ctx != NULL)
+  {
+    if (ret == 0)
+    {
+      ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_CTRL1_OIS, reg, 3);
+    }
+
+    bytecpy((uint8_t *)&ctrl1_ois, &reg[0]);
+    bytecpy((uint8_t *)&ctrl2_ois, &reg[1]);
+    bytecpy((uint8_t *)&ctrl3_ois, &reg[2]);
+  }
+
+  else
+  {
+    if (ctx != NULL)
+    {
+      if (ret == 0)
+      {
+        ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, reg, 3);
+      }
+
+      bytecpy((uint8_t *)&ctrl1_ois, &reg[0]);
+      bytecpy((uint8_t *)&ctrl2_ois, &reg[1]);
+      bytecpy((uint8_t *)&ctrl3_ois, &reg[2]);
+    }
+  }
+
+  /* Check the Finite State Machine data rate constraints */
+  if (val->fsm.sens != LSM6DSO_FSM_DISABLE)
+  {
+    switch (val->fsm.odr)
+    {
+      case LSM6DSO_FSM_12Hz5:
+        if ((val->fsm.sens != LSM6DSO_FSM_GY) && (odr_xl == 0x00U))
+        {
+          odr_xl = 0x01U;
+        }
+
+        if ((val->fsm.sens != LSM6DSO_FSM_XL) && (odr_gy == 0x00U))
+        {
+          xl_ulp_en = PROPERTY_DISABLE;
+          odr_gy = 0x01U;
+        }
+
+        break;
+
+      case LSM6DSO_FSM_26Hz:
+        if ((val->fsm.sens != LSM6DSO_FSM_GY) && (odr_xl < 0x02U))
+        {
+          odr_xl = 0x02U;
+        }
+
+        if ((val->fsm.sens != LSM6DSO_FSM_XL) && (odr_gy < 0x02U))
+        {
+          xl_ulp_en = PROPERTY_DISABLE;
+          odr_gy = 0x02U;
+        }
+
+        break;
+
+      case LSM6DSO_FSM_52Hz:
+        if ((val->fsm.sens != LSM6DSO_FSM_GY) && (odr_xl < 0x03U))
+        {
+          odr_xl = 0x03U;
+        }
+
+        if ((val->fsm.sens != LSM6DSO_FSM_XL) && (odr_gy < 0x03U))
+        {
+          xl_ulp_en = PROPERTY_DISABLE;
+          odr_gy = 0x03U;
+        }
+
+        break;
+
+      case LSM6DSO_FSM_104Hz:
+        if ((val->fsm.sens != LSM6DSO_FSM_GY) && (odr_xl < 0x04U))
+        {
+          odr_xl = 0x04U;
+        }
+
+        if ((val->fsm.sens != LSM6DSO_FSM_XL) && (odr_gy < 0x04U))
+        {
+          xl_ulp_en = PROPERTY_DISABLE;
+          odr_gy = 0x04U;
+        }
+
+        break;
+
+      default:
+        odr_xl = 0x00U;
+        odr_gy = 0x00U;
+        break;
+    }
+  }
+
+  /* Updating the accelerometer data rate configuration */
+  switch ((ctrl5_c.xl_ulp_en << 5) | (ctrl6_c.xl_hm_mode << 4) |
+          ctrl1_xl.odr_xl)
+  {
+    case LSM6DSO_XL_UI_OFF:
+      val->ui.xl.odr = LSM6DSO_XL_UI_OFF;
+      break;
+
+    case LSM6DSO_XL_UI_12Hz5_HP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_12Hz5_HP;
+      break;
+
+    case LSM6DSO_XL_UI_26Hz_HP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_26Hz_HP;
+      break;
+
+    case LSM6DSO_XL_UI_52Hz_HP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_52Hz_HP;
+      break;
+
+    case LSM6DSO_XL_UI_104Hz_HP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_104Hz_HP;
+      break;
+
+    case LSM6DSO_XL_UI_208Hz_HP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_208Hz_HP;
+      break;
+
+    case LSM6DSO_XL_UI_416Hz_HP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_416Hz_HP;
+      break;
+
+    case LSM6DSO_XL_UI_833Hz_HP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_833Hz_HP;
+      break;
+
+    case LSM6DSO_XL_UI_1667Hz_HP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_1667Hz_HP;
+      break;
+
+    case LSM6DSO_XL_UI_3333Hz_HP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_3333Hz_HP;
+      break;
+
+    case LSM6DSO_XL_UI_6667Hz_HP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_6667Hz_HP;
+      break;
+
+    case LSM6DSO_XL_UI_1Hz6_LP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_1Hz6_LP;
+      break;
+
+    case LSM6DSO_XL_UI_12Hz5_LP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_12Hz5_LP;
+      break;
+
+    case LSM6DSO_XL_UI_26Hz_LP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_26Hz_LP;
+      break;
+
+    case LSM6DSO_XL_UI_52Hz_LP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_52Hz_LP;
+      break;
+
+    case LSM6DSO_XL_UI_104Hz_NM:
+      val->ui.xl.odr = LSM6DSO_XL_UI_104Hz_NM;
+      break;
+
+    case LSM6DSO_XL_UI_208Hz_NM:
+      val->ui.xl.odr = LSM6DSO_XL_UI_208Hz_NM;
+      break;
+
+    case LSM6DSO_XL_UI_1Hz6_ULP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_1Hz6_ULP;
+      break;
+
+    case LSM6DSO_XL_UI_12Hz5_ULP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_12Hz5_ULP;
+      break;
+
+    case LSM6DSO_XL_UI_26Hz_ULP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_26Hz_ULP;
+      break;
+
+    case LSM6DSO_XL_UI_52Hz_ULP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_52Hz_ULP;
+      break;
+
+    case LSM6DSO_XL_UI_104Hz_ULP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_104Hz_ULP;
+      break;
+
+    case LSM6DSO_XL_UI_208Hz_ULP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_208Hz_ULP;
+      break;
+
+    default:
+      val->ui.xl.odr = LSM6DSO_XL_UI_OFF;
+      break;
+  }
+
+  /* Updating the accelerometer data rate configuration */
+  switch ((ctrl7_g.g_hm_mode << 4) | ctrl2_g.odr_g)
+  {
+    case LSM6DSO_GY_UI_OFF:
+      val->ui.gy.odr = LSM6DSO_GY_UI_OFF;
+      break;
+
+    case LSM6DSO_GY_UI_12Hz5_LP:
+      val->ui.gy.odr = LSM6DSO_GY_UI_12Hz5_LP;
+      break;
+
+    case LSM6DSO_GY_UI_12Hz5_HP:
+      val->ui.gy.odr = LSM6DSO_GY_UI_12Hz5_HP;
+      break;
+
+    case LSM6DSO_GY_UI_26Hz_LP:
+      val->ui.gy.odr = LSM6DSO_GY_UI_26Hz_LP;
+      break;
+
+    case LSM6DSO_GY_UI_26Hz_HP:
+      val->ui.gy.odr = LSM6DSO_GY_UI_26Hz_HP;
+      break;
+
+    case LSM6DSO_GY_UI_52Hz_LP:
+      val->ui.gy.odr = LSM6DSO_GY_UI_52Hz_LP;
+      break;
+
+    case LSM6DSO_GY_UI_52Hz_HP:
+      val->ui.gy.odr = LSM6DSO_GY_UI_52Hz_HP;
+      break;
+
+    case LSM6DSO_GY_UI_104Hz_NM:
+      val->ui.gy.odr = LSM6DSO_GY_UI_104Hz_NM;
+      break;
+
+    case LSM6DSO_GY_UI_104Hz_HP:
+      val->ui.gy.odr = LSM6DSO_GY_UI_104Hz_HP;
+      break;
+
+    case LSM6DSO_GY_UI_208Hz_NM:
+      val->ui.gy.odr = LSM6DSO_GY_UI_208Hz_NM;
+      break;
+
+    case LSM6DSO_GY_UI_208Hz_HP:
+      val->ui.gy.odr = LSM6DSO_GY_UI_208Hz_HP;
+      break;
+
+    case LSM6DSO_GY_UI_416Hz_HP:
+      val->ui.gy.odr = LSM6DSO_GY_UI_416Hz_HP;
+      break;
+
+    case LSM6DSO_GY_UI_833Hz_HP:
+      val->ui.gy.odr = LSM6DSO_GY_UI_833Hz_HP;
+      break;
+
+    case LSM6DSO_GY_UI_1667Hz_HP:
+      val->ui.gy.odr = LSM6DSO_GY_UI_1667Hz_HP;
+      break;
+
+    case LSM6DSO_GY_UI_3333Hz_HP:
+      val->ui.gy.odr = LSM6DSO_GY_UI_3333Hz_HP;
+      break;
+
+    case LSM6DSO_GY_UI_6667Hz_HP:
+      val->ui.gy.odr = LSM6DSO_GY_UI_6667Hz_HP;
+      break;
+
+    default:
+      val->ui.gy.odr = LSM6DSO_GY_UI_OFF;
+      break;
+  }
+
+  /* Check accelerometer full scale constraints */
+  /* Full scale of 16g must be the same for UI and OIS */
+  if ((val->ui.xl.fs == LSM6DSO_XL_UI_16g) ||
+      (val->ois.xl.fs == LSM6DSO_XL_OIS_16g))
+  {
+    val->ui.xl.fs = LSM6DSO_XL_UI_16g;
+    val->ois.xl.fs = LSM6DSO_XL_OIS_16g;
+  }
+
+  /* prapare new configuration */
+
+  /* Full scale of 16g must be the same for UI and OIS */
+  if (val->ui.xl.fs == LSM6DSO_XL_UI_16g)
+  {
+    ctrl8_xl.xl_fs_mode = PROPERTY_DISABLE;
+  }
+
+  else
+  {
+    ctrl8_xl.xl_fs_mode = PROPERTY_ENABLE;
+  }
+
+  /* OIS new configuration */
+  ctrl7_g.ois_on_en = val->ois.ctrl_md & 0x01U;
+
+  switch (val->ois.ctrl_md)
+  {
+    case LSM6DSO_OIS_ONLY_AUX:
+      ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs;
+      ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr |
+                              (uint8_t)val->ois.xl.odr;
+      ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr;
+      ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs;
+      break;
+
+    case LSM6DSO_OIS_MIXED:
+      ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs;
+      ctrl7_g.ois_on = (uint8_t)val->ois.gy.odr | (uint8_t)val->ois.xl.odr;
+      ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr;
+      ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs;
+      break;
+
+    default:
+      ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs;
+      ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr |
+                              (uint8_t)val->ois.xl.odr;
+      ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr;
+      ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs;
+      break;
+  }
+
+  /* UI new configuration */
+  ctrl1_xl.odr_xl = odr_xl;
+  ctrl1_xl.fs_xl = (uint8_t)val->ui.xl.fs;
+  ctrl5_c.xl_ulp_en = xl_ulp_en;
+  ctrl6_c.xl_hm_mode = xl_hm_mode;
+  ctrl7_g.g_hm_mode = g_hm_mode;
+  ctrl2_g.odr_g = odr_gy;
+  ctrl2_g.fs_g = (uint8_t) val->ui.gy.fs;
+
+  /* writing checked configuration */
+  if (ctx != NULL)
+  {
+    bytecpy(&reg[0], (uint8_t *)&ctrl1_xl);
+    bytecpy(&reg[1], (uint8_t *)&ctrl2_g);
+    bytecpy(&reg[2], (uint8_t *)&ctrl3_c);
+    bytecpy(&reg[3], (uint8_t *)&ctrl4_c);
+    bytecpy(&reg[4], (uint8_t *)&ctrl5_c);
+    bytecpy(&reg[5], (uint8_t *)&ctrl6_c);
+    bytecpy(&reg[6], (uint8_t *)&ctrl7_g);
+    bytecpy(&reg[7], (uint8_t *)&ctrl8_xl);
+
+    if (ret == 0)
+    {
+      ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)&reg, 8);
+    }
+
+    if (ret == 0)
+    {
+      ret = lsm6dso_write_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS,
+                              (uint8_t *)&func_cfg_access, 1);
+    }
+  }
+
+  /* writing OIS checked configuration */
+  if (aux_ctx != NULL)
+  {
+    bytecpy(&reg[0], (uint8_t *)&ctrl1_ois);
+    bytecpy(&reg[1], (uint8_t *)&ctrl2_ois);
+    bytecpy(&reg[2], (uint8_t *)&ctrl3_ois);
+
+    if (ret == 0)
+    {
+      ret = lsm6dso_write_reg(aux_ctx, LSM6DSO_CTRL1_OIS, reg, 3);
+    }
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Sensor conversion parameters selection.[get]
+  *
+  * @param  ctx          communication interface handler. Use NULL to ignore
+  *                      this interface.(ptr)
+  * @param  aux_ctx      auxiliary communication interface handler. Use NULL
+  *                      to ignore this interface.(ptr)
+  * @param  val          get the sensor conversion parameters.(ptr)
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_mode_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
+                         lsm6dso_md_t *val)
+{
+  lsm6dso_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
+  lsm6dso_func_cfg_access_t func_cfg_access;
+  lsm6dso_emb_func_en_b_t emb_func_en_b;
+  lsm6dso_fsm_enable_a_t fsm_enable_a;
+  lsm6dso_fsm_enable_b_t fsm_enable_b;
+  lsm6dso_ctrl1_ois_t ctrl1_ois;
+  lsm6dso_ctrl2_ois_t ctrl2_ois;
+  lsm6dso_ctrl3_ois_t ctrl3_ois;
+  lsm6dso_ctrl1_xl_t ctrl1_xl;
+  lsm6dso_ctrl2_g_t ctrl2_g;
+  lsm6dso_ctrl3_c_t ctrl3_c;
+  lsm6dso_ctrl4_c_t ctrl4_c;
+  lsm6dso_ctrl5_c_t ctrl5_c;
+  lsm6dso_ctrl6_c_t ctrl6_c;
+  lsm6dso_ctrl7_g_t ctrl7_g;
+  uint8_t reg[8];
+  int32_t ret;
+
+  ret = 0;
+
+  /* reading the registers of the device */
+  if (ctx != NULL)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, reg, 7);
+    bytecpy((uint8_t *)&ctrl1_xl, &reg[0]);
+    bytecpy((uint8_t *)&ctrl2_g,  &reg[1]);
+    bytecpy((uint8_t *)&ctrl3_c,  &reg[2]);
+    bytecpy((uint8_t *)&ctrl4_c,  &reg[3]);
+    bytecpy((uint8_t *)&ctrl5_c,  &reg[4]);
+    bytecpy((uint8_t *)&ctrl6_c,  &reg[5]);
+    bytecpy((uint8_t *)&ctrl7_g,  &reg[6]);
+
+    if (ret == 0)
+    {
+      ret = lsm6dso_read_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS,
+                             (uint8_t *)&func_cfg_access, 1);
+    }
+
+    if (ret == 0)
+    {
+      ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+    }
+
+    if (ret == 0)
+    {
+      ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_ODR_CFG_B, reg, 1);
+      bytecpy((uint8_t *)&emb_func_odr_cfg_b, &reg[0]);
+    }
+
+    if (ret == 0)
+    {
+      ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
+                             (uint8_t *)&emb_func_en_b, 1);
+    }
+
+    if (ret == 0)
+    {
+      ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_ENABLE_A, reg, 2);
+      bytecpy((uint8_t *)&fsm_enable_a, &reg[0]);
+      bytecpy((uint8_t *)&fsm_enable_b, &reg[1]);
+    }
+
+    if (ret == 0)
+    {
+      ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+    }
+  }
+
+  if (aux_ctx != NULL)
+  {
+    if (ret == 0)
+    {
+      ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_CTRL1_OIS, reg, 3);
+    }
+
+    bytecpy((uint8_t *)&ctrl1_ois, &reg[0]);
+    bytecpy((uint8_t *)&ctrl2_ois, &reg[1]);
+    bytecpy((uint8_t *)&ctrl3_ois, &reg[2]);
+  }
+
+  else
+  {
+    if (ctx != NULL)
+    {
+      if (ret == 0)
+      {
+        ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, reg, 3);
+      }
+
+      bytecpy((uint8_t *)&ctrl1_ois, &reg[0]);
+      bytecpy((uint8_t *)&ctrl2_ois, &reg[1]);
+      bytecpy((uint8_t *)&ctrl3_ois, &reg[2]);
+    }
+  }
+
+  /* fill the input structure */
+
+  /* get accelerometer configuration */
+  switch ((ctrl5_c.xl_ulp_en << 5) | (ctrl6_c.xl_hm_mode << 4) |
+          ctrl1_xl.odr_xl)
+  {
+    case LSM6DSO_XL_UI_OFF:
+      val->ui.xl.odr = LSM6DSO_XL_UI_OFF;
+      break;
+
+    case LSM6DSO_XL_UI_12Hz5_HP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_12Hz5_HP;
+      break;
+
+    case LSM6DSO_XL_UI_26Hz_HP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_26Hz_HP;
+      break;
+
+    case LSM6DSO_XL_UI_52Hz_HP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_52Hz_HP;
+      break;
+
+    case LSM6DSO_XL_UI_104Hz_HP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_104Hz_HP;
+      break;
+
+    case LSM6DSO_XL_UI_208Hz_HP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_208Hz_HP;
+      break;
+
+    case LSM6DSO_XL_UI_416Hz_HP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_416Hz_HP;
+      break;
+
+    case LSM6DSO_XL_UI_833Hz_HP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_833Hz_HP;
+      break;
+
+    case LSM6DSO_XL_UI_1667Hz_HP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_1667Hz_HP;
+      break;
+
+    case LSM6DSO_XL_UI_3333Hz_HP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_3333Hz_HP;
+      break;
+
+    case LSM6DSO_XL_UI_6667Hz_HP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_6667Hz_HP;
+      break;
+
+    case LSM6DSO_XL_UI_1Hz6_LP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_1Hz6_LP;
+      break;
+
+    case LSM6DSO_XL_UI_12Hz5_LP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_12Hz5_LP;
+      break;
+
+    case LSM6DSO_XL_UI_26Hz_LP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_26Hz_LP;
+      break;
+
+    case LSM6DSO_XL_UI_52Hz_LP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_52Hz_LP;
+      break;
+
+    case LSM6DSO_XL_UI_104Hz_NM:
+      val->ui.xl.odr = LSM6DSO_XL_UI_104Hz_NM;
+      break;
+
+    case LSM6DSO_XL_UI_208Hz_NM:
+      val->ui.xl.odr = LSM6DSO_XL_UI_208Hz_NM;
+      break;
+
+    case LSM6DSO_XL_UI_1Hz6_ULP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_1Hz6_ULP;
+      break;
+
+    case LSM6DSO_XL_UI_12Hz5_ULP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_12Hz5_ULP;
+      break;
+
+    case LSM6DSO_XL_UI_26Hz_ULP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_26Hz_ULP;
+      break;
+
+    case LSM6DSO_XL_UI_52Hz_ULP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_52Hz_ULP;
+      break;
+
+    case LSM6DSO_XL_UI_104Hz_ULP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_104Hz_ULP;
+      break;
+
+    case LSM6DSO_XL_UI_208Hz_ULP:
+      val->ui.xl.odr = LSM6DSO_XL_UI_208Hz_ULP;
+      break;
+
+    default:
+      val->ui.xl.odr = LSM6DSO_XL_UI_OFF;
+      break;
+  }
+
+  switch (ctrl1_xl.fs_xl)
+  {
+    case LSM6DSO_XL_UI_2g:
+      val->ui.xl.fs = LSM6DSO_XL_UI_2g;
+      break;
+
+    case LSM6DSO_XL_UI_4g:
+      val->ui.xl.fs = LSM6DSO_XL_UI_4g;
+      break;
+
+    case LSM6DSO_XL_UI_8g:
+      val->ui.xl.fs = LSM6DSO_XL_UI_8g;
+      break;
+
+    case LSM6DSO_XL_UI_16g:
+      val->ui.xl.fs = LSM6DSO_XL_UI_16g;
+      break;
+
+    default:
+      val->ui.xl.fs = LSM6DSO_XL_UI_2g;
+      break;
+  }
+
+  /* get gyroscope configuration */
+  switch ((ctrl7_g.g_hm_mode << 4) | ctrl2_g.odr_g)
+  {
+    case LSM6DSO_GY_UI_OFF:
+      val->ui.gy.odr = LSM6DSO_GY_UI_OFF;
+      break;
+
+    case LSM6DSO_GY_UI_12Hz5_LP:
+      val->ui.gy.odr = LSM6DSO_GY_UI_12Hz5_LP;
+      break;
+
+    case LSM6DSO_GY_UI_12Hz5_HP:
+      val->ui.gy.odr = LSM6DSO_GY_UI_12Hz5_HP;
+      break;
+
+    case LSM6DSO_GY_UI_26Hz_LP:
+      val->ui.gy.odr = LSM6DSO_GY_UI_26Hz_LP;
+      break;
+
+    case LSM6DSO_GY_UI_26Hz_HP:
+      val->ui.gy.odr = LSM6DSO_GY_UI_26Hz_HP;
+      break;
+
+    case LSM6DSO_GY_UI_52Hz_LP:
+      val->ui.gy.odr = LSM6DSO_GY_UI_52Hz_LP;
+      break;
+
+    case LSM6DSO_GY_UI_52Hz_HP:
+      val->ui.gy.odr = LSM6DSO_GY_UI_52Hz_HP;
+      break;
+
+    case LSM6DSO_GY_UI_104Hz_NM:
+      val->ui.gy.odr = LSM6DSO_GY_UI_104Hz_NM;
+      break;
+
+    case LSM6DSO_GY_UI_104Hz_HP:
+      val->ui.gy.odr = LSM6DSO_GY_UI_104Hz_HP;
+      break;
+
+    case LSM6DSO_GY_UI_208Hz_NM:
+      val->ui.gy.odr = LSM6DSO_GY_UI_208Hz_NM;
+      break;
+
+    case LSM6DSO_GY_UI_208Hz_HP:
+      val->ui.gy.odr = LSM6DSO_GY_UI_208Hz_HP;
+      break;
+
+    case LSM6DSO_GY_UI_416Hz_HP:
+      val->ui.gy.odr = LSM6DSO_GY_UI_416Hz_HP;
+      break;
+
+    case LSM6DSO_GY_UI_833Hz_HP:
+      val->ui.gy.odr = LSM6DSO_GY_UI_833Hz_HP;
+      break;
+
+    case LSM6DSO_GY_UI_1667Hz_HP:
+      val->ui.gy.odr = LSM6DSO_GY_UI_1667Hz_HP;
+      break;
+
+    case LSM6DSO_GY_UI_3333Hz_HP:
+      val->ui.gy.odr = LSM6DSO_GY_UI_3333Hz_HP;
+      break;
+
+    case LSM6DSO_GY_UI_6667Hz_HP:
+      val->ui.gy.odr = LSM6DSO_GY_UI_6667Hz_HP;
+      break;
+
+    default:
+      val->ui.gy.odr = LSM6DSO_GY_UI_OFF;
+      break;
+  }
+
+  switch (ctrl2_g.fs_g)
+  {
+    case LSM6DSO_GY_UI_125dps:
+      val->ui.gy.fs = LSM6DSO_GY_UI_125dps;
+      break;
+
+    case LSM6DSO_GY_UI_250dps:
+      val->ui.gy.fs = LSM6DSO_GY_UI_250dps;
+      break;
+
+    case LSM6DSO_GY_UI_500dps:
+      val->ui.gy.fs = LSM6DSO_GY_UI_500dps;
+      break;
+
+    case LSM6DSO_GY_UI_1000dps:
+      val->ui.gy.fs = LSM6DSO_GY_UI_1000dps;
+      break;
+
+    case LSM6DSO_GY_UI_2000dps:
+      val->ui.gy.fs = LSM6DSO_GY_UI_2000dps;
+      break;
+
+    default:
+      val->ui.gy.fs = LSM6DSO_GY_UI_125dps;
+      break;
+  }
+
+  /* get finite state machine configuration */
+  if ((fsm_enable_a.fsm1_en | fsm_enable_a.fsm2_en |
+       fsm_enable_a.fsm3_en |
+       fsm_enable_a.fsm4_en | fsm_enable_a.fsm5_en | fsm_enable_a.fsm6_en |
+       fsm_enable_a.fsm7_en | fsm_enable_a.fsm8_en | fsm_enable_b.fsm9_en |
+       fsm_enable_b.fsm10_en | fsm_enable_b.fsm11_en |
+       fsm_enable_b.fsm12_en | fsm_enable_b.fsm13_en |
+       fsm_enable_b.fsm14_en | fsm_enable_b.fsm15_en |
+       fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
+  {
+    switch (emb_func_odr_cfg_b.fsm_odr)
+    {
+      case LSM6DSO_FSM_12Hz5:
+        val->fsm.odr = LSM6DSO_FSM_12Hz5;
+        break;
+
+      case LSM6DSO_FSM_26Hz:
+        val->fsm.odr = LSM6DSO_FSM_26Hz;
+        break;
+
+      case LSM6DSO_FSM_52Hz:
+        val->fsm.odr = LSM6DSO_FSM_52Hz;
+        break;
+
+      case LSM6DSO_FSM_104Hz:
+        val->fsm.odr = LSM6DSO_FSM_104Hz;
+        break;
+
+      default:
+        val->fsm.odr = LSM6DSO_FSM_12Hz5;
+        break;
+    }
+
+    val->fsm.sens = LSM6DSO_FSM_XL_GY;
+
+    if (val->ui.gy.odr == LSM6DSO_GY_UI_OFF)
+    {
+      val->fsm.sens = LSM6DSO_FSM_XL;
+    }
+
+    if (val->ui.xl.odr == LSM6DSO_XL_UI_OFF)
+    {
+      val->fsm.sens = LSM6DSO_FSM_GY;
+    }
+  }
+
+  else
+  {
+    val->fsm.sens = LSM6DSO_FSM_DISABLE;
+  }
+
+  /* get ois configuration */
+
+  /* OIS configuration mode */
+  switch (ctrl7_g.ois_on_en)
+  {
+    case LSM6DSO_OIS_ONLY_AUX:
+      switch (ctrl3_ois.fs_xl_ois)
+      {
+        case LSM6DSO_XL_OIS_2g:
+          val->ois.xl.fs = LSM6DSO_XL_OIS_2g;
+          break;
+
+        case LSM6DSO_XL_OIS_4g:
+          val->ois.xl.fs = LSM6DSO_XL_OIS_4g;
+          break;
+
+        case LSM6DSO_XL_OIS_8g:
+          val->ois.xl.fs = LSM6DSO_XL_OIS_8g;
+          break;
+
+        case LSM6DSO_XL_OIS_16g:
+          val->ois.xl.fs = LSM6DSO_XL_OIS_16g;
+          break;
+
+        default:
+          val->ois.xl.fs = LSM6DSO_XL_OIS_2g;
+          break;
+      }
+
+      switch (ctrl1_ois.mode4_en)
+      {
+        case LSM6DSO_XL_OIS_OFF:
+          val->ois.xl.odr = LSM6DSO_XL_OIS_OFF;
+          break;
+
+        case LSM6DSO_XL_OIS_6667Hz_HP:
+          val->ois.xl.odr = LSM6DSO_XL_OIS_6667Hz_HP;
+          break;
+
+        default:
+          val->ois.xl.odr = LSM6DSO_XL_OIS_OFF;
+          break;
+      }
+
+      switch (ctrl1_ois.fs_g_ois)
+      {
+        case LSM6DSO_GY_OIS_250dps:
+          val->ois.gy.fs = LSM6DSO_GY_OIS_250dps;
+          break;
+
+        case LSM6DSO_GY_OIS_500dps:
+          val->ois.gy.fs = LSM6DSO_GY_OIS_500dps;
+          break;
+
+        case LSM6DSO_GY_OIS_1000dps:
+          val->ois.gy.fs = LSM6DSO_GY_OIS_1000dps;
+          break;
+
+        case LSM6DSO_GY_OIS_2000dps:
+          val->ois.gy.fs = LSM6DSO_GY_OIS_2000dps;
+          break;
+
+        default:
+          val->ois.gy.fs = LSM6DSO_GY_OIS_250dps;
+          break;
+      }
+
+      switch (ctrl1_ois.ois_en_spi2)
+      {
+        case LSM6DSO_GY_OIS_OFF:
+          val->ois.gy.odr = LSM6DSO_GY_OIS_OFF;
+          break;
+
+        case LSM6DSO_GY_OIS_6667Hz_HP:
+          val->ois.gy.odr = LSM6DSO_GY_OIS_6667Hz_HP;
+          break;
+
+        default:
+          val->ois.gy.odr = LSM6DSO_GY_OIS_OFF;
+          break;
+      }
+
+      val->ois.ctrl_md = LSM6DSO_OIS_ONLY_AUX;
+      break;
+
+    case LSM6DSO_OIS_MIXED:
+      switch (ctrl3_ois.fs_xl_ois)
+      {
+        case LSM6DSO_XL_OIS_2g:
+          val->ois.xl.fs = LSM6DSO_XL_OIS_2g;
+          break;
+
+        case LSM6DSO_XL_OIS_4g:
+          val->ois.xl.fs = LSM6DSO_XL_OIS_4g;
+          break;
+
+        case LSM6DSO_XL_OIS_8g:
+          val->ois.xl.fs = LSM6DSO_XL_OIS_8g;
+          break;
+
+        case LSM6DSO_XL_OIS_16g:
+          val->ois.xl.fs = LSM6DSO_XL_OIS_16g;
+          break;
+
+        default:
+          val->ois.xl.fs = LSM6DSO_XL_OIS_2g;
+          break;
+      }
+
+      switch (ctrl1_ois.mode4_en)
+      {
+        case LSM6DSO_XL_OIS_OFF:
+          val->ois.xl.odr = LSM6DSO_XL_OIS_OFF;
+          break;
+
+        case LSM6DSO_XL_OIS_6667Hz_HP:
+          val->ois.xl.odr = LSM6DSO_XL_OIS_6667Hz_HP;
+          break;
+
+        default:
+          val->ois.xl.odr = LSM6DSO_XL_OIS_OFF;
+          break;
+      }
+
+      switch (ctrl1_ois.fs_g_ois)
+      {
+        case LSM6DSO_GY_OIS_250dps:
+          val->ois.gy.fs = LSM6DSO_GY_OIS_250dps;
+          break;
+
+        case LSM6DSO_GY_OIS_500dps:
+          val->ois.gy.fs = LSM6DSO_GY_OIS_500dps;
+          break;
+
+        case LSM6DSO_GY_OIS_1000dps:
+          val->ois.gy.fs = LSM6DSO_GY_OIS_1000dps;
+          break;
+
+        case LSM6DSO_GY_OIS_2000dps:
+          val->ois.gy.fs = LSM6DSO_GY_OIS_2000dps;
+          break;
+
+        default:
+          val->ois.gy.fs = LSM6DSO_GY_OIS_250dps;
+          break;
+      }
+
+      switch (ctrl1_ois.ois_en_spi2)
+      {
+        case LSM6DSO_GY_OIS_OFF:
+          val->ois.gy.odr = LSM6DSO_GY_OIS_OFF;
+          break;
+
+        case LSM6DSO_GY_OIS_6667Hz_HP:
+          val->ois.gy.odr = LSM6DSO_GY_OIS_6667Hz_HP;
+          break;
+
+        default:
+          val->ois.gy.odr = LSM6DSO_GY_OIS_OFF;
+          break;
+      }
+
+      val->ois.ctrl_md = LSM6DSO_OIS_MIXED;
+      break;
+
+    default:
+      ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs;
+      ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr |
+                              (uint8_t)val->ois.xl.odr;
+      ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr;
+      ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs;
+      val->ois.ctrl_md = LSM6DSO_OIS_ONLY_AUX;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Read data in engineering unit.[get]
+  *
+  * @param  ctx     communication interface handler.(ptr)
+  * @param  md      the sensor conversion parameters.(ptr)
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_data_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
+                         lsm6dso_md_t *md, lsm6dso_data_t *data)
+{
+  uint8_t buff[14];
+  int32_t ret;
+
+  uint8_t i;
+  uint8_t j;
+  ret = 0;
+
+  /* read data */
+  if (ctx != NULL)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_OUT_TEMP_L, buff, 14);
+  }
+
+  j = 0;
+  /* temperature conversion */
+  data->ui.heat.raw = (int16_t)buff[j + 1U];
+  data->ui.heat.raw = (((int16_t)data->ui.heat.raw * (int16_t)256) +
+                       (int16_t)buff[j]);
+  j += 2U;
+  data->ui.heat.deg_c = lsm6dso_from_lsb_to_celsius((
+                                                      int16_t)data->ui.heat.raw);
+
+  /* angular rate conversion */
+  for (i = 0U; i < 3U; i++)
+  {
+    data->ui.gy.raw[i] = (int16_t)buff[j + 1U];
+    data->ui.gy.raw[i] = (data->ui.gy.raw[i] * 256) + (int16_t) buff[j];
+    j += 2U;
+
+    switch (md->ui.gy.fs)
+    {
+      case LSM6DSO_GY_UI_250dps:
+        data->ui.gy.mdps[i] = lsm6dso_from_fs250_to_mdps(data->ui.gy.raw[i]);
+        break;
+
+      case LSM6DSO_GY_UI_125dps:
+        data->ui.gy.mdps[i] = lsm6dso_from_fs125_to_mdps(data->ui.gy.raw[i]);
+        break;
+
+      case LSM6DSO_GY_UI_500dps:
+        data->ui.gy.mdps[i] = lsm6dso_from_fs500_to_mdps(data->ui.gy.raw[i]);
+        break;
+
+      case LSM6DSO_GY_UI_1000dps:
+        data->ui.gy.mdps[i] = lsm6dso_from_fs1000_to_mdps(data->ui.gy.raw[i]);
+        break;
+
+      case LSM6DSO_GY_UI_2000dps:
+        data->ui.gy.mdps[i] = lsm6dso_from_fs2000_to_mdps(data->ui.gy.raw[i]);
+        break;
+
+      default:
+        data->ui.gy.mdps[i] = 0.0f;
+        break;
+    }
+  }
+
+  /* acceleration conversion */
+  for (i = 0U; i < 3U; i++)
+  {
+    data->ui.xl.raw[i] = (int16_t)buff[j + 1U];
+    data->ui.xl.raw[i] = (data->ui.xl.raw[i] * 256) + (int16_t) buff[j];
+    j += 2U;
+
+    switch (md->ui.xl.fs)
+    {
+      case LSM6DSO_XL_UI_2g:
+        data->ui.xl.mg[i] = lsm6dso_from_fs2_to_mg(data->ui.xl.raw[i]);
+        break;
+
+      case LSM6DSO_XL_UI_4g:
+        data->ui.xl.mg[i] = lsm6dso_from_fs4_to_mg(data->ui.xl.raw[i]);
+        break;
+
+      case LSM6DSO_XL_UI_8g:
+        data->ui.xl.mg[i] = lsm6dso_from_fs8_to_mg(data->ui.xl.raw[i]);
+        break;
+
+      case LSM6DSO_XL_UI_16g:
+        data->ui.xl.mg[i] = lsm6dso_from_fs16_to_mg(data->ui.xl.raw[i]);
+        break;
+
+      default:
+        data->ui.xl.mg[i] = 0.0f;
+        break;
+    }
+  }
+
+  /* read data from ois chain */
+  if (aux_ctx != NULL)
+  {
+    if (ret == 0)
+    {
+      ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_OUTX_L_G, buff, 12);
+    }
+  }
+
+  j = 0;
+
+  /* ois angular rate conversion */
+  for (i = 0U; i < 3U; i++)
+  {
+    data->ois.gy.raw[i] = (int16_t) buff[j + 1U];
+    data->ois.gy.raw[i] = (data->ois.gy.raw[i] * 256) + (int16_t) buff[j];
+    j += 2U;
+
+    switch (md->ois.gy.fs)
+    {
+      case LSM6DSO_GY_UI_250dps:
+        data->ois.gy.mdps[i] = lsm6dso_from_fs250_to_mdps(
+                                 data->ois.gy.raw[i]);
+        break;
+
+      case LSM6DSO_GY_UI_125dps:
+        data->ois.gy.mdps[i] = lsm6dso_from_fs125_to_mdps(
+                                 data->ois.gy.raw[i]);
+        break;
+
+      case LSM6DSO_GY_UI_500dps:
+        data->ois.gy.mdps[i] = lsm6dso_from_fs500_to_mdps(
+                                 data->ois.gy.raw[i]);
+        break;
+
+      case LSM6DSO_GY_UI_1000dps:
+        data->ois.gy.mdps[i] = lsm6dso_from_fs1000_to_mdps(
+                                 data->ois.gy.raw[i]);
+        break;
+
+      case LSM6DSO_GY_UI_2000dps:
+        data->ois.gy.mdps[i] = lsm6dso_from_fs2000_to_mdps(
+                                 data->ois.gy.raw[i]);
+        break;
+
+      default:
+        data->ois.gy.mdps[i] = 0.0f;
+        break;
+    }
+  }
+
+  /* ois acceleration conversion */
+  for (i = 0U; i < 3U; i++)
+  {
+    data->ois.xl.raw[i] = (int16_t) buff[j + 1U];
+    data->ois.xl.raw[i] = (data->ois.xl.raw[i] * 256) + (int16_t) buff[j];
+    j += 2U;
+
+    switch (md->ois.xl.fs)
+    {
+      case LSM6DSO_XL_UI_2g:
+        data->ois.xl.mg[i] = lsm6dso_from_fs2_to_mg(data->ois.xl.raw[i]);
+        break;
+
+      case LSM6DSO_XL_UI_4g:
+        data->ois.xl.mg[i] = lsm6dso_from_fs4_to_mg(data->ois.xl.raw[i]);
+        break;
+
+      case LSM6DSO_XL_UI_8g:
+        data->ois.xl.mg[i] = lsm6dso_from_fs8_to_mg(data->ois.xl.raw[i]);
+        break;
+
+      case LSM6DSO_XL_UI_16g:
+        data->ois.xl.mg[i] = lsm6dso_from_fs16_to_mg(data->ois.xl.raw[i]);
+        break;
+
+      default:
+        data->ois.xl.mg[i] = 0.0f;
+        break;
+    }
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Embedded functions.[set]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      change the values of registers
+  *                  EMB_FUNC_EN_A e EMB_FUNC_EN_B.
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_embedded_sens_set(stmdev_ctx_t *ctx,
+                                  lsm6dso_emb_sens_t *val)
+{
+  lsm6dso_emb_func_en_a_t emb_func_en_a;
+  lsm6dso_emb_func_en_b_t emb_func_en_b;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A,
+                           (uint8_t *)&emb_func_en_a, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
+                           (uint8_t *)&emb_func_en_b, 1);
+    emb_func_en_b.fsm_en = val->fsm;
+    emb_func_en_a.tilt_en = val->tilt;
+    emb_func_en_a.pedo_en = val->step;
+    emb_func_en_b.pedo_adv_en = val->step_adv;
+    emb_func_en_a.sign_motion_en = val->sig_mot;
+    emb_func_en_b.fifo_compr_en = val->fifo_compr;
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_A,
+                            (uint8_t *)&emb_func_en_a, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
+                            (uint8_t *)&emb_func_en_b, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Embedded functions.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      get the values of registers
+  *                  EMB_FUNC_EN_A e EMB_FUNC_EN_B.
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_embedded_sens_get(stmdev_ctx_t *ctx,
+                                  lsm6dso_emb_sens_t *emb_sens)
+{
+  lsm6dso_emb_func_en_a_t emb_func_en_a;
+  lsm6dso_emb_func_en_b_t emb_func_en_b;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A,
+                           (uint8_t *)&emb_func_en_a, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
+                           (uint8_t *)&emb_func_en_b, 1);
+    emb_sens->fsm = emb_func_en_b.fsm_en;
+    emb_sens->tilt = emb_func_en_a.tilt_en;
+    emb_sens->step = emb_func_en_a.pedo_en;
+    emb_sens->step_adv = emb_func_en_b.pedo_adv_en;
+    emb_sens->sig_mot = emb_func_en_a.sign_motion_en;
+    emb_sens->fifo_compr = emb_func_en_b.fifo_compr_en;
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  turn off all embedded functions.[get]
+  *
+  * @param  ctx      read / write interface definitions
+  * @param  val      get the values of registers
+  *                  EMB_FUNC_EN_A e EMB_FUNC_EN_B.
+  * @retval             interface status (MANDATORY: return 0 -> no Error)
+  *
+  */
+int32_t lsm6dso_embedded_sens_off(stmdev_ctx_t *ctx)
+{
+  lsm6dso_emb_func_en_a_t emb_func_en_a;
+  lsm6dso_emb_func_en_b_t emb_func_en_b;
+  int32_t ret;
+
+  ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A,
+                           (uint8_t *)&emb_func_en_a, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
+                           (uint8_t *)&emb_func_en_b, 1);
+    emb_func_en_b.fsm_en = PROPERTY_DISABLE;
+    emb_func_en_a.tilt_en = PROPERTY_DISABLE;
+    emb_func_en_a.pedo_en = PROPERTY_DISABLE;
+    emb_func_en_b.pedo_adv_en = PROPERTY_DISABLE;
+    emb_func_en_a.sign_motion_en = PROPERTY_DISABLE;
+    emb_func_en_b.fifo_compr_en = PROPERTY_DISABLE;
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_A,
+                            (uint8_t *)&emb_func_en_a, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
+                            (uint8_t *)&emb_func_en_b, 1);
+  }
+
+  if (ret == 0)
+  {
+    ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
+  }
+
+  return ret;
+}
+
+/**
+  * @}
+  *
+  */
+
+/**
+  * @}
+  *
+  */

airmouse/lib/lsm6dso-api/lsm6dso_reg.h

@@ -0,0 +1,4486 @@
+/**
+  ******************************************************************************
+  * @file    lsm6dso_reg.h
+  * @author  Sensors Software Solution Team
+  * @brief   This file contains all the functions prototypes for the
+  *          lsm6dso_reg.c driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef LSM6DSO_REGS_H
+#define LSM6DSO_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stdint.h>
+#include <stddef.h>
+#include <math.h>
+
+/** @addtogroup LSM6DSO
+  * @{
+  *
+  */
+
+/** @defgroup  Endianness definitions
+  * @{
+  *
+  */
+
+#ifndef DRV_BYTE_ORDER
+#ifndef __BYTE_ORDER__
+
+#define DRV_LITTLE_ENDIAN 1234
+#define DRV_BIG_ENDIAN    4321
+
+/** if _BYTE_ORDER is not defined, choose the endianness of your architecture
+  * by uncommenting the define which fits your platform endianness
+  */
+//#define DRV_BYTE_ORDER    DRV_BIG_ENDIAN
+#define DRV_BYTE_ORDER    DRV_LITTLE_ENDIAN
+
+#else /* defined __BYTE_ORDER__ */
+
+#define DRV_LITTLE_ENDIAN  __ORDER_LITTLE_ENDIAN__
+#define DRV_BIG_ENDIAN     __ORDER_BIG_ENDIAN__
+#define DRV_BYTE_ORDER     __BYTE_ORDER__
+
+#endif /* __BYTE_ORDER__*/
+#endif /* DRV_BYTE_ORDER */
+
+/**
+  * @}
+  *
+  */
+
+/** @defgroup STMicroelectronics sensors common types
+  * @{
+  *
+  */
+
+#ifndef MEMS_SHARED_TYPES
+#define MEMS_SHARED_TYPES
+
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t bit0       : 1;
+  uint8_t bit1       : 1;
+  uint8_t bit2       : 1;
+  uint8_t bit3       : 1;
+  uint8_t bit4       : 1;
+  uint8_t bit5       : 1;
+  uint8_t bit6       : 1;
+  uint8_t bit7       : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t bit7       : 1;
+  uint8_t bit6       : 1;
+  uint8_t bit5       : 1;
+  uint8_t bit4       : 1;
+  uint8_t bit3       : 1;
+  uint8_t bit2       : 1;
+  uint8_t bit1       : 1;
+  uint8_t bit0       : 1;
+#endif /* DRV_BYTE_ORDER */
+} bitwise_t;
+
+#define PROPERTY_DISABLE                (0U)
+#define PROPERTY_ENABLE                 (1U)
+
+/** @addtogroup  Interfaces_Functions
+  * @brief       This section provide a set of functions used to read and
+  *              write a generic register of the device.
+  *              MANDATORY: return 0 -> no Error.
+  * @{
+  *
+  */
+
+typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t *, uint16_t);
+typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
+typedef void (*stmdev_mdelay_ptr)(uint32_t millisec);
+
+typedef struct
+{
+  /** Component mandatory fields **/
+  stmdev_write_ptr  write_reg;
+  stmdev_read_ptr   read_reg;
+  /** Component optional fields **/
+  stmdev_mdelay_ptr   mdelay;
+  /** Customizable optional pointer **/
+  void *handle;
+} stmdev_ctx_t;
+
+#ifndef __weak
+#define __weak __attribute__((weak))
+#endif /* __weak */
+
+/*
+ * These are the basic platform dependent I/O routines to read
+ * and write device registers connected on a standard bus.
+ * The driver keeps offering a default implementation based on function
+ * pointers to read/write routines for backward compatibility.
+ * The __weak directive allows the final application to overwrite
+ * them with a custom implementation.
+ */
+int32_t lsm6dso_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
+                                uint8_t *data,
+                                uint16_t len);
+int32_t lsm6dso_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
+                                 uint8_t *data,
+                                 uint16_t len);
+
+/**
+  * @}
+  *
+  */
+
+#endif /* MEMS_SHARED_TYPES */
+
+#ifndef MEMS_UCF_SHARED_TYPES
+#define MEMS_UCF_SHARED_TYPES
+
+/** @defgroup    Generic address-data structure definition
+  * @brief       This structure is useful to load a predefined configuration
+  *              of a sensor.
+  *              You can create a sensor configuration by your own or using
+  *              Unico / Unicleo tools available on STMicroelectronics
+  *              web site.
+  *
+  * @{
+  *
+  */
+
+typedef struct
+{
+  uint8_t address;
+  uint8_t data;
+} ucf_line_t;
+
+/**
+  * @}
+  *
+  */
+
+#endif /* MEMS_UCF_SHARED_TYPES */
+
+/**
+  * @}
+  *
+  */
+
+/** @defgroup LSM6DSO_Infos
+  * @{
+  *
+  */
+
+/** I2C Device Address 8 bit format  if SA0=0 -> D5 if SA0=1 -> D7 **/
+#define LSM6DSO_I2C_ADD_L                    0xD5
+#define LSM6DSO_I2C_ADD_H                    0xD7
+
+/** Device Identification (Who am I) **/
+#define LSM6DSO_ID                           0x6C
+
+/**
+  * @}
+  *
+  */
+
+#define LSM6DSO_FUNC_CFG_ACCESS              0x01U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t not_used_01              : 6;
+uint8_t reg_access               :
+  2; /* shub_reg_access + func_cfg_access */
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+uint8_t reg_access               :
+  2; /* shub_reg_access + func_cfg_access */
+  uint8_t not_used_01              : 6;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_func_cfg_access_t;
+
+#define LSM6DSO_PIN_CTRL                     0x02U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t not_used_01              : 6;
+  uint8_t sdo_pu_en                : 1;
+  uint8_t ois_pu_dis               : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t ois_pu_dis               : 1;
+  uint8_t sdo_pu_en                : 1;
+  uint8_t not_used_01              : 6;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_pin_ctrl_t;
+
+#define LSM6DSO_FIFO_CTRL1                   0x07U
+typedef struct
+{
+  uint8_t wtm                      : 8;
+} lsm6dso_fifo_ctrl1_t;
+
+#define LSM6DSO_FIFO_CTRL2                   0x08U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t wtm                      : 1;
+  uint8_t uncoptr_rate             : 2;
+  uint8_t not_used_01              : 1;
+  uint8_t odrchg_en                : 1;
+  uint8_t not_used_02              : 1;
+  uint8_t fifo_compr_rt_en         : 1;
+  uint8_t stop_on_wtm              : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t stop_on_wtm              : 1;
+  uint8_t fifo_compr_rt_en         : 1;
+  uint8_t not_used_02              : 1;
+  uint8_t odrchg_en                : 1;
+  uint8_t not_used_01              : 1;
+  uint8_t uncoptr_rate             : 2;
+  uint8_t wtm                      : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_fifo_ctrl2_t;
+
+#define LSM6DSO_FIFO_CTRL3                   0x09U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t bdr_xl                   : 4;
+  uint8_t bdr_gy                   : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t bdr_gy                   : 4;
+  uint8_t bdr_xl                   : 4;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_fifo_ctrl3_t;
+
+#define LSM6DSO_FIFO_CTRL4                   0x0AU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t fifo_mode                : 3;
+  uint8_t not_used_01              : 1;
+  uint8_t odr_t_batch              : 2;
+  uint8_t odr_ts_batch             : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t odr_ts_batch             : 2;
+  uint8_t odr_t_batch              : 2;
+  uint8_t not_used_01              : 1;
+  uint8_t fifo_mode                : 3;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_fifo_ctrl4_t;
+
+#define LSM6DSO_COUNTER_BDR_REG1             0x0BU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t cnt_bdr_th               : 3;
+  uint8_t not_used_01              : 2;
+  uint8_t trig_counter_bdr         : 1;
+  uint8_t rst_counter_bdr          : 1;
+  uint8_t dataready_pulsed         : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t dataready_pulsed         : 1;
+  uint8_t rst_counter_bdr          : 1;
+  uint8_t trig_counter_bdr         : 1;
+  uint8_t not_used_01              : 2;
+  uint8_t cnt_bdr_th               : 3;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_counter_bdr_reg1_t;
+
+#define LSM6DSO_COUNTER_BDR_REG2             0x0CU
+typedef struct
+{
+  uint8_t cnt_bdr_th               : 8;
+} lsm6dso_counter_bdr_reg2_t;
+
+#define LSM6DSO_INT1_CTRL  0x0D
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t int1_drdy_xl             : 1;
+  uint8_t int1_drdy_g              : 1;
+  uint8_t int1_boot                : 1;
+  uint8_t int1_fifo_th             : 1;
+  uint8_t int1_fifo_ovr            : 1;
+  uint8_t int1_fifo_full           : 1;
+  uint8_t int1_cnt_bdr             : 1;
+  uint8_t den_drdy_flag            : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t den_drdy_flag            : 1;
+  uint8_t int1_cnt_bdr             : 1;
+  uint8_t int1_fifo_full           : 1;
+  uint8_t int1_fifo_ovr            : 1;
+  uint8_t int1_fifo_th             : 1;
+  uint8_t int1_boot                : 1;
+  uint8_t int1_drdy_g              : 1;
+  uint8_t int1_drdy_xl             : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_int1_ctrl_t;
+
+#define LSM6DSO_INT2_CTRL                    0x0EU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t int2_drdy_xl             : 1;
+  uint8_t int2_drdy_g              : 1;
+  uint8_t int2_drdy_temp           : 1;
+  uint8_t int2_fifo_th             : 1;
+  uint8_t int2_fifo_ovr            : 1;
+  uint8_t int2_fifo_full           : 1;
+  uint8_t int2_cnt_bdr             : 1;
+  uint8_t not_used_01              : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t not_used_01              : 1;
+  uint8_t int2_cnt_bdr             : 1;
+  uint8_t int2_fifo_full           : 1;
+  uint8_t int2_fifo_ovr            : 1;
+  uint8_t int2_fifo_th             : 1;
+  uint8_t int2_drdy_temp           : 1;
+  uint8_t int2_drdy_g              : 1;
+  uint8_t int2_drdy_xl             : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_int2_ctrl_t;
+
+#define LSM6DSO_WHO_AM_I                     0x0FU
+#define LSM6DSO_CTRL1_XL                     0x10U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t not_used_01              : 1;
+  uint8_t lpf2_xl_en               : 1;
+  uint8_t fs_xl                    : 2;
+  uint8_t odr_xl                   : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t odr_xl                   : 4;
+  uint8_t fs_xl                    : 2;
+  uint8_t lpf2_xl_en               : 1;
+  uint8_t not_used_01              : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_ctrl1_xl_t;
+
+#define LSM6DSO_CTRL2_G                      0x11U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t not_used_01              : 1;
+  uint8_t fs_g                     : 3; /* fs_125 + fs_g */
+  uint8_t odr_g                    : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t odr_g                    : 4;
+  uint8_t fs_g                     : 3; /* fs_125 + fs_g */
+  uint8_t not_used_01              : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_ctrl2_g_t;
+
+#define LSM6DSO_CTRL3_C                      0x12U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t sw_reset                 : 1;
+  uint8_t not_used_01              : 1;
+  uint8_t if_inc                   : 1;
+  uint8_t sim                      : 1;
+  uint8_t pp_od                    : 1;
+  uint8_t h_lactive                : 1;
+  uint8_t bdu                      : 1;
+  uint8_t boot                     : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t boot                     : 1;
+  uint8_t bdu                      : 1;
+  uint8_t h_lactive                : 1;
+  uint8_t pp_od                    : 1;
+  uint8_t sim                      : 1;
+  uint8_t if_inc                   : 1;
+  uint8_t not_used_01              : 1;
+  uint8_t sw_reset                 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_ctrl3_c_t;
+
+#define LSM6DSO_CTRL4_C                      0x13U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t not_used_01              : 1;
+  uint8_t lpf1_sel_g               : 1;
+  uint8_t i2c_disable              : 1;
+  uint8_t drdy_mask                : 1;
+  uint8_t not_used_02              : 1;
+  uint8_t int2_on_int1             : 1;
+  uint8_t sleep_g                  : 1;
+  uint8_t not_used_03              : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t not_used_03              : 1;
+  uint8_t sleep_g                  : 1;
+  uint8_t int2_on_int1             : 1;
+  uint8_t not_used_02              : 1;
+  uint8_t drdy_mask                : 1;
+  uint8_t i2c_disable              : 1;
+  uint8_t lpf1_sel_g               : 1;
+  uint8_t not_used_01              : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_ctrl4_c_t;
+
+#define LSM6DSO_CTRL5_C                      0x14U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t st_xl                    : 2;
+  uint8_t st_g                     : 2;
+  uint8_t not_used_01              : 1;
+  uint8_t rounding                 : 2;
+  uint8_t xl_ulp_en                : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t xl_ulp_en                : 1;
+  uint8_t rounding                 : 2;
+  uint8_t not_used_01              : 1;
+  uint8_t st_g                     : 2;
+  uint8_t st_xl                    : 2;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_ctrl5_c_t;
+
+#define LSM6DSO_CTRL6_C                      0x15U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t ftype                    : 3;
+  uint8_t usr_off_w                : 1;
+  uint8_t xl_hm_mode               : 1;
+uint8_t den_mode                 :
+  3;   /* trig_en + lvl1_en + lvl2_en */
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+uint8_t den_mode                 :
+  3;   /* trig_en + lvl1_en + lvl2_en */
+  uint8_t xl_hm_mode               : 1;
+  uint8_t usr_off_w                : 1;
+  uint8_t ftype                    : 3;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_ctrl6_c_t;
+
+#define LSM6DSO_CTRL7_G                      0x16U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t ois_on                   : 1;
+  uint8_t usr_off_on_out           : 1;
+  uint8_t ois_on_en                : 1;
+  uint8_t not_used_01              : 1;
+  uint8_t hpm_g                    : 2;
+  uint8_t hp_en_g                  : 1;
+  uint8_t g_hm_mode                : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t g_hm_mode                : 1;
+  uint8_t hp_en_g                  : 1;
+  uint8_t hpm_g                    : 2;
+  uint8_t not_used_01              : 1;
+  uint8_t ois_on_en                : 1;
+  uint8_t usr_off_on_out           : 1;
+  uint8_t ois_on                   : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_ctrl7_g_t;
+
+#define LSM6DSO_CTRL8_XL                     0x17U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t low_pass_on_6d           : 1;
+  uint8_t xl_fs_mode               : 1;
+  uint8_t hp_slope_xl_en           : 1;
+  uint8_t fastsettl_mode_xl        : 1;
+  uint8_t hp_ref_mode_xl           : 1;
+  uint8_t hpcf_xl                  : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t hpcf_xl                  : 3;
+  uint8_t hp_ref_mode_xl           : 1;
+  uint8_t fastsettl_mode_xl        : 1;
+  uint8_t hp_slope_xl_en           : 1;
+  uint8_t xl_fs_mode               : 1;
+  uint8_t low_pass_on_6d           : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_ctrl8_xl_t;
+
+#define LSM6DSO_CTRL9_XL                     0x18U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t not_used_01              : 1;
+  uint8_t i3c_disable              : 1;
+  uint8_t den_lh                   : 1;
+  uint8_t den_xl_g                 : 2;   /* den_xl_en + den_xl_g */
+  uint8_t den_z                    : 1;
+  uint8_t den_y                    : 1;
+  uint8_t den_x                    : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t den_x                    : 1;
+  uint8_t den_y                    : 1;
+  uint8_t den_z                    : 1;
+  uint8_t den_xl_g                 : 2;   /* den_xl_en + den_xl_g */
+  uint8_t den_lh                   : 1;
+  uint8_t i3c_disable              : 1;
+  uint8_t not_used_01              : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_ctrl9_xl_t;
+
+#define LSM6DSO_CTRL10_C                     0x19U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t not_used_01              : 5;
+  uint8_t timestamp_en             : 1;
+  uint8_t not_used_02              : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t not_used_02              : 2;
+  uint8_t timestamp_en             : 1;
+  uint8_t not_used_01              : 5;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_ctrl10_c_t;
+
+#define LSM6DSO_ALL_INT_SRC                  0x1AU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t ff_ia                    : 1;
+  uint8_t wu_ia                    : 1;
+  uint8_t single_tap               : 1;
+  uint8_t double_tap               : 1;
+  uint8_t d6d_ia                   : 1;
+  uint8_t sleep_change_ia          : 1;
+  uint8_t not_used_01              : 1;
+  uint8_t timestamp_endcount       : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t timestamp_endcount       : 1;
+  uint8_t not_used_01              : 1;
+  uint8_t sleep_change_ia          : 1;
+  uint8_t d6d_ia                   : 1;
+  uint8_t double_tap               : 1;
+  uint8_t single_tap               : 1;
+  uint8_t wu_ia                    : 1;
+  uint8_t ff_ia                    : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_all_int_src_t;
+
+#define LSM6DSO_WAKE_UP_SRC                  0x1BU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t z_wu                     : 1;
+  uint8_t y_wu                     : 1;
+  uint8_t x_wu                     : 1;
+  uint8_t wu_ia                    : 1;
+  uint8_t sleep_state              : 1;
+  uint8_t ff_ia                    : 1;
+  uint8_t sleep_change_ia          : 1;
+  uint8_t not_used_01              : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t not_used_01              : 1;
+  uint8_t sleep_change_ia          : 1;
+  uint8_t ff_ia                    : 1;
+  uint8_t sleep_state              : 1;
+  uint8_t wu_ia                    : 1;
+  uint8_t x_wu                     : 1;
+  uint8_t y_wu                     : 1;
+  uint8_t z_wu                     : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_wake_up_src_t;
+
+#define LSM6DSO_TAP_SRC                      0x1CU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t z_tap                    : 1;
+  uint8_t y_tap                    : 1;
+  uint8_t x_tap                    : 1;
+  uint8_t tap_sign                 : 1;
+  uint8_t double_tap               : 1;
+  uint8_t single_tap               : 1;
+  uint8_t tap_ia                   : 1;
+  uint8_t not_used_02              : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t not_used_02              : 1;
+  uint8_t tap_ia                   : 1;
+  uint8_t single_tap               : 1;
+  uint8_t double_tap               : 1;
+  uint8_t tap_sign                 : 1;
+  uint8_t x_tap                    : 1;
+  uint8_t y_tap                    : 1;
+  uint8_t z_tap                    : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_tap_src_t;
+
+#define LSM6DSO_D6D_SRC                      0x1DU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t xl                       : 1;
+  uint8_t xh                       : 1;
+  uint8_t yl                       : 1;
+  uint8_t yh                       : 1;
+  uint8_t zl                       : 1;
+  uint8_t zh                       : 1;
+  uint8_t d6d_ia                   : 1;
+  uint8_t den_drdy                 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t den_drdy                 : 1;
+  uint8_t d6d_ia                   : 1;
+  uint8_t zh                       : 1;
+  uint8_t zl                       : 1;
+  uint8_t yh                       : 1;
+  uint8_t yl                       : 1;
+  uint8_t xh                       : 1;
+  uint8_t xl                       : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_d6d_src_t;
+
+#define LSM6DSO_STATUS_REG                   0x1EU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t xlda                     : 1;
+  uint8_t gda                      : 1;
+  uint8_t tda                      : 1;
+  uint8_t not_used_01              : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t not_used_01              : 5;
+  uint8_t tda                      : 1;
+  uint8_t gda                      : 1;
+  uint8_t xlda                     : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_status_reg_t;
+
+#define LSM6DSO_STATUS_SPIAUX                0x1EU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t xlda                     : 1;
+  uint8_t gda                      : 1;
+  uint8_t gyro_settling            : 1;
+  uint8_t not_used_01              : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t not_used_01              : 5;
+  uint8_t gyro_settling            : 1;
+  uint8_t gda                      : 1;
+  uint8_t xlda                     : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_status_spiaux_t;
+
+#define LSM6DSO_OUT_TEMP_L                   0x20U
+#define LSM6DSO_OUT_TEMP_H                   0x21U
+#define LSM6DSO_OUTX_L_G                     0x22U
+#define LSM6DSO_OUTX_H_G                     0x23U
+#define LSM6DSO_OUTY_L_G                     0x24U
+#define LSM6DSO_OUTY_H_G                     0x25U
+#define LSM6DSO_OUTZ_L_G                     0x26U
+#define LSM6DSO_OUTZ_H_G                     0x27U
+#define LSM6DSO_OUTX_L_A                     0x28U
+#define LSM6DSO_OUTX_H_A                     0x29U
+#define LSM6DSO_OUTY_L_A                     0x2AU
+#define LSM6DSO_OUTY_H_A                     0x2BU
+#define LSM6DSO_OUTZ_L_A                     0x2CU
+#define LSM6DSO_OUTZ_H_A                     0x2DU
+#define LSM6DSO_EMB_FUNC_STATUS_MAINPAGE     0x35U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t not_used_01             : 3;
+  uint8_t is_step_det             : 1;
+  uint8_t is_tilt                 : 1;
+  uint8_t is_sigmot               : 1;
+  uint8_t not_used_02             : 1;
+  uint8_t is_fsm_lc               : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t is_fsm_lc               : 1;
+  uint8_t not_used_02             : 1;
+  uint8_t is_sigmot               : 1;
+  uint8_t is_tilt                 : 1;
+  uint8_t is_step_det             : 1;
+  uint8_t not_used_01             : 3;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_emb_func_status_mainpage_t;
+
+#define LSM6DSO_FSM_STATUS_A_MAINPAGE        0x36U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t is_fsm1                 : 1;
+  uint8_t is_fsm2                 : 1;
+  uint8_t is_fsm3                 : 1;
+  uint8_t is_fsm4                 : 1;
+  uint8_t is_fsm5                 : 1;
+  uint8_t is_fsm6                 : 1;
+  uint8_t is_fsm7                 : 1;
+  uint8_t is_fsm8                 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t is_fsm8                 : 1;
+  uint8_t is_fsm7                 : 1;
+  uint8_t is_fsm6                 : 1;
+  uint8_t is_fsm5                 : 1;
+  uint8_t is_fsm4                 : 1;
+  uint8_t is_fsm3                 : 1;
+  uint8_t is_fsm2                 : 1;
+  uint8_t is_fsm1                 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_fsm_status_a_mainpage_t;
+
+#define LSM6DSO_FSM_STATUS_B_MAINPAGE        0x37U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t is_fsm9                 : 1;
+  uint8_t is_fsm10                : 1;
+  uint8_t is_fsm11                : 1;
+  uint8_t is_fsm12                : 1;
+  uint8_t is_fsm13                : 1;
+  uint8_t is_fsm14                : 1;
+  uint8_t is_fsm15                : 1;
+  uint8_t is_fsm16                : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t is_fsm16                : 1;
+  uint8_t is_fsm15                : 1;
+  uint8_t is_fsm14                : 1;
+  uint8_t is_fsm13                : 1;
+  uint8_t is_fsm12                : 1;
+  uint8_t is_fsm11                : 1;
+  uint8_t is_fsm10                : 1;
+  uint8_t is_fsm9                 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_fsm_status_b_mainpage_t;
+
+#define LSM6DSO_STATUS_MASTER_MAINPAGE       0x39U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t sens_hub_endop          : 1;
+  uint8_t not_used_01             : 2;
+  uint8_t slave0_nack             : 1;
+  uint8_t slave1_nack             : 1;
+  uint8_t slave2_nack             : 1;
+  uint8_t slave3_nack             : 1;
+  uint8_t wr_once_done            : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t wr_once_done            : 1;
+  uint8_t slave3_nack             : 1;
+  uint8_t slave2_nack             : 1;
+  uint8_t slave1_nack             : 1;
+  uint8_t slave0_nack             : 1;
+  uint8_t not_used_01             : 2;
+  uint8_t sens_hub_endop          : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_status_master_mainpage_t;
+
+#define LSM6DSO_FIFO_STATUS1                 0x3AU
+typedef struct
+{
+  uint8_t diff_fifo                : 8;
+} lsm6dso_fifo_status1_t;
+
+#define LSM6DSO_FIFO_STATUS2                 0x3B
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t diff_fifo                : 2;
+  uint8_t not_used_01              : 1;
+  uint8_t over_run_latched         : 1;
+  uint8_t counter_bdr_ia           : 1;
+  uint8_t fifo_full_ia             : 1;
+  uint8_t fifo_ovr_ia              : 1;
+  uint8_t fifo_wtm_ia              : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t fifo_wtm_ia              : 1;
+  uint8_t fifo_ovr_ia              : 1;
+  uint8_t fifo_full_ia             : 1;
+  uint8_t counter_bdr_ia           : 1;
+  uint8_t over_run_latched         : 1;
+  uint8_t not_used_01              : 1;
+  uint8_t diff_fifo                : 2;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_fifo_status2_t;
+
+#define LSM6DSO_TIMESTAMP0                   0x40U
+#define LSM6DSO_TIMESTAMP1                   0x41U
+#define LSM6DSO_TIMESTAMP2                   0x42U
+#define LSM6DSO_TIMESTAMP3                   0x43U
+#define LSM6DSO_TAP_CFG0                     0x56U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t lir                      : 1;
+  uint8_t tap_z_en                 : 1;
+  uint8_t tap_y_en                 : 1;
+  uint8_t tap_x_en                 : 1;
+  uint8_t slope_fds                : 1;
+  uint8_t sleep_status_on_int      : 1;
+  uint8_t int_clr_on_read          : 1;
+  uint8_t not_used_01              : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t not_used_01              : 1;
+  uint8_t int_clr_on_read          : 1;
+  uint8_t sleep_status_on_int      : 1;
+  uint8_t slope_fds                : 1;
+  uint8_t tap_x_en                 : 1;
+  uint8_t tap_y_en                 : 1;
+  uint8_t tap_z_en                 : 1;
+  uint8_t lir                      : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_tap_cfg0_t;
+
+#define LSM6DSO_TAP_CFG1                     0x57U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t tap_ths_x                : 5;
+  uint8_t tap_priority             : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t tap_priority             : 3;
+  uint8_t tap_ths_x                : 5;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_tap_cfg1_t;
+
+#define LSM6DSO_TAP_CFG2                     0x58U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t tap_ths_y                : 5;
+  uint8_t inact_en                 : 2;
+  uint8_t interrupts_enable        : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t interrupts_enable        : 1;
+  uint8_t inact_en                 : 2;
+  uint8_t tap_ths_y                : 5;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_tap_cfg2_t;
+
+#define LSM6DSO_TAP_THS_6D                   0x59U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t tap_ths_z                : 5;
+  uint8_t sixd_ths                 : 2;
+  uint8_t d4d_en                   : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t d4d_en                   : 1;
+  uint8_t sixd_ths                 : 2;
+  uint8_t tap_ths_z                : 5;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_tap_ths_6d_t;
+
+#define LSM6DSO_INT_DUR2                     0x5AU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t shock                    : 2;
+  uint8_t quiet                    : 2;
+  uint8_t dur                      : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t dur                      : 4;
+  uint8_t quiet                    : 2;
+  uint8_t shock                    : 2;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_int_dur2_t;
+
+#define LSM6DSO_WAKE_UP_THS                  0x5BU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t wk_ths                   : 6;
+  uint8_t usr_off_on_wu            : 1;
+  uint8_t single_double_tap        : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t single_double_tap        : 1;
+  uint8_t usr_off_on_wu            : 1;
+  uint8_t wk_ths                   : 6;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_wake_up_ths_t;
+
+#define LSM6DSO_WAKE_UP_DUR                  0x5CU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t sleep_dur                : 4;
+  uint8_t wake_ths_w               : 1;
+  uint8_t wake_dur                 : 2;
+  uint8_t ff_dur                   : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t ff_dur                   : 1;
+  uint8_t wake_dur                 : 2;
+  uint8_t wake_ths_w               : 1;
+  uint8_t sleep_dur                : 4;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_wake_up_dur_t;
+
+#define LSM6DSO_FREE_FALL                    0x5DU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t ff_ths                   : 3;
+  uint8_t ff_dur                   : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t ff_dur                   : 5;
+  uint8_t ff_ths                   : 3;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_free_fall_t;
+
+#define LSM6DSO_MD1_CFG                      0x5EU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t int1_shub                : 1;
+  uint8_t int1_emb_func            : 1;
+  uint8_t int1_6d                  : 1;
+  uint8_t int1_double_tap          : 1;
+  uint8_t int1_ff                  : 1;
+  uint8_t int1_wu                  : 1;
+  uint8_t int1_single_tap          : 1;
+  uint8_t int1_sleep_change        : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t int1_sleep_change        : 1;
+  uint8_t int1_single_tap          : 1;
+  uint8_t int1_wu                  : 1;
+  uint8_t int1_ff                  : 1;
+  uint8_t int1_double_tap          : 1;
+  uint8_t int1_6d                  : 1;
+  uint8_t int1_emb_func            : 1;
+  uint8_t int1_shub                : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_md1_cfg_t;
+
+#define LSM6DSO_MD2_CFG                      0x5FU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t int2_timestamp           : 1;
+  uint8_t int2_emb_func            : 1;
+  uint8_t int2_6d                  : 1;
+  uint8_t int2_double_tap          : 1;
+  uint8_t int2_ff                  : 1;
+  uint8_t int2_wu                  : 1;
+  uint8_t int2_single_tap          : 1;
+  uint8_t int2_sleep_change        : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t int2_sleep_change        : 1;
+  uint8_t int2_single_tap          : 1;
+  uint8_t int2_wu                  : 1;
+  uint8_t int2_ff                  : 1;
+  uint8_t int2_double_tap          : 1;
+  uint8_t int2_6d                  : 1;
+  uint8_t int2_emb_func            : 1;
+  uint8_t int2_timestamp           : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_md2_cfg_t;
+
+#define LSM6DSO_I3C_BUS_AVB                  0x62U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t pd_dis_int1              : 1;
+  uint8_t not_used_01              : 2;
+  uint8_t i3c_bus_avb_sel          : 2;
+  uint8_t not_used_02              : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t not_used_02              : 3;
+  uint8_t i3c_bus_avb_sel          : 2;
+  uint8_t not_used_01              : 2;
+  uint8_t pd_dis_int1              : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_i3c_bus_avb_t;
+
+#define LSM6DSO_INTERNAL_FREQ_FINE           0x63U
+typedef struct
+{
+  uint8_t freq_fine                : 8;
+} lsm6dso_internal_freq_fine_t;
+
+#define LSM6DSO_INT_OIS                      0x6FU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t st_xl_ois                : 2;
+  uint8_t not_used_01              : 3;
+  uint8_t den_lh_ois               : 1;
+  uint8_t lvl2_ois                 : 1;
+  uint8_t int2_drdy_ois            : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t int2_drdy_ois            : 1;
+  uint8_t lvl2_ois                 : 1;
+  uint8_t den_lh_ois               : 1;
+  uint8_t not_used_01              : 3;
+  uint8_t st_xl_ois                : 2;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_int_ois_t;
+
+#define LSM6DSO_CTRL1_OIS                    0x70U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t ois_en_spi2              : 1;
+  uint8_t fs_g_ois                 : 3; /* fs_125_ois + fs[1:0]_g_ois */
+  uint8_t mode4_en                 : 1;
+  uint8_t sim_ois                  : 1;
+  uint8_t lvl1_ois                 : 1;
+  uint8_t not_used_01              : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t not_used_01              : 1;
+  uint8_t lvl1_ois                 : 1;
+  uint8_t sim_ois                  : 1;
+  uint8_t mode4_en                 : 1;
+  uint8_t fs_g_ois                 : 3; /* fs_125_ois + fs[1:0]_g_ois */
+  uint8_t ois_en_spi2              : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_ctrl1_ois_t;
+
+#define LSM6DSO_CTRL2_OIS                    0x71U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t hp_en_ois                : 1;
+  uint8_t ftype_ois                : 2;
+  uint8_t not_used_01              : 1;
+  uint8_t hpm_ois                  : 2;
+  uint8_t not_used_02              : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t not_used_02              : 2;
+  uint8_t hpm_ois                  : 2;
+  uint8_t not_used_01              : 1;
+  uint8_t ftype_ois                : 2;
+  uint8_t hp_en_ois                : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_ctrl2_ois_t;
+
+#define LSM6DSO_CTRL3_OIS                    0x72U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t st_ois_clampdis          : 1;
+  uint8_t st_ois                   : 2;
+  uint8_t filter_xl_conf_ois       : 3;
+  uint8_t fs_xl_ois                : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t fs_xl_ois                : 2;
+  uint8_t filter_xl_conf_ois       : 3;
+  uint8_t st_ois                   : 2;
+  uint8_t st_ois_clampdis          : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_ctrl3_ois_t;
+
+#define LSM6DSO_X_OFS_USR                    0x73U
+#define LSM6DSO_Y_OFS_USR                    0x74U
+#define LSM6DSO_Z_OFS_USR                    0x75U
+#define LSM6DSO_FIFO_DATA_OUT_TAG            0x78U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t tag_parity               : 1;
+  uint8_t tag_cnt                  : 2;
+  uint8_t tag_sensor               : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t tag_sensor               : 5;
+  uint8_t tag_cnt                  : 2;
+  uint8_t tag_parity               : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_fifo_data_out_tag_t;
+
+#define LSM6DSO_FIFO_DATA_OUT_X_L            0x79U
+#define LSM6DSO_FIFO_DATA_OUT_X_H            0x7AU
+#define LSM6DSO_FIFO_DATA_OUT_Y_L            0x7BU
+#define LSM6DSO_FIFO_DATA_OUT_Y_H            0x7CU
+#define LSM6DSO_FIFO_DATA_OUT_Z_L            0x7DU
+#define LSM6DSO_FIFO_DATA_OUT_Z_H            0x7EU
+#define LSM6DSO_PAGE_SEL                     0x02U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t not_used_01              : 4;
+  uint8_t page_sel                 : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t page_sel                 : 4;
+  uint8_t not_used_01              : 4;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_page_sel_t;
+
+#define LSM6DSO_EMB_FUNC_EN_A                0x04U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t not_used_01              : 3;
+  uint8_t pedo_en                  : 1;
+  uint8_t tilt_en                  : 1;
+  uint8_t sign_motion_en           : 1;
+  uint8_t not_used_02              : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t not_used_02              : 2;
+  uint8_t sign_motion_en           : 1;
+  uint8_t tilt_en                  : 1;
+  uint8_t pedo_en                  : 1;
+  uint8_t not_used_01              : 3;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_emb_func_en_a_t;
+
+#define LSM6DSO_EMB_FUNC_EN_B                0x05U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t fsm_en                   : 1;
+  uint8_t not_used_01              : 2;
+  uint8_t fifo_compr_en            : 1;
+  uint8_t pedo_adv_en              : 1;
+  uint8_t not_used_02              : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t not_used_02              : 3;
+  uint8_t pedo_adv_en              : 1;
+  uint8_t fifo_compr_en            : 1;
+  uint8_t not_used_01              : 2;
+  uint8_t fsm_en                   : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_emb_func_en_b_t;
+
+#define LSM6DSO_PAGE_ADDRESS                 0x08U
+typedef struct
+{
+  uint8_t page_addr                : 8;
+} lsm6dso_page_address_t;
+
+#define LSM6DSO_PAGE_VALUE                   0x09U
+typedef struct
+{
+  uint8_t page_value               : 8;
+} lsm6dso_page_value_t;
+
+#define LSM6DSO_EMB_FUNC_INT1                0x0AU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t not_used_01              : 3;
+  uint8_t int1_step_detector       : 1;
+  uint8_t int1_tilt                : 1;
+  uint8_t int1_sig_mot             : 1;
+  uint8_t not_used_02              : 1;
+  uint8_t int1_fsm_lc              : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t int1_fsm_lc              : 1;
+  uint8_t not_used_02              : 1;
+  uint8_t int1_sig_mot             : 1;
+  uint8_t int1_tilt                : 1;
+  uint8_t int1_step_detector       : 1;
+  uint8_t not_used_01              : 3;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_emb_func_int1_t;
+
+#define LSM6DSO_FSM_INT1_A                   0x0BU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t int1_fsm1                : 1;
+  uint8_t int1_fsm2                : 1;
+  uint8_t int1_fsm3                : 1;
+  uint8_t int1_fsm4                : 1;
+  uint8_t int1_fsm5                : 1;
+  uint8_t int1_fsm6                : 1;
+  uint8_t int1_fsm7                : 1;
+  uint8_t int1_fsm8                : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t int1_fsm8                : 1;
+  uint8_t int1_fsm7                : 1;
+  uint8_t int1_fsm6                : 1;
+  uint8_t int1_fsm5                : 1;
+  uint8_t int1_fsm4                : 1;
+  uint8_t int1_fsm3                : 1;
+  uint8_t int1_fsm2                : 1;
+  uint8_t int1_fsm1                : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_fsm_int1_a_t;
+
+#define LSM6DSO_FSM_INT1_B                   0x0CU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t int1_fsm9                : 1;
+  uint8_t int1_fsm10               : 1;
+  uint8_t int1_fsm11               : 1;
+  uint8_t int1_fsm12               : 1;
+  uint8_t int1_fsm13               : 1;
+  uint8_t int1_fsm14               : 1;
+  uint8_t int1_fsm15               : 1;
+  uint8_t int1_fsm16               : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t int1_fsm16               : 1;
+  uint8_t int1_fsm15               : 1;
+  uint8_t int1_fsm14               : 1;
+  uint8_t int1_fsm13               : 1;
+  uint8_t int1_fsm12               : 1;
+  uint8_t int1_fsm11               : 1;
+  uint8_t int1_fsm10               : 1;
+  uint8_t int1_fsm9                : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_fsm_int1_b_t;
+
+#define LSM6DSO_EMB_FUNC_INT2                0x0EU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t not_used_01              : 3;
+  uint8_t int2_step_detector       : 1;
+  uint8_t int2_tilt                : 1;
+  uint8_t int2_sig_mot             : 1;
+  uint8_t not_used_02              : 1;
+  uint8_t int2_fsm_lc              : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t int2_fsm_lc              : 1;
+  uint8_t not_used_02              : 1;
+  uint8_t int2_sig_mot             : 1;
+  uint8_t int2_tilt                : 1;
+  uint8_t int2_step_detector       : 1;
+  uint8_t not_used_01              : 3;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_emb_func_int2_t;
+
+#define LSM6DSO_FSM_INT2_A                   0x0FU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t int2_fsm1                : 1;
+  uint8_t int2_fsm2                : 1;
+  uint8_t int2_fsm3                : 1;
+  uint8_t int2_fsm4                : 1;
+  uint8_t int2_fsm5                : 1;
+  uint8_t int2_fsm6                : 1;
+  uint8_t int2_fsm7                : 1;
+  uint8_t int2_fsm8                : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t int2_fsm8                : 1;
+  uint8_t int2_fsm7                : 1;
+  uint8_t int2_fsm6                : 1;
+  uint8_t int2_fsm5                : 1;
+  uint8_t int2_fsm4                : 1;
+  uint8_t int2_fsm3                : 1;
+  uint8_t int2_fsm2                : 1;
+  uint8_t int2_fsm1                : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_fsm_int2_a_t;
+
+#define LSM6DSO_FSM_INT2_B                   0x10U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t int2_fsm9                : 1;
+  uint8_t int2_fsm10               : 1;
+  uint8_t int2_fsm11               : 1;
+  uint8_t int2_fsm12               : 1;
+  uint8_t int2_fsm13               : 1;
+  uint8_t int2_fsm14               : 1;
+  uint8_t int2_fsm15               : 1;
+  uint8_t int2_fsm16               : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t int2_fsm16               : 1;
+  uint8_t int2_fsm15               : 1;
+  uint8_t int2_fsm14               : 1;
+  uint8_t int2_fsm13               : 1;
+  uint8_t int2_fsm12               : 1;
+  uint8_t int2_fsm11               : 1;
+  uint8_t int2_fsm10               : 1;
+  uint8_t int2_fsm9                : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_fsm_int2_b_t;
+
+#define LSM6DSO_EMB_FUNC_STATUS              0x12U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t not_used_01              : 3;
+  uint8_t is_step_det              : 1;
+  uint8_t is_tilt                  : 1;
+  uint8_t is_sigmot                : 1;
+  uint8_t not_used_02              : 1;
+  uint8_t is_fsm_lc                : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t is_fsm_lc                : 1;
+  uint8_t not_used_02              : 1;
+  uint8_t is_sigmot                : 1;
+  uint8_t is_tilt                  : 1;
+  uint8_t is_step_det              : 1;
+  uint8_t not_used_01              : 3;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_emb_func_status_t;
+
+#define LSM6DSO_FSM_STATUS_A                 0x13U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t is_fsm1                  : 1;
+  uint8_t is_fsm2                  : 1;
+  uint8_t is_fsm3                  : 1;
+  uint8_t is_fsm4                  : 1;
+  uint8_t is_fsm5                  : 1;
+  uint8_t is_fsm6                  : 1;
+  uint8_t is_fsm7                  : 1;
+  uint8_t is_fsm8                  : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t is_fsm8                  : 1;
+  uint8_t is_fsm7                  : 1;
+  uint8_t is_fsm6                  : 1;
+  uint8_t is_fsm5                  : 1;
+  uint8_t is_fsm4                  : 1;
+  uint8_t is_fsm3                  : 1;
+  uint8_t is_fsm2                  : 1;
+  uint8_t is_fsm1                  : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_fsm_status_a_t;
+
+#define LSM6DSO_FSM_STATUS_B                 0x14U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t is_fsm9                  : 1;
+  uint8_t is_fsm10                 : 1;
+  uint8_t is_fsm11                 : 1;
+  uint8_t is_fsm12                 : 1;
+  uint8_t is_fsm13                 : 1;
+  uint8_t is_fsm14                 : 1;
+  uint8_t is_fsm15                 : 1;
+  uint8_t is_fsm16                 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t is_fsm16                 : 1;
+  uint8_t is_fsm15                 : 1;
+  uint8_t is_fsm14                 : 1;
+  uint8_t is_fsm13                 : 1;
+  uint8_t is_fsm12                 : 1;
+  uint8_t is_fsm11                 : 1;
+  uint8_t is_fsm10                 : 1;
+  uint8_t is_fsm9                  : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_fsm_status_b_t;
+
+#define LSM6DSO_PAGE_RW                      0x17U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t not_used_01              : 5;
+  uint8_t page_rw                  : 2;  /* page_write + page_read */
+  uint8_t emb_func_lir             : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t emb_func_lir             : 1;
+  uint8_t page_rw                  : 2;  /* page_write + page_read */
+  uint8_t not_used_01              : 5;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_page_rw_t;
+
+#define LSM6DSO_EMB_FUNC_FIFO_CFG             0x44U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t not_used_00              : 6;
+  uint8_t pedo_fifo_en             : 1;
+  uint8_t not_used_01              : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t not_used_01              : 1;
+  uint8_t pedo_fifo_en             : 1;
+  uint8_t not_used_00              : 6;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_emb_func_fifo_cfg_t;
+
+#define LSM6DSO_FSM_ENABLE_A                 0x46U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t fsm1_en                  : 1;
+  uint8_t fsm2_en                  : 1;
+  uint8_t fsm3_en                  : 1;
+  uint8_t fsm4_en                  : 1;
+  uint8_t fsm5_en                  : 1;
+  uint8_t fsm6_en                  : 1;
+  uint8_t fsm7_en                  : 1;
+  uint8_t fsm8_en                  : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t fsm8_en                  : 1;
+  uint8_t fsm7_en                  : 1;
+  uint8_t fsm6_en                  : 1;
+  uint8_t fsm5_en                  : 1;
+  uint8_t fsm4_en                  : 1;
+  uint8_t fsm3_en                  : 1;
+  uint8_t fsm2_en                  : 1;
+  uint8_t fsm1_en                  : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_fsm_enable_a_t;
+
+#define LSM6DSO_FSM_ENABLE_B                 0x47U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t fsm9_en                  : 1;
+  uint8_t fsm10_en                 : 1;
+  uint8_t fsm11_en                 : 1;
+  uint8_t fsm12_en                 : 1;
+  uint8_t fsm13_en                 : 1;
+  uint8_t fsm14_en                 : 1;
+  uint8_t fsm15_en                 : 1;
+  uint8_t fsm16_en                 : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t fsm16_en                  : 1;
+  uint8_t fsm15_en                 : 1;
+  uint8_t fsm14_en                 : 1;
+  uint8_t fsm13_en                 : 1;
+  uint8_t fsm12_en                 : 1;
+  uint8_t fsm11_en                 : 1;
+  uint8_t fsm10_en                 : 1;
+  uint8_t fsm9_en                  : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_fsm_enable_b_t;
+
+#define LSM6DSO_FSM_LONG_COUNTER_L           0x48U
+#define LSM6DSO_FSM_LONG_COUNTER_H           0x49U
+#define LSM6DSO_FSM_LONG_COUNTER_CLEAR       0x4AU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+uint8_t fsm_lc_clr               :
+  2;  /* fsm_lc_cleared + fsm_lc_clear */
+  uint8_t not_used_01              : 6;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t not_used_01              : 6;
+uint8_t fsm_lc_clr               :
+  2;  /* fsm_lc_cleared + fsm_lc_clear */
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_fsm_long_counter_clear_t;
+
+#define LSM6DSO_FSM_OUTS1                    0x4CU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t n_v                      : 1;
+  uint8_t p_v                      : 1;
+  uint8_t n_z                      : 1;
+  uint8_t p_z                      : 1;
+  uint8_t n_y                      : 1;
+  uint8_t p_y                      : 1;
+  uint8_t n_x                      : 1;
+  uint8_t p_x                      : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t p_x                      : 1;
+  uint8_t n_x                      : 1;
+  uint8_t p_y                      : 1;
+  uint8_t n_y                      : 1;
+  uint8_t p_z                      : 1;
+  uint8_t n_z                      : 1;
+  uint8_t p_v                      : 1;
+  uint8_t n_v                      : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_fsm_outs1_t;
+
+#define LSM6DSO_FSM_OUTS2                    0x4DU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t n_v                      : 1;
+  uint8_t p_v                      : 1;
+  uint8_t n_z                      : 1;
+  uint8_t p_z                      : 1;
+  uint8_t n_y                      : 1;
+  uint8_t p_y                      : 1;
+  uint8_t n_x                      : 1;
+  uint8_t p_x                      : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t p_x                      : 1;
+  uint8_t n_x                      : 1;
+  uint8_t p_y                      : 1;
+  uint8_t n_y                      : 1;
+  uint8_t p_z                      : 1;
+  uint8_t n_z                      : 1;
+  uint8_t p_v                      : 1;
+  uint8_t n_v                      : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_fsm_outs2_t;
+
+#define LSM6DSO_FSM_OUTS3                    0x4EU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t n_v                      : 1;
+  uint8_t p_v                      : 1;
+  uint8_t n_z                      : 1;
+  uint8_t p_z                      : 1;
+  uint8_t n_y                      : 1;
+  uint8_t p_y                      : 1;
+  uint8_t n_x                      : 1;
+  uint8_t p_x                      : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t p_x                      : 1;
+  uint8_t n_x                      : 1;
+  uint8_t p_y                      : 1;
+  uint8_t n_y                      : 1;
+  uint8_t p_z                      : 1;
+  uint8_t n_z                      : 1;
+  uint8_t p_v                      : 1;
+  uint8_t n_v                      : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_fsm_outs3_t;
+
+#define LSM6DSO_FSM_OUTS4                    0x4FU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t n_v                      : 1;
+  uint8_t p_v                      : 1;
+  uint8_t n_z                      : 1;
+  uint8_t p_z                      : 1;
+  uint8_t n_y                      : 1;
+  uint8_t p_y                      : 1;
+  uint8_t n_x                      : 1;
+  uint8_t p_x                      : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t p_x                      : 1;
+  uint8_t n_x                      : 1;
+  uint8_t p_y                      : 1;
+  uint8_t n_y                      : 1;
+  uint8_t p_z                      : 1;
+  uint8_t n_z                      : 1;
+  uint8_t p_v                      : 1;
+  uint8_t n_v                      : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_fsm_outs4_t;
+
+#define LSM6DSO_FSM_OUTS5                    0x50U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t n_v                      : 1;
+  uint8_t p_v                      : 1;
+  uint8_t n_z                      : 1;
+  uint8_t p_z                      : 1;
+  uint8_t n_y                      : 1;
+  uint8_t p_y                      : 1;
+  uint8_t n_x                      : 1;
+  uint8_t p_x                      : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t p_x                      : 1;
+  uint8_t n_x                      : 1;
+  uint8_t p_y                      : 1;
+  uint8_t n_y                      : 1;
+  uint8_t p_z                      : 1;
+  uint8_t n_z                      : 1;
+  uint8_t p_v                      : 1;
+  uint8_t n_v                      : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_fsm_outs5_t;
+
+#define LSM6DSO_FSM_OUTS6                    0x51U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t n_v                      : 1;
+  uint8_t p_v                      : 1;
+  uint8_t n_z                      : 1;
+  uint8_t p_z                      : 1;
+  uint8_t n_y                      : 1;
+  uint8_t p_y                      : 1;
+  uint8_t n_x                      : 1;
+  uint8_t p_x                      : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t p_x                      : 1;
+  uint8_t n_x                      : 1;
+  uint8_t p_y                      : 1;
+  uint8_t n_y                      : 1;
+  uint8_t p_z                      : 1;
+  uint8_t n_z                      : 1;
+  uint8_t p_v                      : 1;
+  uint8_t n_v                      : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_fsm_outs6_t;
+
+#define LSM6DSO_FSM_OUTS7                    0x52U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t n_v                      : 1;
+  uint8_t p_v                      : 1;
+  uint8_t n_z                      : 1;
+  uint8_t p_z                      : 1;
+  uint8_t n_y                      : 1;
+  uint8_t p_y                      : 1;
+  uint8_t n_x                      : 1;
+  uint8_t p_x                      : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t p_x                      : 1;
+  uint8_t n_x                      : 1;
+  uint8_t p_y                      : 1;
+  uint8_t n_y                      : 1;
+  uint8_t p_z                      : 1;
+  uint8_t n_z                      : 1;
+  uint8_t p_v                      : 1;
+  uint8_t n_v                      : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_fsm_outs7_t;
+
+#define LSM6DSO_FSM_OUTS8                    0x53U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t n_v                      : 1;
+  uint8_t p_v                      : 1;
+  uint8_t n_z                      : 1;
+  uint8_t p_z                      : 1;
+  uint8_t n_y                      : 1;
+  uint8_t p_y                      : 1;
+  uint8_t n_x                      : 1;
+  uint8_t p_x                      : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t p_x                      : 1;
+  uint8_t n_x                      : 1;
+  uint8_t p_y                      : 1;
+  uint8_t n_y                      : 1;
+  uint8_t p_z                      : 1;
+  uint8_t n_z                      : 1;
+  uint8_t p_v                      : 1;
+  uint8_t n_v                      : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_fsm_outs8_t;
+
+#define LSM6DSO_FSM_OUTS9                    0x54U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t n_v                      : 1;
+  uint8_t p_v                      : 1;
+  uint8_t n_z                      : 1;
+  uint8_t p_z                      : 1;
+  uint8_t n_y                      : 1;
+  uint8_t p_y                      : 1;
+  uint8_t n_x                      : 1;
+  uint8_t p_x                      : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t p_x                      : 1;
+  uint8_t n_x                      : 1;
+  uint8_t p_y                      : 1;
+  uint8_t n_y                      : 1;
+  uint8_t p_z                      : 1;
+  uint8_t n_z                      : 1;
+  uint8_t p_v                      : 1;
+  uint8_t n_v                      : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_fsm_outs9_t;
+
+#define LSM6DSO_FSM_OUTS10                   0x55U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t n_v                      : 1;
+  uint8_t p_v                      : 1;
+  uint8_t n_z                      : 1;
+  uint8_t p_z                      : 1;
+  uint8_t n_y                      : 1;
+  uint8_t p_y                      : 1;
+  uint8_t n_x                      : 1;
+  uint8_t p_x                      : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t p_x                      : 1;
+  uint8_t n_x                      : 1;
+  uint8_t p_y                      : 1;
+  uint8_t n_y                      : 1;
+  uint8_t p_z                      : 1;
+  uint8_t n_z                      : 1;
+  uint8_t p_v                      : 1;
+  uint8_t n_v                      : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_fsm_outs10_t;
+
+#define LSM6DSO_FSM_OUTS11                   0x56U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t n_v                      : 1;
+  uint8_t p_v                      : 1;
+  uint8_t n_z                      : 1;
+  uint8_t p_z                      : 1;
+  uint8_t n_y                      : 1;
+  uint8_t p_y                      : 1;
+  uint8_t n_x                      : 1;
+  uint8_t p_x                      : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t p_x                      : 1;
+  uint8_t n_x                      : 1;
+  uint8_t p_y                      : 1;
+  uint8_t n_y                      : 1;
+  uint8_t p_z                      : 1;
+  uint8_t n_z                      : 1;
+  uint8_t p_v                      : 1;
+  uint8_t n_v                      : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_fsm_outs11_t;
+
+#define LSM6DSO_FSM_OUTS12                   0x57U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t n_v                      : 1;
+  uint8_t p_v                      : 1;
+  uint8_t n_z                      : 1;
+  uint8_t p_z                      : 1;
+  uint8_t n_y                      : 1;
+  uint8_t p_y                      : 1;
+  uint8_t n_x                      : 1;
+  uint8_t p_x                      : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t p_x                      : 1;
+  uint8_t n_x                      : 1;
+  uint8_t p_y                      : 1;
+  uint8_t n_y                      : 1;
+  uint8_t p_z                      : 1;
+  uint8_t n_z                      : 1;
+  uint8_t p_v                      : 1;
+  uint8_t n_v                      : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_fsm_outs12_t;
+
+#define LSM6DSO_FSM_OUTS13                   0x58U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t n_v                      : 1;
+  uint8_t p_v                      : 1;
+  uint8_t n_z                      : 1;
+  uint8_t p_z                      : 1;
+  uint8_t n_y                      : 1;
+  uint8_t p_y                      : 1;
+  uint8_t n_x                      : 1;
+  uint8_t p_x                      : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t p_x                      : 1;
+  uint8_t n_x                      : 1;
+  uint8_t p_y                      : 1;
+  uint8_t n_y                      : 1;
+  uint8_t p_z                      : 1;
+  uint8_t n_z                      : 1;
+  uint8_t p_v                      : 1;
+  uint8_t n_v                      : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_fsm_outs13_t;
+
+#define LSM6DSO_FSM_OUTS14                   0x59U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t n_v                      : 1;
+  uint8_t p_v                      : 1;
+  uint8_t n_z                      : 1;
+  uint8_t p_z                      : 1;
+  uint8_t n_y                      : 1;
+  uint8_t p_y                      : 1;
+  uint8_t n_x                      : 1;
+  uint8_t p_x                      : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t p_x                      : 1;
+  uint8_t n_x                      : 1;
+  uint8_t p_y                      : 1;
+  uint8_t n_y                      : 1;
+  uint8_t p_z                      : 1;
+  uint8_t n_z                      : 1;
+  uint8_t p_v                      : 1;
+  uint8_t n_v                      : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_fsm_outs14_t;
+
+#define LSM6DSO_FSM_OUTS15                   0x5AU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t n_v                      : 1;
+  uint8_t p_v                      : 1;
+  uint8_t n_z                      : 1;
+  uint8_t p_z                      : 1;
+  uint8_t n_y                      : 1;
+  uint8_t p_y                      : 1;
+  uint8_t n_x                      : 1;
+  uint8_t p_x                      : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t p_x                      : 1;
+  uint8_t n_x                      : 1;
+  uint8_t p_y                      : 1;
+  uint8_t n_y                      : 1;
+  uint8_t p_z                      : 1;
+  uint8_t n_z                      : 1;
+  uint8_t p_v                      : 1;
+  uint8_t n_v                      : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_fsm_outs15_t;
+
+#define LSM6DSO_FSM_OUTS16                   0x5BU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t n_v                      : 1;
+  uint8_t p_v                      : 1;
+  uint8_t n_z                      : 1;
+  uint8_t p_z                      : 1;
+  uint8_t n_y                      : 1;
+  uint8_t p_y                      : 1;
+  uint8_t n_x                      : 1;
+  uint8_t p_x                      : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t p_x                      : 1;
+  uint8_t n_x                      : 1;
+  uint8_t p_y                      : 1;
+  uint8_t n_y                      : 1;
+  uint8_t p_z                      : 1;
+  uint8_t n_z                      : 1;
+  uint8_t p_v                      : 1;
+  uint8_t n_v                      : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_fsm_outs16_t;
+
+#define LSM6DSO_EMB_FUNC_ODR_CFG_B           0x5FU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t not_used_01              : 3;
+  uint8_t fsm_odr                  : 2;
+  uint8_t not_used_02              : 3;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t not_used_02              : 3;
+  uint8_t fsm_odr                  : 2;
+  uint8_t not_used_01              : 3;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_emb_func_odr_cfg_b_t;
+
+#define LSM6DSO_STEP_COUNTER_L               0x62U
+#define LSM6DSO_STEP_COUNTER_H               0x63U
+#define LSM6DSO_EMB_FUNC_SRC                 0x64U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t not_used_01              : 2;
+  uint8_t stepcounter_bit_set      : 1;
+  uint8_t step_overflow            : 1;
+  uint8_t step_count_delta_ia      : 1;
+  uint8_t step_detected            : 1;
+  uint8_t not_used_02              : 1;
+  uint8_t pedo_rst_step            : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t pedo_rst_step            : 1;
+  uint8_t not_used_02              : 1;
+  uint8_t step_detected            : 1;
+  uint8_t step_count_delta_ia      : 1;
+  uint8_t step_overflow            : 1;
+  uint8_t stepcounter_bit_set      : 1;
+  uint8_t not_used_01              : 2;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_emb_func_src_t;
+
+#define LSM6DSO_EMB_FUNC_INIT_A              0x66U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t not_used_01               : 3;
+  uint8_t step_det_init             : 1;
+  uint8_t tilt_init                 : 1;
+  uint8_t sig_mot_init              : 1;
+  uint8_t not_used_02               : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t not_used_02               : 2;
+  uint8_t sig_mot_init              : 1;
+  uint8_t tilt_init                 : 1;
+  uint8_t step_det_init             : 1;
+  uint8_t not_used_01               : 3;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_emb_func_init_a_t;
+
+#define LSM6DSO_EMB_FUNC_INIT_B              0x67U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t fsm_init                 : 1;
+  uint8_t not_used_01              : 2;
+  uint8_t fifo_compr_init          : 1;
+  uint8_t not_used_02              : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t not_used_02              : 4;
+  uint8_t fifo_compr_init          : 1;
+  uint8_t not_used_01              : 2;
+  uint8_t fsm_init                 : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_emb_func_init_b_t;
+
+#define LSM6DSO_MAG_SENSITIVITY_L            0xBAU
+#define LSM6DSO_MAG_SENSITIVITY_H            0xBBU
+#define LSM6DSO_MAG_OFFX_L                   0xC0U
+#define LSM6DSO_MAG_OFFX_H                   0xC1U
+#define LSM6DSO_MAG_OFFY_L                   0xC2U
+#define LSM6DSO_MAG_OFFY_H                   0xC3U
+#define LSM6DSO_MAG_OFFZ_L                   0xC4U
+#define LSM6DSO_MAG_OFFZ_H                   0xC5U
+#define LSM6DSO_MAG_SI_XX_L                  0xC6U
+#define LSM6DSO_MAG_SI_XX_H                  0xC7U
+#define LSM6DSO_MAG_SI_XY_L                  0xC8U
+#define LSM6DSO_MAG_SI_XY_H                  0xC9U
+#define LSM6DSO_MAG_SI_XZ_L                  0xCAU
+#define LSM6DSO_MAG_SI_XZ_H                  0xCBU
+#define LSM6DSO_MAG_SI_YY_L                  0xCCU
+#define LSM6DSO_MAG_SI_YY_H                  0xCDU
+#define LSM6DSO_MAG_SI_YZ_L                  0xCEU
+#define LSM6DSO_MAG_SI_YZ_H                  0xCFU
+#define LSM6DSO_MAG_SI_ZZ_L                  0xD0U
+#define LSM6DSO_MAG_SI_ZZ_H                  0xD1U
+#define LSM6DSO_MAG_CFG_A                    0xD4U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t mag_z_axis               : 3;
+  uint8_t not_used_01              : 1;
+  uint8_t mag_y_axis               : 3;
+  uint8_t not_used_02              : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t not_used_02              : 1;
+  uint8_t mag_y_axis               : 3;
+  uint8_t not_used_01              : 1;
+  uint8_t mag_z_axis               : 3;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_mag_cfg_a_t;
+
+#define LSM6DSO_MAG_CFG_B                    0xD5U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t mag_x_axis               : 3;
+  uint8_t not_used_01              : 5;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t not_used_01              : 5;
+  uint8_t mag_x_axis               : 3;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_mag_cfg_b_t;
+
+#define LSM6DSO_FSM_LC_TIMEOUT_L             0x17AU
+#define LSM6DSO_FSM_LC_TIMEOUT_H             0x17BU
+#define LSM6DSO_FSM_PROGRAMS                 0x17CU
+#define LSM6DSO_FSM_START_ADD_L              0x17EU
+#define LSM6DSO_FSM_START_ADD_H              0x17FU
+#define LSM6DSO_PEDO_CMD_REG                 0x183U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t ad_det_en                : 1;
+  uint8_t not_used_01              : 1;
+  uint8_t fp_rejection_en          : 1;
+  uint8_t carry_count_en           : 1;
+  uint8_t not_used_02              : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t not_used_02              : 4;
+  uint8_t carry_count_en           : 1;
+  uint8_t fp_rejection_en          : 1;
+  uint8_t not_used_01              : 1;
+  uint8_t ad_det_en                : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_pedo_cmd_reg_t;
+
+#define LSM6DSO_PEDO_DEB_STEPS_CONF          0x184U
+#define LSM6DSO_PEDO_SC_DELTAT_L             0x1D0U
+#define LSM6DSO_PEDO_SC_DELTAT_H             0x1D1U
+#define LSM6DSO_SENSOR_HUB_1                 0x02U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t bit0                    : 1;
+  uint8_t bit1                    : 1;
+  uint8_t bit2                    : 1;
+  uint8_t bit3                    : 1;
+  uint8_t bit4                    : 1;
+  uint8_t bit5                    : 1;
+  uint8_t bit6                    : 1;
+  uint8_t bit7                    : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t bit7                    : 1;
+  uint8_t bit6                    : 1;
+  uint8_t bit5                    : 1;
+  uint8_t bit4                    : 1;
+  uint8_t bit3                    : 1;
+  uint8_t bit2                    : 1;
+  uint8_t bit1                    : 1;
+  uint8_t bit0                    : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_sensor_hub_1_t;
+
+#define LSM6DSO_SENSOR_HUB_2                 0x03U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t bit0                    : 1;
+  uint8_t bit1                    : 1;
+  uint8_t bit2                    : 1;
+  uint8_t bit3                    : 1;
+  uint8_t bit4                    : 1;
+  uint8_t bit5                    : 1;
+  uint8_t bit6                    : 1;
+  uint8_t bit7                    : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t bit7                    : 1;
+  uint8_t bit6                    : 1;
+  uint8_t bit5                    : 1;
+  uint8_t bit4                    : 1;
+  uint8_t bit3                    : 1;
+  uint8_t bit2                    : 1;
+  uint8_t bit1                    : 1;
+  uint8_t bit0                    : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_sensor_hub_2_t;
+
+#define LSM6DSO_SENSOR_HUB_3                 0x04U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t bit0                    : 1;
+  uint8_t bit1                    : 1;
+  uint8_t bit2                    : 1;
+  uint8_t bit3                    : 1;
+  uint8_t bit4                    : 1;
+  uint8_t bit5                    : 1;
+  uint8_t bit6                    : 1;
+  uint8_t bit7                    : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t bit7                    : 1;
+  uint8_t bit6                    : 1;
+  uint8_t bit5                    : 1;
+  uint8_t bit4                    : 1;
+  uint8_t bit3                    : 1;
+  uint8_t bit2                    : 1;
+  uint8_t bit1                    : 1;
+  uint8_t bit0                    : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_sensor_hub_3_t;
+
+#define LSM6DSO_SENSOR_HUB_4                 0x05U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t bit0                    : 1;
+  uint8_t bit1                    : 1;
+  uint8_t bit2                    : 1;
+  uint8_t bit3                    : 1;
+  uint8_t bit4                    : 1;
+  uint8_t bit5                    : 1;
+  uint8_t bit6                    : 1;
+  uint8_t bit7                    : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t bit7                    : 1;
+  uint8_t bit6                    : 1;
+  uint8_t bit5                    : 1;
+  uint8_t bit4                    : 1;
+  uint8_t bit3                    : 1;
+  uint8_t bit2                    : 1;
+  uint8_t bit1                    : 1;
+  uint8_t bit0                    : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_sensor_hub_4_t;
+
+#define LSM6DSO_SENSOR_HUB_5                 0x06U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t bit0                    : 1;
+  uint8_t bit1                    : 1;
+  uint8_t bit2                    : 1;
+  uint8_t bit3                    : 1;
+  uint8_t bit4                    : 1;
+  uint8_t bit5                    : 1;
+  uint8_t bit6                    : 1;
+  uint8_t bit7                    : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t bit7                    : 1;
+  uint8_t bit6                    : 1;
+  uint8_t bit5                    : 1;
+  uint8_t bit4                    : 1;
+  uint8_t bit3                    : 1;
+  uint8_t bit2                    : 1;
+  uint8_t bit1                    : 1;
+  uint8_t bit0                    : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_sensor_hub_5_t;
+
+#define LSM6DSO_SENSOR_HUB_6                 0x07U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t bit0                    : 1;
+  uint8_t bit1                    : 1;
+  uint8_t bit2                    : 1;
+  uint8_t bit3                    : 1;
+  uint8_t bit4                    : 1;
+  uint8_t bit5                    : 1;
+  uint8_t bit6                    : 1;
+  uint8_t bit7                    : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t bit7                    : 1;
+  uint8_t bit6                    : 1;
+  uint8_t bit5                    : 1;
+  uint8_t bit4                    : 1;
+  uint8_t bit3                    : 1;
+  uint8_t bit2                    : 1;
+  uint8_t bit1                    : 1;
+  uint8_t bit0                    : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_sensor_hub_6_t;
+
+#define LSM6DSO_SENSOR_HUB_7                 0x08U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t bit0                    : 1;
+  uint8_t bit1                    : 1;
+  uint8_t bit2                    : 1;
+  uint8_t bit3                    : 1;
+  uint8_t bit4                    : 1;
+  uint8_t bit5                    : 1;
+  uint8_t bit6                    : 1;
+  uint8_t bit7                    : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t bit7                    : 1;
+  uint8_t bit6                    : 1;
+  uint8_t bit5                    : 1;
+  uint8_t bit4                    : 1;
+  uint8_t bit3                    : 1;
+  uint8_t bit2                    : 1;
+  uint8_t bit1                    : 1;
+  uint8_t bit0                    : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_sensor_hub_7_t;
+
+#define LSM6DSO_SENSOR_HUB_8                 0x09U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t bit0                    : 1;
+  uint8_t bit1                    : 1;
+  uint8_t bit2                    : 1;
+  uint8_t bit3                    : 1;
+  uint8_t bit4                    : 1;
+  uint8_t bit5                    : 1;
+  uint8_t bit6                    : 1;
+  uint8_t bit7                    : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t bit7                    : 1;
+  uint8_t bit6                    : 1;
+  uint8_t bit5                    : 1;
+  uint8_t bit4                    : 1;
+  uint8_t bit3                    : 1;
+  uint8_t bit2                    : 1;
+  uint8_t bit1                    : 1;
+  uint8_t bit0                    : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_sensor_hub_8_t;
+
+#define LSM6DSO_SENSOR_HUB_9                 0x0AU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t bit0                    : 1;
+  uint8_t bit1                    : 1;
+  uint8_t bit2                    : 1;
+  uint8_t bit3                    : 1;
+  uint8_t bit4                    : 1;
+  uint8_t bit5                    : 1;
+  uint8_t bit6                    : 1;
+  uint8_t bit7                    : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t bit7                    : 1;
+  uint8_t bit6                    : 1;
+  uint8_t bit5                    : 1;
+  uint8_t bit4                    : 1;
+  uint8_t bit3                    : 1;
+  uint8_t bit2                    : 1;
+  uint8_t bit1                    : 1;
+  uint8_t bit0                    : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_sensor_hub_9_t;
+
+#define LSM6DSO_SENSOR_HUB_10                0x0BU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t bit0                    : 1;
+  uint8_t bit1                    : 1;
+  uint8_t bit2                    : 1;
+  uint8_t bit3                    : 1;
+  uint8_t bit4                    : 1;
+  uint8_t bit5                    : 1;
+  uint8_t bit6                    : 1;
+  uint8_t bit7                    : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t bit7                    : 1;
+  uint8_t bit6                    : 1;
+  uint8_t bit5                    : 1;
+  uint8_t bit4                    : 1;
+  uint8_t bit3                    : 1;
+  uint8_t bit2                    : 1;
+  uint8_t bit1                    : 1;
+  uint8_t bit0                    : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_sensor_hub_10_t;
+
+#define LSM6DSO_SENSOR_HUB_11                0x0CU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t bit0                    : 1;
+  uint8_t bit1                    : 1;
+  uint8_t bit2                    : 1;
+  uint8_t bit3                    : 1;
+  uint8_t bit4                    : 1;
+  uint8_t bit5                    : 1;
+  uint8_t bit6                    : 1;
+  uint8_t bit7                    : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t bit7                    : 1;
+  uint8_t bit6                    : 1;
+  uint8_t bit5                    : 1;
+  uint8_t bit4                    : 1;
+  uint8_t bit3                    : 1;
+  uint8_t bit2                    : 1;
+  uint8_t bit1                    : 1;
+  uint8_t bit0                    : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_sensor_hub_11_t;
+
+#define LSM6DSO_SENSOR_HUB_12                0x0DU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t bit0                    : 1;
+  uint8_t bit1                    : 1;
+  uint8_t bit2                    : 1;
+  uint8_t bit3                    : 1;
+  uint8_t bit4                    : 1;
+  uint8_t bit5                    : 1;
+  uint8_t bit6                    : 1;
+  uint8_t bit7                    : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t bit7                    : 1;
+  uint8_t bit6                    : 1;
+  uint8_t bit5                    : 1;
+  uint8_t bit4                    : 1;
+  uint8_t bit3                    : 1;
+  uint8_t bit2                    : 1;
+  uint8_t bit1                    : 1;
+  uint8_t bit0                    : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_sensor_hub_12_t;
+
+#define LSM6DSO_SENSOR_HUB_13                0x0EU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t bit0                    : 1;
+  uint8_t bit1                    : 1;
+  uint8_t bit2                    : 1;
+  uint8_t bit3                    : 1;
+  uint8_t bit4                    : 1;
+  uint8_t bit5                    : 1;
+  uint8_t bit6                    : 1;
+  uint8_t bit7                    : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t bit7                    : 1;
+  uint8_t bit6                    : 1;
+  uint8_t bit5                    : 1;
+  uint8_t bit4                    : 1;
+  uint8_t bit3                    : 1;
+  uint8_t bit2                    : 1;
+  uint8_t bit1                    : 1;
+  uint8_t bit0                    : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_sensor_hub_13_t;
+
+#define LSM6DSO_SENSOR_HUB_14                0x0FU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t bit0                    : 1;
+  uint8_t bit1                    : 1;
+  uint8_t bit2                    : 1;
+  uint8_t bit3                    : 1;
+  uint8_t bit4                    : 1;
+  uint8_t bit5                    : 1;
+  uint8_t bit6                    : 1;
+  uint8_t bit7                    : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t bit7                    : 1;
+  uint8_t bit6                    : 1;
+  uint8_t bit5                    : 1;
+  uint8_t bit4                    : 1;
+  uint8_t bit3                    : 1;
+  uint8_t bit2                    : 1;
+  uint8_t bit1                    : 1;
+  uint8_t bit0                    : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_sensor_hub_14_t;
+
+#define LSM6DSO_SENSOR_HUB_15                0x10U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t bit0                    : 1;
+  uint8_t bit1                    : 1;
+  uint8_t bit2                    : 1;
+  uint8_t bit3                    : 1;
+  uint8_t bit4                    : 1;
+  uint8_t bit5                    : 1;
+  uint8_t bit6                    : 1;
+  uint8_t bit7                    : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t bit7                    : 1;
+  uint8_t bit6                    : 1;
+  uint8_t bit5                    : 1;
+  uint8_t bit4                    : 1;
+  uint8_t bit3                    : 1;
+  uint8_t bit2                    : 1;
+  uint8_t bit1                    : 1;
+  uint8_t bit0                    : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_sensor_hub_15_t;
+
+#define LSM6DSO_SENSOR_HUB_16                0x11U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t bit0                    : 1;
+  uint8_t bit1                    : 1;
+  uint8_t bit2                    : 1;
+  uint8_t bit3                    : 1;
+  uint8_t bit4                    : 1;
+  uint8_t bit5                    : 1;
+  uint8_t bit6                    : 1;
+  uint8_t bit7                    : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t bit7                    : 1;
+  uint8_t bit6                    : 1;
+  uint8_t bit5                    : 1;
+  uint8_t bit4                    : 1;
+  uint8_t bit3                    : 1;
+  uint8_t bit2                    : 1;
+  uint8_t bit1                    : 1;
+  uint8_t bit0                    : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_sensor_hub_16_t;
+
+#define LSM6DSO_SENSOR_HUB_17                0x12U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t bit0                    : 1;
+  uint8_t bit1                    : 1;
+  uint8_t bit2                    : 1;
+  uint8_t bit3                    : 1;
+  uint8_t bit4                    : 1;
+  uint8_t bit5                    : 1;
+  uint8_t bit6                    : 1;
+  uint8_t bit7                    : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t bit7                    : 1;
+  uint8_t bit6                    : 1;
+  uint8_t bit5                    : 1;
+  uint8_t bit4                    : 1;
+  uint8_t bit3                    : 1;
+  uint8_t bit2                    : 1;
+  uint8_t bit1                    : 1;
+  uint8_t bit0                    : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_sensor_hub_17_t;
+
+#define LSM6DSO_SENSOR_HUB_18                0x13U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t bit0                    : 1;
+  uint8_t bit1                    : 1;
+  uint8_t bit2                    : 1;
+  uint8_t bit3                    : 1;
+  uint8_t bit4                    : 1;
+  uint8_t bit5                    : 1;
+  uint8_t bit6                    : 1;
+  uint8_t bit7                    : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t bit7                    : 1;
+  uint8_t bit6                    : 1;
+  uint8_t bit5                    : 1;
+  uint8_t bit4                    : 1;
+  uint8_t bit3                    : 1;
+  uint8_t bit2                    : 1;
+  uint8_t bit1                    : 1;
+  uint8_t bit0                    : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_sensor_hub_18_t;
+
+#define LSM6DSO_MASTER_CONFIG                0x14U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t aux_sens_on              : 2;
+  uint8_t master_on                : 1;
+  uint8_t shub_pu_en               : 1;
+  uint8_t pass_through_mode        : 1;
+  uint8_t start_config             : 1;
+  uint8_t write_once               : 1;
+  uint8_t rst_master_regs          : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t rst_master_regs          : 1;
+  uint8_t write_once               : 1;
+  uint8_t start_config             : 1;
+  uint8_t pass_through_mode        : 1;
+  uint8_t shub_pu_en               : 1;
+  uint8_t master_on                : 1;
+  uint8_t aux_sens_on              : 2;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_master_config_t;
+
+#define LSM6DSO_SLV0_ADD                     0x15U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t rw_0                     : 1;
+  uint8_t slave0                   : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t slave0                   : 7;
+  uint8_t rw_0                     : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_slv0_add_t;
+
+#define LSM6DSO_SLV0_SUBADD                  0x16U
+typedef struct
+{
+  uint8_t slave0_reg               : 8;
+} lsm6dso_slv0_subadd_t;
+
+#define LSM6DSO_SLV0_CONFIG                  0x17U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t slave0_numop             : 3;
+  uint8_t batch_ext_sens_0_en      : 1;
+  uint8_t not_used_01              : 2;
+  uint8_t shub_odr                 : 2;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t shub_odr                 : 2;
+  uint8_t not_used_01              : 2;
+  uint8_t batch_ext_sens_0_en      : 1;
+  uint8_t slave0_numop             : 3;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_slv0_config_t;
+
+#define LSM6DSO_SLV1_ADD                     0x18U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t r_1                      : 1;
+  uint8_t slave1_add               : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t slave1_add               : 7;
+  uint8_t r_1                      : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_slv1_add_t;
+
+#define LSM6DSO_SLV1_SUBADD                  0x19U
+typedef struct
+{
+  uint8_t slave1_reg               : 8;
+} lsm6dso_slv1_subadd_t;
+
+#define LSM6DSO_SLV1_CONFIG                  0x1AU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t slave1_numop             : 3;
+  uint8_t batch_ext_sens_1_en      : 1;
+  uint8_t not_used_01              : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t not_used_01              : 4;
+  uint8_t batch_ext_sens_1_en      : 1;
+  uint8_t slave1_numop             : 3;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_slv1_config_t;
+
+#define LSM6DSO_SLV2_ADD                     0x1BU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t r_2                      : 1;
+  uint8_t slave2_add               : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t slave2_add               : 7;
+  uint8_t r_2                      : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_slv2_add_t;
+
+#define LSM6DSO_SLV2_SUBADD                  0x1CU
+typedef struct
+{
+  uint8_t slave2_reg               : 8;
+} lsm6dso_slv2_subadd_t;
+
+#define LSM6DSO_SLV2_CONFIG                  0x1DU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t slave2_numop             : 3;
+  uint8_t batch_ext_sens_2_en      : 1;
+  uint8_t not_used_01              : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t not_used_01              : 4;
+  uint8_t batch_ext_sens_2_en      : 1;
+  uint8_t slave2_numop             : 3;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_slv2_config_t;
+
+#define LSM6DSO_SLV3_ADD                     0x1EU
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t r_3                      : 1;
+  uint8_t slave3_add               : 7;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t slave3_add               : 7;
+  uint8_t r_3                      : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_slv3_add_t;
+
+#define LSM6DSO_SLV3_SUBADD                  0x1FU
+typedef struct
+{
+  uint8_t slave3_reg               : 8;
+} lsm6dso_slv3_subadd_t;
+
+#define LSM6DSO_SLV3_CONFIG                  0x20U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t slave3_numop             : 3;
+  uint8_t  batch_ext_sens_3_en     : 1;
+  uint8_t not_used_01              : 4;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t not_used_01              : 4;
+  uint8_t  batch_ext_sens_3_en     : 1;
+  uint8_t slave3_numop             : 3;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_slv3_config_t;
+
+#define LSM6DSO_DATAWRITE_SLV0               0x21U
+typedef struct
+{
+  uint8_t slave0_dataw             : 8;
+} lsm6dso_datawrite_src_mode_sub_slv0_t;
+
+#define LSM6DSO_STATUS_MASTER                0x22U
+typedef struct
+{
+#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
+  uint8_t sens_hub_endop           : 1;
+  uint8_t not_used_01              : 2;
+  uint8_t slave0_nack              : 1;
+  uint8_t slave1_nack              : 1;
+  uint8_t slave2_nack              : 1;
+  uint8_t slave3_nack              : 1;
+  uint8_t wr_once_done             : 1;
+#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
+  uint8_t wr_once_done             : 1;
+  uint8_t slave3_nack              : 1;
+  uint8_t slave2_nack              : 1;
+  uint8_t slave1_nack              : 1;
+  uint8_t slave0_nack              : 1;
+  uint8_t not_used_01              : 2;
+  uint8_t sens_hub_endop           : 1;
+#endif /* DRV_BYTE_ORDER */
+} lsm6dso_status_master_t;
+
+#define LSM6DSO_START_FSM_ADD                0x0400U
+
+/**
+  * @defgroup LSM6DSO_Register_Union
+  * @brief    This union group all the registers having a bit-field
+  *           description.
+  *           This union is useful but it's not needed by the driver.
+  *
+  *           REMOVING this union you are compliant with:
+  *           MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
+  *
+  * @{
+  *
+  */
+typedef union
+{
+  lsm6dso_func_cfg_access_t               func_cfg_access;
+  lsm6dso_pin_ctrl_t                      pin_ctrl;
+  lsm6dso_fifo_ctrl1_t                    fifo_ctrl1;
+  lsm6dso_fifo_ctrl2_t                    fifo_ctrl2;
+  lsm6dso_fifo_ctrl3_t                    fifo_ctrl3;
+  lsm6dso_fifo_ctrl4_t                    fifo_ctrl4;
+  lsm6dso_counter_bdr_reg1_t              counter_bdr_reg1;
+  lsm6dso_counter_bdr_reg2_t              counter_bdr_reg2;
+  lsm6dso_int1_ctrl_t                     int1_ctrl;
+  lsm6dso_int2_ctrl_t                     int2_ctrl;
+  lsm6dso_ctrl1_xl_t                      ctrl1_xl;
+  lsm6dso_ctrl2_g_t                       ctrl2_g;
+  lsm6dso_ctrl3_c_t                       ctrl3_c;
+  lsm6dso_ctrl4_c_t                       ctrl4_c;
+  lsm6dso_ctrl5_c_t                       ctrl5_c;
+  lsm6dso_ctrl6_c_t                       ctrl6_c;
+  lsm6dso_ctrl7_g_t                       ctrl7_g;
+  lsm6dso_ctrl8_xl_t                      ctrl8_xl;
+  lsm6dso_ctrl9_xl_t                      ctrl9_xl;
+  lsm6dso_ctrl10_c_t                      ctrl10_c;
+  lsm6dso_all_int_src_t                   all_int_src;
+  lsm6dso_wake_up_src_t                   wake_up_src;
+  lsm6dso_tap_src_t                       tap_src;
+  lsm6dso_d6d_src_t                       d6d_src;
+  lsm6dso_status_reg_t                    status_reg;
+  lsm6dso_status_spiaux_t                 status_spiaux;
+  lsm6dso_fifo_status1_t                  fifo_status1;
+  lsm6dso_fifo_status2_t                  fifo_status2;
+  lsm6dso_tap_cfg0_t                      tap_cfg0;
+  lsm6dso_tap_cfg1_t                      tap_cfg1;
+  lsm6dso_tap_cfg2_t                      tap_cfg2;
+  lsm6dso_tap_ths_6d_t                    tap_ths_6d;
+  lsm6dso_int_dur2_t                      int_dur2;
+  lsm6dso_wake_up_ths_t                   wake_up_ths;
+  lsm6dso_wake_up_dur_t                   wake_up_dur;
+  lsm6dso_free_fall_t                     free_fall;
+  lsm6dso_md1_cfg_t                       md1_cfg;
+  lsm6dso_md2_cfg_t                       md2_cfg;
+  lsm6dso_i3c_bus_avb_t                   i3c_bus_avb;
+  lsm6dso_internal_freq_fine_t            internal_freq_fine;
+  lsm6dso_int_ois_t                       int_ois;
+  lsm6dso_ctrl1_ois_t                     ctrl1_ois;
+  lsm6dso_ctrl2_ois_t                     ctrl2_ois;
+  lsm6dso_ctrl3_ois_t                     ctrl3_ois;
+  lsm6dso_fifo_data_out_tag_t             fifo_data_out_tag;
+  lsm6dso_page_sel_t                      page_sel;
+  lsm6dso_emb_func_en_a_t                 emb_func_en_a;
+  lsm6dso_emb_func_en_b_t                 emb_func_en_b;
+  lsm6dso_page_address_t                  page_address;
+  lsm6dso_page_value_t                    page_value;
+  lsm6dso_emb_func_int1_t                 emb_func_int1;
+  lsm6dso_fsm_int1_a_t                    fsm_int1_a;
+  lsm6dso_fsm_int1_b_t                    fsm_int1_b;
+  lsm6dso_emb_func_int2_t                 emb_func_int2;
+  lsm6dso_fsm_int2_a_t                    fsm_int2_a;
+  lsm6dso_fsm_int2_b_t                    fsm_int2_b;
+  lsm6dso_emb_func_status_t               emb_func_status;
+  lsm6dso_fsm_status_a_t                  fsm_status_a;
+  lsm6dso_fsm_status_b_t                  fsm_status_b;
+  lsm6dso_page_rw_t                       page_rw;
+  lsm6dso_emb_func_fifo_cfg_t              emb_func_fifo_cfg;
+  lsm6dso_fsm_enable_a_t                  fsm_enable_a;
+  lsm6dso_fsm_enable_b_t                  fsm_enable_b;
+  lsm6dso_fsm_long_counter_clear_t        fsm_long_counter_clear;
+  lsm6dso_fsm_outs1_t                     fsm_outs1;
+  lsm6dso_fsm_outs2_t                     fsm_outs2;
+  lsm6dso_fsm_outs3_t                     fsm_outs3;
+  lsm6dso_fsm_outs4_t                     fsm_outs4;
+  lsm6dso_fsm_outs5_t                     fsm_outs5;
+  lsm6dso_fsm_outs6_t                     fsm_outs6;
+  lsm6dso_fsm_outs7_t                     fsm_outs7;
+  lsm6dso_fsm_outs8_t                     fsm_outs8;
+  lsm6dso_fsm_outs9_t                     fsm_outs9;
+  lsm6dso_fsm_outs10_t                    fsm_outs10;
+  lsm6dso_fsm_outs11_t                    fsm_outs11;
+  lsm6dso_fsm_outs12_t                    fsm_outs12;
+  lsm6dso_fsm_outs13_t                    fsm_outs13;
+  lsm6dso_fsm_outs14_t                    fsm_outs14;
+  lsm6dso_fsm_outs15_t                    fsm_outs15;
+  lsm6dso_fsm_outs16_t                    fsm_outs16;
+  lsm6dso_emb_func_odr_cfg_b_t            emb_func_odr_cfg_b;
+  lsm6dso_emb_func_src_t                  emb_func_src;
+  lsm6dso_emb_func_init_a_t               emb_func_init_a;
+  lsm6dso_emb_func_init_b_t               emb_func_init_b;
+  lsm6dso_mag_cfg_a_t                     mag_cfg_a;
+  lsm6dso_mag_cfg_b_t                     mag_cfg_b;
+  lsm6dso_pedo_cmd_reg_t                  pedo_cmd_reg;
+  lsm6dso_sensor_hub_1_t                  sensor_hub_1;
+  lsm6dso_sensor_hub_2_t                  sensor_hub_2;
+  lsm6dso_sensor_hub_3_t                  sensor_hub_3;
+  lsm6dso_sensor_hub_4_t                  sensor_hub_4;
+  lsm6dso_sensor_hub_5_t                  sensor_hub_5;
+  lsm6dso_sensor_hub_6_t                  sensor_hub_6;
+  lsm6dso_sensor_hub_7_t                  sensor_hub_7;
+  lsm6dso_sensor_hub_8_t                  sensor_hub_8;
+  lsm6dso_sensor_hub_9_t                  sensor_hub_9;
+  lsm6dso_sensor_hub_10_t                 sensor_hub_10;
+  lsm6dso_sensor_hub_11_t                 sensor_hub_11;
+  lsm6dso_sensor_hub_12_t                 sensor_hub_12;
+  lsm6dso_sensor_hub_13_t                 sensor_hub_13;
+  lsm6dso_sensor_hub_14_t                 sensor_hub_14;
+  lsm6dso_sensor_hub_15_t                 sensor_hub_15;
+  lsm6dso_sensor_hub_16_t                 sensor_hub_16;
+  lsm6dso_sensor_hub_17_t                 sensor_hub_17;
+  lsm6dso_sensor_hub_18_t                 sensor_hub_18;
+  lsm6dso_master_config_t                 master_config;
+  lsm6dso_slv0_add_t                      slv0_add;
+  lsm6dso_slv0_subadd_t                   slv0_subadd;
+  lsm6dso_slv0_config_t                   slv0_config;
+  lsm6dso_slv1_add_t                      slv1_add;
+  lsm6dso_slv1_subadd_t                   slv1_subadd;
+  lsm6dso_slv1_config_t                   slv1_config;
+  lsm6dso_slv2_add_t                      slv2_add;
+  lsm6dso_slv2_subadd_t                   slv2_subadd;
+  lsm6dso_slv2_config_t                   slv2_config;
+  lsm6dso_slv3_add_t                      slv3_add;
+  lsm6dso_slv3_subadd_t                   slv3_subadd;
+  lsm6dso_slv3_config_t                   slv3_config;
+  lsm6dso_datawrite_src_mode_sub_slv0_t   datawrite_src_mode_sub_slv0;
+  lsm6dso_status_master_t                 status_master;
+  bitwise_t                               bitwise;
+  uint8_t                                 byte;
+} lsm6dso_reg_t;
+
+/**
+  * @}
+  *
+  */
+
+float_t lsm6dso_from_fs2_to_mg(int16_t lsb);
+float_t lsm6dso_from_fs4_to_mg(int16_t lsb);
+float_t lsm6dso_from_fs8_to_mg(int16_t lsb);
+float_t lsm6dso_from_fs16_to_mg(int16_t lsb);
+
+float_t lsm6dso_from_fs125_to_mdps(int16_t lsb);
+float_t lsm6dso_from_fs500_to_mdps(int16_t lsb);
+float_t lsm6dso_from_fs250_to_mdps(int16_t lsb);
+float_t lsm6dso_from_fs1000_to_mdps(int16_t lsb);
+float_t lsm6dso_from_fs2000_to_mdps(int16_t lsb);
+
+float_t lsm6dso_from_lsb_to_celsius(int16_t lsb);
+
+float_t lsm6dso_from_lsb_to_nsec(int16_t lsb);
+
+typedef enum
+{
+  LSM6DSO_2g   = 0,
+  LSM6DSO_16g  = 1, /* if XL_FS_MODE = '1' -> LSM6DSO_2g */
+  LSM6DSO_4g   = 2,
+  LSM6DSO_8g   = 3,
+} lsm6dso_fs_xl_t;
+int32_t lsm6dso_xl_full_scale_set(stmdev_ctx_t *ctx,
+                                  lsm6dso_fs_xl_t val);
+int32_t lsm6dso_xl_full_scale_get(stmdev_ctx_t *ctx,
+                                  lsm6dso_fs_xl_t *val);
+
+typedef enum
+{
+  LSM6DSO_XL_ODR_OFF    = 0,
+  LSM6DSO_XL_ODR_12Hz5  = 1,
+  LSM6DSO_XL_ODR_26Hz   = 2,
+  LSM6DSO_XL_ODR_52Hz   = 3,
+  LSM6DSO_XL_ODR_104Hz  = 4,
+  LSM6DSO_XL_ODR_208Hz  = 5,
+  LSM6DSO_XL_ODR_417Hz  = 6,
+  LSM6DSO_XL_ODR_833Hz  = 7,
+  LSM6DSO_XL_ODR_1667Hz = 8,
+  LSM6DSO_XL_ODR_3333Hz = 9,
+  LSM6DSO_XL_ODR_6667Hz = 10,
+  LSM6DSO_XL_ODR_1Hz6   = 11, /* (low power only) */
+} lsm6dso_odr_xl_t;
+int32_t lsm6dso_xl_data_rate_set(stmdev_ctx_t *ctx,
+                                 lsm6dso_odr_xl_t val);
+int32_t lsm6dso_xl_data_rate_get(stmdev_ctx_t *ctx,
+                                 lsm6dso_odr_xl_t *val);
+
+typedef enum
+{
+  LSM6DSO_250dps   = 0,
+  LSM6DSO_125dps   = 1,
+  LSM6DSO_500dps   = 2,
+  LSM6DSO_1000dps  = 4,
+  LSM6DSO_2000dps  = 6,
+} lsm6dso_fs_g_t;
+int32_t lsm6dso_gy_full_scale_set(stmdev_ctx_t *ctx,
+                                  lsm6dso_fs_g_t val);
+int32_t lsm6dso_gy_full_scale_get(stmdev_ctx_t *ctx,
+                                  lsm6dso_fs_g_t *val);
+
+typedef enum
+{
+  LSM6DSO_GY_ODR_OFF    = 0,
+  LSM6DSO_GY_ODR_12Hz5  = 1,
+  LSM6DSO_GY_ODR_26Hz   = 2,
+  LSM6DSO_GY_ODR_52Hz   = 3,
+  LSM6DSO_GY_ODR_104Hz  = 4,
+  LSM6DSO_GY_ODR_208Hz  = 5,
+  LSM6DSO_GY_ODR_417Hz  = 6,
+  LSM6DSO_GY_ODR_833Hz  = 7,
+  LSM6DSO_GY_ODR_1667Hz = 8,
+  LSM6DSO_GY_ODR_3333Hz = 9,
+  LSM6DSO_GY_ODR_6667Hz = 10,
+} lsm6dso_odr_g_t;
+int32_t lsm6dso_gy_data_rate_set(stmdev_ctx_t *ctx,
+                                 lsm6dso_odr_g_t val);
+int32_t lsm6dso_gy_data_rate_get(stmdev_ctx_t *ctx,
+                                 lsm6dso_odr_g_t *val);
+
+int32_t lsm6dso_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso_block_data_update_get(stmdev_ctx_t *ctx,
+                                      uint8_t *val);
+
+typedef enum
+{
+  LSM6DSO_LSb_1mg  = 0,
+  LSM6DSO_LSb_16mg = 1,
+} lsm6dso_usr_off_w_t;
+int32_t lsm6dso_xl_offset_weight_set(stmdev_ctx_t *ctx,
+                                     lsm6dso_usr_off_w_t val);
+int32_t lsm6dso_xl_offset_weight_get(stmdev_ctx_t *ctx,
+                                     lsm6dso_usr_off_w_t *val);
+
+typedef enum
+{
+  LSM6DSO_HIGH_PERFORMANCE_MD  = 0,
+  LSM6DSO_LOW_NORMAL_POWER_MD  = 1,
+  LSM6DSO_ULTRA_LOW_POWER_MD   = 2,
+} lsm6dso_xl_hm_mode_t;
+int32_t lsm6dso_xl_power_mode_set(stmdev_ctx_t *ctx,
+                                  lsm6dso_xl_hm_mode_t val);
+int32_t lsm6dso_xl_power_mode_get(stmdev_ctx_t *ctx,
+                                  lsm6dso_xl_hm_mode_t *val);
+
+typedef enum
+{
+  LSM6DSO_GY_HIGH_PERFORMANCE  = 0,
+  LSM6DSO_GY_NORMAL            = 1,
+} lsm6dso_g_hm_mode_t;
+int32_t lsm6dso_gy_power_mode_set(stmdev_ctx_t *ctx,
+                                  lsm6dso_g_hm_mode_t val);
+int32_t lsm6dso_gy_power_mode_get(stmdev_ctx_t *ctx,
+                                  lsm6dso_g_hm_mode_t *val);
+
+int32_t lsm6dso_status_reg_get(stmdev_ctx_t *ctx,
+                               lsm6dso_status_reg_t *val);
+
+int32_t lsm6dso_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+                                       uint8_t *val);
+
+int32_t lsm6dso_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+                                       uint8_t *val);
+
+int32_t lsm6dso_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
+                                         uint8_t *val);
+
+int32_t lsm6dso_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dso_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff);
+
+int32_t lsm6dso_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dso_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff);
+
+int32_t lsm6dso_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff);
+int32_t lsm6dso_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff);
+
+int32_t lsm6dso_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lsm6dso_timestamp_rst(stmdev_ctx_t *ctx);
+
+int32_t lsm6dso_timestamp_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lsm6dso_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val);
+
+typedef enum
+{
+  LSM6DSO_NO_ROUND      = 0,
+  LSM6DSO_ROUND_XL      = 1,
+  LSM6DSO_ROUND_GY      = 2,
+  LSM6DSO_ROUND_GY_XL   = 3,
+} lsm6dso_rounding_t;
+int32_t lsm6dso_rounding_mode_set(stmdev_ctx_t *ctx,
+                                  lsm6dso_rounding_t val);
+int32_t lsm6dso_rounding_mode_get(stmdev_ctx_t *ctx,
+                                  lsm6dso_rounding_t *val);
+
+int32_t lsm6dso_temperature_raw_get(stmdev_ctx_t *ctx,  int16_t *val);
+
+int32_t lsm6dso_angular_rate_raw_get(stmdev_ctx_t *ctx,
+                                     int16_t *val);
+
+int32_t lsm6dso_acceleration_raw_get(stmdev_ctx_t *ctx,
+                                     int16_t *val);
+
+int32_t lsm6dso_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff);
+
+int32_t lsm6dso_number_of_steps_get(stmdev_ctx_t *ctx, uint16_t *val);
+
+int32_t lsm6dso_steps_reset(stmdev_ctx_t *ctx);
+
+int32_t lsm6dso_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+typedef enum
+{
+  LSM6DSO_USER_BANK           = 0,
+  LSM6DSO_SENSOR_HUB_BANK     = 1,
+  LSM6DSO_EMBEDDED_FUNC_BANK  = 2,
+} lsm6dso_reg_access_t;
+int32_t lsm6dso_mem_bank_set(stmdev_ctx_t *ctx,
+                             lsm6dso_reg_access_t val);
+int32_t lsm6dso_mem_bank_get(stmdev_ctx_t *ctx,
+                             lsm6dso_reg_access_t *val);
+
+int32_t lsm6dso_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t address,
+                                 uint8_t *val);
+int32_t lsm6dso_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t address,
+                                uint8_t *val);
+int32_t lsm6dso_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address,
+                            uint8_t *buf, uint8_t len);
+int32_t lsm6dso_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address,
+                           uint8_t *val);
+
+typedef enum
+{
+  LSM6DSO_DRDY_LATCHED = 0,
+  LSM6DSO_DRDY_PULSED  = 1,
+} lsm6dso_dataready_pulsed_t;
+int32_t lsm6dso_data_ready_mode_set(stmdev_ctx_t *ctx,
+                                    lsm6dso_dataready_pulsed_t val);
+int32_t lsm6dso_data_ready_mode_get(stmdev_ctx_t *ctx,
+                                    lsm6dso_dataready_pulsed_t *val);
+
+int32_t lsm6dso_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
+
+int32_t lsm6dso_reset_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lsm6dso_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lsm6dso_boot_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+typedef enum
+{
+  LSM6DSO_XL_ST_DISABLE  = 0,
+  LSM6DSO_XL_ST_POSITIVE = 1,
+  LSM6DSO_XL_ST_NEGATIVE = 2,
+} lsm6dso_st_xl_t;
+int32_t lsm6dso_xl_self_test_set(stmdev_ctx_t *ctx,
+                                 lsm6dso_st_xl_t val);
+int32_t lsm6dso_xl_self_test_get(stmdev_ctx_t *ctx,
+                                 lsm6dso_st_xl_t *val);
+
+typedef enum
+{
+  LSM6DSO_GY_ST_DISABLE  = 0,
+  LSM6DSO_GY_ST_POSITIVE = 1,
+  LSM6DSO_GY_ST_NEGATIVE = 3,
+} lsm6dso_st_g_t;
+int32_t lsm6dso_gy_self_test_set(stmdev_ctx_t *ctx,
+                                 lsm6dso_st_g_t val);
+int32_t lsm6dso_gy_self_test_get(stmdev_ctx_t *ctx,
+                                 lsm6dso_st_g_t *val);
+
+int32_t lsm6dso_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lsm6dso_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lsm6dso_filter_settling_mask_set(stmdev_ctx_t *ctx,
+                                         uint8_t val);
+int32_t lsm6dso_filter_settling_mask_get(stmdev_ctx_t *ctx,
+                                         uint8_t *val);
+
+typedef enum
+{
+  LSM6DSO_ULTRA_LIGHT  = 0,
+  LSM6DSO_VERY_LIGHT   = 1,
+  LSM6DSO_LIGHT        = 2,
+  LSM6DSO_MEDIUM       = 3,
+  LSM6DSO_STRONG       = 4, /* not available for data rate > 1k670Hz */
+  LSM6DSO_VERY_STRONG  = 5, /* not available for data rate > 1k670Hz */
+  LSM6DSO_AGGRESSIVE   = 6, /* not available for data rate > 1k670Hz */
+  LSM6DSO_XTREME       = 7, /* not available for data rate > 1k670Hz */
+} lsm6dso_ftype_t;
+int32_t lsm6dso_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
+                                     lsm6dso_ftype_t val);
+int32_t lsm6dso_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
+                                     lsm6dso_ftype_t *val);
+
+int32_t lsm6dso_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+typedef enum
+{
+  LSM6DSO_HP_PATH_DISABLE_ON_OUT    = 0x00,
+  LSM6DSO_SLOPE_ODR_DIV_4           = 0x10,
+  LSM6DSO_HP_ODR_DIV_10             = 0x11,
+  LSM6DSO_HP_ODR_DIV_20             = 0x12,
+  LSM6DSO_HP_ODR_DIV_45             = 0x13,
+  LSM6DSO_HP_ODR_DIV_100            = 0x14,
+  LSM6DSO_HP_ODR_DIV_200            = 0x15,
+  LSM6DSO_HP_ODR_DIV_400            = 0x16,
+  LSM6DSO_HP_ODR_DIV_800            = 0x17,
+  LSM6DSO_HP_REF_MD_ODR_DIV_10      = 0x31,
+  LSM6DSO_HP_REF_MD_ODR_DIV_20      = 0x32,
+  LSM6DSO_HP_REF_MD_ODR_DIV_45      = 0x33,
+  LSM6DSO_HP_REF_MD_ODR_DIV_100     = 0x34,
+  LSM6DSO_HP_REF_MD_ODR_DIV_200     = 0x35,
+  LSM6DSO_HP_REF_MD_ODR_DIV_400     = 0x36,
+  LSM6DSO_HP_REF_MD_ODR_DIV_800     = 0x37,
+  LSM6DSO_LP_ODR_DIV_10             = 0x01,
+  LSM6DSO_LP_ODR_DIV_20             = 0x02,
+  LSM6DSO_LP_ODR_DIV_45             = 0x03,
+  LSM6DSO_LP_ODR_DIV_100            = 0x04,
+  LSM6DSO_LP_ODR_DIV_200            = 0x05,
+  LSM6DSO_LP_ODR_DIV_400            = 0x06,
+  LSM6DSO_LP_ODR_DIV_800            = 0x07,
+} lsm6dso_hp_slope_xl_en_t;
+int32_t lsm6dso_xl_hp_path_on_out_set(stmdev_ctx_t *ctx,
+                                      lsm6dso_hp_slope_xl_en_t val);
+int32_t lsm6dso_xl_hp_path_on_out_get(stmdev_ctx_t *ctx,
+                                      lsm6dso_hp_slope_xl_en_t *val);
+
+int32_t lsm6dso_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+typedef enum
+{
+  LSM6DSO_USE_SLOPE = 0,
+  LSM6DSO_USE_HPF   = 1,
+} lsm6dso_slope_fds_t;
+int32_t lsm6dso_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
+                                        lsm6dso_slope_fds_t val);
+int32_t lsm6dso_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
+                                        lsm6dso_slope_fds_t *val);
+
+typedef enum
+{
+  LSM6DSO_HP_FILTER_NONE     = 0x00,
+  LSM6DSO_HP_FILTER_16mHz    = 0x80,
+  LSM6DSO_HP_FILTER_65mHz    = 0x81,
+  LSM6DSO_HP_FILTER_260mHz   = 0x82,
+  LSM6DSO_HP_FILTER_1Hz04    = 0x83,
+} lsm6dso_hpm_g_t;
+int32_t lsm6dso_gy_hp_path_internal_set(stmdev_ctx_t *ctx,
+                                        lsm6dso_hpm_g_t val);
+int32_t lsm6dso_gy_hp_path_internal_get(stmdev_ctx_t *ctx,
+                                        lsm6dso_hpm_g_t *val);
+
+typedef enum
+{
+  LSM6DSO_AUX_PULL_UP_DISC       = 0,
+  LSM6DSO_AUX_PULL_UP_CONNECT    = 1,
+} lsm6dso_ois_pu_dis_t;
+int32_t lsm6dso_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx,
+                                     lsm6dso_ois_pu_dis_t val);
+int32_t lsm6dso_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx,
+                                     lsm6dso_ois_pu_dis_t *val);
+
+typedef enum
+{
+  LSM6DSO_AUX_ON                    = 1,
+  LSM6DSO_AUX_ON_BY_AUX_INTERFACE   = 0,
+} lsm6dso_ois_on_t;
+int32_t lsm6dso_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx,
+                                   lsm6dso_ois_on_t val);
+int32_t lsm6dso_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx,
+                                   lsm6dso_ois_on_t *val);
+
+typedef enum
+{
+  LSM6DSO_USE_SAME_XL_FS        = 0,
+  LSM6DSO_USE_DIFFERENT_XL_FS   = 1,
+} lsm6dso_xl_fs_mode_t;
+int32_t lsm6dso_aux_xl_fs_mode_set(stmdev_ctx_t *ctx,
+                                   lsm6dso_xl_fs_mode_t val);
+int32_t lsm6dso_aux_xl_fs_mode_get(stmdev_ctx_t *ctx,
+                                   lsm6dso_xl_fs_mode_t *val);
+
+int32_t lsm6dso_aux_status_reg_get(stmdev_ctx_t *ctx,
+                                   lsm6dso_status_spiaux_t *val);
+
+int32_t lsm6dso_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
+                                           uint8_t *val);
+
+int32_t lsm6dso_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
+                                           uint8_t *val);
+
+int32_t lsm6dso_aux_gy_flag_settling_get(stmdev_ctx_t *ctx,
+                                         uint8_t *val);
+
+typedef enum
+{
+  LSM6DSO_AUX_XL_DISABLE = 0,
+  LSM6DSO_AUX_XL_POS     = 1,
+  LSM6DSO_AUX_XL_NEG     = 2,
+} lsm6dso_st_xl_ois_t;
+int32_t lsm6dso_aux_xl_self_test_set(stmdev_ctx_t *ctx,
+                                     lsm6dso_st_xl_ois_t val);
+int32_t lsm6dso_aux_xl_self_test_get(stmdev_ctx_t *ctx,
+                                     lsm6dso_st_xl_ois_t *val);
+
+typedef enum
+{
+  LSM6DSO_AUX_DEN_ACTIVE_LOW     = 0,
+  LSM6DSO_AUX_DEN_ACTIVE_HIGH    = 1,
+} lsm6dso_den_lh_ois_t;
+int32_t lsm6dso_aux_den_polarity_set(stmdev_ctx_t *ctx,
+                                     lsm6dso_den_lh_ois_t val);
+int32_t lsm6dso_aux_den_polarity_get(stmdev_ctx_t *ctx,
+                                     lsm6dso_den_lh_ois_t *val);
+
+typedef enum
+{
+  LSM6DSO_AUX_DEN_DISABLE         = 0,
+  LSM6DSO_AUX_DEN_LEVEL_LATCH     = 3,
+  LSM6DSO_AUX_DEN_LEVEL_TRIG      = 2,
+} lsm6dso_lvl2_ois_t;
+int32_t lsm6dso_aux_den_mode_set(stmdev_ctx_t *ctx,
+                                 lsm6dso_lvl2_ois_t val);
+int32_t lsm6dso_aux_den_mode_get(stmdev_ctx_t *ctx,
+                                 lsm6dso_lvl2_ois_t *val);
+
+int32_t lsm6dso_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+typedef enum
+{
+  LSM6DSO_AUX_DISABLE  = 0,
+  LSM6DSO_MODE_3_GY    = 1,
+  LSM6DSO_MODE_4_GY_XL = 3,
+} lsm6dso_ois_en_spi2_t;
+int32_t lsm6dso_aux_mode_set(stmdev_ctx_t *ctx,
+                             lsm6dso_ois_en_spi2_t val);
+int32_t lsm6dso_aux_mode_get(stmdev_ctx_t *ctx,
+                             lsm6dso_ois_en_spi2_t *val);
+
+typedef enum
+{
+  LSM6DSO_250dps_AUX  = 0,
+  LSM6DSO_125dps_AUX  = 1,
+  LSM6DSO_500dps_AUX  = 2,
+  LSM6DSO_1000dps_AUX = 4,
+  LSM6DSO_2000dps_AUX = 6,
+} lsm6dso_fs_g_ois_t;
+int32_t lsm6dso_aux_gy_full_scale_set(stmdev_ctx_t *ctx,
+                                      lsm6dso_fs_g_ois_t val);
+int32_t lsm6dso_aux_gy_full_scale_get(stmdev_ctx_t *ctx,
+                                      lsm6dso_fs_g_ois_t *val);
+
+typedef enum
+{
+  LSM6DSO_AUX_SPI_4_WIRE = 0,
+  LSM6DSO_AUX_SPI_3_WIRE = 1,
+} lsm6dso_sim_ois_t;
+int32_t lsm6dso_aux_spi_mode_set(stmdev_ctx_t *ctx,
+                                 lsm6dso_sim_ois_t val);
+int32_t lsm6dso_aux_spi_mode_get(stmdev_ctx_t *ctx,
+                                 lsm6dso_sim_ois_t *val);
+
+typedef enum
+{
+  LSM6DSO_351Hz39 = 0,
+  LSM6DSO_236Hz63 = 1,
+  LSM6DSO_172Hz70 = 2,
+  LSM6DSO_937Hz91 = 3,
+} lsm6dso_ftype_ois_t;
+int32_t lsm6dso_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
+                                         lsm6dso_ftype_ois_t val);
+int32_t lsm6dso_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
+                                         lsm6dso_ftype_ois_t *val);
+
+typedef enum
+{
+  LSM6DSO_AUX_HP_DISABLE = 0x00,
+  LSM6DSO_AUX_HP_Hz016   = 0x10,
+  LSM6DSO_AUX_HP_Hz065   = 0x11,
+  LSM6DSO_AUX_HP_Hz260   = 0x12,
+  LSM6DSO_AUX_HP_1Hz040  = 0x13,
+} lsm6dso_hpm_ois_t;
+int32_t lsm6dso_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx,
+                                        lsm6dso_hpm_ois_t val);
+int32_t lsm6dso_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx,
+                                        lsm6dso_hpm_ois_t *val);
+
+typedef enum
+{
+  LSM6DSO_ENABLE_CLAMP  = 0,
+  LSM6DSO_DISABLE_CLAMP = 1,
+} lsm6dso_st_ois_clampdis_t;
+int32_t lsm6dso_aux_gy_clamp_set(stmdev_ctx_t *ctx,
+                                 lsm6dso_st_ois_clampdis_t val);
+int32_t lsm6dso_aux_gy_clamp_get(stmdev_ctx_t *ctx,
+                                 lsm6dso_st_ois_clampdis_t *val);
+
+typedef enum
+{
+  LSM6DSO_AUX_GY_DISABLE = 0,
+  LSM6DSO_AUX_GY_POS     = 1,
+  LSM6DSO_AUX_GY_NEG     = 3,
+} lsm6dso_st_ois_t;
+int32_t lsm6dso_aux_gy_self_test_set(stmdev_ctx_t *ctx,
+                                     lsm6dso_st_ois_t val);
+int32_t lsm6dso_aux_gy_self_test_get(stmdev_ctx_t *ctx,
+                                     lsm6dso_st_ois_t *val);
+
+typedef enum
+{
+  LSM6DSO_289Hz = 0,
+  LSM6DSO_258Hz = 1,
+  LSM6DSO_120Hz = 2,
+  LSM6DSO_65Hz2 = 3,
+  LSM6DSO_33Hz2 = 4,
+  LSM6DSO_16Hz6 = 5,
+  LSM6DSO_8Hz30 = 6,
+  LSM6DSO_4Hz15 = 7,
+} lsm6dso_filter_xl_conf_ois_t;
+int32_t lsm6dso_aux_xl_bandwidth_set(stmdev_ctx_t *ctx,
+                                     lsm6dso_filter_xl_conf_ois_t val);
+int32_t lsm6dso_aux_xl_bandwidth_get(stmdev_ctx_t *ctx,
+                                     lsm6dso_filter_xl_conf_ois_t *val);
+
+typedef enum
+{
+  LSM6DSO_AUX_2g  = 0,
+  LSM6DSO_AUX_16g = 1,
+  LSM6DSO_AUX_4g  = 2,
+  LSM6DSO_AUX_8g  = 3,
+} lsm6dso_fs_xl_ois_t;
+int32_t lsm6dso_aux_xl_full_scale_set(stmdev_ctx_t *ctx,
+                                      lsm6dso_fs_xl_ois_t val);
+int32_t lsm6dso_aux_xl_full_scale_get(stmdev_ctx_t *ctx,
+                                      lsm6dso_fs_xl_ois_t *val);
+
+typedef enum
+{
+  LSM6DSO_PULL_UP_DISC       = 0,
+  LSM6DSO_PULL_UP_CONNECT    = 1,
+} lsm6dso_sdo_pu_en_t;
+int32_t lsm6dso_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
+                                 lsm6dso_sdo_pu_en_t val);
+int32_t lsm6dso_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
+                                 lsm6dso_sdo_pu_en_t *val);
+
+typedef enum
+{
+  LSM6DSO_SPI_4_WIRE = 0,
+  LSM6DSO_SPI_3_WIRE = 1,
+} lsm6dso_sim_t;
+int32_t lsm6dso_spi_mode_set(stmdev_ctx_t *ctx, lsm6dso_sim_t val);
+int32_t lsm6dso_spi_mode_get(stmdev_ctx_t *ctx, lsm6dso_sim_t *val);
+
+typedef enum
+{
+  LSM6DSO_I2C_ENABLE  = 0,
+  LSM6DSO_I2C_DISABLE = 1,
+} lsm6dso_i2c_disable_t;
+int32_t lsm6dso_i2c_interface_set(stmdev_ctx_t *ctx,
+                                  lsm6dso_i2c_disable_t val);
+int32_t lsm6dso_i2c_interface_get(stmdev_ctx_t *ctx,
+                                  lsm6dso_i2c_disable_t *val);
+
+typedef enum
+{
+  LSM6DSO_I3C_DISABLE         = 0x80,
+  LSM6DSO_I3C_ENABLE_T_50us   = 0x00,
+  LSM6DSO_I3C_ENABLE_T_2us    = 0x01,
+  LSM6DSO_I3C_ENABLE_T_1ms    = 0x02,
+  LSM6DSO_I3C_ENABLE_T_25ms   = 0x03,
+} lsm6dso_i3c_disable_t;
+int32_t lsm6dso_i3c_disable_set(stmdev_ctx_t *ctx,
+                                lsm6dso_i3c_disable_t val);
+int32_t lsm6dso_i3c_disable_get(stmdev_ctx_t *ctx,
+                                lsm6dso_i3c_disable_t *val);
+
+typedef enum
+{
+  LSM6DSO_PULL_DOWN_DISC       = 0,
+  LSM6DSO_PULL_DOWN_CONNECT    = 1,
+} lsm6dso_int1_pd_en_t;
+int32_t lsm6dso_int1_mode_set(stmdev_ctx_t *ctx,
+                              lsm6dso_int1_pd_en_t val);
+int32_t lsm6dso_int1_mode_get(stmdev_ctx_t *ctx,
+                              lsm6dso_int1_pd_en_t *val);
+
+typedef enum
+{
+  LSM6DSO_PUSH_PULL   = 0,
+  LSM6DSO_OPEN_DRAIN  = 1,
+} lsm6dso_pp_od_t;
+int32_t lsm6dso_pin_mode_set(stmdev_ctx_t *ctx, lsm6dso_pp_od_t val);
+int32_t lsm6dso_pin_mode_get(stmdev_ctx_t *ctx, lsm6dso_pp_od_t *val);
+
+typedef enum
+{
+  LSM6DSO_ACTIVE_HIGH = 0,
+  LSM6DSO_ACTIVE_LOW  = 1,
+} lsm6dso_h_lactive_t;
+int32_t lsm6dso_pin_polarity_set(stmdev_ctx_t *ctx,
+                                 lsm6dso_h_lactive_t val);
+int32_t lsm6dso_pin_polarity_get(stmdev_ctx_t *ctx,
+                                 lsm6dso_h_lactive_t *val);
+
+int32_t lsm6dso_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+typedef enum
+{
+  LSM6DSO_ALL_INT_PULSED            = 0,
+  LSM6DSO_BASE_LATCHED_EMB_PULSED   = 1,
+  LSM6DSO_BASE_PULSED_EMB_LATCHED   = 2,
+  LSM6DSO_ALL_INT_LATCHED           = 3,
+} lsm6dso_lir_t;
+int32_t lsm6dso_int_notification_set(stmdev_ctx_t *ctx,
+                                     lsm6dso_lir_t val);
+int32_t lsm6dso_int_notification_get(stmdev_ctx_t *ctx,
+                                     lsm6dso_lir_t *val);
+
+typedef enum
+{
+  LSM6DSO_LSb_FS_DIV_64       = 0,
+  LSM6DSO_LSb_FS_DIV_256      = 1,
+} lsm6dso_wake_ths_w_t;
+int32_t lsm6dso_wkup_ths_weight_set(stmdev_ctx_t *ctx,
+                                    lsm6dso_wake_ths_w_t val);
+int32_t lsm6dso_wkup_ths_weight_get(stmdev_ctx_t *ctx,
+                                    lsm6dso_wake_ths_w_t *val);
+
+int32_t lsm6dso_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lsm6dso_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx,
+                                          uint8_t val);
+int32_t lsm6dso_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx,
+                                          uint8_t *val);
+
+int32_t lsm6dso_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lsm6dso_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+typedef enum
+{
+  LSM6DSO_DRIVE_SLEEP_CHG_EVENT = 0,
+  LSM6DSO_DRIVE_SLEEP_STATUS    = 1,
+} lsm6dso_sleep_status_on_int_t;
+int32_t lsm6dso_act_pin_notification_set(stmdev_ctx_t *ctx,
+                                         lsm6dso_sleep_status_on_int_t val);
+int32_t lsm6dso_act_pin_notification_get(stmdev_ctx_t *ctx,
+                                         lsm6dso_sleep_status_on_int_t *val);
+
+typedef enum
+{
+  LSM6DSO_XL_AND_GY_NOT_AFFECTED      = 0,
+  LSM6DSO_XL_12Hz5_GY_NOT_AFFECTED    = 1,
+  LSM6DSO_XL_12Hz5_GY_SLEEP           = 2,
+  LSM6DSO_XL_12Hz5_GY_PD              = 3,
+} lsm6dso_inact_en_t;
+int32_t lsm6dso_act_mode_set(stmdev_ctx_t *ctx,
+                             lsm6dso_inact_en_t val);
+int32_t lsm6dso_act_mode_get(stmdev_ctx_t *ctx,
+                             lsm6dso_inact_en_t *val);
+
+int32_t lsm6dso_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lsm6dso_tap_detection_on_z_set(stmdev_ctx_t *ctx,
+                                       uint8_t val);
+int32_t lsm6dso_tap_detection_on_z_get(stmdev_ctx_t *ctx,
+                                       uint8_t *val);
+
+int32_t lsm6dso_tap_detection_on_y_set(stmdev_ctx_t *ctx,
+                                       uint8_t val);
+int32_t lsm6dso_tap_detection_on_y_get(stmdev_ctx_t *ctx,
+                                       uint8_t *val);
+
+int32_t lsm6dso_tap_detection_on_x_set(stmdev_ctx_t *ctx,
+                                       uint8_t val);
+int32_t lsm6dso_tap_detection_on_x_get(stmdev_ctx_t *ctx,
+                                       uint8_t *val);
+
+int32_t lsm6dso_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+typedef enum
+{
+  LSM6DSO_XYZ = 0,
+  LSM6DSO_YXZ = 1,
+  LSM6DSO_XZY = 2,
+  LSM6DSO_ZYX = 3,
+  LSM6DSO_YZX = 5,
+  LSM6DSO_ZXY = 6,
+} lsm6dso_tap_priority_t;
+int32_t lsm6dso_tap_axis_priority_set(stmdev_ctx_t *ctx,
+                                      lsm6dso_tap_priority_t val);
+int32_t lsm6dso_tap_axis_priority_get(stmdev_ctx_t *ctx,
+                                      lsm6dso_tap_priority_t *val);
+
+int32_t lsm6dso_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lsm6dso_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lsm6dso_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lsm6dso_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lsm6dso_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+typedef enum
+{
+  LSM6DSO_ONLY_SINGLE = 0,
+  LSM6DSO_BOTH_SINGLE_DOUBLE = 1,
+} lsm6dso_single_double_tap_t;
+int32_t lsm6dso_tap_mode_set(stmdev_ctx_t *ctx,
+                             lsm6dso_single_double_tap_t val);
+int32_t lsm6dso_tap_mode_get(stmdev_ctx_t *ctx,
+                             lsm6dso_single_double_tap_t *val);
+
+typedef enum
+{
+  LSM6DSO_DEG_80  = 0,
+  LSM6DSO_DEG_70  = 1,
+  LSM6DSO_DEG_60  = 2,
+  LSM6DSO_DEG_50  = 3,
+} lsm6dso_sixd_ths_t;
+int32_t lsm6dso_6d_threshold_set(stmdev_ctx_t *ctx,
+                                 lsm6dso_sixd_ths_t val);
+int32_t lsm6dso_6d_threshold_get(stmdev_ctx_t *ctx,
+                                 lsm6dso_sixd_ths_t *val);
+
+int32_t lsm6dso_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+typedef enum
+{
+  LSM6DSO_FF_TSH_156mg = 0,
+  LSM6DSO_FF_TSH_219mg = 1,
+  LSM6DSO_FF_TSH_250mg = 2,
+  LSM6DSO_FF_TSH_312mg = 3,
+  LSM6DSO_FF_TSH_344mg = 4,
+  LSM6DSO_FF_TSH_406mg = 5,
+  LSM6DSO_FF_TSH_469mg = 6,
+  LSM6DSO_FF_TSH_500mg = 7,
+} lsm6dso_ff_ths_t;
+int32_t lsm6dso_ff_threshold_set(stmdev_ctx_t *ctx,
+                                 lsm6dso_ff_ths_t val);
+int32_t lsm6dso_ff_threshold_get(stmdev_ctx_t *ctx,
+                                 lsm6dso_ff_ths_t *val);
+
+int32_t lsm6dso_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lsm6dso_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val);
+int32_t lsm6dso_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val);
+
+int32_t lsm6dso_compression_algo_init_set(stmdev_ctx_t *ctx,
+                                          uint8_t val);
+int32_t lsm6dso_compression_algo_init_get(stmdev_ctx_t *ctx,
+                                          uint8_t *val);
+
+typedef enum
+{
+  LSM6DSO_CMP_DISABLE  = 0x00,
+  LSM6DSO_CMP_ALWAYS   = 0x04,
+  LSM6DSO_CMP_8_TO_1   = 0x05,
+  LSM6DSO_CMP_16_TO_1  = 0x06,
+  LSM6DSO_CMP_32_TO_1  = 0x07,
+} lsm6dso_uncoptr_rate_t;
+int32_t lsm6dso_compression_algo_set(stmdev_ctx_t *ctx,
+                                     lsm6dso_uncoptr_rate_t val);
+int32_t lsm6dso_compression_algo_get(stmdev_ctx_t *ctx,
+                                     lsm6dso_uncoptr_rate_t *val);
+
+int32_t lsm6dso_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx,
+                                              uint8_t val);
+int32_t lsm6dso_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx,
+                                              uint8_t *val);
+
+int32_t lsm6dso_compression_algo_real_time_set(stmdev_ctx_t *ctx,
+                                               uint8_t val);
+int32_t lsm6dso_compression_algo_real_time_get(stmdev_ctx_t *ctx,
+                                               uint8_t *val);
+
+int32_t lsm6dso_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+typedef enum
+{
+  LSM6DSO_XL_NOT_BATCHED       =  0,
+  LSM6DSO_XL_BATCHED_AT_12Hz5   =  1,
+  LSM6DSO_XL_BATCHED_AT_26Hz    =  2,
+  LSM6DSO_XL_BATCHED_AT_52Hz    =  3,
+  LSM6DSO_XL_BATCHED_AT_104Hz   =  4,
+  LSM6DSO_XL_BATCHED_AT_208Hz   =  5,
+  LSM6DSO_XL_BATCHED_AT_417Hz   =  6,
+  LSM6DSO_XL_BATCHED_AT_833Hz   =  7,
+  LSM6DSO_XL_BATCHED_AT_1667Hz  =  8,
+  LSM6DSO_XL_BATCHED_AT_3333Hz  =  9,
+  LSM6DSO_XL_BATCHED_AT_6667Hz  = 10,
+  LSM6DSO_XL_BATCHED_AT_6Hz5    = 11,
+} lsm6dso_bdr_xl_t;
+int32_t lsm6dso_fifo_xl_batch_set(stmdev_ctx_t *ctx,
+                                  lsm6dso_bdr_xl_t val);
+int32_t lsm6dso_fifo_xl_batch_get(stmdev_ctx_t *ctx,
+                                  lsm6dso_bdr_xl_t *val);
+
+typedef enum
+{
+  LSM6DSO_GY_NOT_BATCHED         = 0,
+  LSM6DSO_GY_BATCHED_AT_12Hz5    = 1,
+  LSM6DSO_GY_BATCHED_AT_26Hz     = 2,
+  LSM6DSO_GY_BATCHED_AT_52Hz     = 3,
+  LSM6DSO_GY_BATCHED_AT_104Hz    = 4,
+  LSM6DSO_GY_BATCHED_AT_208Hz    = 5,
+  LSM6DSO_GY_BATCHED_AT_417Hz    = 6,
+  LSM6DSO_GY_BATCHED_AT_833Hz    = 7,
+  LSM6DSO_GY_BATCHED_AT_1667Hz   = 8,
+  LSM6DSO_GY_BATCHED_AT_3333Hz   = 9,
+  LSM6DSO_GY_BATCHED_AT_6667Hz   = 10,
+  LSM6DSO_GY_BATCHED_AT_6Hz5     = 11,
+} lsm6dso_bdr_gy_t;
+int32_t lsm6dso_fifo_gy_batch_set(stmdev_ctx_t *ctx,
+                                  lsm6dso_bdr_gy_t val);
+int32_t lsm6dso_fifo_gy_batch_get(stmdev_ctx_t *ctx,
+                                  lsm6dso_bdr_gy_t *val);
+
+typedef enum
+{
+  LSM6DSO_BYPASS_MODE             = 0,
+  LSM6DSO_FIFO_MODE               = 1,
+  LSM6DSO_STREAM_TO_FIFO_MODE     = 3,
+  LSM6DSO_BYPASS_TO_STREAM_MODE   = 4,
+  LSM6DSO_STREAM_MODE             = 6,
+  LSM6DSO_BYPASS_TO_FIFO_MODE     = 7,
+} lsm6dso_fifo_mode_t;
+int32_t lsm6dso_fifo_mode_set(stmdev_ctx_t *ctx,
+                              lsm6dso_fifo_mode_t val);
+int32_t lsm6dso_fifo_mode_get(stmdev_ctx_t *ctx,
+                              lsm6dso_fifo_mode_t *val);
+
+typedef enum
+{
+  LSM6DSO_TEMP_NOT_BATCHED        = 0,
+  LSM6DSO_TEMP_BATCHED_AT_1Hz6    = 1,
+  LSM6DSO_TEMP_BATCHED_AT_12Hz5   = 2,
+  LSM6DSO_TEMP_BATCHED_AT_52Hz    = 3,
+} lsm6dso_odr_t_batch_t;
+int32_t lsm6dso_fifo_temp_batch_set(stmdev_ctx_t *ctx,
+                                    lsm6dso_odr_t_batch_t val);
+int32_t lsm6dso_fifo_temp_batch_get(stmdev_ctx_t *ctx,
+                                    lsm6dso_odr_t_batch_t *val);
+
+typedef enum
+{
+  LSM6DSO_NO_DECIMATION = 0,
+  LSM6DSO_DEC_1         = 1,
+  LSM6DSO_DEC_8         = 2,
+  LSM6DSO_DEC_32        = 3,
+} lsm6dso_odr_ts_batch_t;
+int32_t lsm6dso_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
+                                              lsm6dso_odr_ts_batch_t val);
+int32_t lsm6dso_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
+                                              lsm6dso_odr_ts_batch_t *val);
+
+typedef enum
+{
+  LSM6DSO_XL_BATCH_EVENT   = 0,
+  LSM6DSO_GYRO_BATCH_EVENT = 1,
+} lsm6dso_trig_counter_bdr_t;
+
+typedef enum
+{
+  LSM6DSO_GYRO_NC_TAG    = 1,
+  LSM6DSO_XL_NC_TAG,
+  LSM6DSO_TEMPERATURE_TAG,
+  LSM6DSO_TIMESTAMP_TAG,
+  LSM6DSO_CFG_CHANGE_TAG,
+  LSM6DSO_XL_NC_T_2_TAG,
+  LSM6DSO_XL_NC_T_1_TAG,
+  LSM6DSO_XL_2XC_TAG,
+  LSM6DSO_XL_3XC_TAG,
+  LSM6DSO_GYRO_NC_T_2_TAG,
+  LSM6DSO_GYRO_NC_T_1_TAG,
+  LSM6DSO_GYRO_2XC_TAG,
+  LSM6DSO_GYRO_3XC_TAG,
+  LSM6DSO_SENSORHUB_SLAVE0_TAG,
+  LSM6DSO_SENSORHUB_SLAVE1_TAG,
+  LSM6DSO_SENSORHUB_SLAVE2_TAG,
+  LSM6DSO_SENSORHUB_SLAVE3_TAG,
+  LSM6DSO_STEP_CPUNTER_TAG,
+  LSM6DSO_GAME_ROTATION_TAG,
+  LSM6DSO_GEOMAG_ROTATION_TAG,
+  LSM6DSO_ROTATION_TAG,
+  LSM6DSO_SENSORHUB_NACK_TAG  = 0x19,
+} lsm6dso_fifo_tag_t;
+int32_t lsm6dso_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx,
+                                         lsm6dso_trig_counter_bdr_t val);
+int32_t lsm6dso_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx,
+                                         lsm6dso_trig_counter_bdr_t *val);
+
+int32_t lsm6dso_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso_rst_batch_counter_get(stmdev_ctx_t *ctx,
+                                      uint8_t *val);
+
+int32_t lsm6dso_batch_counter_threshold_set(stmdev_ctx_t *ctx,
+                                            uint16_t val);
+int32_t lsm6dso_batch_counter_threshold_get(stmdev_ctx_t *ctx,
+                                            uint16_t *val);
+
+int32_t lsm6dso_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val);
+
+int32_t lsm6dso_fifo_status_get(stmdev_ctx_t *ctx,
+                                lsm6dso_fifo_status2_t *val);
+
+int32_t lsm6dso_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lsm6dso_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lsm6dso_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lsm6dso_fifo_sensor_tag_get(stmdev_ctx_t *ctx,
+                                    lsm6dso_fifo_tag_t *val);
+
+int32_t lsm6dso_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lsm6dso_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lsm6dso_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lsm6dso_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lsm6dso_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+typedef enum
+{
+  LSM6DSO_DEN_DISABLE    = 0,
+  LSM6DSO_LEVEL_FIFO     = 6,
+  LSM6DSO_LEVEL_LETCHED  = 3,
+  LSM6DSO_LEVEL_TRIGGER  = 2,
+  LSM6DSO_EDGE_TRIGGER   = 4,
+} lsm6dso_den_mode_t;
+int32_t lsm6dso_den_mode_set(stmdev_ctx_t *ctx,
+                             lsm6dso_den_mode_t val);
+int32_t lsm6dso_den_mode_get(stmdev_ctx_t *ctx,
+                             lsm6dso_den_mode_t *val);
+
+typedef enum
+{
+  LSM6DSO_DEN_ACT_LOW  = 0,
+  LSM6DSO_DEN_ACT_HIGH = 1,
+} lsm6dso_den_lh_t;
+int32_t lsm6dso_den_polarity_set(stmdev_ctx_t *ctx,
+                                 lsm6dso_den_lh_t val);
+int32_t lsm6dso_den_polarity_get(stmdev_ctx_t *ctx,
+                                 lsm6dso_den_lh_t *val);
+
+typedef enum
+{
+  LSM6DSO_STAMP_IN_GY_DATA     = 0,
+  LSM6DSO_STAMP_IN_XL_DATA     = 1,
+  LSM6DSO_STAMP_IN_GY_XL_DATA  = 2,
+} lsm6dso_den_xl_g_t;
+int32_t lsm6dso_den_enable_set(stmdev_ctx_t *ctx,
+                               lsm6dso_den_xl_g_t val);
+int32_t lsm6dso_den_enable_get(stmdev_ctx_t *ctx,
+                               lsm6dso_den_xl_g_t *val);
+
+int32_t lsm6dso_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lsm6dso_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lsm6dso_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+typedef enum
+{
+  LSM6DSO_PEDO_BASE_MODE            = 0x00,
+  LSM6DSO_FALSE_STEP_REJ            = 0x10,
+  LSM6DSO_FALSE_STEP_REJ_ADV_MODE   = 0x30,
+} lsm6dso_pedo_md_t;
+int32_t lsm6dso_pedo_sens_set(stmdev_ctx_t *ctx,
+                              lsm6dso_pedo_md_t val);
+int32_t lsm6dso_pedo_sens_get(stmdev_ctx_t *ctx,
+                              lsm6dso_pedo_md_t *val);
+
+int32_t lsm6dso_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lsm6dso_pedo_debounce_steps_set(stmdev_ctx_t *ctx,
+                                        uint8_t *buff);
+int32_t lsm6dso_pedo_debounce_steps_get(stmdev_ctx_t *ctx,
+                                        uint8_t *buff);
+
+int32_t lsm6dso_pedo_steps_period_set(stmdev_ctx_t *ctx,
+                                      uint16_t val);
+int32_t lsm6dso_pedo_steps_period_get(stmdev_ctx_t *ctx,
+                                      uint16_t *val);
+
+typedef enum
+{
+  LSM6DSO_EVERY_STEP     = 0,
+  LSM6DSO_COUNT_OVERFLOW = 1,
+} lsm6dso_carry_count_en_t;
+int32_t lsm6dso_pedo_int_mode_set(stmdev_ctx_t *ctx,
+                                  lsm6dso_carry_count_en_t val);
+int32_t lsm6dso_pedo_int_mode_get(stmdev_ctx_t *ctx,
+                                  lsm6dso_carry_count_en_t *val);
+
+int32_t lsm6dso_motion_flag_data_ready_get(stmdev_ctx_t *ctx,
+                                           uint8_t *val);
+
+int32_t lsm6dso_tilt_flag_data_ready_get(stmdev_ctx_t *ctx,
+                                         uint8_t *val);
+
+int32_t lsm6dso_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val);
+int32_t lsm6dso_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val);
+
+int32_t lsm6dso_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val);
+int32_t lsm6dso_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val);
+
+int32_t lsm6dso_mag_soft_iron_set(stmdev_ctx_t *ctx, int16_t *val);
+int32_t lsm6dso_mag_soft_iron_get(stmdev_ctx_t *ctx, int16_t *val);
+
+typedef enum
+{
+  LSM6DSO_Z_EQ_Y     = 0,
+  LSM6DSO_Z_EQ_MIN_Y = 1,
+  LSM6DSO_Z_EQ_X     = 2,
+  LSM6DSO_Z_EQ_MIN_X = 3,
+  LSM6DSO_Z_EQ_MIN_Z = 4,
+  LSM6DSO_Z_EQ_Z     = 5,
+} lsm6dso_mag_z_axis_t;
+int32_t lsm6dso_mag_z_orient_set(stmdev_ctx_t *ctx,
+                                 lsm6dso_mag_z_axis_t val);
+int32_t lsm6dso_mag_z_orient_get(stmdev_ctx_t *ctx,
+                                 lsm6dso_mag_z_axis_t *val);
+
+typedef enum
+{
+  LSM6DSO_Y_EQ_Y     = 0,
+  LSM6DSO_Y_EQ_MIN_Y = 1,
+  LSM6DSO_Y_EQ_X     = 2,
+  LSM6DSO_Y_EQ_MIN_X = 3,
+  LSM6DSO_Y_EQ_MIN_Z = 4,
+  LSM6DSO_Y_EQ_Z     = 5,
+} lsm6dso_mag_y_axis_t;
+int32_t lsm6dso_mag_y_orient_set(stmdev_ctx_t *ctx,
+                                 lsm6dso_mag_y_axis_t val);
+int32_t lsm6dso_mag_y_orient_get(stmdev_ctx_t *ctx,
+                                 lsm6dso_mag_y_axis_t *val);
+
+typedef enum
+{
+  LSM6DSO_X_EQ_Y     = 0,
+  LSM6DSO_X_EQ_MIN_Y = 1,
+  LSM6DSO_X_EQ_X     = 2,
+  LSM6DSO_X_EQ_MIN_X = 3,
+  LSM6DSO_X_EQ_MIN_Z = 4,
+  LSM6DSO_X_EQ_Z     = 5,
+} lsm6dso_mag_x_axis_t;
+int32_t lsm6dso_mag_x_orient_set(stmdev_ctx_t *ctx,
+                                 lsm6dso_mag_x_axis_t val);
+int32_t lsm6dso_mag_x_orient_get(stmdev_ctx_t *ctx,
+                                 lsm6dso_mag_x_axis_t *val);
+
+int32_t lsm6dso_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx,
+                                             uint8_t *val);
+
+typedef struct
+{
+  lsm6dso_fsm_enable_a_t          fsm_enable_a;
+  lsm6dso_fsm_enable_b_t          fsm_enable_b;
+} lsm6dso_emb_fsm_enable_t;
+int32_t lsm6dso_fsm_enable_set(stmdev_ctx_t *ctx,
+                               lsm6dso_emb_fsm_enable_t *val);
+int32_t lsm6dso_fsm_enable_get(stmdev_ctx_t *ctx,
+                               lsm6dso_emb_fsm_enable_t *val);
+
+int32_t lsm6dso_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val);
+int32_t lsm6dso_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val);
+
+typedef enum
+{
+  LSM6DSO_LC_NORMAL     = 0,
+  LSM6DSO_LC_CLEAR      = 1,
+  LSM6DSO_LC_CLEAR_DONE = 2,
+} lsm6dso_fsm_lc_clr_t;
+int32_t lsm6dso_long_clr_set(stmdev_ctx_t *ctx,
+                             lsm6dso_fsm_lc_clr_t val);
+int32_t lsm6dso_long_clr_get(stmdev_ctx_t *ctx,
+                             lsm6dso_fsm_lc_clr_t *val);
+
+typedef struct
+{
+  lsm6dso_fsm_outs1_t    fsm_outs1;
+  lsm6dso_fsm_outs2_t    fsm_outs2;
+  lsm6dso_fsm_outs3_t    fsm_outs3;
+  lsm6dso_fsm_outs4_t    fsm_outs4;
+  lsm6dso_fsm_outs5_t    fsm_outs5;
+  lsm6dso_fsm_outs6_t    fsm_outs6;
+  lsm6dso_fsm_outs7_t    fsm_outs7;
+  lsm6dso_fsm_outs8_t    fsm_outs8;
+  lsm6dso_fsm_outs9_t    fsm_outs9;
+  lsm6dso_fsm_outs10_t   fsm_outs10;
+  lsm6dso_fsm_outs11_t   fsm_outs11;
+  lsm6dso_fsm_outs12_t   fsm_outs12;
+  lsm6dso_fsm_outs13_t   fsm_outs13;
+  lsm6dso_fsm_outs14_t   fsm_outs14;
+  lsm6dso_fsm_outs15_t   fsm_outs15;
+  lsm6dso_fsm_outs16_t   fsm_outs16;
+} lsm6dso_fsm_out_t;
+int32_t lsm6dso_fsm_out_get(stmdev_ctx_t *ctx,
+                            lsm6dso_fsm_out_t *val);
+
+typedef enum
+{
+  LSM6DSO_ODR_FSM_12Hz5 = 0,
+  LSM6DSO_ODR_FSM_26Hz  = 1,
+  LSM6DSO_ODR_FSM_52Hz  = 2,
+  LSM6DSO_ODR_FSM_104Hz = 3,
+} lsm6dso_fsm_odr_t;
+int32_t lsm6dso_fsm_data_rate_set(stmdev_ctx_t *ctx,
+                                  lsm6dso_fsm_odr_t val);
+int32_t lsm6dso_fsm_data_rate_get(stmdev_ctx_t *ctx,
+                                  lsm6dso_fsm_odr_t *val);
+
+int32_t lsm6dso_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+int32_t lsm6dso_long_cnt_int_value_set(stmdev_ctx_t *ctx,
+                                       uint16_t val);
+int32_t lsm6dso_long_cnt_int_value_get(stmdev_ctx_t *ctx,
+                                       uint16_t *val);
+
+int32_t lsm6dso_fsm_number_of_programs_set(stmdev_ctx_t *ctx,
+                                           uint8_t val);
+int32_t lsm6dso_fsm_number_of_programs_get(stmdev_ctx_t *ctx,
+                                           uint8_t *val);
+
+int32_t lsm6dso_fsm_start_address_set(stmdev_ctx_t *ctx,
+                                      uint16_t val);
+int32_t lsm6dso_fsm_start_address_get(stmdev_ctx_t *ctx,
+                                      uint16_t *val);
+
+int32_t lsm6dso_sh_read_data_raw_get(stmdev_ctx_t *ctx, uint8_t *val,
+                                     uint8_t len);
+
+typedef enum
+{
+  LSM6DSO_SLV_0       = 0,
+  LSM6DSO_SLV_0_1     = 1,
+  LSM6DSO_SLV_0_1_2   = 2,
+  LSM6DSO_SLV_0_1_2_3 = 3,
+} lsm6dso_aux_sens_on_t;
+int32_t lsm6dso_sh_slave_connected_set(stmdev_ctx_t *ctx,
+                                       lsm6dso_aux_sens_on_t val);
+int32_t lsm6dso_sh_slave_connected_get(stmdev_ctx_t *ctx,
+                                       lsm6dso_aux_sens_on_t *val);
+
+int32_t lsm6dso_sh_master_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+typedef enum
+{
+  LSM6DSO_EXT_PULL_UP      = 0,
+  LSM6DSO_INTERNAL_PULL_UP = 1,
+} lsm6dso_shub_pu_en_t;
+int32_t lsm6dso_sh_pin_mode_set(stmdev_ctx_t *ctx,
+                                lsm6dso_shub_pu_en_t val);
+int32_t lsm6dso_sh_pin_mode_get(stmdev_ctx_t *ctx,
+                                lsm6dso_shub_pu_en_t *val);
+
+int32_t lsm6dso_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val);
+int32_t lsm6dso_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+typedef enum
+{
+  LSM6DSO_EXT_ON_INT2_PIN = 1,
+  LSM6DSO_XL_GY_DRDY      = 0,
+} lsm6dso_start_config_t;
+int32_t lsm6dso_sh_syncro_mode_set(stmdev_ctx_t *ctx,
+                                   lsm6dso_start_config_t val);
+int32_t lsm6dso_sh_syncro_mode_get(stmdev_ctx_t *ctx,
+                                   lsm6dso_start_config_t *val);
+
+typedef enum
+{
+  LSM6DSO_EACH_SH_CYCLE    = 0,
+  LSM6DSO_ONLY_FIRST_CYCLE = 1,
+} lsm6dso_write_once_t;
+int32_t lsm6dso_sh_write_mode_set(stmdev_ctx_t *ctx,
+                                  lsm6dso_write_once_t val);
+int32_t lsm6dso_sh_write_mode_get(stmdev_ctx_t *ctx,
+                                  lsm6dso_write_once_t *val);
+
+int32_t lsm6dso_sh_reset_set(stmdev_ctx_t *ctx);
+int32_t lsm6dso_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
+
+typedef enum
+{
+  LSM6DSO_SH_ODR_104Hz = 0,
+  LSM6DSO_SH_ODR_52Hz  = 1,
+  LSM6DSO_SH_ODR_26Hz  = 2,
+  LSM6DSO_SH_ODR_13Hz  = 3,
+} lsm6dso_shub_odr_t;
+int32_t lsm6dso_sh_data_rate_set(stmdev_ctx_t *ctx,
+                                 lsm6dso_shub_odr_t val);
+int32_t lsm6dso_sh_data_rate_get(stmdev_ctx_t *ctx,
+                                 lsm6dso_shub_odr_t *val);
+
+typedef struct
+{
+  uint8_t   slv0_add;
+  uint8_t   slv0_subadd;
+  uint8_t   slv0_data;
+} lsm6dso_sh_cfg_write_t;
+int32_t lsm6dso_sh_cfg_write(stmdev_ctx_t *ctx,
+                             lsm6dso_sh_cfg_write_t *val);
+
+typedef struct
+{
+  uint8_t   slv_add;
+  uint8_t   slv_subadd;
+  uint8_t   slv_len;
+} lsm6dso_sh_cfg_read_t;
+int32_t lsm6dso_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
+                                 lsm6dso_sh_cfg_read_t *val);
+int32_t lsm6dso_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
+                                 lsm6dso_sh_cfg_read_t *val);
+int32_t lsm6dso_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
+                                 lsm6dso_sh_cfg_read_t *val);
+int32_t lsm6dso_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
+                                 lsm6dso_sh_cfg_read_t *val);
+
+int32_t lsm6dso_sh_status_get(stmdev_ctx_t *ctx,
+                              lsm6dso_status_master_t *val);
+
+
+typedef struct
+{
+  uint8_t ui;
+  uint8_t aux;
+} lsm6dso_id_t;
+int32_t lsm6dso_id_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
+                       lsm6dso_id_t *val);
+
+typedef enum
+{
+  LSM6DSO_SEL_BY_HW   = 0x00, /* bus mode select by HW (SPI 3W disable) */
+  LSM6DSO_SPI_4W      = 0x06, /* Only SPI: SDO / SDI separated pins */
+  LSM6DSO_SPI_3W      = 0x07, /* Only SPI: SDO / SDI share the same pin */
+  LSM6DSO_I2C         = 0x04, /* Only I2C */
+  LSM6DSO_I3C_T_50us  = 0x02, /* I3C: available time equal to 50 us */
+  LSM6DSO_I3C_T_2us   = 0x12, /* I3C: available time equal to 2 us */
+  LSM6DSO_I3C_T_1ms   = 0x22, /* I3C: available time equal to 1 ms */
+  LSM6DSO_I3C_T_25ms  = 0x32, /* I3C: available time equal to 25 ms */
+} lsm6dso_ui_bus_md_t;
+
+typedef enum
+{
+  LSM6DSO_SPI_4W_AUX  = 0x00,
+  LSM6DSO_SPI_3W_AUX  = 0x01,
+} lsm6dso_aux_bus_md_t;
+
+typedef struct
+{
+  lsm6dso_ui_bus_md_t ui_bus_md;
+  lsm6dso_aux_bus_md_t aux_bus_md;
+} lsm6dso_bus_mode_t;
+int32_t lsm6dso_bus_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
+                             lsm6dso_bus_mode_t val);
+int32_t lsm6dso_bus_mode_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
+                             lsm6dso_bus_mode_t *val);
+
+typedef enum
+{
+  LSM6DSO_DRV_RDY   = 0x00, /* Initialize the device for driver usage */
+  LSM6DSO_BOOT      = 0x01, /* Restore calib. param. ( it takes 10ms ) */
+  LSM6DSO_RESET     = 0x02, /* Reset configuration registers */
+  LSM6DSO_FIFO_COMP = 0x04, /* FIFO compression initialization request. */
+  LSM6DSO_FSM       = 0x08, /* Finite State Machine initialization request */
+  LSM6DSO_PEDO      = 0x20, /* Pedometer algo initialization request. */
+  LSM6DSO_TILT      = 0x40, /* Tilt algo initialization request */
+  LSM6DSO_SMOTION   = 0x80, /* Significant Motion initialization request */
+} lsm6dso_init_t;
+int32_t lsm6dso_init_set(stmdev_ctx_t *ctx, lsm6dso_init_t val);
+
+typedef struct
+{
+uint8_t sw_reset           :
+  1; /* Restoring configuration registers */
+  uint8_t boot               : 1; /* Restoring calibration parameters */
+  uint8_t drdy_xl            : 1; /* Accelerometer data ready */
+  uint8_t drdy_g             : 1; /* Gyroscope data ready */
+  uint8_t drdy_temp          : 1; /* Temperature data ready */
+  uint8_t ois_drdy_xl        : 1; /* Accelerometer data ready on OIS */
+  uint8_t ois_drdy_g         : 1; /* Gyroscope data ready on OIS */
+uint8_t ois_gyro_settling  :
+  1; /* Gyroscope is in the settling phase */
+} lsm6dso_status_t;
+int32_t lsm6dso_status_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
+                           lsm6dso_status_t *val);
+
+typedef struct
+{
+  uint8_t sdo_sa0_pull_up     : 1; /* 1 = pull-up on SDO/SA0 pin */
+uint8_t aux_sdo_ocs_pull_up :
+  1; /* 1 = pull-up on OCS_Aux/SDO_Aux pins */
+  uint8_t int1_int2_push_pull : 1; /* 1 = push-pull / 0 = open-drain*/
+uint8_t int1_pull_down      :
+  1; /* 1 = pull-down always disabled (0=auto) */
+} lsm6dso_pin_conf_t;
+int32_t lsm6dso_pin_conf_set(stmdev_ctx_t *ctx,
+                             lsm6dso_pin_conf_t val);
+int32_t lsm6dso_pin_conf_get(stmdev_ctx_t *ctx,
+                             lsm6dso_pin_conf_t *val);
+
+typedef struct
+{
+  uint8_t active_low   : 1; /* 1 = active low / 0 = active high */
+uint8_t base_latched :
+  1; /* base functions are: FF, WU, 6D, Tap, Act/Inac */
+uint8_t emb_latched  :
+  1; /* emb functions are: Pedo, Tilt, SMot, Timestamp */
+} lsm6dso_int_mode_t;
+int32_t lsm6dso_interrupt_mode_set(stmdev_ctx_t *ctx,
+                                   lsm6dso_int_mode_t val);
+int32_t lsm6dso_interrupt_mode_get(stmdev_ctx_t *ctx,
+                                   lsm6dso_int_mode_t *val);
+
+typedef struct
+{
+  uint8_t drdy_xl       : 1; /* Accelerometer data ready */
+  uint8_t drdy_g        : 1; /* Gyroscope data ready */
+uint8_t drdy_temp     :
+  1; /* Temperature data ready (1 = int2 pin disable) */
+  uint8_t boot          : 1; /* Restoring calibration parameters */
+  uint8_t fifo_th       : 1; /* FIFO threshold reached */
+  uint8_t fifo_ovr      : 1; /* FIFO overrun */
+  uint8_t fifo_full     : 1; /* FIFO full */
+  uint8_t fifo_bdr      : 1; /* FIFO Batch counter threshold reached */
+uint8_t den_flag      :
+  1; /* external trigger level recognition (DEN) */
+  uint8_t sh_endop      : 1; /* sensor hub end operation */
+uint8_t timestamp     :
+  1; /* timestamp overflow (1 = int2 pin disable) */
+  uint8_t six_d         : 1; /* orientation change (6D/4D detection) */
+  uint8_t double_tap    : 1; /* double-tap event */
+  uint8_t free_fall     : 1; /* free fall event */
+  uint8_t wake_up       : 1; /* wake up event */
+  uint8_t single_tap    : 1; /* single-tap event */
+uint8_t sleep_change  :
+  1; /* Act/Inact (or Vice-versa) status changed */
+  uint8_t step_detector : 1; /* Step detected */
+  uint8_t tilt          : 1; /* Relative tilt event detected */
+  uint8_t sig_mot       : 1; /* "significant motion" event detected */
+uint8_t fsm_lc        :
+  1; /* fsm long counter timeout interrupt event */
+  uint8_t fsm1          : 1; /* fsm 1 interrupt event */
+  uint8_t fsm2          : 1; /* fsm 2 interrupt event */
+  uint8_t fsm3          : 1; /* fsm 3 interrupt event */
+  uint8_t fsm4          : 1; /* fsm 4 interrupt event */
+  uint8_t fsm5          : 1; /* fsm 5 interrupt event */
+  uint8_t fsm6          : 1; /* fsm 6 interrupt event */
+  uint8_t fsm7          : 1; /* fsm 7 interrupt event */
+  uint8_t fsm8          : 1; /* fsm 8 interrupt event */
+  uint8_t fsm9          : 1; /* fsm 9 interrupt event */
+  uint8_t fsm10         : 1; /* fsm 10 interrupt event */
+  uint8_t fsm11         : 1; /* fsm 11 interrupt event */
+  uint8_t fsm12         : 1; /* fsm 12 interrupt event */
+  uint8_t fsm13         : 1; /* fsm 13 interrupt event */
+  uint8_t fsm14         : 1; /* fsm 14 interrupt event */
+  uint8_t fsm15         : 1; /* fsm 15 interrupt event */
+  uint8_t fsm16         : 1; /* fsm 16 interrupt event */
+  uint8_t mlc1          : 1; /* mlc 1 interrupt event */
+  uint8_t mlc2          : 1; /* mlc 2 interrupt event */
+  uint8_t mlc3          : 1; /* mlc 3 interrupt event */
+  uint8_t mlc4          : 1; /* mlc 4 interrupt event */
+  uint8_t mlc5          : 1; /* mlc 5 interrupt event */
+  uint8_t mlc6          : 1; /* mlc 6 interrupt event */
+  uint8_t mlc7          : 1; /* mlc 7 interrupt event */
+  uint8_t mlc8          : 1; /* mlc 8 interrupt event */
+} lsm6dso_pin_int1_route_t;
+
+int32_t lsm6dso_pin_int1_route_set(stmdev_ctx_t *ctx,
+                                   lsm6dso_pin_int1_route_t val);
+int32_t lsm6dso_pin_int1_route_get(stmdev_ctx_t *ctx,
+                                   lsm6dso_pin_int1_route_t *val);
+
+typedef struct
+{
+  uint8_t drdy_ois      : 1; /* OIS chain data ready */
+  uint8_t drdy_xl       : 1; /* Accelerometer data ready */
+  uint8_t drdy_g        : 1; /* Gyroscope data ready */
+  uint8_t drdy_temp     : 1; /* Temperature data ready */
+  uint8_t fifo_th       : 1; /* FIFO threshold reached */
+  uint8_t fifo_ovr      : 1; /* FIFO overrun */
+  uint8_t fifo_full     : 1; /* FIFO full */
+  uint8_t fifo_bdr      : 1; /* FIFO Batch counter threshold reached */
+  uint8_t timestamp     : 1; /* timestamp overflow */
+  uint8_t six_d         : 1; /* orientation change (6D/4D detection) */
+  uint8_t double_tap    : 1; /* double-tap event */
+  uint8_t free_fall     : 1; /* free fall event */
+  uint8_t wake_up       : 1; /* wake up event */
+  uint8_t single_tap    : 1; /* single-tap event */
+uint8_t sleep_change  :
+  1; /* Act/Inact (or Vice-versa) status changed */
+  uint8_t step_detector : 1; /* Step detected */
+  uint8_t tilt          : 1; /* Relative tilt event detected */
+  uint8_t sig_mot       : 1; /* "significant motion" event detected */
+uint8_t fsm_lc        :
+  1; /* fsm long counter timeout interrupt event */
+  uint8_t fsm1          : 1; /* fsm 1 interrupt event */
+  uint8_t fsm2          : 1; /* fsm 2 interrupt event */
+  uint8_t fsm3          : 1; /* fsm 3 interrupt event */
+  uint8_t fsm4          : 1; /* fsm 4 interrupt event */
+  uint8_t fsm5          : 1; /* fsm 5 interrupt event */
+  uint8_t fsm6          : 1; /* fsm 6 interrupt event */
+  uint8_t fsm7          : 1; /* fsm 7 interrupt event */
+  uint8_t fsm8          : 1; /* fsm 8 interrupt event */
+  uint8_t fsm9          : 1; /* fsm 9 interrupt event */
+  uint8_t fsm10         : 1; /* fsm 10 interrupt event */
+  uint8_t fsm11         : 1; /* fsm 11 interrupt event */
+  uint8_t fsm12         : 1; /* fsm 12 interrupt event */
+  uint8_t fsm13         : 1; /* fsm 13 interrupt event */
+  uint8_t fsm14         : 1; /* fsm 14 interrupt event */
+  uint8_t fsm15         : 1; /* fsm 15 interrupt event */
+  uint8_t fsm16         : 1; /* fsm 16 interrupt event */
+  uint8_t mlc1          : 1; /* mlc 1 interrupt event */
+  uint8_t mlc2          : 1; /* mlc 2 interrupt event */
+  uint8_t mlc3          : 1; /* mlc 3 interrupt event */
+  uint8_t mlc4          : 1; /* mlc 4 interrupt event */
+  uint8_t mlc5          : 1; /* mlc 5 interrupt event */
+  uint8_t mlc6          : 1; /* mlc 6 interrupt event */
+  uint8_t mlc7          : 1; /* mlc 7 interrupt event */
+  uint8_t mlc8          : 1; /* mlc 8 interrupt event */
+} lsm6dso_pin_int2_route_t;
+
+int32_t lsm6dso_pin_int2_route_set(stmdev_ctx_t *ctx,
+                                   stmdev_ctx_t *aux_ctx,
+                                   lsm6dso_pin_int2_route_t val);
+int32_t lsm6dso_pin_int2_route_get(stmdev_ctx_t *ctx,
+                                   stmdev_ctx_t *aux_ctx,
+                                   lsm6dso_pin_int2_route_t *val);
+
+typedef struct
+{
+  uint8_t drdy_xl          :  1; /* Accelerometer data ready */
+  uint8_t drdy_g           :  1; /* Gyroscope data ready */
+  uint8_t drdy_temp        :  1; /* Temperature data ready */
+uint8_t den_flag         :
+  1; /* external trigger level recognition (DEN) */
+uint8_t timestamp        :
+  1; /* timestamp overflow (1 = int2 pin disable) */
+  uint8_t free_fall        :  1; /* free fall event */
+  uint8_t wake_up          :  1; /* wake up event */
+  uint8_t wake_up_z        :  1; /* wake up on Z axis event */
+  uint8_t wake_up_y        :  1; /* wake up on Y axis event */
+  uint8_t wake_up_x        :  1; /* wake up on X axis event */
+  uint8_t single_tap       :  1; /* single-tap event */
+  uint8_t double_tap       :  1; /* double-tap event */
+  uint8_t tap_z            :  1; /* single-tap on Z axis event */
+  uint8_t tap_y            :  1; /* single-tap on Y axis event */
+  uint8_t tap_x            :  1; /* single-tap on X axis event */
+  uint8_t tap_sign         :  1; /* sign of tap event (0-pos / 1-neg) */
+uint8_t six_d            :
+  1; /* orientation change (6D/4D detection) */
+uint8_t six_d_xl         :
+  1; /* X-axis low 6D/4D event (under threshold) */
+uint8_t six_d_xh         :
+  1; /* X-axis high 6D/4D event (over threshold) */
+uint8_t six_d_yl         :
+  1; /* Y-axis low 6D/4D event (under threshold) */
+uint8_t six_d_yh         :
+  1; /* Y-axis high 6D/4D event (over threshold) */
+uint8_t six_d_zl         :
+  1; /* Z-axis low 6D/4D event (under threshold) */
+uint8_t six_d_zh         :
+  1; /* Z-axis high 6D/4D event (over threshold) */
+uint8_t sleep_change     :
+  1; /* Act/Inact (or Vice-versa) status changed */
+uint8_t sleep_state      :
+  1; /* Act/Inact status flag (0-Act / 1-Inact) */
+  uint8_t step_detector    :  1; /* Step detected */
+  uint8_t tilt             :  1; /* Relative tilt event detected */
+uint8_t sig_mot          :
+  1; /* "significant motion" event detected */
+uint8_t fsm_lc           :
+  1; /* fsm long counter timeout interrupt event */
+  uint8_t fsm1             :  1; /* fsm 1 interrupt event */
+  uint8_t fsm2             :  1; /* fsm 2 interrupt event */
+  uint8_t fsm3             :  1; /* fsm 3 interrupt event */
+  uint8_t fsm4             :  1; /* fsm 4 interrupt event */
+  uint8_t fsm5             :  1; /* fsm 5 interrupt event */
+  uint8_t fsm6             :  1; /* fsm 6 interrupt event */
+  uint8_t fsm7             :  1; /* fsm 7 interrupt event */
+  uint8_t fsm8             :  1; /* fsm 8 interrupt event */
+  uint8_t fsm9             :  1; /* fsm 9 interrupt event */
+  uint8_t fsm10            :  1; /* fsm 10 interrupt event */
+  uint8_t fsm11            :  1; /* fsm 11 interrupt event */
+  uint8_t fsm12            :  1; /* fsm 12 interrupt event */
+  uint8_t fsm13            :  1; /* fsm 13 interrupt event */
+  uint8_t fsm14            :  1; /* fsm 14 interrupt event */
+  uint8_t fsm15            :  1; /* fsm 15 interrupt event */
+  uint8_t fsm16            :  1; /* fsm 16 interrupt event */
+  uint8_t mlc1             :  1; /* mlc 1 interrupt event */
+  uint8_t mlc2             :  1; /* mlc 2 interrupt event */
+  uint8_t mlc3             :  1; /* mlc 3 interrupt event */
+  uint8_t mlc4             :  1; /* mlc 4 interrupt event */
+  uint8_t mlc5             :  1; /* mlc 5 interrupt event */
+  uint8_t mlc6             :  1; /* mlc 6 interrupt event */
+  uint8_t mlc7             :  1; /* mlc 7 interrupt event */
+  uint8_t mlc8             :  1; /* mlc 8 interrupt event */
+  uint8_t sh_endop         :  1; /* sensor hub end operation */
+uint8_t sh_slave0_nack   :
+  1; /* Not acknowledge on sensor hub slave 0 */
+uint8_t sh_slave1_nack   :
+  1; /* Not acknowledge on sensor hub slave 1 */
+uint8_t sh_slave2_nack   :
+  1; /* Not acknowledge on sensor hub slave 2 */
+uint8_t sh_slave3_nack   :
+  1; /* Not acknowledge on sensor hub slave 3 */
+uint8_t sh_wr_once       :
+  1; /* "WRITE_ONCE" end on sensor hub slave 0 */
+uint16_t fifo_diff       :
+  10; /* Number of unread sensor data in FIFO*/
+  uint8_t fifo_ovr_latched :  1; /* Latched FIFO overrun status */
+uint8_t fifo_bdr         :
+  1; /* FIFO Batch counter threshold reached */
+  uint8_t fifo_full        :  1; /* FIFO full */
+  uint8_t fifo_ovr         :  1; /* FIFO overrun */
+  uint8_t fifo_th          :  1; /* FIFO threshold reached */
+} lsm6dso_all_sources_t;
+int32_t lsm6dso_all_sources_get(stmdev_ctx_t *ctx,
+                                lsm6dso_all_sources_t *val);
+
+typedef struct
+{
+  uint8_t odr_fine_tune;
+} dev_cal_t;
+int32_t lsm6dso_calibration_get(stmdev_ctx_t *ctx, dev_cal_t *val);
+
+typedef enum
+{
+  LSM6DSO_XL_UI_OFF       = 0x00, /* in power down */
+  LSM6DSO_XL_UI_1Hz6_LP   = 0x1B, /* @1Hz6 (low power) */
+  LSM6DSO_XL_UI_1Hz6_ULP  = 0x2B, /* @1Hz6 (ultra low/Gy, OIS imu off) */
+  LSM6DSO_XL_UI_12Hz5_HP  = 0x01, /* @12Hz5 (high performance) */
+  LSM6DSO_XL_UI_12Hz5_LP  = 0x11, /* @12Hz5 (low power) */
+  LSM6DSO_XL_UI_12Hz5_ULP = 0x21, /* @12Hz5 (ultra low/Gy, OIS imu off) */
+  LSM6DSO_XL_UI_26Hz_HP   = 0x02, /* @26Hz  (high performance) */
+  LSM6DSO_XL_UI_26Hz_LP   = 0x12, /* @26Hz  (low power) */
+  LSM6DSO_XL_UI_26Hz_ULP  = 0x22, /* @26Hz  (ultra low/Gy, OIS imu off) */
+  LSM6DSO_XL_UI_52Hz_HP   = 0x03, /* @52Hz  (high performance) */
+  LSM6DSO_XL_UI_52Hz_LP   = 0x13, /* @52Hz  (low power) */
+  LSM6DSO_XL_UI_52Hz_ULP  = 0x23, /* @52Hz  (ultra low/Gy, OIS imu off) */
+  LSM6DSO_XL_UI_104Hz_HP  = 0x04, /* @104Hz (high performance) */
+  LSM6DSO_XL_UI_104Hz_NM  = 0x14, /* @104Hz (normal mode) */
+  LSM6DSO_XL_UI_104Hz_ULP = 0x24, /* @104Hz (ultra low/Gy, OIS imu off) */
+  LSM6DSO_XL_UI_208Hz_HP  = 0x05, /* @208Hz (high performance) */
+  LSM6DSO_XL_UI_208Hz_NM  = 0x15, /* @208Hz (normal mode) */
+  LSM6DSO_XL_UI_208Hz_ULP = 0x25, /* @208Hz (ultra low/Gy, OIS imu off) */
+  LSM6DSO_XL_UI_416Hz_HP  = 0x06, /* @416Hz (high performance) */
+  LSM6DSO_XL_UI_833Hz_HP  = 0x07, /* @833Hz (high performance) */
+  LSM6DSO_XL_UI_1667Hz_HP = 0x08, /* @1kHz66 (high performance) */
+  LSM6DSO_XL_UI_3333Hz_HP = 0x09, /* @3kHz33 (high performance) */
+  LSM6DSO_XL_UI_6667Hz_HP = 0x0A, /* @6kHz66 (high performance) */
+} lsm6dso_odr_xl_ui_t;
+
+typedef enum
+{
+  LSM6DSO_XL_UI_2g   = 0,
+  LSM6DSO_XL_UI_4g   = 2,
+  LSM6DSO_XL_UI_8g   = 3,
+  LSM6DSO_XL_UI_16g  = 1, /* OIS full scale is also forced to be 16g */
+} lsm6dso_fs_xl_ui_t;
+
+typedef enum
+{
+  LSM6DSO_GY_UI_OFF       = 0x00, /* gy in power down */
+  LSM6DSO_GY_UI_12Hz5_LP  = 0x11, /* gy @12Hz5 (low power) */
+  LSM6DSO_GY_UI_12Hz5_HP  = 0x01, /* gy @12Hz5 (high performance) */
+  LSM6DSO_GY_UI_26Hz_LP   = 0x12, /* gy @26Hz  (low power) */
+  LSM6DSO_GY_UI_26Hz_HP   = 0x02, /* gy @26Hz  (high performance) */
+  LSM6DSO_GY_UI_52Hz_LP   = 0x13, /* gy @52Hz  (low power) */
+  LSM6DSO_GY_UI_52Hz_HP   = 0x03, /* gy @52Hz  (high performance) */
+  LSM6DSO_GY_UI_104Hz_NM  = 0x14, /* gy @104Hz (low power) */
+  LSM6DSO_GY_UI_104Hz_HP  = 0x04, /* gy @104Hz (high performance) */
+  LSM6DSO_GY_UI_208Hz_NM  = 0x15, /* gy @208Hz (low power) */
+  LSM6DSO_GY_UI_208Hz_HP  = 0x05, /* gy @208Hz (high performance) */
+  LSM6DSO_GY_UI_416Hz_HP  = 0x06, /* gy @416Hz (high performance) */
+  LSM6DSO_GY_UI_833Hz_HP  = 0x07, /* gy @833Hz (high performance) */
+  LSM6DSO_GY_UI_1667Hz_HP = 0x08, /* gy @1kHz66 (high performance) */
+  LSM6DSO_GY_UI_3333Hz_HP = 0x09, /* gy @3kHz33 (high performance) */
+  LSM6DSO_GY_UI_6667Hz_HP = 0x0A, /* gy @6kHz66 (high performance) */
+} lsm6dso_odr_g_ui_t;
+
+typedef enum
+{
+  LSM6DSO_GY_UI_250dps   = 0,
+  LSM6DSO_GY_UI_125dps   = 1,
+  LSM6DSO_GY_UI_500dps   = 2,
+  LSM6DSO_GY_UI_1000dps  = 4,
+  LSM6DSO_GY_UI_2000dps  = 6,
+} lsm6dso_fs_g_ui_t;
+
+typedef enum
+{
+  LSM6DSO_OIS_ONLY_AUX    = 0x00, /* Auxiliary SPI full control */
+  LSM6DSO_OIS_MIXED       = 0x01, /* Enabling by UI / read-config by AUX */
+} lsm6dso_ctrl_md_t;
+
+typedef enum
+{
+  LSM6DSO_XL_OIS_OFF       = 0x00, /* in power down */
+  LSM6DSO_XL_OIS_6667Hz_HP = 0x01, /* @6kHz OIS imu active/NO ULP on UI */
+} lsm6dso_odr_xl_ois_noaux_t;
+
+typedef enum
+{
+  LSM6DSO_XL_OIS_2g   = 0,
+  LSM6DSO_XL_OIS_4g   = 2,
+  LSM6DSO_XL_OIS_8g   = 3,
+  LSM6DSO_XL_OIS_16g  = 1, /* UI full scale is also forced to be 16g */
+} lsm6dso_fs_xl_ois_noaux_t;
+
+typedef enum
+{
+  LSM6DSO_GY_OIS_OFF       = 0x00, /* in power down */
+  LSM6DSO_GY_OIS_6667Hz_HP = 0x01, /* @6kHz No Ultra Low Power*/
+} lsm6dso_odr_g_ois_noaux_t;
+
+typedef enum
+{
+  LSM6DSO_GY_OIS_250dps   = 0,
+  LSM6DSO_GY_OIS_125dps   = 1,
+  LSM6DSO_GY_OIS_500dps   = 2,
+  LSM6DSO_GY_OIS_1000dps  = 4,
+  LSM6DSO_GY_OIS_2000dps  = 6,
+} lsm6dso_fs_g_ois_noaux_t;
+
+typedef enum
+{
+  LSM6DSO_FSM_DISABLE = 0x00,
+  LSM6DSO_FSM_XL      = 0x01,
+  LSM6DSO_FSM_GY      = 0x02,
+  LSM6DSO_FSM_XL_GY   = 0x03,
+} lsm6dso_sens_fsm_t;
+
+typedef enum
+{
+  LSM6DSO_FSM_12Hz5 = 0x00,
+  LSM6DSO_FSM_26Hz  = 0x01,
+  LSM6DSO_FSM_52Hz  = 0x02,
+  LSM6DSO_FSM_104Hz = 0x03,
+} lsm6dso_odr_fsm_t;
+
+typedef struct
+{
+  struct
+  {
+    struct
+    {
+      lsm6dso_odr_xl_ui_t odr;
+      lsm6dso_fs_xl_ui_t fs;
+    } xl;
+    struct
+    {
+      lsm6dso_odr_g_ui_t odr;
+      lsm6dso_fs_g_ui_t fs;
+    } gy;
+  } ui;
+  struct
+  {
+    lsm6dso_ctrl_md_t ctrl_md;
+    struct
+    {
+      lsm6dso_odr_xl_ois_noaux_t odr;
+      lsm6dso_fs_xl_ois_noaux_t fs;
+    } xl;
+    struct
+    {
+      lsm6dso_odr_g_ois_noaux_t odr;
+      lsm6dso_fs_g_ois_noaux_t fs;
+    } gy;
+  } ois;
+  struct
+  {
+    lsm6dso_sens_fsm_t sens;
+    lsm6dso_odr_fsm_t odr;
+  } fsm;
+} lsm6dso_md_t;
+int32_t lsm6dso_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
+                         lsm6dso_md_t *val);
+int32_t lsm6dso_mode_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
+                         lsm6dso_md_t *val);
+typedef struct
+{
+  struct
+  {
+    struct
+    {
+      float_t mg[3];
+      int16_t raw[3];
+    } xl;
+    struct
+    {
+      float_t mdps[3];
+      int16_t raw[3];
+    } gy;
+    struct
+    {
+      float_t deg_c;
+      int16_t raw;
+    } heat;
+  } ui;
+  struct
+  {
+    struct
+    {
+      float_t mg[3];
+      int16_t raw[3];
+    } xl;
+    struct
+    {
+      float_t mdps[3];
+      int16_t raw[3];
+    } gy;
+  } ois;
+} lsm6dso_data_t;
+int32_t lsm6dso_data_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
+                         lsm6dso_md_t *md, lsm6dso_data_t *data);
+
+typedef struct
+{
+  uint8_t sig_mot      : 1; /* significant motion */
+  uint8_t tilt         : 1; /* tilt detection  */
+  uint8_t step         : 1; /* step counter/detector */
+  uint8_t step_adv     : 1; /* step counter advanced mode */
+  uint8_t fsm          : 1; /* finite state machine */
+  uint8_t fifo_compr   : 1; /* FIFO compression */
+} lsm6dso_emb_sens_t;
+int32_t lsm6dso_embedded_sens_set(stmdev_ctx_t *ctx,
+                                  lsm6dso_emb_sens_t *emb_sens);
+int32_t lsm6dso_embedded_sens_get(stmdev_ctx_t *ctx,
+                                  lsm6dso_emb_sens_t *emb_sens);
+int32_t lsm6dso_embedded_sens_off(stmdev_ctx_t *ctx);
+
+/**
+  * @}
+  *
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*LSM6DSO_DRIVER_H */