wb.cmake 1.1 KB

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  1. set(STM32_WB_TYPES
  2. WB55xx WB55xx WB35xx WB15xx WB50xx WB30xx WB10xx WB5Mxx
  3. )
  4. set(STM32_WB_TYPE_MATCH
  5. "WB55.C" "WB55.[EGY]" "WB35.." "WB15.." "WB50.." "WB30.." "WB10.." "WB5M.."
  6. )
  7. # this is not full RAM of the chip but only the part allocated to M4 core (SRAM1 in datasheet)
  8. set(STM32_WB_RAM_SIZES
  9. 64K 192K 32K 12K 64K 32K 12K 192K
  10. )
  11. # WB series need special area for SRAM2 shared with core M0PLUS
  12. set(STM32_WB_RAM_SHARE_SIZES
  13. 10K 10K 10K 10K 10K 10K 10K 10K
  14. )
  15. set(STM32_WB_CCRAM_SIZES
  16. 0K 0K 0K 0K 0K 0K 0K 0K
  17. )
  18. stm32_util_create_family_targets(WB M4)
  19. target_compile_options(STM32::WB::M4 INTERFACE
  20. -mcpu=cortex-m4 -mfpu=fpv5-sp-d16 -mfloat-abi=hard
  21. )
  22. target_link_options(STM32::WB::M4 INTERFACE
  23. -mcpu=cortex-m4 -mfpu=fpv5-sp-d16 -mfloat-abi=hard
  24. )
  25. function(stm32wb_get_memory_info DEVICE TYPE CORE RAM RAM_ORIGIN TWO_FLASH_BANKS)
  26. set(${TWO_FLASH_BANKS} TRUE PARENT_SCOPE)
  27. list(FIND STM32_WB_TYPES ${TYPE} TYPE_INDEX)
  28. list(GET STM32_WB_RAM_SIZES ${TYPE_INDEX} RAM_VALUE)
  29. set(${RAM} "${RAM_VALUE}-4" PARENT_SCOPE)
  30. set(${RAM_ORIGIN} 0x20000004 PARENT_SCOPE)
  31. endfunction()