wb.cmake 1.5 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667
  1. set(STM32_WB_TYPES
  2. WB55xx WB55xx WB35xx WB15xx WB50xx WB30xx WB10xx WB5Mxx
  3. )
  4. set(STM32_WB_TYPE_MATCH
  5. "WB55.C" "WB55.[EGY]" "WB35.." "WB15.." "WB50.." "WB30.." "WB10.." "WB5M.."
  6. )
  7. # this is not full RAM of the chip but only the part allocated to M4 core (SRAM1 in datasheet)
  8. set(STM32_WB_RAM_SIZES
  9. 64K 192K 32K 12K 64K 32K 12K 192K
  10. )
  11. # WB series need special area for SRAM2 shared with core M0PLUS
  12. set(STM32_WB_RAM_SHARE_SIZES
  13. 10K 10K 10K 10K 10K 10K 10K 10K
  14. )
  15. set(STM32_WB_CCRAM_SIZES
  16. 0K 0K 0K 0K 0K 0K 0K 0K
  17. )
  18. stm32_util_create_family_targets(WB M4)
  19. target_compile_options(STM32::WB::M4 INTERFACE
  20. -mcpu=cortex-m4 -mfpu=fpv5-sp-d16 -mfloat-abi=hard
  21. )
  22. target_link_options(STM32::WB::M4 INTERFACE
  23. -mcpu=cortex-m4 -mfpu=fpv5-sp-d16 -mfloat-abi=hard
  24. )
  25. function(stm32wb_get_memory_info DEVICE TYPE CORE RAM RAM_ORIGIN TWO_FLASH_BANKS)
  26. set(${TWO_FLASH_BANKS} TRUE PARENT_SCOPE)
  27. list(FIND STM32_WB_TYPES ${TYPE} TYPE_INDEX)
  28. list(GET STM32_WB_RAM_SIZES ${TYPE_INDEX} RAM_VALUE)
  29. set(${RAM} "${RAM_VALUE}-4" PARENT_SCOPE)
  30. set(${RAM_ORIGIN} 0x20000004 PARENT_SCOPE)
  31. endfunction()
  32. list(APPEND STM32_ALL_DEVICES
  33. WB5MMG
  34. WB50CG
  35. WB30CE
  36. WB10CC
  37. WB55CC
  38. WB55CE
  39. WB55CG
  40. WB55RC
  41. WB55RE
  42. WB55RG
  43. WB55VC
  44. WB55VE
  45. WB55VG
  46. WB55VY
  47. WB15CC
  48. WB35CC
  49. WB35CE
  50. )
  51. list(APPEND STM32_SUPPORTED_FAMILIES_LONG_NAME
  52. STM32WB_M4
  53. )
  54. list(APPEND STM32_FETCH_FAMILIES WB)
  55. set(CUBE_WB_VERSION v1.12.0)
  56. set(CMSIS_WB_VERSION v1.9.0)
  57. set(HAL_WB_VERSION v1.9.0)