api-hal-subghz.c 18 KB

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  1. #include "api-hal-subghz.h"
  2. #include <api-hal-gpio.h>
  3. #include <api-hal-spi.h>
  4. #include <api-hal-interrupt.h>
  5. #include <api-hal-resources.h>
  6. #include <furi.h>
  7. #include <cc1101.h>
  8. #include <stdio.h>
  9. static volatile SubGhzState api_hal_subghz_state = SubGhzStateInit;
  10. static const uint8_t api_hal_subghz_preset_ook_async_regs[][2] = {
  11. // https://e2e.ti.com/support/wireless-connectivity/sub-1-ghz-group/sub-1-ghz/f/sub-1-ghz-forum/382066/cc1101---don-t-know-the-correct-registers-configuration
  12. /* GPIO GD0 */
  13. { CC1101_IOCFG0, 0x0D }, // GD0 as async serial data output/input
  14. /* FIFO and internals */
  15. { CC1101_FIFOTHR, 0x47 }, // The only important bit is ADC_RETENTION
  16. /* Packet engine */
  17. { CC1101_PKTCTRL0, 0x32 }, // Async, continious, no whitening
  18. /* Frequency Synthesizer Control */
  19. { CC1101_FSCTRL1, 0x06 }, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
  20. // Modem Configuration
  21. { CC1101_MDMCFG0, 0x00 }, // Channel spacing is 25kHz
  22. { CC1101_MDMCFG1, 0x00 }, // Channel spacing is 25kHz
  23. { CC1101_MDMCFG2, 0x30 }, // Format ASK/OOK, No preamble/sync
  24. { CC1101_MDMCFG3, 0x32 }, // Data rate is 3.79372 kBaud
  25. { CC1101_MDMCFG4, 0x67 }, // Rx BW filter is 270.833333kHz
  26. /* Main Radio Control State Machine */
  27. { CC1101_MCSM0, 0x18 }, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
  28. /* Frequency Offset Compensation Configuration */
  29. { CC1101_FOCCFG, 0x18 }, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
  30. /* Automatic Gain Control */
  31. { CC1101_AGCTRL1, 0x00 }, // LNA 2 gain is decreased to minimum before decreasing LNA gain
  32. { CC1101_AGCTRL2, 0x07 }, // MAGN_TARGET is 42 dB
  33. /* Wake on radio and timeouts control */
  34. { CC1101_WORCTRL, 0xFB }, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
  35. /* Frontend configuration */
  36. { CC1101_FREND0, 0x11 }, // Adjusts current TX LO buffer + high is PATABLE[1]
  37. { CC1101_FREND1, 0xB6 }, //
  38. /* Frequency Synthesizer Calibration, valid for 433.92 */
  39. { CC1101_FSCAL3, 0xE9 },
  40. { CC1101_FSCAL2, 0x2A },
  41. { CC1101_FSCAL1, 0x00 },
  42. { CC1101_FSCAL0, 0x1F },
  43. /* Magic f4ckery */
  44. { CC1101_TEST2, 0x81 }, // FIFOTHR ADC_RETENTION=1 matched value
  45. { CC1101_TEST1, 0x35 }, // FIFOTHR ADC_RETENTION=1 matched value
  46. { CC1101_TEST0, 0x09 }, // VCO selection calibration stage is disabled
  47. /* End */
  48. { 0, 0 },
  49. };
  50. static const uint8_t api_hal_subghz_preset_ook_async_patable[8] = {
  51. 0x00,
  52. 0xC0, // 10dBm 0xC0, 7dBm 0xC8, 5dBm 0x84, 0dBm 0x60, -10dBm 0x34, -15dBm 0x1D, -20dBm 0x0E, -30dBm 0x12
  53. 0x00,
  54. 0x00,
  55. 0x00,
  56. 0x00,
  57. 0x00,
  58. 0x00
  59. };
  60. void api_hal_subghz_init() {
  61. furi_assert(api_hal_subghz_state == SubGhzStateInit);
  62. api_hal_subghz_state = SubGhzStateIdle;
  63. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  64. #ifdef API_HAL_SUBGHZ_TX_GPIO
  65. hal_gpio_init(&API_HAL_SUBGHZ_TX_GPIO, GpioModeOutputPushPull, GpioPullNo, GpioSpeedLow);
  66. #endif
  67. // Reset
  68. hal_gpio_init(&gpio_cc1101_g0, GpioModeAnalog, GpioPullNo, GpioSpeedLow);
  69. cc1101_reset(device);
  70. cc1101_write_reg(device, CC1101_IOCFG0, CC1101IocfgHighImpedance);
  71. // Prepare GD0 for power on self test
  72. hal_gpio_init(&gpio_cc1101_g0, GpioModeInput, GpioPullNo, GpioSpeedLow);
  73. // GD0 low
  74. cc1101_write_reg(device, CC1101_IOCFG0, CC1101IocfgHW);
  75. while(hal_gpio_read(&gpio_cc1101_g0) != false);
  76. // GD0 high
  77. cc1101_write_reg(device, CC1101_IOCFG0, CC1101IocfgHW | CC1101_IOCFG_INV);
  78. while(hal_gpio_read(&gpio_cc1101_g0) != true);
  79. // Reset GD0 to floating state
  80. cc1101_write_reg(device, CC1101_IOCFG0, CC1101IocfgHighImpedance);
  81. hal_gpio_init(&gpio_cc1101_g0, GpioModeAnalog, GpioPullNo, GpioSpeedLow);
  82. // RF switches
  83. hal_gpio_init(&gpio_rf_sw_0, GpioModeOutputPushPull, GpioPullNo, GpioSpeedLow);
  84. cc1101_write_reg(device, CC1101_IOCFG2, CC1101IocfgHW);
  85. // Go to sleep
  86. cc1101_shutdown(device);
  87. api_hal_spi_device_return(device);
  88. }
  89. void api_hal_subghz_sleep() {
  90. furi_assert(api_hal_subghz_state == SubGhzStateIdle);
  91. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  92. cc1101_switch_to_idle(device);
  93. cc1101_write_reg(device, CC1101_IOCFG0, CC1101IocfgHighImpedance);
  94. hal_gpio_init(&gpio_cc1101_g0, GpioModeAnalog, GpioPullNo, GpioSpeedLow);
  95. cc1101_shutdown(device);
  96. api_hal_spi_device_return(device);
  97. }
  98. void api_hal_subghz_dump_state() {
  99. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  100. printf(
  101. "[api_hal_subghz] cc1101 chip %d, version %d\r\n",
  102. cc1101_get_partnumber(device),
  103. cc1101_get_version(device)
  104. );
  105. api_hal_spi_device_return(device);
  106. }
  107. void api_hal_subghz_load_preset(ApiHalSubGhzPreset preset) {
  108. if(preset == ApiHalSubGhzPresetOokAsync) {
  109. api_hal_subghz_load_registers(api_hal_subghz_preset_ook_async_regs);
  110. api_hal_subghz_load_patable(api_hal_subghz_preset_ook_async_patable);
  111. } else {
  112. furi_check(0);
  113. }
  114. }
  115. uint8_t api_hal_subghz_get_status() {
  116. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  117. CC1101StatusRaw st;
  118. st.status = cc1101_get_status(device);
  119. api_hal_spi_device_return(device);
  120. return st.status_raw;
  121. }
  122. void api_hal_subghz_load_registers(const uint8_t data[][2]) {
  123. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  124. cc1101_reset(device);
  125. uint32_t i = 0;
  126. while (data[i][0]) {
  127. cc1101_write_reg(device, data[i][0], data[i][1]);
  128. i++;
  129. }
  130. api_hal_spi_device_return(device);
  131. }
  132. void api_hal_subghz_load_patable(const uint8_t data[8]) {
  133. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  134. cc1101_set_pa_table(device, data);
  135. api_hal_spi_device_return(device);
  136. }
  137. void api_hal_subghz_write_packet(const uint8_t* data, uint8_t size) {
  138. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  139. cc1101_flush_tx(device);
  140. cc1101_write_fifo(device, data, size);
  141. api_hal_spi_device_return(device);
  142. }
  143. void api_hal_subghz_flush_rx() {
  144. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  145. cc1101_flush_rx(device);
  146. api_hal_spi_device_return(device);
  147. }
  148. void api_hal_subghz_read_packet(uint8_t* data, uint8_t* size) {
  149. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  150. cc1101_read_fifo(device, data, size);
  151. api_hal_spi_device_return(device);
  152. }
  153. void api_hal_subghz_shutdown() {
  154. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  155. // Reset and shutdown
  156. cc1101_shutdown(device);
  157. api_hal_spi_device_return(device);
  158. }
  159. void api_hal_subghz_reset() {
  160. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  161. hal_gpio_init(&gpio_cc1101_g0, GpioModeAnalog, GpioPullNo, GpioSpeedLow);
  162. cc1101_switch_to_idle(device);
  163. cc1101_reset(device);
  164. cc1101_write_reg(device, CC1101_IOCFG0, CC1101IocfgHighImpedance);
  165. api_hal_spi_device_return(device);
  166. }
  167. void api_hal_subghz_idle() {
  168. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  169. cc1101_switch_to_idle(device);
  170. api_hal_spi_device_return(device);
  171. }
  172. void api_hal_subghz_rx() {
  173. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  174. cc1101_switch_to_rx(device);
  175. api_hal_spi_device_return(device);
  176. }
  177. void api_hal_subghz_tx() {
  178. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  179. cc1101_switch_to_tx(device);
  180. api_hal_spi_device_return(device);
  181. }
  182. float api_hal_subghz_get_rssi() {
  183. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  184. int32_t rssi_dec = cc1101_get_rssi(device);
  185. api_hal_spi_device_return(device);
  186. float rssi = rssi_dec;
  187. if(rssi_dec >= 128) {
  188. rssi = ((rssi - 256.0f) / 2.0f) - 74.0f;
  189. } else {
  190. rssi = (rssi / 2.0f) - 74.0f;
  191. }
  192. return rssi;
  193. }
  194. uint32_t api_hal_subghz_set_frequency_and_path(uint32_t value) {
  195. value = api_hal_subghz_set_frequency(value);
  196. if(value >= 300000000 && value <= 348000335) {
  197. api_hal_subghz_set_path(ApiHalSubGhzPath315);
  198. } else if(value >= 387000000 && value <= 464000000) {
  199. api_hal_subghz_set_path(ApiHalSubGhzPath433);
  200. } else if(value >= 779000000 && value <= 928000000) {
  201. api_hal_subghz_set_path(ApiHalSubGhzPath868);
  202. } else {
  203. furi_check(0);
  204. }
  205. return value;
  206. }
  207. uint32_t api_hal_subghz_set_frequency(uint32_t value) {
  208. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  209. uint32_t real_frequency = cc1101_set_frequency(device, value);
  210. cc1101_calibrate(device);
  211. api_hal_spi_device_return(device);
  212. return real_frequency;
  213. }
  214. void api_hal_subghz_set_path(ApiHalSubGhzPath path) {
  215. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  216. if (path == ApiHalSubGhzPath433) {
  217. hal_gpio_write(&gpio_rf_sw_0, 0);
  218. cc1101_write_reg(device, CC1101_IOCFG2, CC1101IocfgHW | CC1101_IOCFG_INV);
  219. } else if (path == ApiHalSubGhzPath315) {
  220. hal_gpio_write(&gpio_rf_sw_0, 1);
  221. cc1101_write_reg(device, CC1101_IOCFG2, CC1101IocfgHW);
  222. } else if (path == ApiHalSubGhzPath868) {
  223. hal_gpio_write(&gpio_rf_sw_0, 1);
  224. cc1101_write_reg(device, CC1101_IOCFG2, CC1101IocfgHW | CC1101_IOCFG_INV);
  225. } else if (path == ApiHalSubGhzPathIsolate) {
  226. hal_gpio_write(&gpio_rf_sw_0, 0);
  227. cc1101_write_reg(device, CC1101_IOCFG2, CC1101IocfgHW);
  228. } else {
  229. furi_check(0);
  230. }
  231. api_hal_spi_device_return(device);
  232. }
  233. volatile uint32_t api_hal_subghz_capture_delta_duration = 0;
  234. volatile ApiHalSubGhzCaptureCallback api_hal_subghz_capture_callback = NULL;
  235. volatile void* api_hal_subghz_capture_callback_context = NULL;
  236. static void api_hal_subghz_capture_ISR() {
  237. // Channel 1
  238. if(LL_TIM_IsActiveFlag_CC1(TIM2)) {
  239. LL_TIM_ClearFlag_CC1(TIM2);
  240. api_hal_subghz_capture_delta_duration = LL_TIM_IC_GetCaptureCH1(TIM2);
  241. if (api_hal_subghz_capture_callback) {
  242. api_hal_subghz_capture_callback(true, api_hal_subghz_capture_delta_duration,
  243. (void*)api_hal_subghz_capture_callback_context
  244. );
  245. }
  246. }
  247. // Channel 2
  248. if(LL_TIM_IsActiveFlag_CC2(TIM2)) {
  249. LL_TIM_ClearFlag_CC2(TIM2);
  250. if (api_hal_subghz_capture_callback) {
  251. api_hal_subghz_capture_callback(false, LL_TIM_IC_GetCaptureCH2(TIM2) - api_hal_subghz_capture_delta_duration,
  252. (void*)api_hal_subghz_capture_callback_context
  253. );
  254. }
  255. }
  256. }
  257. void api_hal_subghz_set_async_rx_callback(ApiHalSubGhzCaptureCallback callback, void* context) {
  258. api_hal_subghz_capture_callback = callback;
  259. api_hal_subghz_capture_callback_context = context;
  260. }
  261. void api_hal_subghz_start_async_rx() {
  262. furi_assert(api_hal_subghz_state == SubGhzStateIdle);
  263. api_hal_subghz_state = SubGhzStateAsyncRx;
  264. hal_gpio_init_ex(&gpio_cc1101_g0, GpioModeAltFunctionPushPull, GpioPullNo, GpioSpeedLow, GpioAltFn1TIM2);
  265. // Timer: base
  266. LL_TIM_InitTypeDef TIM_InitStruct = {0};
  267. TIM_InitStruct.Prescaler = 64-1;
  268. TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;
  269. TIM_InitStruct.Autoreload = 0x7FFFFFFE;
  270. TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
  271. LL_TIM_Init(TIM2, &TIM_InitStruct);
  272. // Timer: advanced
  273. LL_TIM_SetClockSource(TIM2, LL_TIM_CLOCKSOURCE_INTERNAL);
  274. LL_TIM_DisableARRPreload(TIM2);
  275. LL_TIM_SetTriggerInput(TIM2, LL_TIM_TS_TI2FP2);
  276. LL_TIM_SetSlaveMode(TIM2, LL_TIM_SLAVEMODE_RESET);
  277. LL_TIM_SetTriggerOutput(TIM2, LL_TIM_TRGO_RESET);
  278. LL_TIM_EnableMasterSlaveMode(TIM2);
  279. LL_TIM_DisableDMAReq_TRIG(TIM2);
  280. LL_TIM_DisableIT_TRIG(TIM2);
  281. // Timer: channel 1 indirect
  282. LL_TIM_IC_SetActiveInput(TIM2, LL_TIM_CHANNEL_CH1, LL_TIM_ACTIVEINPUT_INDIRECTTI);
  283. LL_TIM_IC_SetPrescaler(TIM2, LL_TIM_CHANNEL_CH1, LL_TIM_ICPSC_DIV1);
  284. LL_TIM_IC_SetPolarity(TIM2, LL_TIM_CHANNEL_CH1, LL_TIM_IC_POLARITY_FALLING);
  285. LL_TIM_IC_SetFilter(TIM2, LL_TIM_CHANNEL_CH1, LL_TIM_IC_FILTER_FDIV1);
  286. // Timer: channel 2 direct
  287. LL_TIM_IC_SetActiveInput(TIM2, LL_TIM_CHANNEL_CH2, LL_TIM_ACTIVEINPUT_DIRECTTI);
  288. LL_TIM_IC_SetPrescaler(TIM2, LL_TIM_CHANNEL_CH2, LL_TIM_ICPSC_DIV1);
  289. LL_TIM_IC_SetPolarity(TIM2, LL_TIM_CHANNEL_CH2, LL_TIM_IC_POLARITY_RISING);
  290. LL_TIM_IC_SetFilter(TIM2, LL_TIM_CHANNEL_CH2, LL_TIM_IC_FILTER_FDIV1);
  291. // ISR setup
  292. api_hal_interrupt_set_timer_isr(TIM2, api_hal_subghz_capture_ISR);
  293. NVIC_SetPriority(TIM2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),5, 0));
  294. NVIC_EnableIRQ(TIM2_IRQn);
  295. // Interrupts and channels
  296. LL_TIM_EnableIT_CC1(TIM2);
  297. LL_TIM_EnableIT_CC2(TIM2);
  298. LL_TIM_CC_EnableChannel(TIM2, LL_TIM_CHANNEL_CH1);
  299. LL_TIM_CC_EnableChannel(TIM2, LL_TIM_CHANNEL_CH2);
  300. // Start timer
  301. LL_TIM_SetCounter(TIM2, 0);
  302. LL_TIM_EnableCounter(TIM2);
  303. // Switch to RX
  304. api_hal_subghz_rx();
  305. }
  306. void api_hal_subghz_stop_async_rx() {
  307. furi_assert(api_hal_subghz_state == SubGhzStateAsyncRx);
  308. api_hal_subghz_state = SubGhzStateIdle;
  309. // Shutdown radio
  310. api_hal_subghz_idle();
  311. LL_TIM_DeInit(TIM2);
  312. api_hal_interrupt_set_timer_isr(TIM2, NULL);
  313. hal_gpio_init(&gpio_cc1101_g0, GpioModeAnalog, GpioPullNo, GpioSpeedLow);
  314. }
  315. volatile size_t api_hal_subghz_tx_repeat = 0;
  316. static void api_hal_subghz_tx_dma_isr() {
  317. if (LL_DMA_IsActiveFlag_TC1(DMA1)) {
  318. LL_DMA_ClearFlag_TC1(DMA1);
  319. furi_assert(api_hal_subghz_state == SubGhzStateAsyncTx);
  320. if (--api_hal_subghz_tx_repeat == 0) {
  321. api_hal_subghz_state = SubGhzStateAsyncTxLast;
  322. LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_1);
  323. }
  324. }
  325. }
  326. static void api_hal_subghz_tx_timer_isr() {
  327. if(LL_TIM_IsActiveFlag_UPDATE(TIM2)) {
  328. LL_TIM_ClearFlag_UPDATE(TIM2);
  329. if (api_hal_subghz_state == SubGhzStateAsyncTxLast) {
  330. LL_TIM_DisableCounter(TIM2);
  331. api_hal_subghz_state = SubGhzStateAsyncTxEnd;
  332. }
  333. }
  334. }
  335. void api_hal_subghz_start_async_tx(uint32_t* buffer, size_t buffer_size, size_t repeat) {
  336. furi_assert(api_hal_subghz_state == SubGhzStateIdle);
  337. api_hal_subghz_state = SubGhzStateAsyncTx;
  338. api_hal_subghz_tx_repeat = repeat;
  339. // Connect CC1101_GD0 to TIM2 as output
  340. hal_gpio_init_ex(&gpio_cc1101_g0, GpioModeAltFunctionPushPull, GpioPullDown, GpioSpeedLow, GpioAltFn1TIM2);
  341. // Configure DMA
  342. LL_DMA_InitTypeDef dma_config = {0};
  343. dma_config.PeriphOrM2MSrcAddress = (uint32_t)&(TIM2->ARR);
  344. dma_config.MemoryOrM2MDstAddress = (uint32_t)buffer;
  345. dma_config.Direction = LL_DMA_DIRECTION_MEMORY_TO_PERIPH;
  346. dma_config.Mode = LL_DMA_MODE_CIRCULAR;
  347. dma_config.PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
  348. dma_config.MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT;
  349. dma_config.PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_WORD;
  350. dma_config.MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_WORD;
  351. dma_config.NbData = buffer_size / sizeof(uint32_t);
  352. dma_config.PeriphRequest = LL_DMAMUX_REQ_TIM2_UP;
  353. dma_config.Priority = LL_DMA_MODE_NORMAL;
  354. LL_DMA_Init(DMA1, LL_DMA_CHANNEL_1, &dma_config);
  355. api_hal_interrupt_set_dma_channel_isr(DMA1, LL_DMA_CHANNEL_1, api_hal_subghz_tx_dma_isr);
  356. LL_DMA_EnableIT_TC(DMA1, LL_DMA_CHANNEL_1);
  357. LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_1);
  358. // Configure TIM2
  359. LL_TIM_InitTypeDef TIM_InitStruct = {0};
  360. TIM_InitStruct.Prescaler = 64-1;
  361. TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;
  362. TIM_InitStruct.Autoreload = 1000;
  363. TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
  364. LL_TIM_Init(TIM2, &TIM_InitStruct);
  365. LL_TIM_SetClockSource(TIM2, LL_TIM_CLOCKSOURCE_INTERNAL);
  366. LL_TIM_EnableARRPreload(TIM2);
  367. // Configure TIM2 CH2
  368. LL_TIM_OC_InitTypeDef TIM_OC_InitStruct = {0};
  369. TIM_OC_InitStruct.OCMode = LL_TIM_OCMODE_TOGGLE;
  370. TIM_OC_InitStruct.OCState = LL_TIM_OCSTATE_DISABLE;
  371. TIM_OC_InitStruct.OCNState = LL_TIM_OCSTATE_DISABLE;
  372. TIM_OC_InitStruct.CompareValue = 0;
  373. TIM_OC_InitStruct.OCPolarity = LL_TIM_OCPOLARITY_HIGH;
  374. LL_TIM_OC_Init(TIM2, LL_TIM_CHANNEL_CH2, &TIM_OC_InitStruct);
  375. LL_TIM_OC_DisableFast(TIM2, LL_TIM_CHANNEL_CH2);
  376. LL_TIM_DisableMasterSlaveMode(TIM2);
  377. api_hal_interrupt_set_timer_isr(TIM2, api_hal_subghz_tx_timer_isr);
  378. LL_TIM_EnableIT_UPDATE(TIM2);
  379. LL_TIM_EnableDMAReq_UPDATE(TIM2);
  380. LL_TIM_CC_EnableChannel(TIM2, LL_TIM_CHANNEL_CH2);
  381. // Start counter
  382. LL_TIM_GenerateEvent_UPDATE(TIM2);
  383. #ifdef API_HAL_SUBGHZ_TX_GPIO
  384. hal_gpio_write(&API_HAL_SUBGHZ_TX_GPIO, true);
  385. #endif
  386. api_hal_subghz_tx();
  387. LL_TIM_SetCounter(TIM2, 0);
  388. LL_TIM_EnableCounter(TIM2);
  389. }
  390. size_t api_hal_subghz_get_async_tx_repeat_left() {
  391. return api_hal_subghz_tx_repeat;
  392. }
  393. void api_hal_subghz_wait_async_tx() {
  394. while(api_hal_subghz_state != SubGhzStateAsyncTxEnd) osDelay(1);
  395. }
  396. void api_hal_subghz_stop_async_tx() {
  397. furi_assert(
  398. api_hal_subghz_state == SubGhzStateAsyncTx
  399. || api_hal_subghz_state == SubGhzStateAsyncTxLast
  400. || api_hal_subghz_state == SubGhzStateAsyncTxEnd
  401. );
  402. // Shutdown radio
  403. api_hal_subghz_idle();
  404. #ifdef API_HAL_SUBGHZ_TX_GPIO
  405. hal_gpio_write(&API_HAL_SUBGHZ_TX_GPIO, false);
  406. #endif
  407. // Deinitialize Timer
  408. LL_TIM_DeInit(TIM2);
  409. api_hal_interrupt_set_timer_isr(TIM2, NULL);
  410. // Deinitialize DMA
  411. LL_DMA_DeInit(DMA1, LL_DMA_CHANNEL_1);
  412. api_hal_interrupt_set_dma_channel_isr(DMA1, LL_DMA_CHANNEL_1, NULL);
  413. // Deinitialize GPIO
  414. hal_gpio_init(&gpio_cc1101_g0, GpioModeAnalog, GpioPullNo, GpioSpeedLow);
  415. api_hal_subghz_state = SubGhzStateIdle;
  416. }