furi_hal_interrupt.c 6.7 KB

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  1. #include "furi_hal_interrupt.h"
  2. #include "furi_hal_delay.h"
  3. #include <furi.h>
  4. #include <stm32wbxx.h>
  5. #include <stm32wbxx_ll_tim.h>
  6. #include <stm32wbxx_ll_rcc.h>
  7. #define TAG "FuriHalInterrupt"
  8. #define FURI_HAL_INTERRUPT_DEFAULT_PRIORITY 5
  9. typedef struct {
  10. FuriHalInterruptISR isr;
  11. void* context;
  12. } FuriHalInterruptISRPair;
  13. FuriHalInterruptISRPair furi_hal_interrupt_isr[FuriHalInterruptIdMax] = {0};
  14. const IRQn_Type furi_hal_interrupt_irqn[FuriHalInterruptIdMax] = {
  15. // TIM1, TIM16, TIM17
  16. [FuriHalInterruptIdTim1TrgComTim17] = TIM1_TRG_COM_TIM17_IRQn,
  17. [FuriHalInterruptIdTim1Cc] = TIM1_CC_IRQn,
  18. [FuriHalInterruptIdTim1UpTim16] = TIM1_UP_TIM16_IRQn,
  19. // TIM2
  20. [FuriHalInterruptIdTIM2] = TIM2_IRQn,
  21. // DMA1
  22. [FuriHalInterruptIdDma1Ch1] = DMA1_Channel1_IRQn,
  23. [FuriHalInterruptIdDma1Ch2] = DMA1_Channel2_IRQn,
  24. [FuriHalInterruptIdDma1Ch3] = DMA1_Channel3_IRQn,
  25. [FuriHalInterruptIdDma1Ch4] = DMA1_Channel4_IRQn,
  26. [FuriHalInterruptIdDma1Ch5] = DMA1_Channel5_IRQn,
  27. [FuriHalInterruptIdDma1Ch6] = DMA1_Channel6_IRQn,
  28. [FuriHalInterruptIdDma1Ch7] = DMA1_Channel7_IRQn,
  29. // DMA2
  30. [FuriHalInterruptIdDma2Ch1] = DMA2_Channel1_IRQn,
  31. [FuriHalInterruptIdDma2Ch2] = DMA2_Channel2_IRQn,
  32. [FuriHalInterruptIdDma2Ch3] = DMA2_Channel3_IRQn,
  33. [FuriHalInterruptIdDma2Ch4] = DMA2_Channel4_IRQn,
  34. [FuriHalInterruptIdDma2Ch5] = DMA2_Channel5_IRQn,
  35. [FuriHalInterruptIdDma2Ch6] = DMA2_Channel6_IRQn,
  36. [FuriHalInterruptIdDma2Ch7] = DMA2_Channel7_IRQn,
  37. // RCC
  38. [FuriHalInterruptIdRcc] = RCC_IRQn,
  39. // COMP
  40. [FuriHalInterruptIdCOMP] = COMP_IRQn,
  41. // HSEM
  42. [FuriHalInterruptIdHsem] = HSEM_IRQn,
  43. };
  44. __attribute__((always_inline)) static inline void
  45. furi_hal_interrupt_call(FuriHalInterruptId index) {
  46. furi_assert(furi_hal_interrupt_isr[index].isr);
  47. furi_hal_interrupt_isr[index].isr(furi_hal_interrupt_isr[index].context);
  48. }
  49. __attribute__((always_inline)) static inline void
  50. furi_hal_interrupt_enable(FuriHalInterruptId index, uint16_t priority) {
  51. NVIC_SetPriority(
  52. furi_hal_interrupt_irqn[index],
  53. NVIC_EncodePriority(NVIC_GetPriorityGrouping(), priority, 0));
  54. NVIC_EnableIRQ(furi_hal_interrupt_irqn[index]);
  55. }
  56. __attribute__((always_inline)) static inline void
  57. furi_hal_interrupt_disable(FuriHalInterruptId index) {
  58. NVIC_DisableIRQ(furi_hal_interrupt_irqn[index]);
  59. }
  60. void furi_hal_interrupt_init() {
  61. NVIC_SetPriority(
  62. TAMP_STAMP_LSECSS_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0));
  63. NVIC_EnableIRQ(TAMP_STAMP_LSECSS_IRQn);
  64. NVIC_SetPriority(PendSV_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 15, 0));
  65. FURI_LOG_I(TAG, "Init OK");
  66. }
  67. void furi_hal_interrupt_set_isr(FuriHalInterruptId index, FuriHalInterruptISR isr, void* context) {
  68. furi_hal_interrupt_set_isr_ex(index, FURI_HAL_INTERRUPT_DEFAULT_PRIORITY, isr, context);
  69. }
  70. void furi_hal_interrupt_set_isr_ex(
  71. FuriHalInterruptId index,
  72. uint16_t priority,
  73. FuriHalInterruptISR isr,
  74. void* context) {
  75. furi_assert(index < FuriHalInterruptIdMax);
  76. furi_assert(priority < 15);
  77. furi_assert(furi_hal_interrupt_irqn[index]);
  78. if(isr) {
  79. // Pre ISR set
  80. furi_assert(furi_hal_interrupt_isr[index].isr == NULL);
  81. } else {
  82. // Pre ISR clear
  83. furi_assert(furi_hal_interrupt_isr[index].isr != NULL);
  84. furi_hal_interrupt_disable(index);
  85. }
  86. furi_hal_interrupt_isr[index].isr = isr;
  87. furi_hal_interrupt_isr[index].context = context;
  88. __DMB();
  89. if(isr) {
  90. // Post ISR set
  91. furi_hal_interrupt_enable(index, priority);
  92. } else {
  93. // Post ISR clear
  94. }
  95. }
  96. /* Timer 2 */
  97. void TIM2_IRQHandler(void) {
  98. furi_hal_interrupt_call(FuriHalInterruptIdTIM2);
  99. }
  100. /* Timer 1 Update */
  101. void TIM1_UP_TIM16_IRQHandler(void) {
  102. furi_hal_interrupt_call(FuriHalInterruptIdTim1UpTim16);
  103. }
  104. void TIM1_TRG_COM_TIM17_IRQHandler(void) {
  105. furi_hal_interrupt_call(FuriHalInterruptIdTim1TrgComTim17);
  106. }
  107. void TIM1_CC_IRQHandler(void) {
  108. furi_hal_interrupt_call(FuriHalInterruptIdTim1Cc);
  109. }
  110. /* DMA 1 */
  111. void DMA1_Channel1_IRQHandler(void) {
  112. furi_hal_interrupt_call(FuriHalInterruptIdDma1Ch1);
  113. }
  114. void DMA1_Channel2_IRQHandler(void) {
  115. furi_hal_interrupt_call(FuriHalInterruptIdDma1Ch2);
  116. }
  117. void DMA1_Channel3_IRQHandler(void) {
  118. furi_hal_interrupt_call(FuriHalInterruptIdDma1Ch3);
  119. }
  120. void DMA1_Channel4_IRQHandler(void) {
  121. furi_hal_interrupt_call(FuriHalInterruptIdDma1Ch4);
  122. }
  123. void DMA1_Channel5_IRQHandler(void) {
  124. furi_hal_interrupt_call(FuriHalInterruptIdDma1Ch5);
  125. }
  126. void DMA1_Channel6_IRQHandler(void) {
  127. furi_hal_interrupt_call(FuriHalInterruptIdDma1Ch6);
  128. }
  129. void DMA1_Channel7_IRQHandler(void) {
  130. furi_hal_interrupt_call(FuriHalInterruptIdDma1Ch7);
  131. }
  132. /* DMA 2 */
  133. void DMA2_Channel1_IRQHandler(void) {
  134. furi_hal_interrupt_call(FuriHalInterruptIdDma2Ch1);
  135. }
  136. void DMA2_Channel2_IRQHandler(void) {
  137. furi_hal_interrupt_call(FuriHalInterruptIdDma2Ch2);
  138. }
  139. void DMA2_Channel3_IRQHandler(void) {
  140. furi_hal_interrupt_call(FuriHalInterruptIdDma2Ch3);
  141. }
  142. void DMA2_Channel4_IRQHandler(void) {
  143. furi_hal_interrupt_call(FuriHalInterruptIdDma2Ch4);
  144. }
  145. void DMA2_Channel5_IRQHandler(void) {
  146. furi_hal_interrupt_call(FuriHalInterruptIdDma2Ch5);
  147. }
  148. void DMA2_Channel6_IRQHandler(void) {
  149. furi_hal_interrupt_call(FuriHalInterruptIdDma2Ch6);
  150. }
  151. void DMA2_Channel7_IRQHandler(void) {
  152. furi_hal_interrupt_call(FuriHalInterruptIdDma2Ch7);
  153. }
  154. void HSEM_IRQHandler(void) {
  155. furi_hal_interrupt_call(FuriHalInterruptIdHsem);
  156. }
  157. void TAMP_STAMP_LSECSS_IRQHandler(void) {
  158. if(LL_RCC_IsActiveFlag_LSECSS()) {
  159. LL_RCC_ClearFlag_LSECSS();
  160. if(!LL_RCC_LSE_IsReady()) {
  161. FURI_LOG_E(TAG, "LSE CSS fired: resetting system");
  162. NVIC_SystemReset();
  163. } else {
  164. FURI_LOG_E(TAG, "LSE CSS fired: but LSE is alive");
  165. }
  166. }
  167. }
  168. void RCC_IRQHandler(void) {
  169. furi_hal_interrupt_call(FuriHalInterruptIdRcc);
  170. }
  171. void NMI_Handler(void) {
  172. if(LL_RCC_IsActiveFlag_HSECSS()) {
  173. LL_RCC_ClearFlag_HSECSS();
  174. FURI_LOG_E(TAG, "HSE CSS fired: resetting system");
  175. NVIC_SystemReset();
  176. }
  177. }
  178. void HardFault_Handler(void) {
  179. furi_crash("HardFault");
  180. }
  181. void MemManage_Handler(void) {
  182. furi_crash("MemManage");
  183. }
  184. void BusFault_Handler(void) {
  185. furi_crash("BusFault");
  186. }
  187. void UsageFault_Handler(void) {
  188. furi_crash("UsageFault");
  189. }
  190. void DebugMon_Handler(void) {
  191. }
  192. #include "usbd_core.h"
  193. extern usbd_device udev;
  194. extern void HW_IPCC_Tx_Handler();
  195. extern void HW_IPCC_Rx_Handler();
  196. void SysTick_Handler(void) {
  197. furi_hal_tick();
  198. }
  199. void USB_LP_IRQHandler(void) {
  200. #ifndef FURI_RAM_EXEC
  201. usbd_poll(&udev);
  202. #endif
  203. }
  204. void IPCC_C1_TX_IRQHandler(void) {
  205. HW_IPCC_Tx_Handler();
  206. }
  207. void IPCC_C1_RX_IRQHandler(void) {
  208. HW_IPCC_Rx_Handler();
  209. }