spi_mem_chip_i.h 2.3 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485
  1. #pragma once
  2. #include <furi.h>
  3. #include "spi_mem_chip.h"
  4. typedef enum {
  5. SPIMemChipVendorUnknown,
  6. SPIMemChipVendorADESTO,
  7. SPIMemChipVendorAMIC,
  8. SPIMemChipVendorBoya,
  9. SPIMemChipVendorEON,
  10. SPIMemChipVendorPFLASH,
  11. SPIMemChipVendorTERRA,
  12. SPIMemChipVendorGeneralplus,
  13. SPIMemChipVendorDEUTRON,
  14. SPIMemChipVendorEFST,
  15. SPIMemChipVendorEXCELSEMI,
  16. SPIMemChipVendorFIDELIX,
  17. SPIMemChipVendorGIGADEVICE,
  18. SPIMemChipVendorICE,
  19. SPIMemChipVendorINTEL,
  20. SPIMemChipVendorKHIC,
  21. SPIMemChipVendorMACRONIX,
  22. SPIMemChipVendorMICRON,
  23. SPIMemChipVendorMSHINE,
  24. SPIMemChipVendorNANTRONICS,
  25. SPIMemChipVendorNEXFLASH,
  26. SPIMemChipVendorNUMONYX,
  27. SPIMemChipVendorPCT,
  28. SPIMemChipVendorSPANSION,
  29. SPIMemChipVendorSST,
  30. SPIMemChipVendorST,
  31. SPIMemChipVendorWINBOND,
  32. SPIMemChipVendorZEMPRO,
  33. SPIMemChipVendorZbit,
  34. SPIMemChipVendorBerg_Micro,
  35. SPIMemChipVendorATMEL,
  36. SPIMemChipVendorACE,
  37. SPIMemChipVendorATO,
  38. SPIMemChipVendorDOUQI,
  39. SPIMemChipVendorFremont,
  40. SPIMemChipVendorFudan,
  41. SPIMemChipVendorGenitop,
  42. SPIMemChipVendorParagon
  43. } SPIMemChipVendor;
  44. typedef enum {
  45. SPIMemChipCMDReadJEDECChipID = 0x9F,
  46. SPIMemChipCMDReadData = 0x03,
  47. SPIMemChipCMDChipErase = 0xC7,
  48. SPIMemChipCMDWriteEnable = 0x06,
  49. SPIMemChipCMDWriteDisable = 0x04,
  50. SPIMemChipCMDReadStatus = 0x05,
  51. SPIMemChipCMDWriteData = 0x02,
  52. SPIMemChipCMDReleasePowerDown = 0xAB
  53. } SPIMemChipCMD;
  54. enum SPIMemChipStatusBit {
  55. SPIMemChipStatusBitBusy = (0x01 << 0),
  56. SPIMemChipStatusBitWriteEnabled = (0x01 << 1),
  57. SPIMemChipStatusBitBitProtection1 = (0x01 << 2),
  58. SPIMemChipStatusBitBitProtection2 = (0x01 << 3),
  59. SPIMemChipStatusBitBitProtection3 = (0x01 << 4),
  60. SPIMemChipStatusBitTopBottomProtection = (0x01 << 5),
  61. SPIMemChipStatusBitSectorProtect = (0x01 << 6),
  62. SPIMemChipStatusBitRegisterProtect = (0x01 << 7)
  63. };
  64. typedef struct {
  65. const char* vendor_name;
  66. SPIMemChipVendor vendor_enum;
  67. } SPIMemChipVendorName;
  68. struct SPIMemChip {
  69. uint8_t vendor_id;
  70. uint8_t type_id;
  71. uint8_t capacity_id;
  72. const char* model_name;
  73. size_t size;
  74. size_t page_size;
  75. SPIMemChipVendor vendor_enum;
  76. SPIMemChipWriteMode write_mode;
  77. };
  78. extern const SPIMemChip SPIMemChips[];