furi_hal_interrupt.c 8.0 KB

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  1. #include "furi_hal_interrupt.h"
  2. #include "furi_hal_os.h"
  3. #include <furi.h>
  4. #include <stm32wbxx.h>
  5. #include <stm32wbxx_ll_tim.h>
  6. #include <stm32wbxx_ll_rcc.h>
  7. #include <stm32wbxx_ll_cortex.h>
  8. #define TAG "FuriHalInterrupt"
  9. #define FURI_HAL_INTERRUPT_DEFAULT_PRIORITY 5
  10. typedef struct {
  11. FuriHalInterruptISR isr;
  12. void* context;
  13. } FuriHalInterruptISRPair;
  14. FuriHalInterruptISRPair furi_hal_interrupt_isr[FuriHalInterruptIdMax] = {0};
  15. const IRQn_Type furi_hal_interrupt_irqn[FuriHalInterruptIdMax] = {
  16. // TIM1, TIM16, TIM17
  17. [FuriHalInterruptIdTim1TrgComTim17] = TIM1_TRG_COM_TIM17_IRQn,
  18. [FuriHalInterruptIdTim1Cc] = TIM1_CC_IRQn,
  19. [FuriHalInterruptIdTim1UpTim16] = TIM1_UP_TIM16_IRQn,
  20. // TIM2
  21. [FuriHalInterruptIdTIM2] = TIM2_IRQn,
  22. // DMA1
  23. [FuriHalInterruptIdDma1Ch1] = DMA1_Channel1_IRQn,
  24. [FuriHalInterruptIdDma1Ch2] = DMA1_Channel2_IRQn,
  25. [FuriHalInterruptIdDma1Ch3] = DMA1_Channel3_IRQn,
  26. [FuriHalInterruptIdDma1Ch4] = DMA1_Channel4_IRQn,
  27. [FuriHalInterruptIdDma1Ch5] = DMA1_Channel5_IRQn,
  28. [FuriHalInterruptIdDma1Ch6] = DMA1_Channel6_IRQn,
  29. [FuriHalInterruptIdDma1Ch7] = DMA1_Channel7_IRQn,
  30. // DMA2
  31. [FuriHalInterruptIdDma2Ch1] = DMA2_Channel1_IRQn,
  32. [FuriHalInterruptIdDma2Ch2] = DMA2_Channel2_IRQn,
  33. [FuriHalInterruptIdDma2Ch3] = DMA2_Channel3_IRQn,
  34. [FuriHalInterruptIdDma2Ch4] = DMA2_Channel4_IRQn,
  35. [FuriHalInterruptIdDma2Ch5] = DMA2_Channel5_IRQn,
  36. [FuriHalInterruptIdDma2Ch6] = DMA2_Channel6_IRQn,
  37. [FuriHalInterruptIdDma2Ch7] = DMA2_Channel7_IRQn,
  38. // RCC
  39. [FuriHalInterruptIdRcc] = RCC_IRQn,
  40. // COMP
  41. [FuriHalInterruptIdCOMP] = COMP_IRQn,
  42. // HSEM
  43. [FuriHalInterruptIdHsem] = HSEM_IRQn,
  44. // LPTIMx
  45. [FuriHalInterruptIdLpTim1] = LPTIM1_IRQn,
  46. [FuriHalInterruptIdLpTim2] = LPTIM2_IRQn,
  47. };
  48. __attribute__((always_inline)) static inline void
  49. furi_hal_interrupt_call(FuriHalInterruptId index) {
  50. furi_assert(furi_hal_interrupt_isr[index].isr);
  51. furi_hal_interrupt_isr[index].isr(furi_hal_interrupt_isr[index].context);
  52. }
  53. __attribute__((always_inline)) static inline void
  54. furi_hal_interrupt_enable(FuriHalInterruptId index, uint16_t priority) {
  55. NVIC_SetPriority(
  56. furi_hal_interrupt_irqn[index],
  57. NVIC_EncodePriority(NVIC_GetPriorityGrouping(), priority, 0));
  58. NVIC_EnableIRQ(furi_hal_interrupt_irqn[index]);
  59. }
  60. __attribute__((always_inline)) static inline void
  61. furi_hal_interrupt_disable(FuriHalInterruptId index) {
  62. NVIC_DisableIRQ(furi_hal_interrupt_irqn[index]);
  63. }
  64. void furi_hal_interrupt_init() {
  65. NVIC_SetPriority(
  66. TAMP_STAMP_LSECSS_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0));
  67. NVIC_EnableIRQ(TAMP_STAMP_LSECSS_IRQn);
  68. NVIC_SetPriority(PendSV_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 15, 0));
  69. NVIC_SetPriority(FPU_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 15, 0));
  70. NVIC_EnableIRQ(FPU_IRQn);
  71. LL_SYSCFG_DisableIT_FPU_IOC();
  72. LL_SYSCFG_DisableIT_FPU_DZC();
  73. LL_SYSCFG_DisableIT_FPU_UFC();
  74. LL_SYSCFG_DisableIT_FPU_OFC();
  75. LL_SYSCFG_DisableIT_FPU_IDC();
  76. LL_SYSCFG_DisableIT_FPU_IXC();
  77. LL_HANDLER_EnableFault(LL_HANDLER_FAULT_USG);
  78. LL_HANDLER_EnableFault(LL_HANDLER_FAULT_BUS);
  79. LL_HANDLER_EnableFault(LL_HANDLER_FAULT_MEM);
  80. FURI_LOG_I(TAG, "Init OK");
  81. }
  82. void furi_hal_interrupt_set_isr(FuriHalInterruptId index, FuriHalInterruptISR isr, void* context) {
  83. furi_hal_interrupt_set_isr_ex(index, FURI_HAL_INTERRUPT_DEFAULT_PRIORITY, isr, context);
  84. }
  85. void furi_hal_interrupt_set_isr_ex(
  86. FuriHalInterruptId index,
  87. uint16_t priority,
  88. FuriHalInterruptISR isr,
  89. void* context) {
  90. furi_assert(index < FuriHalInterruptIdMax);
  91. furi_assert(priority < 15);
  92. furi_assert(furi_hal_interrupt_irqn[index]);
  93. if(isr) {
  94. // Pre ISR set
  95. furi_assert(furi_hal_interrupt_isr[index].isr == NULL);
  96. } else {
  97. // Pre ISR clear
  98. furi_assert(furi_hal_interrupt_isr[index].isr != NULL);
  99. furi_hal_interrupt_disable(index);
  100. }
  101. furi_hal_interrupt_isr[index].isr = isr;
  102. furi_hal_interrupt_isr[index].context = context;
  103. __DMB();
  104. if(isr) {
  105. // Post ISR set
  106. furi_hal_interrupt_enable(index, priority);
  107. } else {
  108. // Post ISR clear
  109. }
  110. }
  111. /* Timer 2 */
  112. void TIM2_IRQHandler() {
  113. furi_hal_interrupt_call(FuriHalInterruptIdTIM2);
  114. }
  115. /* Timer 1 Update */
  116. void TIM1_UP_TIM16_IRQHandler() {
  117. furi_hal_interrupt_call(FuriHalInterruptIdTim1UpTim16);
  118. }
  119. void TIM1_TRG_COM_TIM17_IRQHandler() {
  120. furi_hal_interrupt_call(FuriHalInterruptIdTim1TrgComTim17);
  121. }
  122. void TIM1_CC_IRQHandler() {
  123. furi_hal_interrupt_call(FuriHalInterruptIdTim1Cc);
  124. }
  125. /* DMA 1 */
  126. void DMA1_Channel1_IRQHandler() {
  127. furi_hal_interrupt_call(FuriHalInterruptIdDma1Ch1);
  128. }
  129. void DMA1_Channel2_IRQHandler() {
  130. furi_hal_interrupt_call(FuriHalInterruptIdDma1Ch2);
  131. }
  132. void DMA1_Channel3_IRQHandler() {
  133. furi_hal_interrupt_call(FuriHalInterruptIdDma1Ch3);
  134. }
  135. void DMA1_Channel4_IRQHandler() {
  136. furi_hal_interrupt_call(FuriHalInterruptIdDma1Ch4);
  137. }
  138. void DMA1_Channel5_IRQHandler() {
  139. furi_hal_interrupt_call(FuriHalInterruptIdDma1Ch5);
  140. }
  141. void DMA1_Channel6_IRQHandler() {
  142. furi_hal_interrupt_call(FuriHalInterruptIdDma1Ch6);
  143. }
  144. void DMA1_Channel7_IRQHandler() {
  145. furi_hal_interrupt_call(FuriHalInterruptIdDma1Ch7);
  146. }
  147. /* DMA 2 */
  148. void DMA2_Channel1_IRQHandler() {
  149. furi_hal_interrupt_call(FuriHalInterruptIdDma2Ch1);
  150. }
  151. void DMA2_Channel2_IRQHandler() {
  152. furi_hal_interrupt_call(FuriHalInterruptIdDma2Ch2);
  153. }
  154. void DMA2_Channel3_IRQHandler() {
  155. furi_hal_interrupt_call(FuriHalInterruptIdDma2Ch3);
  156. }
  157. void DMA2_Channel4_IRQHandler() {
  158. furi_hal_interrupt_call(FuriHalInterruptIdDma2Ch4);
  159. }
  160. void DMA2_Channel5_IRQHandler() {
  161. furi_hal_interrupt_call(FuriHalInterruptIdDma2Ch5);
  162. }
  163. void DMA2_Channel6_IRQHandler() {
  164. furi_hal_interrupt_call(FuriHalInterruptIdDma2Ch6);
  165. }
  166. void DMA2_Channel7_IRQHandler() {
  167. furi_hal_interrupt_call(FuriHalInterruptIdDma2Ch7);
  168. }
  169. void HSEM_IRQHandler() {
  170. furi_hal_interrupt_call(FuriHalInterruptIdHsem);
  171. }
  172. void TAMP_STAMP_LSECSS_IRQHandler(void) {
  173. if(LL_RCC_IsActiveFlag_LSECSS()) {
  174. LL_RCC_ClearFlag_LSECSS();
  175. if(!LL_RCC_LSE_IsReady()) {
  176. FURI_LOG_E(TAG, "LSE CSS fired: resetting system");
  177. NVIC_SystemReset();
  178. } else {
  179. FURI_LOG_E(TAG, "LSE CSS fired: but LSE is alive");
  180. }
  181. }
  182. }
  183. void RCC_IRQHandler() {
  184. furi_hal_interrupt_call(FuriHalInterruptIdRcc);
  185. }
  186. void NMI_Handler() {
  187. if(LL_RCC_IsActiveFlag_HSECSS()) {
  188. LL_RCC_ClearFlag_HSECSS();
  189. FURI_LOG_E(TAG, "HSE CSS fired: resetting system");
  190. NVIC_SystemReset();
  191. }
  192. }
  193. void HardFault_Handler() {
  194. furi_crash("HardFault");
  195. }
  196. void MemManage_Handler() {
  197. if(FURI_BIT(SCB->CFSR, SCB_CFSR_MMARVALID_Pos)) {
  198. uint32_t memfault_address = SCB->MMFAR;
  199. if(memfault_address < (1024 * 1024)) {
  200. // from 0x00 to 1MB, see FuriHalMpuRegionNULL
  201. furi_crash("NULL pointer dereference");
  202. } else {
  203. // write or read of MPU region 1 (FuriHalMpuRegionStack)
  204. furi_crash("MPU fault, possibly stack overflow");
  205. }
  206. } else if(FURI_BIT(SCB->CFSR, SCB_CFSR_MSTKERR_Pos)) {
  207. // push to stack on MPU region 1 (FuriHalMpuRegionStack)
  208. furi_crash("MemManage fault, possibly stack overflow");
  209. }
  210. furi_crash("MemManage");
  211. }
  212. void BusFault_Handler() {
  213. furi_crash("BusFault");
  214. }
  215. void UsageFault_Handler() {
  216. furi_crash("UsageFault");
  217. }
  218. void DebugMon_Handler() {
  219. }
  220. #include "usbd_core.h"
  221. extern usbd_device udev;
  222. extern void HW_IPCC_Tx_Handler();
  223. extern void HW_IPCC_Rx_Handler();
  224. void SysTick_Handler() {
  225. furi_hal_os_tick();
  226. }
  227. void USB_LP_IRQHandler() {
  228. #ifndef FURI_RAM_EXEC
  229. usbd_poll(&udev);
  230. #endif
  231. }
  232. void USB_HP_IRQHandler() {
  233. }
  234. void IPCC_C1_TX_IRQHandler() {
  235. HW_IPCC_Tx_Handler();
  236. }
  237. void IPCC_C1_RX_IRQHandler() {
  238. HW_IPCC_Rx_Handler();
  239. }
  240. void FPU_IRQHandler() {
  241. furi_crash("FpuFault");
  242. }
  243. void LPTIM1_IRQHandler() {
  244. furi_hal_interrupt_call(FuriHalInterruptIdLpTim1);
  245. }
  246. void LPTIM2_IRQHandler() {
  247. furi_hal_interrupt_call(FuriHalInterruptIdLpTim2);
  248. }