furi_hal_interrupt.c 6.7 KB

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  1. #include "furi_hal_interrupt.h"
  2. #include "furi_hal_delay.h"
  3. #include "furi_hal_os.h"
  4. #include <furi.h>
  5. #include <stm32wbxx.h>
  6. #include <stm32wbxx_ll_tim.h>
  7. #include <stm32wbxx_ll_rcc.h>
  8. #define TAG "FuriHalInterrupt"
  9. #define FURI_HAL_INTERRUPT_DEFAULT_PRIORITY 5
  10. typedef struct {
  11. FuriHalInterruptISR isr;
  12. void* context;
  13. } FuriHalInterruptISRPair;
  14. FuriHalInterruptISRPair furi_hal_interrupt_isr[FuriHalInterruptIdMax] = {0};
  15. const IRQn_Type furi_hal_interrupt_irqn[FuriHalInterruptIdMax] = {
  16. // TIM1, TIM16, TIM17
  17. [FuriHalInterruptIdTim1TrgComTim17] = TIM1_TRG_COM_TIM17_IRQn,
  18. [FuriHalInterruptIdTim1Cc] = TIM1_CC_IRQn,
  19. [FuriHalInterruptIdTim1UpTim16] = TIM1_UP_TIM16_IRQn,
  20. // TIM2
  21. [FuriHalInterruptIdTIM2] = TIM2_IRQn,
  22. // DMA1
  23. [FuriHalInterruptIdDma1Ch1] = DMA1_Channel1_IRQn,
  24. [FuriHalInterruptIdDma1Ch2] = DMA1_Channel2_IRQn,
  25. [FuriHalInterruptIdDma1Ch3] = DMA1_Channel3_IRQn,
  26. [FuriHalInterruptIdDma1Ch4] = DMA1_Channel4_IRQn,
  27. [FuriHalInterruptIdDma1Ch5] = DMA1_Channel5_IRQn,
  28. [FuriHalInterruptIdDma1Ch6] = DMA1_Channel6_IRQn,
  29. [FuriHalInterruptIdDma1Ch7] = DMA1_Channel7_IRQn,
  30. // DMA2
  31. [FuriHalInterruptIdDma2Ch1] = DMA2_Channel1_IRQn,
  32. [FuriHalInterruptIdDma2Ch2] = DMA2_Channel2_IRQn,
  33. [FuriHalInterruptIdDma2Ch3] = DMA2_Channel3_IRQn,
  34. [FuriHalInterruptIdDma2Ch4] = DMA2_Channel4_IRQn,
  35. [FuriHalInterruptIdDma2Ch5] = DMA2_Channel5_IRQn,
  36. [FuriHalInterruptIdDma2Ch6] = DMA2_Channel6_IRQn,
  37. [FuriHalInterruptIdDma2Ch7] = DMA2_Channel7_IRQn,
  38. // RCC
  39. [FuriHalInterruptIdRcc] = RCC_IRQn,
  40. // COMP
  41. [FuriHalInterruptIdCOMP] = COMP_IRQn,
  42. // HSEM
  43. [FuriHalInterruptIdHsem] = HSEM_IRQn,
  44. };
  45. __attribute__((always_inline)) static inline void
  46. furi_hal_interrupt_call(FuriHalInterruptId index) {
  47. furi_assert(furi_hal_interrupt_isr[index].isr);
  48. furi_hal_interrupt_isr[index].isr(furi_hal_interrupt_isr[index].context);
  49. }
  50. __attribute__((always_inline)) static inline void
  51. furi_hal_interrupt_enable(FuriHalInterruptId index, uint16_t priority) {
  52. NVIC_SetPriority(
  53. furi_hal_interrupt_irqn[index],
  54. NVIC_EncodePriority(NVIC_GetPriorityGrouping(), priority, 0));
  55. NVIC_EnableIRQ(furi_hal_interrupt_irqn[index]);
  56. }
  57. __attribute__((always_inline)) static inline void
  58. furi_hal_interrupt_disable(FuriHalInterruptId index) {
  59. NVIC_DisableIRQ(furi_hal_interrupt_irqn[index]);
  60. }
  61. void furi_hal_interrupt_init() {
  62. NVIC_SetPriority(
  63. TAMP_STAMP_LSECSS_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0));
  64. NVIC_EnableIRQ(TAMP_STAMP_LSECSS_IRQn);
  65. NVIC_SetPriority(PendSV_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 15, 0));
  66. FURI_LOG_I(TAG, "Init OK");
  67. }
  68. void furi_hal_interrupt_set_isr(FuriHalInterruptId index, FuriHalInterruptISR isr, void* context) {
  69. furi_hal_interrupt_set_isr_ex(index, FURI_HAL_INTERRUPT_DEFAULT_PRIORITY, isr, context);
  70. }
  71. void furi_hal_interrupt_set_isr_ex(
  72. FuriHalInterruptId index,
  73. uint16_t priority,
  74. FuriHalInterruptISR isr,
  75. void* context) {
  76. furi_assert(index < FuriHalInterruptIdMax);
  77. furi_assert(priority < 15);
  78. furi_assert(furi_hal_interrupt_irqn[index]);
  79. if(isr) {
  80. // Pre ISR set
  81. furi_assert(furi_hal_interrupt_isr[index].isr == NULL);
  82. } else {
  83. // Pre ISR clear
  84. furi_assert(furi_hal_interrupt_isr[index].isr != NULL);
  85. furi_hal_interrupt_disable(index);
  86. }
  87. furi_hal_interrupt_isr[index].isr = isr;
  88. furi_hal_interrupt_isr[index].context = context;
  89. __DMB();
  90. if(isr) {
  91. // Post ISR set
  92. furi_hal_interrupt_enable(index, priority);
  93. } else {
  94. // Post ISR clear
  95. }
  96. }
  97. /* Timer 2 */
  98. void TIM2_IRQHandler(void) {
  99. furi_hal_interrupt_call(FuriHalInterruptIdTIM2);
  100. }
  101. /* Timer 1 Update */
  102. void TIM1_UP_TIM16_IRQHandler(void) {
  103. furi_hal_interrupt_call(FuriHalInterruptIdTim1UpTim16);
  104. }
  105. void TIM1_TRG_COM_TIM17_IRQHandler(void) {
  106. furi_hal_interrupt_call(FuriHalInterruptIdTim1TrgComTim17);
  107. }
  108. void TIM1_CC_IRQHandler(void) {
  109. furi_hal_interrupt_call(FuriHalInterruptIdTim1Cc);
  110. }
  111. /* DMA 1 */
  112. void DMA1_Channel1_IRQHandler(void) {
  113. furi_hal_interrupt_call(FuriHalInterruptIdDma1Ch1);
  114. }
  115. void DMA1_Channel2_IRQHandler(void) {
  116. furi_hal_interrupt_call(FuriHalInterruptIdDma1Ch2);
  117. }
  118. void DMA1_Channel3_IRQHandler(void) {
  119. furi_hal_interrupt_call(FuriHalInterruptIdDma1Ch3);
  120. }
  121. void DMA1_Channel4_IRQHandler(void) {
  122. furi_hal_interrupt_call(FuriHalInterruptIdDma1Ch4);
  123. }
  124. void DMA1_Channel5_IRQHandler(void) {
  125. furi_hal_interrupt_call(FuriHalInterruptIdDma1Ch5);
  126. }
  127. void DMA1_Channel6_IRQHandler(void) {
  128. furi_hal_interrupt_call(FuriHalInterruptIdDma1Ch6);
  129. }
  130. void DMA1_Channel7_IRQHandler(void) {
  131. furi_hal_interrupt_call(FuriHalInterruptIdDma1Ch7);
  132. }
  133. /* DMA 2 */
  134. void DMA2_Channel1_IRQHandler(void) {
  135. furi_hal_interrupt_call(FuriHalInterruptIdDma2Ch1);
  136. }
  137. void DMA2_Channel2_IRQHandler(void) {
  138. furi_hal_interrupt_call(FuriHalInterruptIdDma2Ch2);
  139. }
  140. void DMA2_Channel3_IRQHandler(void) {
  141. furi_hal_interrupt_call(FuriHalInterruptIdDma2Ch3);
  142. }
  143. void DMA2_Channel4_IRQHandler(void) {
  144. furi_hal_interrupt_call(FuriHalInterruptIdDma2Ch4);
  145. }
  146. void DMA2_Channel5_IRQHandler(void) {
  147. furi_hal_interrupt_call(FuriHalInterruptIdDma2Ch5);
  148. }
  149. void DMA2_Channel6_IRQHandler(void) {
  150. furi_hal_interrupt_call(FuriHalInterruptIdDma2Ch6);
  151. }
  152. void DMA2_Channel7_IRQHandler(void) {
  153. furi_hal_interrupt_call(FuriHalInterruptIdDma2Ch7);
  154. }
  155. void HSEM_IRQHandler(void) {
  156. furi_hal_interrupt_call(FuriHalInterruptIdHsem);
  157. }
  158. void TAMP_STAMP_LSECSS_IRQHandler(void) {
  159. if(LL_RCC_IsActiveFlag_LSECSS()) {
  160. LL_RCC_ClearFlag_LSECSS();
  161. if(!LL_RCC_LSE_IsReady()) {
  162. FURI_LOG_E(TAG, "LSE CSS fired: resetting system");
  163. NVIC_SystemReset();
  164. } else {
  165. FURI_LOG_E(TAG, "LSE CSS fired: but LSE is alive");
  166. }
  167. }
  168. }
  169. void RCC_IRQHandler(void) {
  170. furi_hal_interrupt_call(FuriHalInterruptIdRcc);
  171. }
  172. void NMI_Handler(void) {
  173. if(LL_RCC_IsActiveFlag_HSECSS()) {
  174. LL_RCC_ClearFlag_HSECSS();
  175. FURI_LOG_E(TAG, "HSE CSS fired: resetting system");
  176. NVIC_SystemReset();
  177. }
  178. }
  179. void HardFault_Handler(void) {
  180. furi_crash("HardFault");
  181. }
  182. void MemManage_Handler(void) {
  183. furi_crash("MemManage");
  184. }
  185. void BusFault_Handler(void) {
  186. furi_crash("BusFault");
  187. }
  188. void UsageFault_Handler(void) {
  189. furi_crash("UsageFault");
  190. }
  191. void DebugMon_Handler(void) {
  192. }
  193. #include "usbd_core.h"
  194. extern usbd_device udev;
  195. extern void HW_IPCC_Tx_Handler();
  196. extern void HW_IPCC_Rx_Handler();
  197. void SysTick_Handler(void) {
  198. furi_hal_os_tick();
  199. }
  200. void USB_LP_IRQHandler(void) {
  201. #ifndef FURI_RAM_EXEC
  202. usbd_poll(&udev);
  203. #endif
  204. }
  205. void IPCC_C1_TX_IRQHandler(void) {
  206. HW_IPCC_Tx_Handler();
  207. }
  208. void IPCC_C1_RX_IRQHandler(void) {
  209. HW_IPCC_Rx_Handler();
  210. }