ICM42688P_regs.h 6.3 KB

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  1. #pragma once
  2. #define ICM42688_WHOAMI 0x47
  3. // Bank 0
  4. #define ICM42688_DEVICE_CONFIG 0x11
  5. #define ICM42688_DRIVE_CONFIG 0x13
  6. #define ICM42688_INT_CONFIG 0x14
  7. #define ICM42688_FIFO_CONFIG 0x16
  8. #define ICM42688_TEMP_DATA1 0x1D
  9. #define ICM42688_TEMP_DATA0 0x1E
  10. #define ICM42688_ACCEL_DATA_X1 0x1F
  11. #define ICM42688_ACCEL_DATA_X0 0x20
  12. #define ICM42688_ACCEL_DATA_Y1 0x21
  13. #define ICM42688_ACCEL_DATA_Y0 0x22
  14. #define ICM42688_ACCEL_DATA_Z1 0x23
  15. #define ICM42688_ACCEL_DATA_Z0 0x24
  16. #define ICM42688_GYRO_DATA_X1 0x25
  17. #define ICM42688_GYRO_DATA_X0 0x26
  18. #define ICM42688_GYRO_DATA_Y1 0x27
  19. #define ICM42688_GYRO_DATA_Y0 0x28
  20. #define ICM42688_GYRO_DATA_Z1 0x29
  21. #define ICM42688_GYRO_DATA_Z0 0x2A
  22. #define ICM42688_TMST_FSYNCH 0x2B
  23. #define ICM42688_TMST_FSYNCL 0x2C
  24. #define ICM42688_INT_STATUS 0x2D
  25. #define ICM42688_FIFO_COUNTH 0x2E
  26. #define ICM42688_FIFO_COUNTL 0x2F
  27. #define ICM42688_FIFO_DATA 0x30
  28. #define ICM42688_APEX_DATA0 0x31
  29. #define ICM42688_APEX_DATA1 0x32
  30. #define ICM42688_APEX_DATA2 0x33
  31. #define ICM42688_APEX_DATA3 0x34
  32. #define ICM42688_APEX_DATA4 0x35
  33. #define ICM42688_APEX_DATA5 0x36
  34. #define ICM42688_INT_STATUS2 0x37
  35. #define ICM42688_INT_STATUS3 0x38
  36. #define ICM42688_SIGNAL_PATH_RESET 0x4B
  37. #define ICM42688_INTF_CONFIG0 0x4C
  38. #define ICM42688_INTF_CONFIG1 0x4D
  39. #define ICM42688_PWR_MGMT0 0x4E
  40. #define ICM42688_GYRO_CONFIG0 0x4F
  41. #define ICM42688_ACCEL_CONFIG0 0x50
  42. #define ICM42688_GYRO_CONFIG1 0x51
  43. #define ICM42688_GYRO_ACCEL_CONFIG0 0x52
  44. #define ICM42688_ACCEL_CONFIG1 0x53
  45. #define ICM42688_TMST_CONFIG 0x54
  46. #define ICM42688_APEX_CONFIG0 0x56
  47. #define ICM42688_SMD_CONFIG 0x57
  48. #define ICM42688_FIFO_CONFIG1 0x5F
  49. #define ICM42688_FIFO_CONFIG2 0x60
  50. #define ICM42688_FIFO_CONFIG3 0x61
  51. #define ICM42688_FSYNC_CONFIG 0x62
  52. #define ICM42688_INT_CONFIG0 0x63
  53. #define ICM42688_INT_CONFIG1 0x64
  54. #define ICM42688_INT_SOURCE0 0x65
  55. #define ICM42688_INT_SOURCE1 0x66
  56. #define ICM42688_INT_SOURCE3 0x68
  57. #define ICM42688_INT_SOURCE4 0x69
  58. #define ICM42688_FIFO_LOST_PKT0 0x6C
  59. #define ICM42688_FIFO_LOST_PKT1 0x6D
  60. #define ICM42688_SELF_TEST_CONFIG 0x70
  61. #define ICM42688_WHO_AM_I 0x75
  62. #define ICM42688_REG_BANK_SEL 0x76
  63. // Bank 1
  64. #define ICM42688_SENSOR_CONFIG0 0x03
  65. #define ICM42688_GYRO_CONFIG_STATIC2 0x0B
  66. #define ICM42688_GYRO_CONFIG_STATIC3 0x0C
  67. #define ICM42688_GYRO_CONFIG_STATIC4 0x0D
  68. #define ICM42688_GYRO_CONFIG_STATIC5 0x0E
  69. #define ICM42688_GYRO_CONFIG_STATIC6 0x0F
  70. #define ICM42688_GYRO_CONFIG_STATIC7 0x10
  71. #define ICM42688_GYRO_CONFIG_STATIC8 0x11
  72. #define ICM42688_GYRO_CONFIG_STATIC9 0x12
  73. #define ICM42688_GYRO_CONFIG_STATIC10 0x13
  74. #define ICM42688_XG_ST_DATA 0x5F
  75. #define ICM42688_YG_ST_DATA 0x60
  76. #define ICM42688_ZG_ST_DATA 0x61
  77. #define ICM42688_TMSTVAL0 0x62
  78. #define ICM42688_TMSTVAL1 0x63
  79. #define ICM42688_TMSTVAL2 0x64
  80. #define ICM42688_INTF_CONFIG4 0x7A
  81. #define ICM42688_INTF_CONFIG5 0x7B
  82. #define ICM42688_INTF_CONFIG6 0x7C
  83. // Bank 2
  84. #define ICM42688_ACCEL_CONFIG_STATIC2 0x03
  85. #define ICM42688_ACCEL_CONFIG_STATIC3 0x04
  86. #define ICM42688_ACCEL_CONFIG_STATIC4 0x05
  87. #define ICM42688_XA_ST_DATA 0x3B
  88. #define ICM42688_YA_ST_DATA 0x3C
  89. #define ICM42688_ZA_ST_DATA 0x3D
  90. // Bank 4
  91. #define ICM42688_APEX_CONFIG1 0x40
  92. #define ICM42688_APEX_CONFIG2 0x41
  93. #define ICM42688_APEX_CONFIG3 0x42
  94. #define ICM42688_APEX_CONFIG4 0x43
  95. #define ICM42688_APEX_CONFIG5 0x44
  96. #define ICM42688_APEX_CONFIG6 0x45
  97. #define ICM42688_APEX_CONFIG7 0x46
  98. #define ICM42688_APEX_CONFIG8 0x47
  99. #define ICM42688_APEX_CONFIG9 0x48
  100. #define ICM42688_ACCEL_WOM_X_THR 0x4A
  101. #define ICM42688_ACCEL_WOM_Y_THR 0x4B
  102. #define ICM42688_ACCEL_WOM_Z_THR 0x4C
  103. #define ICM42688_INT_SOURCE6 0x4D
  104. #define ICM42688_INT_SOURCE7 0x4E
  105. #define ICM42688_INT_SOURCE8 0x4F
  106. #define ICM42688_INT_SOURCE9 0x50
  107. #define ICM42688_INT_SOURCE10 0x51
  108. #define ICM42688_OFFSET_USER0 0x77
  109. #define ICM42688_OFFSET_USER1 0x78
  110. #define ICM42688_OFFSET_USER2 0x79
  111. #define ICM42688_OFFSET_USER3 0x7A
  112. #define ICM42688_OFFSET_USER4 0x7B
  113. #define ICM42688_OFFSET_USER5 0x7C
  114. #define ICM42688_OFFSET_USER6 0x7D
  115. #define ICM42688_OFFSET_USER7 0x7E
  116. #define ICM42688_OFFSET_USER8 0x7F
  117. // PWR_MGMT0
  118. #define ICM42688_PWR_TEMP_ON (0 << 5)
  119. #define ICM42688_PWR_TEMP_OFF (1 << 5)
  120. #define ICM42688_PWR_IDLE (1 << 4)
  121. #define ICM42688_PWR_GYRO_MODE_OFF (0 << 2)
  122. #define ICM42688_PWR_GYRO_MODE_LN (3 << 2)
  123. #define ICM42688_PWR_ACCEL_MODE_OFF (0 << 0)
  124. #define ICM42688_PWR_ACCEL_MODE_LP (2 << 0)
  125. #define ICM42688_PWR_ACCEL_MODE_LN (3 << 0)
  126. // GYRO_CONFIG0
  127. #define ICM42688_GFS_2000DPS (0x00 << 5)
  128. #define ICM42688_GFS_1000DPS (0x01 << 5)
  129. #define ICM42688_GFS_500DPS (0x02 << 5)
  130. #define ICM42688_GFS_250DPS (0x03 << 5)
  131. #define ICM42688_GFS_125DPS (0x04 << 5)
  132. #define ICM42688_GFS_62_5DPS (0x05 << 5)
  133. #define ICM42688_GFS_31_25DPS (0x06 << 5)
  134. #define ICM42688_GFS_15_625DPS (0x07 << 5)
  135. #define ICM42688_GODR_32kHz 0x01
  136. #define ICM42688_GODR_16kHz 0x02
  137. #define ICM42688_GODR_8kHz 0x03
  138. #define ICM42688_GODR_4kHz 0x04
  139. #define ICM42688_GODR_2kHz 0x05
  140. #define ICM42688_GODR_1kHz 0x06
  141. #define ICM42688_GODR_200Hz 0x07
  142. #define ICM42688_GODR_100Hz 0x08
  143. #define ICM42688_GODR_50Hz 0x09
  144. #define ICM42688_GODR_25Hz 0x0A
  145. #define ICM42688_GODR_12_5Hz 0x0B
  146. #define ICM42688_GODR_500Hz 0x0F
  147. // ACCEL_CONFIG0
  148. #define ICM42688_AFS_16G (0x00 << 5)
  149. #define ICM42688_AFS_8G (0x01 << 5)
  150. #define ICM42688_AFS_4G (0x02 << 5)
  151. #define ICM42688_AFS_2G (0x03 << 5)
  152. #define ICM42688_AODR_32kHz 0x01
  153. #define ICM42688_AODR_16kHz 0x02
  154. #define ICM42688_AODR_8kHz 0x03
  155. #define ICM42688_AODR_4kHz 0x04
  156. #define ICM42688_AODR_2kHz 0x05
  157. #define ICM42688_AODR_1kHz 0x06
  158. #define ICM42688_AODR_200Hz 0x07
  159. #define ICM42688_AODR_100Hz 0x08
  160. #define ICM42688_AODR_50Hz 0x09
  161. #define ICM42688_AODR_25Hz 0x0A
  162. #define ICM42688_AODR_12_5Hz 0x0B
  163. #define ICM42688_AODR_6_25Hz 0x0C
  164. #define ICM42688_AODR_3_125Hz 0x0D
  165. #define ICM42688_AODR_1_5625Hz 0x0E
  166. #define ICM42688_AODR_500Hz 0x0F