imu_lsm6dso.c 3.3 KB

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  1. #include "imu_lsm6dso.h"
  2. stmdev_ctx_t lsm6dso_ctx;
  3. int32_t lsm6dso_write_i2c(void* handle, uint8_t reg_addr, uint8_t* data, uint16_t len) {
  4. if(furi_hal_i2c_write_mem(handle, LSM6DSO_ADDRESS, reg_addr, data, len, 50))
  5. return 0;
  6. return -2;
  7. }
  8. int32_t lsm6dso_read_i2c(void* handle, uint8_t reg_addr, uint8_t* read_data, uint16_t len) {
  9. if(furi_hal_i2c_read_mem(handle, LSM6DSO_ADDRESS, reg_addr, read_data, len, 50))
  10. return 0;
  11. return -2;
  12. }
  13. void lsm6dso_scan_i2c() {
  14. unsigned int address;
  15. for(address = 1; address < 0xff; address++) {
  16. if(!furi_hal_i2c_is_device_ready(&furi_hal_i2c_handle_external, address, 50)) {
  17. FURI_LOG_E(LSM6DSO_TAG, "No answer on ID 0x%X", address);
  18. } else {
  19. FURI_LOG_E(LSM6DSO_TAG, "<<<<<<<found Device>>>>>>> ID 0x%X", address);
  20. }
  21. }
  22. }
  23. bool lsm6dso_begin() {
  24. FURI_LOG_I(LSM6DSO_TAG, "Init LSM6DSOTR-C");
  25. if(!furi_hal_i2c_is_device_ready(&furi_hal_i2c_handle_external, LSM6DSO_ADDRESS, 50)) {
  26. FURI_LOG_E(LSM6DSO_TAG, "Not ready");
  27. return false;
  28. }
  29. lsm6dso_ctx.write_reg = lsm6dso_write_i2c;
  30. lsm6dso_ctx.read_reg = lsm6dso_read_i2c;
  31. lsm6dso_ctx.mdelay = furi_delay_ms;
  32. lsm6dso_ctx.handle = &furi_hal_i2c_handle_external;
  33. uint8_t whoami;
  34. lsm6dso_device_id_get(&lsm6dso_ctx, &whoami);
  35. if(whoami != LSM6DSO_ID) {
  36. FURI_LOG_I(LSM6DSO_TAG, "Unknown model: %x", (int)whoami);
  37. return false;
  38. }
  39. lsm6dso_reset_set(&lsm6dso_ctx, PROPERTY_ENABLE);
  40. uint8_t rst = PROPERTY_ENABLE;
  41. while(rst) lsm6dso_reset_get(&lsm6dso_ctx, &rst);
  42. lsm6dso_block_data_update_set(&lsm6dso_ctx, PROPERTY_ENABLE);
  43. lsm6dso_fifo_mode_set(&lsm6dso_ctx, LSM6DSO_BYPASS_MODE);
  44. lsm6dso_xl_data_rate_set(&lsm6dso_ctx, LSM6DSO_XL_ODR_104Hz);
  45. lsm6dso_xl_full_scale_set(&lsm6dso_ctx, LSM6DSO_4g);
  46. //lsm6dso_xl_lp1_bandwidth_set(&lsm6dso_ctx, LSM6DSO_XL_LP1_ODR_DIV_4);
  47. //lsm6dso_aux_gy_lp1_bandwidth_set() ???
  48. lsm6dso_gy_data_rate_set(&lsm6dso_ctx, LSM6DSO_GY_ODR_104Hz);
  49. lsm6dso_gy_full_scale_set(&lsm6dso_ctx, LSM6DSO_2000dps);
  50. lsm6dso_gy_power_mode_set(&lsm6dso_ctx, LSM6DSO_GY_HIGH_PERFORMANCE);
  51. //lsm6dso_gy_band_pass_set(&lsm6dso_ctx, LSM6DSO_LP2_ONLY);
  52. FURI_LOG_I(LSM6DSO_TAG, "Init OK");
  53. return true;
  54. }
  55. void lsm6dso_end() {
  56. lsm6dso_xl_data_rate_set(&lsm6dso_ctx, LSM6DSO_XL_ODR_OFF);
  57. lsm6dso_gy_data_rate_set(&lsm6dso_ctx, LSM6DSO_GY_ODR_OFF);
  58. }
  59. int lsm6dso_read(double* vec) {
  60. int ret = 0;
  61. int16_t data[3];
  62. lsm6dso_reg_t reg;
  63. lsm6dso_status_reg_get(&lsm6dso_ctx, &reg.status_reg);
  64. if(reg.status_reg.xlda) {
  65. lsm6dso_acceleration_raw_get(&lsm6dso_ctx, data);
  66. vec[2] = (double)lsm6dso_from_fs2_to_mg(data[0]) / 1000;
  67. vec[0] = (double)lsm6dso_from_fs2_to_mg(data[1]) / 1000;
  68. vec[1] = (double)lsm6dso_from_fs2_to_mg(data[2]) / 1000;
  69. ret |= ACC_DATA_READY;
  70. }
  71. if(reg.status_reg.gda) {
  72. lsm6dso_angular_rate_raw_get(&lsm6dso_ctx, data);
  73. vec[5] = (double)lsm6dso_from_fs2000_to_mdps(data[0]) * LSM6DSO_DEG_TO_RAD / 1000;
  74. vec[3] = (double)lsm6dso_from_fs2000_to_mdps(data[1]) * LSM6DSO_DEG_TO_RAD / 1000;
  75. vec[4] = (double)lsm6dso_from_fs2000_to_mdps(data[2]) * LSM6DSO_DEG_TO_RAD / 1000;
  76. ret |= GYR_DATA_READY;
  77. }
  78. return ret;
  79. }