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usbhs.h

usbhs.h 27 KB
Cronologia Originale

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  1. /**
    2. 

  2.  * \file
    3. 

  3.  *
    4. 

  4.  * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
    5. 

  5.  *
    6. 

  6.  * \asf_license_start
    7. 

  7.  *
    8. 

  8.  * \page License
    9. 

  9.  *
    10. 

  10.  * Subject to your compliance with these terms, you may use Microchip
    11. 

  11.  * software and any derivatives exclusively with Microchip products.
    12. 

  12.  * It is your responsibility to comply with third party license terms applicable
    13. 

  13.  * to your use of third party software (including open source software) that
    14. 

  14.  * may accompany Microchip software.
    15. 

  15.  *
    16. 

  16.  * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
    17. 

  17.  * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
    18. 

  18.  * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
    19. 

  19.  * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
    20. 

  20.  * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
    21. 

  21.  * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
    22. 

  22.  * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
    23. 

  23.  * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
    24. 

  24.  * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
    25. 

  25.  * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
    26. 

  26.  * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
    27. 

  27.  *
    28. 

  28.  * \asf_license_stop
    29. 

  29.  *
    30. 

  30.  */
    31. 

  31. /*
    32. 

  32.  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
    33. 

  33.  */
    34. 

  34. 

  35. #ifndef _SAME70_USBHS_INSTANCE_
    36. 

  36. #define _SAME70_USBHS_INSTANCE_
    37. 

  37. 

  38. /* ========== Register definition for USBHS peripheral ========== */
    39. 

  39. #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
    40. 

  40.   #define REG_USBHS_DEVCTRL                         (0x40038000U) /**< \brief (USBHS) Device General Control Register */
    41. 

  41.   #define REG_USBHS_DEVISR                          (0x40038004U) /**< \brief (USBHS) Device Global Interrupt Status Register */
    42. 

  42.   #define REG_USBHS_DEVICR                          (0x40038008U) /**< \brief (USBHS) Device Global Interrupt Clear Register */
    43. 

  43.   #define REG_USBHS_DEVIFR                          (0x4003800CU) /**< \brief (USBHS) Device Global Interrupt Set Register */
    44. 

  44.   #define REG_USBHS_DEVIMR                          (0x40038010U) /**< \brief (USBHS) Device Global Interrupt Mask Register */
    45. 

  45.   #define REG_USBHS_DEVIDR                          (0x40038014U) /**< \brief (USBHS) Device Global Interrupt Disable Register */
    46. 

  46.   #define REG_USBHS_DEVIER                          (0x40038018U) /**< \brief (USBHS) Device Global Interrupt Enable Register */
    47. 

  47.   #define REG_USBHS_DEVEPT                          (0x4003801CU) /**< \brief (USBHS) Device Endpoint Register */
    48. 

  48.   #define REG_USBHS_DEVFNUM                         (0x40038020U) /**< \brief (USBHS) Device Frame Number Register */
    49. 

  49.   #define REG_USBHS_DEVEPTCFG                       (0x40038100U) /**< \brief (USBHS) Device Endpoint Configuration Register (n = 0) */
    50. 

  50.   #define REG_USBHS_DEVEPTISR                       (0x40038130U) /**< \brief (USBHS) Device Endpoint Status Register (n = 0) */
    51. 

  51.   #define REG_USBHS_DEVEPTICR                       (0x40038160U) /**< \brief (USBHS) Device Endpoint Clear Register (n = 0) */
    52. 

  52.   #define REG_USBHS_DEVEPTIFR                       (0x40038190U) /**< \brief (USBHS) Device Endpoint Set Register (n = 0) */
    53. 

  53.   #define REG_USBHS_DEVEPTIMR                       (0x400381C0U) /**< \brief (USBHS) Device Endpoint Mask Register (n = 0) */
    54. 

  54.   #define REG_USBHS_DEVEPTIER                       (0x400381F0U) /**< \brief (USBHS) Device Endpoint Enable Register (n = 0) */
    55. 

  55.   #define REG_USBHS_DEVEPTIDR                       (0x40038220U) /**< \brief (USBHS) Device Endpoint Disable Register (n = 0) */
    56. 

  56.   #define REG_USBHS_DEVDMANXTDSC1                   (0x40038310U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) */
    57. 

  57.   #define REG_USBHS_DEVDMAADDRESS1                  (0x40038314U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 1) */
    58. 

  58.   #define REG_USBHS_DEVDMACONTROL1                  (0x40038318U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 1) */
    59. 

  59.   #define REG_USBHS_DEVDMASTATUS1                   (0x4003831CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 1) */
    60. 

  60.   #define REG_USBHS_DEVDMANXTDSC2                   (0x40038320U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 2) */
    61. 

  61.   #define REG_USBHS_DEVDMAADDRESS2                  (0x40038324U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 2) */
    62. 

  62.   #define REG_USBHS_DEVDMACONTROL2                  (0x40038328U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 2) */
    63. 

  63.   #define REG_USBHS_DEVDMASTATUS2                   (0x4003832CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 2) */
    64. 

  64.   #define REG_USBHS_DEVDMANXTDSC3                   (0x40038330U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 3) */
    65. 

  65.   #define REG_USBHS_DEVDMAADDRESS3                  (0x40038334U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 3) */
    66. 

  66.   #define REG_USBHS_DEVDMACONTROL3                  (0x40038338U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 3) */
    67. 

  67.   #define REG_USBHS_DEVDMASTATUS3                   (0x4003833CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 3) */
    68. 

  68.   #define REG_USBHS_DEVDMANXTDSC4                   (0x40038340U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 4) */
    69. 

  69.   #define REG_USBHS_DEVDMAADDRESS4                  (0x40038344U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 4) */
    70. 

  70.   #define REG_USBHS_DEVDMACONTROL4                  (0x40038348U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 4) */
    71. 

  71.   #define REG_USBHS_DEVDMASTATUS4                   (0x4003834CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 4) */
    72. 

  72.   #define REG_USBHS_DEVDMANXTDSC5                   (0x40038350U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 5) */
    73. 

  73.   #define REG_USBHS_DEVDMAADDRESS5                  (0x40038354U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 5) */
    74. 

  74.   #define REG_USBHS_DEVDMACONTROL5                  (0x40038358U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 5) */
    75. 

  75.   #define REG_USBHS_DEVDMASTATUS5                   (0x4003835CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 5) */
    76. 

  76.   #define REG_USBHS_DEVDMANXTDSC6                   (0x40038360U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 6) */
    77. 

  77.   #define REG_USBHS_DEVDMAADDRESS6                  (0x40038364U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 6) */
    78. 

  78.   #define REG_USBHS_DEVDMACONTROL6                  (0x40038368U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 6) */
    79. 

  79.   #define REG_USBHS_DEVDMASTATUS6                   (0x4003836CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 6) */
    80. 

  80.   #define REG_USBHS_DEVDMANXTDSC7                   (0x40038370U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 7) */
    81. 

  81.   #define REG_USBHS_DEVDMAADDRESS7                  (0x40038374U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 7) */
    82. 

  82.   #define REG_USBHS_DEVDMACONTROL7                  (0x40038378U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 7) */
    83. 

  83.   #define REG_USBHS_DEVDMASTATUS7                   (0x4003837CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 7) */
    84. 

  84.   #define REG_USBHS_HSTCTRL                         (0x40038400U) /**< \brief (USBHS) Host General Control Register */
    85. 

  85.   #define REG_USBHS_HSTISR                          (0x40038404U) /**< \brief (USBHS) Host Global Interrupt Status Register */
    86. 

  86.   #define REG_USBHS_HSTICR                          (0x40038408U) /**< \brief (USBHS) Host Global Interrupt Clear Register */
    87. 

  87.   #define REG_USBHS_HSTIFR                          (0x4003840CU) /**< \brief (USBHS) Host Global Interrupt Set Register */
    88. 

  88.   #define REG_USBHS_HSTIMR                          (0x40038410U) /**< \brief (USBHS) Host Global Interrupt Mask Register */
    89. 

  89.   #define REG_USBHS_HSTIDR                          (0x40038414U) /**< \brief (USBHS) Host Global Interrupt Disable Register */
    90. 

  90.   #define REG_USBHS_HSTIER                          (0x40038418U) /**< \brief (USBHS) Host Global Interrupt Enable Register */
    91. 

  91.   #define REG_USBHS_HSTPIP                          (0x4003841CU) /**< \brief (USBHS) Host Pipe Register */
    92. 

  92.   #define REG_USBHS_HSTFNUM                         (0x40038420U) /**< \brief (USBHS) Host Frame Number Register */
    93. 

  93.   #define REG_USBHS_HSTADDR1                        (0x40038424U) /**< \brief (USBHS) Host Address 1 Register */
    94. 

  94.   #define REG_USBHS_HSTADDR2                        (0x40038428U) /**< \brief (USBHS) Host Address 2 Register */
    95. 

  95.   #define REG_USBHS_HSTADDR3                        (0x4003842CU) /**< \brief (USBHS) Host Address 3 Register */
    96. 

  96.   #define REG_USBHS_HSTPIPCFG                       (0x40038500U) /**< \brief (USBHS) Host Pipe Configuration Register (n = 0) */
    97. 

  97.   #define REG_USBHS_HSTPIPISR                       (0x40038530U) /**< \brief (USBHS) Host Pipe Status Register (n = 0) */
    98. 

  98.   #define REG_USBHS_HSTPIPICR                       (0x40038560U) /**< \brief (USBHS) Host Pipe Clear Register (n = 0) */
    99. 

  99.   #define REG_USBHS_HSTPIPIFR                       (0x40038590U) /**< \brief (USBHS) Host Pipe Set Register (n = 0) */
    100. 

  100.   #define REG_USBHS_HSTPIPIMR                       (0x400385C0U) /**< \brief (USBHS) Host Pipe Mask Register (n = 0) */
    101. 

  101.   #define REG_USBHS_HSTPIPIER                       (0x400385F0U) /**< \brief (USBHS) Host Pipe Enable Register (n = 0) */
    102. 

  102.   #define REG_USBHS_HSTPIPIDR                       (0x40038620U) /**< \brief (USBHS) Host Pipe Disable Register (n = 0) */
    103. 

  103.   #define REG_USBHS_HSTPIPINRQ                      (0x40038650U) /**< \brief (USBHS) Host Pipe IN Request Register (n = 0) */
    104. 

  104.   #define REG_USBHS_HSTPIPERR                       (0x40038680U) /**< \brief (USBHS) Host Pipe Error Register (n = 0) */
    105. 

  105.   #define REG_USBHS_HSTDMANXTDSC1                   (0x40038710U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) */
    106. 

  106.   #define REG_USBHS_HSTDMAADDRESS1                  (0x40038714U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 1) */
    107. 

  107.   #define REG_USBHS_HSTDMACONTROL1                  (0x40038718U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 1) */
    108. 

  108.   #define REG_USBHS_HSTDMASTATUS1                   (0x4003871CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 1) */
    109. 

  109.   #define REG_USBHS_HSTDMANXTDSC2                   (0x40038720U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 2) */
    110. 

  110.   #define REG_USBHS_HSTDMAADDRESS2                  (0x40038724U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 2) */
    111. 

  111.   #define REG_USBHS_HSTDMACONTROL2                  (0x40038728U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 2) */
    112. 

  112.   #define REG_USBHS_HSTDMASTATUS2                   (0x4003872CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 2) */
    113. 

  113.   #define REG_USBHS_HSTDMANXTDSC3                   (0x40038730U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 3) */
    114. 

  114.   #define REG_USBHS_HSTDMAADDRESS3                  (0x40038734U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 3) */
    115. 

  115.   #define REG_USBHS_HSTDMACONTROL3                  (0x40038738U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 3) */
    116. 

  116.   #define REG_USBHS_HSTDMASTATUS3                   (0x4003873CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 3) */
    117. 

  117.   #define REG_USBHS_HSTDMANXTDSC4                   (0x40038740U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 4) */
    118. 

  118.   #define REG_USBHS_HSTDMAADDRESS4                  (0x40038744U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 4) */
    119. 

  119.   #define REG_USBHS_HSTDMACONTROL4                  (0x40038748U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 4) */
    120. 

  120.   #define REG_USBHS_HSTDMASTATUS4                   (0x4003874CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 4) */
    121. 

  121.   #define REG_USBHS_HSTDMANXTDSC5                   (0x40038750U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 5) */
    122. 

  122.   #define REG_USBHS_HSTDMAADDRESS5                  (0x40038754U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 5) */
    123. 

  123.   #define REG_USBHS_HSTDMACONTROL5                  (0x40038758U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 5) */
    124. 

  124.   #define REG_USBHS_HSTDMASTATUS5                   (0x4003875CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 5) */
    125. 

  125.   #define REG_USBHS_HSTDMANXTDSC6                   (0x40038760U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 6) */
    126. 

  126.   #define REG_USBHS_HSTDMAADDRESS6                  (0x40038764U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 6) */
    127. 

  127.   #define REG_USBHS_HSTDMACONTROL6                  (0x40038768U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 6) */
    128. 

  128.   #define REG_USBHS_HSTDMASTATUS6                   (0x4003876CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 6) */
    129. 

  129.   #define REG_USBHS_HSTDMANXTDSC7                   (0x40038770U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 7) */
    130. 

  130.   #define REG_USBHS_HSTDMAADDRESS7                  (0x40038774U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 7) */
    131. 

  131.   #define REG_USBHS_HSTDMACONTROL7                  (0x40038778U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 7) */
    132. 

  132.   #define REG_USBHS_HSTDMASTATUS7                   (0x4003877CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 7) */
    133. 

  133.   #define REG_USBHS_CTRL                            (0x40038800U) /**< \brief (USBHS) General Control Register */
    134. 

  134.   #define REG_USBHS_SR                              (0x40038804U) /**< \brief (USBHS) General Status Register */
    135. 

  135.   #define REG_USBHS_SCR                             (0x40038808U) /**< \brief (USBHS) General Status Clear Register */
    136. 

  136.   #define REG_USBHS_SFR                             (0x4003880CU) /**< \brief (USBHS) General Status Set Register */
    137. 

  137.   #define REG_USBHS_TSTA1                           (0x40038810U) /**< \brief (USBHS) General Test A1 Register */
    138. 

  138.   #define REG_USBHS_TSTA2                           (0x40038814U) /**< \brief (USBHS) General Test A2 Register */
    139. 

  139.   #define REG_USBHS_VERSION                         (0x40038818U) /**< \brief (USBHS) General Version Register */
    140. 

  140.   #define REG_USBHS_FSM                             (0x4003882CU) /**< \brief (USBHS) General Finite State Machine Register */
    141. 

  141. #else
    142. 

  142.   #define REG_USBHS_DEVCTRL        (*(__IO uint32_t*)0x40038000U) /**< \brief (USBHS) Device General Control Register */
    143. 

  143.   #define REG_USBHS_DEVISR         (*(__I  uint32_t*)0x40038004U) /**< \brief (USBHS) Device Global Interrupt Status Register */
    144. 

  144.   #define REG_USBHS_DEVICR         (*(__O  uint32_t*)0x40038008U) /**< \brief (USBHS) Device Global Interrupt Clear Register */
    145. 

  145.   #define REG_USBHS_DEVIFR         (*(__O  uint32_t*)0x4003800CU) /**< \brief (USBHS) Device Global Interrupt Set Register */
    146. 

  146.   #define REG_USBHS_DEVIMR         (*(__I  uint32_t*)0x40038010U) /**< \brief (USBHS) Device Global Interrupt Mask Register */
    147. 

  147.   #define REG_USBHS_DEVIDR         (*(__O  uint32_t*)0x40038014U) /**< \brief (USBHS) Device Global Interrupt Disable Register */
    148. 

  148.   #define REG_USBHS_DEVIER         (*(__O  uint32_t*)0x40038018U) /**< \brief (USBHS) Device Global Interrupt Enable Register */
    149. 

  149.   #define REG_USBHS_DEVEPT         (*(__IO uint32_t*)0x4003801CU) /**< \brief (USBHS) Device Endpoint Register */
    150. 

  150.   #define REG_USBHS_DEVFNUM        (*(__I  uint32_t*)0x40038020U) /**< \brief (USBHS) Device Frame Number Register */
    151. 

  151.   #define REG_USBHS_DEVEPTCFG      (*(__IO uint32_t*)0x40038100U) /**< \brief (USBHS) Device Endpoint Configuration Register (n = 0) */
    152. 

  152.   #define REG_USBHS_DEVEPTISR      (*(__I  uint32_t*)0x40038130U) /**< \brief (USBHS) Device Endpoint Status Register (n = 0) */
    153. 

  153.   #define REG_USBHS_DEVEPTICR      (*(__O  uint32_t*)0x40038160U) /**< \brief (USBHS) Device Endpoint Clear Register (n = 0) */
    154. 

  154.   #define REG_USBHS_DEVEPTIFR      (*(__O  uint32_t*)0x40038190U) /**< \brief (USBHS) Device Endpoint Set Register (n = 0) */
    155. 

  155.   #define REG_USBHS_DEVEPTIMR      (*(__I  uint32_t*)0x400381C0U) /**< \brief (USBHS) Device Endpoint Mask Register (n = 0) */
    156. 

  156.   #define REG_USBHS_DEVEPTIER      (*(__O  uint32_t*)0x400381F0U) /**< \brief (USBHS) Device Endpoint Enable Register (n = 0) */
    157. 

  157.   #define REG_USBHS_DEVEPTIDR      (*(__O  uint32_t*)0x40038220U) /**< \brief (USBHS) Device Endpoint Disable Register (n = 0) */
    158. 

  158.   #define REG_USBHS_DEVDMANXTDSC1  (*(__IO uint32_t*)0x40038310U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) */
    159. 

  159.   #define REG_USBHS_DEVDMAADDRESS1 (*(__IO uint32_t*)0x40038314U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 1) */
    160. 

  160.   #define REG_USBHS_DEVDMACONTROL1 (*(__IO uint32_t*)0x40038318U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 1) */
    161. 

  161.   #define REG_USBHS_DEVDMASTATUS1  (*(__IO uint32_t*)0x4003831CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 1) */
    162. 

  162.   #define REG_USBHS_DEVDMANXTDSC2  (*(__IO uint32_t*)0x40038320U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 2) */
    163. 

  163.   #define REG_USBHS_DEVDMAADDRESS2 (*(__IO uint32_t*)0x40038324U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 2) */
    164. 

  164.   #define REG_USBHS_DEVDMACONTROL2 (*(__IO uint32_t*)0x40038328U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 2) */
    165. 

  165.   #define REG_USBHS_DEVDMASTATUS2  (*(__IO uint32_t*)0x4003832CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 2) */
    166. 

  166.   #define REG_USBHS_DEVDMANXTDSC3  (*(__IO uint32_t*)0x40038330U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 3) */
    167. 

  167.   #define REG_USBHS_DEVDMAADDRESS3 (*(__IO uint32_t*)0x40038334U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 3) */
    168. 

  168.   #define REG_USBHS_DEVDMACONTROL3 (*(__IO uint32_t*)0x40038338U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 3) */
    169. 

  169.   #define REG_USBHS_DEVDMASTATUS3  (*(__IO uint32_t*)0x4003833CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 3) */
    170. 

  170.   #define REG_USBHS_DEVDMANXTDSC4  (*(__IO uint32_t*)0x40038340U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 4) */
    171. 

  171.   #define REG_USBHS_DEVDMAADDRESS4 (*(__IO uint32_t*)0x40038344U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 4) */
    172. 

  172.   #define REG_USBHS_DEVDMACONTROL4 (*(__IO uint32_t*)0x40038348U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 4) */
    173. 

  173.   #define REG_USBHS_DEVDMASTATUS4  (*(__IO uint32_t*)0x4003834CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 4) */
    174. 

  174.   #define REG_USBHS_DEVDMANXTDSC5  (*(__IO uint32_t*)0x40038350U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 5) */
    175. 

  175.   #define REG_USBHS_DEVDMAADDRESS5 (*(__IO uint32_t*)0x40038354U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 5) */
    176. 

  176.   #define REG_USBHS_DEVDMACONTROL5 (*(__IO uint32_t*)0x40038358U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 5) */
    177. 

  177.   #define REG_USBHS_DEVDMASTATUS5  (*(__IO uint32_t*)0x4003835CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 5) */
    178. 

  178.   #define REG_USBHS_DEVDMANXTDSC6  (*(__IO uint32_t*)0x40038360U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 6) */
    179. 

  179.   #define REG_USBHS_DEVDMAADDRESS6 (*(__IO uint32_t*)0x40038364U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 6) */
    180. 

  180.   #define REG_USBHS_DEVDMACONTROL6 (*(__IO uint32_t*)0x40038368U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 6) */
    181. 

  181.   #define REG_USBHS_DEVDMASTATUS6  (*(__IO uint32_t*)0x4003836CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 6) */
    182. 

  182.   #define REG_USBHS_DEVDMANXTDSC7  (*(__IO uint32_t*)0x40038370U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 7) */
    183. 

  183.   #define REG_USBHS_DEVDMAADDRESS7 (*(__IO uint32_t*)0x40038374U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 7) */
    184. 

  184.   #define REG_USBHS_DEVDMACONTROL7 (*(__IO uint32_t*)0x40038378U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 7) */
    185. 

  185.   #define REG_USBHS_DEVDMASTATUS7  (*(__IO uint32_t*)0x4003837CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 7) */
    186. 

  186.   #define REG_USBHS_HSTCTRL        (*(__IO uint32_t*)0x40038400U) /**< \brief (USBHS) Host General Control Register */
    187. 

  187.   #define REG_USBHS_HSTISR         (*(__I  uint32_t*)0x40038404U) /**< \brief (USBHS) Host Global Interrupt Status Register */
    188. 

  188.   #define REG_USBHS_HSTICR         (*(__O  uint32_t*)0x40038408U) /**< \brief (USBHS) Host Global Interrupt Clear Register */
    189. 

  189.   #define REG_USBHS_HSTIFR         (*(__O  uint32_t*)0x4003840CU) /**< \brief (USBHS) Host Global Interrupt Set Register */
    190. 

  190.   #define REG_USBHS_HSTIMR         (*(__I  uint32_t*)0x40038410U) /**< \brief (USBHS) Host Global Interrupt Mask Register */
    191. 

  191.   #define REG_USBHS_HSTIDR         (*(__O  uint32_t*)0x40038414U) /**< \brief (USBHS) Host Global Interrupt Disable Register */
    192. 

  192.   #define REG_USBHS_HSTIER         (*(__O  uint32_t*)0x40038418U) /**< \brief (USBHS) Host Global Interrupt Enable Register */
    193. 

  193.   #define REG_USBHS_HSTPIP         (*(__IO uint32_t*)0x4003841CU) /**< \brief (USBHS) Host Pipe Register */
    194. 

  194.   #define REG_USBHS_HSTFNUM        (*(__IO uint32_t*)0x40038420U) /**< \brief (USBHS) Host Frame Number Register */
    195. 

  195.   #define REG_USBHS_HSTADDR1       (*(__IO uint32_t*)0x40038424U) /**< \brief (USBHS) Host Address 1 Register */
    196. 

  196.   #define REG_USBHS_HSTADDR2       (*(__IO uint32_t*)0x40038428U) /**< \brief (USBHS) Host Address 2 Register */
    197. 

  197.   #define REG_USBHS_HSTADDR3       (*(__IO uint32_t*)0x4003842CU) /**< \brief (USBHS) Host Address 3 Register */
    198. 

  198.   #define REG_USBHS_HSTPIPCFG      (*(__IO uint32_t*)0x40038500U) /**< \brief (USBHS) Host Pipe Configuration Register (n = 0) */
    199. 

  199.   #define REG_USBHS_HSTPIPISR      (*(__I  uint32_t*)0x40038530U) /**< \brief (USBHS) Host Pipe Status Register (n = 0) */
    200. 

  200.   #define REG_USBHS_HSTPIPICR      (*(__O  uint32_t*)0x40038560U) /**< \brief (USBHS) Host Pipe Clear Register (n = 0) */
    201. 

  201.   #define REG_USBHS_HSTPIPIFR      (*(__O  uint32_t*)0x40038590U) /**< \brief (USBHS) Host Pipe Set Register (n = 0) */
    202. 

  202.   #define REG_USBHS_HSTPIPIMR      (*(__I  uint32_t*)0x400385C0U) /**< \brief (USBHS) Host Pipe Mask Register (n = 0) */
    203. 

  203.   #define REG_USBHS_HSTPIPIER      (*(__O  uint32_t*)0x400385F0U) /**< \brief (USBHS) Host Pipe Enable Register (n = 0) */
    204. 

  204.   #define REG_USBHS_HSTPIPIDR      (*(__O  uint32_t*)0x40038620U) /**< \brief (USBHS) Host Pipe Disable Register (n = 0) */
    205. 

  205.   #define REG_USBHS_HSTPIPINRQ     (*(__IO uint32_t*)0x40038650U) /**< \brief (USBHS) Host Pipe IN Request Register (n = 0) */
    206. 

  206.   #define REG_USBHS_HSTPIPERR      (*(__IO uint32_t*)0x40038680U) /**< \brief (USBHS) Host Pipe Error Register (n = 0) */
    207. 

  207.   #define REG_USBHS_HSTDMANXTDSC1  (*(__IO uint32_t*)0x40038710U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) */
    208. 

  208.   #define REG_USBHS_HSTDMAADDRESS1 (*(__IO uint32_t*)0x40038714U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 1) */
    209. 

  209.   #define REG_USBHS_HSTDMACONTROL1 (*(__IO uint32_t*)0x40038718U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 1) */
    210. 

  210.   #define REG_USBHS_HSTDMASTATUS1  (*(__IO uint32_t*)0x4003871CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 1) */
    211. 

  211.   #define REG_USBHS_HSTDMANXTDSC2  (*(__IO uint32_t*)0x40038720U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 2) */
    212. 

  212.   #define REG_USBHS_HSTDMAADDRESS2 (*(__IO uint32_t*)0x40038724U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 2) */
    213. 

  213.   #define REG_USBHS_HSTDMACONTROL2 (*(__IO uint32_t*)0x40038728U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 2) */
    214. 

  214.   #define REG_USBHS_HSTDMASTATUS2  (*(__IO uint32_t*)0x4003872CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 2) */
    215. 

  215.   #define REG_USBHS_HSTDMANXTDSC3  (*(__IO uint32_t*)0x40038730U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 3) */
    216. 

  216.   #define REG_USBHS_HSTDMAADDRESS3 (*(__IO uint32_t*)0x40038734U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 3) */
    217. 

  217.   #define REG_USBHS_HSTDMACONTROL3 (*(__IO uint32_t*)0x40038738U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 3) */
    218. 

  218.   #define REG_USBHS_HSTDMASTATUS3  (*(__IO uint32_t*)0x4003873CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 3) */
    219. 

  219.   #define REG_USBHS_HSTDMANXTDSC4  (*(__IO uint32_t*)0x40038740U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 4) */
    220. 

  220.   #define REG_USBHS_HSTDMAADDRESS4 (*(__IO uint32_t*)0x40038744U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 4) */
    221. 

  221.   #define REG_USBHS_HSTDMACONTROL4 (*(__IO uint32_t*)0x40038748U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 4) */
    222. 

  222.   #define REG_USBHS_HSTDMASTATUS4  (*(__IO uint32_t*)0x4003874CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 4) */
    223. 

  223.   #define REG_USBHS_HSTDMANXTDSC5  (*(__IO uint32_t*)0x40038750U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 5) */
    224. 

  224.   #define REG_USBHS_HSTDMAADDRESS5 (*(__IO uint32_t*)0x40038754U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 5) */
    225. 

  225.   #define REG_USBHS_HSTDMACONTROL5 (*(__IO uint32_t*)0x40038758U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 5) */
    226. 

  226.   #define REG_USBHS_HSTDMASTATUS5  (*(__IO uint32_t*)0x4003875CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 5) */
    227. 

  227.   #define REG_USBHS_HSTDMANXTDSC6  (*(__IO uint32_t*)0x40038760U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 6) */
    228. 

  228.   #define REG_USBHS_HSTDMAADDRESS6 (*(__IO uint32_t*)0x40038764U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 6) */
    229. 

  229.   #define REG_USBHS_HSTDMACONTROL6 (*(__IO uint32_t*)0x40038768U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 6) */
    230. 

  230.   #define REG_USBHS_HSTDMASTATUS6  (*(__IO uint32_t*)0x4003876CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 6) */
    231. 

  231.   #define REG_USBHS_HSTDMANXTDSC7  (*(__IO uint32_t*)0x40038770U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 7) */
    232. 

  232.   #define REG_USBHS_HSTDMAADDRESS7 (*(__IO uint32_t*)0x40038774U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 7) */
    233. 

  233.   #define REG_USBHS_HSTDMACONTROL7 (*(__IO uint32_t*)0x40038778U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 7) */
    234. 

  234.   #define REG_USBHS_HSTDMASTATUS7  (*(__IO uint32_t*)0x4003877CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 7) */
    235. 

  235.   #define REG_USBHS_CTRL           (*(__IO uint32_t*)0x40038800U) /**< \brief (USBHS) General Control Register */
    236. 

  236.   #define REG_USBHS_SR             (*(__I  uint32_t*)0x40038804U) /**< \brief (USBHS) General Status Register */
    237. 

  237.   #define REG_USBHS_SCR            (*(__O  uint32_t*)0x40038808U) /**< \brief (USBHS) General Status Clear Register */
    238. 

  238.   #define REG_USBHS_SFR            (*(__O  uint32_t*)0x4003880CU) /**< \brief (USBHS) General Status Set Register */
    239. 

  239.   #define REG_USBHS_TSTA1          (*(__IO uint32_t*)0x40038810U) /**< \brief (USBHS) General Test A1 Register */
    240. 

  240.   #define REG_USBHS_TSTA2          (*(__IO uint32_t*)0x40038814U) /**< \brief (USBHS) General Test A2 Register */
    241. 

  241.   #define REG_USBHS_VERSION        (*(__I  uint32_t*)0x40038818U) /**< \brief (USBHS) General Version Register */
    242. 

  242.   #define REG_USBHS_FSM            (*(__I  uint32_t*)0x4003882CU) /**< \brief (USBHS) General Finite State Machine Register */
    243. 

  243. #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
    244. 

  244. 

  245. #endif /* _SAME70_USBHS_INSTANCE_ */
    246.