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usart2.h

usart2.h 8.5 KB
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  1. /**
    2. 

  2.  * \file
    3. 

  3.  *
    4. 

  4.  * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
    5. 

  5.  *
    6. 

  6.  * \asf_license_start
    7. 

  7.  *
    8. 

  8.  * \page License
    9. 

  9.  *
    10. 

  10.  * Subject to your compliance with these terms, you may use Microchip
    11. 

  11.  * software and any derivatives exclusively with Microchip products.
    12. 

  12.  * It is your responsibility to comply with third party license terms applicable
    13. 

  13.  * to your use of third party software (including open source software) that
    14. 

  14.  * may accompany Microchip software.
    15. 

  15.  *
    16. 

  16.  * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
    17. 

  17.  * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
    18. 

  18.  * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
    19. 

  19.  * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
    20. 

  20.  * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
    21. 

  21.  * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
    22. 

  22.  * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
    23. 

  23.  * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
    24. 

  24.  * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
    25. 

  25.  * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
    26. 

  26.  * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
    27. 

  27.  *
    28. 

  28.  * \asf_license_stop
    29. 

  29.  *
    30. 

  30.  */
    31. 

  31. /*
    32. 

  32.  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
    33. 

  33.  */
    34. 

  34. 

  35. #ifndef _SAME70_USART2_INSTANCE_
    36. 

  36. #define _SAME70_USART2_INSTANCE_
    37. 

  37. 

  38. /* ========== Register definition for USART2 peripheral ========== */
    39. 

  39. #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
    40. 

  40.   #define REG_USART2_CR                        (0x4002C000U) /**< \brief (USART2) Control Register */
    41. 

  41.   #define REG_USART2_MR                        (0x4002C004U) /**< \brief (USART2) Mode Register */
    42. 

  42.   #define REG_USART2_IER                       (0x4002C008U) /**< \brief (USART2) Interrupt Enable Register */
    43. 

  43.   #define REG_USART2_IDR                       (0x4002C00CU) /**< \brief (USART2) Interrupt Disable Register */
    44. 

  44.   #define REG_USART2_IMR                       (0x4002C010U) /**< \brief (USART2) Interrupt Mask Register */
    45. 

  45.   #define REG_USART2_CSR                       (0x4002C014U) /**< \brief (USART2) Channel Status Register */
    46. 

  46.   #define REG_USART2_RHR                       (0x4002C018U) /**< \brief (USART2) Receive Holding Register */
    47. 

  47.   #define REG_USART2_THR                       (0x4002C01CU) /**< \brief (USART2) Transmit Holding Register */
    48. 

  48.   #define REG_USART2_BRGR                      (0x4002C020U) /**< \brief (USART2) Baud Rate Generator Register */
    49. 

  49.   #define REG_USART2_RTOR                      (0x4002C024U) /**< \brief (USART2) Receiver Time-out Register */
    50. 

  50.   #define REG_USART2_TTGR                      (0x4002C028U) /**< \brief (USART2) Transmitter Timeguard Register */
    51. 

  51.   #define REG_USART2_FIDI                      (0x4002C040U) /**< \brief (USART2) FI DI Ratio Register */
    52. 

  52.   #define REG_USART2_NER                       (0x4002C044U) /**< \brief (USART2) Number of Errors Register */
    53. 

  53.   #define REG_USART2_IF                        (0x4002C04CU) /**< \brief (USART2) IrDA Filter Register */
    54. 

  54.   #define REG_USART2_MAN                       (0x4002C050U) /**< \brief (USART2) Manchester Configuration Register */
    55. 

  55.   #define REG_USART2_LINMR                     (0x4002C054U) /**< \brief (USART2) LIN Mode Register */
    56. 

  56.   #define REG_USART2_LINIR                     (0x4002C058U) /**< \brief (USART2) LIN Identifier Register */
    57. 

  57.   #define REG_USART2_LINBRR                    (0x4002C05CU) /**< \brief (USART2) LIN Baud Rate Register */
    58. 

  58.   #define REG_USART2_LONMR                     (0x4002C060U) /**< \brief (USART2) LON Mode Register */
    59. 

  59.   #define REG_USART2_LONPR                     (0x4002C064U) /**< \brief (USART2) LON Preamble Register */
    60. 

  60.   #define REG_USART2_LONDL                     (0x4002C068U) /**< \brief (USART2) LON Data Length Register */
    61. 

  61.   #define REG_USART2_LONL2HDR                  (0x4002C06CU) /**< \brief (USART2) LON L2HDR Register */
    62. 

  62.   #define REG_USART2_LONBL                     (0x4002C070U) /**< \brief (USART2) LON Backlog Register */
    63. 

  63.   #define REG_USART2_LONB1TX                   (0x4002C074U) /**< \brief (USART2) LON Beta1 Tx Register */
    64. 

  64.   #define REG_USART2_LONB1RX                   (0x4002C078U) /**< \brief (USART2) LON Beta1 Rx Register */
    65. 

  65.   #define REG_USART2_LONPRIO                   (0x4002C07CU) /**< \brief (USART2) LON Priority Register */
    66. 

  66.   #define REG_USART2_IDTTX                     (0x4002C080U) /**< \brief (USART2) LON IDT Tx Register */
    67. 

  67.   #define REG_USART2_IDTRX                     (0x4002C084U) /**< \brief (USART2) LON IDT Rx Register */
    68. 

  68.   #define REG_USART2_ICDIFF                    (0x4002C088U) /**< \brief (USART2) IC DIFF Register */
    69. 

  69.   #define REG_USART2_WPMR                      (0x4002C0E4U) /**< \brief (USART2) Write Protection Mode Register */
    70. 

  70.   #define REG_USART2_WPSR                      (0x4002C0E8U) /**< \brief (USART2) Write Protection Status Register */
    71. 

  71.   #define REG_USART2_VERSION                   (0x4002C0FCU) /**< \brief (USART2) Version Register */
    72. 

  72. #else
    73. 

  73.   #define REG_USART2_CR       (*(__O  uint32_t*)0x4002C000U) /**< \brief (USART2) Control Register */
    74. 

  74.   #define REG_USART2_MR       (*(__IO uint32_t*)0x4002C004U) /**< \brief (USART2) Mode Register */
    75. 

  75.   #define REG_USART2_IER      (*(__O  uint32_t*)0x4002C008U) /**< \brief (USART2) Interrupt Enable Register */
    76. 

  76.   #define REG_USART2_IDR      (*(__O  uint32_t*)0x4002C00CU) /**< \brief (USART2) Interrupt Disable Register */
    77. 

  77.   #define REG_USART2_IMR      (*(__I  uint32_t*)0x4002C010U) /**< \brief (USART2) Interrupt Mask Register */
    78. 

  78.   #define REG_USART2_CSR      (*(__I  uint32_t*)0x4002C014U) /**< \brief (USART2) Channel Status Register */
    79. 

  79.   #define REG_USART2_RHR      (*(__I  uint32_t*)0x4002C018U) /**< \brief (USART2) Receive Holding Register */
    80. 

  80.   #define REG_USART2_THR      (*(__O  uint32_t*)0x4002C01CU) /**< \brief (USART2) Transmit Holding Register */
    81. 

  81.   #define REG_USART2_BRGR     (*(__IO uint32_t*)0x4002C020U) /**< \brief (USART2) Baud Rate Generator Register */
    82. 

  82.   #define REG_USART2_RTOR     (*(__IO uint32_t*)0x4002C024U) /**< \brief (USART2) Receiver Time-out Register */
    83. 

  83.   #define REG_USART2_TTGR     (*(__IO uint32_t*)0x4002C028U) /**< \brief (USART2) Transmitter Timeguard Register */
    84. 

  84.   #define REG_USART2_FIDI     (*(__IO uint32_t*)0x4002C040U) /**< \brief (USART2) FI DI Ratio Register */
    85. 

  85.   #define REG_USART2_NER      (*(__I  uint32_t*)0x4002C044U) /**< \brief (USART2) Number of Errors Register */
    86. 

  86.   #define REG_USART2_IF       (*(__IO uint32_t*)0x4002C04CU) /**< \brief (USART2) IrDA Filter Register */
    87. 

  87.   #define REG_USART2_MAN      (*(__IO uint32_t*)0x4002C050U) /**< \brief (USART2) Manchester Configuration Register */
    88. 

  88.   #define REG_USART2_LINMR    (*(__IO uint32_t*)0x4002C054U) /**< \brief (USART2) LIN Mode Register */
    89. 

  89.   #define REG_USART2_LINIR    (*(__IO uint32_t*)0x4002C058U) /**< \brief (USART2) LIN Identifier Register */
    90. 

  90.   #define REG_USART2_LINBRR   (*(__I  uint32_t*)0x4002C05CU) /**< \brief (USART2) LIN Baud Rate Register */
    91. 

  91.   #define REG_USART2_LONMR    (*(__IO uint32_t*)0x4002C060U) /**< \brief (USART2) LON Mode Register */
    92. 

  92.   #define REG_USART2_LONPR    (*(__IO uint32_t*)0x4002C064U) /**< \brief (USART2) LON Preamble Register */
    93. 

  93.   #define REG_USART2_LONDL    (*(__IO uint32_t*)0x4002C068U) /**< \brief (USART2) LON Data Length Register */
    94. 

  94.   #define REG_USART2_LONL2HDR (*(__IO uint32_t*)0x4002C06CU) /**< \brief (USART2) LON L2HDR Register */
    95. 

  95.   #define REG_USART2_LONBL    (*(__I  uint32_t*)0x4002C070U) /**< \brief (USART2) LON Backlog Register */
    96. 

  96.   #define REG_USART2_LONB1TX  (*(__IO uint32_t*)0x4002C074U) /**< \brief (USART2) LON Beta1 Tx Register */
    97. 

  97.   #define REG_USART2_LONB1RX  (*(__IO uint32_t*)0x4002C078U) /**< \brief (USART2) LON Beta1 Rx Register */
    98. 

  98.   #define REG_USART2_LONPRIO  (*(__IO uint32_t*)0x4002C07CU) /**< \brief (USART2) LON Priority Register */
    99. 

  99.   #define REG_USART2_IDTTX    (*(__IO uint32_t*)0x4002C080U) /**< \brief (USART2) LON IDT Tx Register */
    100. 

  100.   #define REG_USART2_IDTRX    (*(__IO uint32_t*)0x4002C084U) /**< \brief (USART2) LON IDT Rx Register */
    101. 

  101.   #define REG_USART2_ICDIFF   (*(__IO uint32_t*)0x4002C088U) /**< \brief (USART2) IC DIFF Register */
    102. 

  102.   #define REG_USART2_WPMR     (*(__IO uint32_t*)0x4002C0E4U) /**< \brief (USART2) Write Protection Mode Register */
    103. 

  103.   #define REG_USART2_WPSR     (*(__I  uint32_t*)0x4002C0E8U) /**< \brief (USART2) Write Protection Status Register */
    104. 

  104.   #define REG_USART2_VERSION  (*(__I  uint32_t*)0x4002C0FCU) /**< \brief (USART2) Version Register */
    105. 

  105. #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
    106. 

  106. 

  107. #endif /* _SAME70_USART2_INSTANCE_ */
    108.