Inicio Explorar Ayuda
Iniciar sesión
torambo.com
/
Momentum-Apps
2
0
Fork 0
Archivos Incidencias 0 Pull Requests 0 Wiki
Árbol: bab62cf596
Ramas Etiquetas
Momentum-Apps
/
lib
/
free-dap
/
platform
/
same70
/
include
/
instance
/
pwm0.h

pwm0.h 27 KB
Histórico Raw

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259 
  1. /**
    2. 

  2.  * \file
    3. 

  3.  *
    4. 

  4.  * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
    5. 

  5.  *
    6. 

  6.  * \asf_license_start
    7. 

  7.  *
    8. 

  8.  * \page License
    9. 

  9.  *
    10. 

  10.  * Subject to your compliance with these terms, you may use Microchip
    11. 

  11.  * software and any derivatives exclusively with Microchip products.
    12. 

  12.  * It is your responsibility to comply with third party license terms applicable
    13. 

  13.  * to your use of third party software (including open source software) that
    14. 

  14.  * may accompany Microchip software.
    15. 

  15.  *
    16. 

  16.  * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
    17. 

  17.  * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
    18. 

  18.  * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
    19. 

  19.  * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
    20. 

  20.  * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
    21. 

  21.  * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
    22. 

  22.  * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
    23. 

  23.  * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
    24. 

  24.  * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
    25. 

  25.  * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
    26. 

  26.  * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
    27. 

  27.  *
    28. 

  28.  * \asf_license_stop
    29. 

  29.  *
    30. 

  30.  */
    31. 

  31. /*
    32. 

  32.  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
    33. 

  33.  */
    34. 

  34. 

  35. #ifndef _SAME70_PWM0_INSTANCE_
    36. 

  36. #define _SAME70_PWM0_INSTANCE_
    37. 

  37. 

  38. /* ========== Register definition for PWM0 peripheral ========== */
    39. 

  39. #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
    40. 

  40.   #define REG_PWM0_CLK                       (0x40020000U) /**< \brief (PWM0) PWM Clock Register */
    41. 

  41.   #define REG_PWM0_ENA                       (0x40020004U) /**< \brief (PWM0) PWM Enable Register */
    42. 

  42.   #define REG_PWM0_DIS                       (0x40020008U) /**< \brief (PWM0) PWM Disable Register */
    43. 

  43.   #define REG_PWM0_SR                        (0x4002000CU) /**< \brief (PWM0) PWM Status Register */
    44. 

  44.   #define REG_PWM0_IER1                      (0x40020010U) /**< \brief (PWM0) PWM Interrupt Enable Register 1 */
    45. 

  45.   #define REG_PWM0_IDR1                      (0x40020014U) /**< \brief (PWM0) PWM Interrupt Disable Register 1 */
    46. 

  46.   #define REG_PWM0_IMR1                      (0x40020018U) /**< \brief (PWM0) PWM Interrupt Mask Register 1 */
    47. 

  47.   #define REG_PWM0_ISR1                      (0x4002001CU) /**< \brief (PWM0) PWM Interrupt Status Register 1 */
    48. 

  48.   #define REG_PWM0_SCM                       (0x40020020U) /**< \brief (PWM0) PWM Sync Channels Mode Register */
    49. 

  49.   #define REG_PWM0_DMAR                      (0x40020024U) /**< \brief (PWM0) PWM DMA Register */
    50. 

  50.   #define REG_PWM0_SCUC                      (0x40020028U) /**< \brief (PWM0) PWM Sync Channels Update Control Register */
    51. 

  51.   #define REG_PWM0_SCUP                      (0x4002002CU) /**< \brief (PWM0) PWM Sync Channels Update Period Register */
    52. 

  52.   #define REG_PWM0_SCUPUPD                   (0x40020030U) /**< \brief (PWM0) PWM Sync Channels Update Period Update Register */
    53. 

  53.   #define REG_PWM0_IER2                      (0x40020034U) /**< \brief (PWM0) PWM Interrupt Enable Register 2 */
    54. 

  54.   #define REG_PWM0_IDR2                      (0x40020038U) /**< \brief (PWM0) PWM Interrupt Disable Register 2 */
    55. 

  55.   #define REG_PWM0_IMR2                      (0x4002003CU) /**< \brief (PWM0) PWM Interrupt Mask Register 2 */
    56. 

  56.   #define REG_PWM0_ISR2                      (0x40020040U) /**< \brief (PWM0) PWM Interrupt Status Register 2 */
    57. 

  57.   #define REG_PWM0_OOV                       (0x40020044U) /**< \brief (PWM0) PWM Output Override Value Register */
    58. 

  58.   #define REG_PWM0_OS                        (0x40020048U) /**< \brief (PWM0) PWM Output Selection Register */
    59. 

  59.   #define REG_PWM0_OSS                       (0x4002004CU) /**< \brief (PWM0) PWM Output Selection Set Register */
    60. 

  60.   #define REG_PWM0_OSC                       (0x40020050U) /**< \brief (PWM0) PWM Output Selection Clear Register */
    61. 

  61.   #define REG_PWM0_OSSUPD                    (0x40020054U) /**< \brief (PWM0) PWM Output Selection Set Update Register */
    62. 

  62.   #define REG_PWM0_OSCUPD                    (0x40020058U) /**< \brief (PWM0) PWM Output Selection Clear Update Register */
    63. 

  63.   #define REG_PWM0_FMR                       (0x4002005CU) /**< \brief (PWM0) PWM Fault Mode Register */
    64. 

  64.   #define REG_PWM0_FSR                       (0x40020060U) /**< \brief (PWM0) PWM Fault Status Register */
    65. 

  65.   #define REG_PWM0_FCR                       (0x40020064U) /**< \brief (PWM0) PWM Fault Clear Register */
    66. 

  66.   #define REG_PWM0_FPV1                      (0x40020068U) /**< \brief (PWM0) PWM Fault Protection Value Register 1 */
    67. 

  67.   #define REG_PWM0_FPE                       (0x4002006CU) /**< \brief (PWM0) PWM Fault Protection Enable Register */
    68. 

  68.   #define REG_PWM0_ELMR                      (0x4002007CU) /**< \brief (PWM0) PWM Event Line 0 Mode Register */
    69. 

  69.   #define REG_PWM0_SSPR                      (0x400200A0U) /**< \brief (PWM0) PWM Spread Spectrum Register */
    70. 

  70.   #define REG_PWM0_SSPUP                     (0x400200A4U) /**< \brief (PWM0) PWM Spread Spectrum Update Register */
    71. 

  71.   #define REG_PWM0_SMMR                      (0x400200B0U) /**< \brief (PWM0) PWM Stepper Motor Mode Register */
    72. 

  72.   #define REG_PWM0_FPV2                      (0x400200C0U) /**< \brief (PWM0) PWM Fault Protection Value 2 Register */
    73. 

  73.   #define REG_PWM0_WPCR                      (0x400200E4U) /**< \brief (PWM0) PWM Write Protection Control Register */
    74. 

  74.   #define REG_PWM0_WPSR                      (0x400200E8U) /**< \brief (PWM0) PWM Write Protection Status Register */
    75. 

  75.   #define REG_PWM0_VERSION                   (0x400200FCU) /**< \brief (PWM0) Version Register */
    76. 

  76.   #define REG_PWM0_CMPV0                     (0x40020130U) /**< \brief (PWM0) PWM Comparison 0 Value Register */
    77. 

  77.   #define REG_PWM0_CMPVUPD0                  (0x40020134U) /**< \brief (PWM0) PWM Comparison 0 Value Update Register */
    78. 

  78.   #define REG_PWM0_CMPM0                     (0x40020138U) /**< \brief (PWM0) PWM Comparison 0 Mode Register */
    79. 

  79.   #define REG_PWM0_CMPMUPD0                  (0x4002013CU) /**< \brief (PWM0) PWM Comparison 0 Mode Update Register */
    80. 

  80.   #define REG_PWM0_CMPV1                     (0x40020140U) /**< \brief (PWM0) PWM Comparison 1 Value Register */
    81. 

  81.   #define REG_PWM0_CMPVUPD1                  (0x40020144U) /**< \brief (PWM0) PWM Comparison 1 Value Update Register */
    82. 

  82.   #define REG_PWM0_CMPM1                     (0x40020148U) /**< \brief (PWM0) PWM Comparison 1 Mode Register */
    83. 

  83.   #define REG_PWM0_CMPMUPD1                  (0x4002014CU) /**< \brief (PWM0) PWM Comparison 1 Mode Update Register */
    84. 

  84.   #define REG_PWM0_CMPV2                     (0x40020150U) /**< \brief (PWM0) PWM Comparison 2 Value Register */
    85. 

  85.   #define REG_PWM0_CMPVUPD2                  (0x40020154U) /**< \brief (PWM0) PWM Comparison 2 Value Update Register */
    86. 

  86.   #define REG_PWM0_CMPM2                     (0x40020158U) /**< \brief (PWM0) PWM Comparison 2 Mode Register */
    87. 

  87.   #define REG_PWM0_CMPMUPD2                  (0x4002015CU) /**< \brief (PWM0) PWM Comparison 2 Mode Update Register */
    88. 

  88.   #define REG_PWM0_CMPV3                     (0x40020160U) /**< \brief (PWM0) PWM Comparison 3 Value Register */
    89. 

  89.   #define REG_PWM0_CMPVUPD3                  (0x40020164U) /**< \brief (PWM0) PWM Comparison 3 Value Update Register */
    90. 

  90.   #define REG_PWM0_CMPM3                     (0x40020168U) /**< \brief (PWM0) PWM Comparison 3 Mode Register */
    91. 

  91.   #define REG_PWM0_CMPMUPD3                  (0x4002016CU) /**< \brief (PWM0) PWM Comparison 3 Mode Update Register */
    92. 

  92.   #define REG_PWM0_CMPV4                     (0x40020170U) /**< \brief (PWM0) PWM Comparison 4 Value Register */
    93. 

  93.   #define REG_PWM0_CMPVUPD4                  (0x40020174U) /**< \brief (PWM0) PWM Comparison 4 Value Update Register */
    94. 

  94.   #define REG_PWM0_CMPM4                     (0x40020178U) /**< \brief (PWM0) PWM Comparison 4 Mode Register */
    95. 

  95.   #define REG_PWM0_CMPMUPD4                  (0x4002017CU) /**< \brief (PWM0) PWM Comparison 4 Mode Update Register */
    96. 

  96.   #define REG_PWM0_CMPV5                     (0x40020180U) /**< \brief (PWM0) PWM Comparison 5 Value Register */
    97. 

  97.   #define REG_PWM0_CMPVUPD5                  (0x40020184U) /**< \brief (PWM0) PWM Comparison 5 Value Update Register */
    98. 

  98.   #define REG_PWM0_CMPM5                     (0x40020188U) /**< \brief (PWM0) PWM Comparison 5 Mode Register */
    99. 

  99.   #define REG_PWM0_CMPMUPD5                  (0x4002018CU) /**< \brief (PWM0) PWM Comparison 5 Mode Update Register */
    100. 

  100.   #define REG_PWM0_CMPV6                     (0x40020190U) /**< \brief (PWM0) PWM Comparison 6 Value Register */
    101. 

  101.   #define REG_PWM0_CMPVUPD6                  (0x40020194U) /**< \brief (PWM0) PWM Comparison 6 Value Update Register */
    102. 

  102.   #define REG_PWM0_CMPM6                     (0x40020198U) /**< \brief (PWM0) PWM Comparison 6 Mode Register */
    103. 

  103.   #define REG_PWM0_CMPMUPD6                  (0x4002019CU) /**< \brief (PWM0) PWM Comparison 6 Mode Update Register */
    104. 

  104.   #define REG_PWM0_CMPV7                     (0x400201A0U) /**< \brief (PWM0) PWM Comparison 7 Value Register */
    105. 

  105.   #define REG_PWM0_CMPVUPD7                  (0x400201A4U) /**< \brief (PWM0) PWM Comparison 7 Value Update Register */
    106. 

  106.   #define REG_PWM0_CMPM7                     (0x400201A8U) /**< \brief (PWM0) PWM Comparison 7 Mode Register */
    107. 

  107.   #define REG_PWM0_CMPMUPD7                  (0x400201ACU) /**< \brief (PWM0) PWM Comparison 7 Mode Update Register */
    108. 

  108.   #define REG_PWM0_CMR0                      (0x40020200U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 0) */
    109. 

  109.   #define REG_PWM0_CDTY0                     (0x40020204U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 0) */
    110. 

  110.   #define REG_PWM0_CDTYUPD0                  (0x40020208U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 0) */
    111. 

  111.   #define REG_PWM0_CPRD0                     (0x4002020CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 0) */
    112. 

  112.   #define REG_PWM0_CPRDUPD0                  (0x40020210U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 0) */
    113. 

  113.   #define REG_PWM0_CCNT0                     (0x40020214U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 0) */
    114. 

  114.   #define REG_PWM0_DT0                       (0x40020218U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 0) */
    115. 

  115.   #define REG_PWM0_DTUPD0                    (0x4002021CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 0) */
    116. 

  116.   #define REG_PWM0_CMR1                      (0x40020220U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 1) */
    117. 

  117.   #define REG_PWM0_CDTY1                     (0x40020224U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 1) */
    118. 

  118.   #define REG_PWM0_CDTYUPD1                  (0x40020228U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 1) */
    119. 

  119.   #define REG_PWM0_CPRD1                     (0x4002022CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 1) */
    120. 

  120.   #define REG_PWM0_CPRDUPD1                  (0x40020230U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 1) */
    121. 

  121.   #define REG_PWM0_CCNT1                     (0x40020234U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 1) */
    122. 

  122.   #define REG_PWM0_DT1                       (0x40020238U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 1) */
    123. 

  123.   #define REG_PWM0_DTUPD1                    (0x4002023CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 1) */
    124. 

  124.   #define REG_PWM0_CMR2                      (0x40020240U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 2) */
    125. 

  125.   #define REG_PWM0_CDTY2                     (0x40020244U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 2) */
    126. 

  126.   #define REG_PWM0_CDTYUPD2                  (0x40020248U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 2) */
    127. 

  127.   #define REG_PWM0_CPRD2                     (0x4002024CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 2) */
    128. 

  128.   #define REG_PWM0_CPRDUPD2                  (0x40020250U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 2) */
    129. 

  129.   #define REG_PWM0_CCNT2                     (0x40020254U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 2) */
    130. 

  130.   #define REG_PWM0_DT2                       (0x40020258U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 2) */
    131. 

  131.   #define REG_PWM0_DTUPD2                    (0x4002025CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 2) */
    132. 

  132.   #define REG_PWM0_CMR3                      (0x40020260U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 3) */
    133. 

  133.   #define REG_PWM0_CDTY3                     (0x40020264U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 3) */
    134. 

  134.   #define REG_PWM0_CDTYUPD3                  (0x40020268U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 3) */
    135. 

  135.   #define REG_PWM0_CPRD3                     (0x4002026CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 3) */
    136. 

  136.   #define REG_PWM0_CPRDUPD3                  (0x40020270U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 3) */
    137. 

  137.   #define REG_PWM0_CCNT3                     (0x40020274U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 3) */
    138. 

  138.   #define REG_PWM0_DT3                       (0x40020278U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 3) */
    139. 

  139.   #define REG_PWM0_DTUPD3                    (0x4002027CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 3) */
    140. 

  140.   #define REG_PWM0_CMUPD0                    (0x40020400U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 0) */
    141. 

  141.   #define REG_PWM0_CMUPD1                    (0x40020420U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 1) */
    142. 

  142.   #define REG_PWM0_ETRG1                     (0x4002042CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 1) */
    143. 

  143.   #define REG_PWM0_LEBR1                     (0x40020430U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 1) */
    144. 

  144.   #define REG_PWM0_CMUPD2                    (0x40020440U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 2) */
    145. 

  145.   #define REG_PWM0_ETRG2                     (0x4002044CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 2) */
    146. 

  146.   #define REG_PWM0_LEBR2                     (0x40020450U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 2) */
    147. 

  147.   #define REG_PWM0_CMUPD3                    (0x40020460U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 3) */
    148. 

  148. #else
    149. 

  149.   #define REG_PWM0_CLK      (*(__IO uint32_t*)0x40020000U) /**< \brief (PWM0) PWM Clock Register */
    150. 

  150.   #define REG_PWM0_ENA      (*(__O  uint32_t*)0x40020004U) /**< \brief (PWM0) PWM Enable Register */
    151. 

  151.   #define REG_PWM0_DIS      (*(__O  uint32_t*)0x40020008U) /**< \brief (PWM0) PWM Disable Register */
    152. 

  152.   #define REG_PWM0_SR       (*(__I  uint32_t*)0x4002000CU) /**< \brief (PWM0) PWM Status Register */
    153. 

  153.   #define REG_PWM0_IER1     (*(__O  uint32_t*)0x40020010U) /**< \brief (PWM0) PWM Interrupt Enable Register 1 */
    154. 

  154.   #define REG_PWM0_IDR1     (*(__O  uint32_t*)0x40020014U) /**< \brief (PWM0) PWM Interrupt Disable Register 1 */
    155. 

  155.   #define REG_PWM0_IMR1     (*(__I  uint32_t*)0x40020018U) /**< \brief (PWM0) PWM Interrupt Mask Register 1 */
    156. 

  156.   #define REG_PWM0_ISR1     (*(__I  uint32_t*)0x4002001CU) /**< \brief (PWM0) PWM Interrupt Status Register 1 */
    157. 

  157.   #define REG_PWM0_SCM      (*(__IO uint32_t*)0x40020020U) /**< \brief (PWM0) PWM Sync Channels Mode Register */
    158. 

  158.   #define REG_PWM0_DMAR     (*(__O  uint32_t*)0x40020024U) /**< \brief (PWM0) PWM DMA Register */
    159. 

  159.   #define REG_PWM0_SCUC     (*(__IO uint32_t*)0x40020028U) /**< \brief (PWM0) PWM Sync Channels Update Control Register */
    160. 

  160.   #define REG_PWM0_SCUP     (*(__IO uint32_t*)0x4002002CU) /**< \brief (PWM0) PWM Sync Channels Update Period Register */
    161. 

  161.   #define REG_PWM0_SCUPUPD  (*(__O  uint32_t*)0x40020030U) /**< \brief (PWM0) PWM Sync Channels Update Period Update Register */
    162. 

  162.   #define REG_PWM0_IER2     (*(__O  uint32_t*)0x40020034U) /**< \brief (PWM0) PWM Interrupt Enable Register 2 */
    163. 

  163.   #define REG_PWM0_IDR2     (*(__O  uint32_t*)0x40020038U) /**< \brief (PWM0) PWM Interrupt Disable Register 2 */
    164. 

  164.   #define REG_PWM0_IMR2     (*(__I  uint32_t*)0x4002003CU) /**< \brief (PWM0) PWM Interrupt Mask Register 2 */
    165. 

  165.   #define REG_PWM0_ISR2     (*(__I  uint32_t*)0x40020040U) /**< \brief (PWM0) PWM Interrupt Status Register 2 */
    166. 

  166.   #define REG_PWM0_OOV      (*(__IO uint32_t*)0x40020044U) /**< \brief (PWM0) PWM Output Override Value Register */
    167. 

  167.   #define REG_PWM0_OS       (*(__IO uint32_t*)0x40020048U) /**< \brief (PWM0) PWM Output Selection Register */
    168. 

  168.   #define REG_PWM0_OSS      (*(__O  uint32_t*)0x4002004CU) /**< \brief (PWM0) PWM Output Selection Set Register */
    169. 

  169.   #define REG_PWM0_OSC      (*(__O  uint32_t*)0x40020050U) /**< \brief (PWM0) PWM Output Selection Clear Register */
    170. 

  170.   #define REG_PWM0_OSSUPD   (*(__O  uint32_t*)0x40020054U) /**< \brief (PWM0) PWM Output Selection Set Update Register */
    171. 

  171.   #define REG_PWM0_OSCUPD   (*(__O  uint32_t*)0x40020058U) /**< \brief (PWM0) PWM Output Selection Clear Update Register */
    172. 

  172.   #define REG_PWM0_FMR      (*(__IO uint32_t*)0x4002005CU) /**< \brief (PWM0) PWM Fault Mode Register */
    173. 

  173.   #define REG_PWM0_FSR      (*(__I  uint32_t*)0x40020060U) /**< \brief (PWM0) PWM Fault Status Register */
    174. 

  174.   #define REG_PWM0_FCR      (*(__O  uint32_t*)0x40020064U) /**< \brief (PWM0) PWM Fault Clear Register */
    175. 

  175.   #define REG_PWM0_FPV1     (*(__IO uint32_t*)0x40020068U) /**< \brief (PWM0) PWM Fault Protection Value Register 1 */
    176. 

  176.   #define REG_PWM0_FPE      (*(__IO uint32_t*)0x4002006CU) /**< \brief (PWM0) PWM Fault Protection Enable Register */
    177. 

  177.   #define REG_PWM0_ELMR     (*(__IO uint32_t*)0x4002007CU) /**< \brief (PWM0) PWM Event Line 0 Mode Register */
    178. 

  178.   #define REG_PWM0_SSPR     (*(__IO uint32_t*)0x400200A0U) /**< \brief (PWM0) PWM Spread Spectrum Register */
    179. 

  179.   #define REG_PWM0_SSPUP    (*(__O  uint32_t*)0x400200A4U) /**< \brief (PWM0) PWM Spread Spectrum Update Register */
    180. 

  180.   #define REG_PWM0_SMMR     (*(__IO uint32_t*)0x400200B0U) /**< \brief (PWM0) PWM Stepper Motor Mode Register */
    181. 

  181.   #define REG_PWM0_FPV2     (*(__IO uint32_t*)0x400200C0U) /**< \brief (PWM0) PWM Fault Protection Value 2 Register */
    182. 

  182.   #define REG_PWM0_WPCR     (*(__O  uint32_t*)0x400200E4U) /**< \brief (PWM0) PWM Write Protection Control Register */
    183. 

  183.   #define REG_PWM0_WPSR     (*(__I  uint32_t*)0x400200E8U) /**< \brief (PWM0) PWM Write Protection Status Register */
    184. 

  184.   #define REG_PWM0_VERSION  (*(__I  uint32_t*)0x400200FCU) /**< \brief (PWM0) Version Register */
    185. 

  185.   #define REG_PWM0_CMPV0    (*(__IO uint32_t*)0x40020130U) /**< \brief (PWM0) PWM Comparison 0 Value Register */
    186. 

  186.   #define REG_PWM0_CMPVUPD0 (*(__O  uint32_t*)0x40020134U) /**< \brief (PWM0) PWM Comparison 0 Value Update Register */
    187. 

  187.   #define REG_PWM0_CMPM0    (*(__IO uint32_t*)0x40020138U) /**< \brief (PWM0) PWM Comparison 0 Mode Register */
    188. 

  188.   #define REG_PWM0_CMPMUPD0 (*(__O  uint32_t*)0x4002013CU) /**< \brief (PWM0) PWM Comparison 0 Mode Update Register */
    189. 

  189.   #define REG_PWM0_CMPV1    (*(__IO uint32_t*)0x40020140U) /**< \brief (PWM0) PWM Comparison 1 Value Register */
    190. 

  190.   #define REG_PWM0_CMPVUPD1 (*(__O  uint32_t*)0x40020144U) /**< \brief (PWM0) PWM Comparison 1 Value Update Register */
    191. 

  191.   #define REG_PWM0_CMPM1    (*(__IO uint32_t*)0x40020148U) /**< \brief (PWM0) PWM Comparison 1 Mode Register */
    192. 

  192.   #define REG_PWM0_CMPMUPD1 (*(__O  uint32_t*)0x4002014CU) /**< \brief (PWM0) PWM Comparison 1 Mode Update Register */
    193. 

  193.   #define REG_PWM0_CMPV2    (*(__IO uint32_t*)0x40020150U) /**< \brief (PWM0) PWM Comparison 2 Value Register */
    194. 

  194.   #define REG_PWM0_CMPVUPD2 (*(__O  uint32_t*)0x40020154U) /**< \brief (PWM0) PWM Comparison 2 Value Update Register */
    195. 

  195.   #define REG_PWM0_CMPM2    (*(__IO uint32_t*)0x40020158U) /**< \brief (PWM0) PWM Comparison 2 Mode Register */
    196. 

  196.   #define REG_PWM0_CMPMUPD2 (*(__O  uint32_t*)0x4002015CU) /**< \brief (PWM0) PWM Comparison 2 Mode Update Register */
    197. 

  197.   #define REG_PWM0_CMPV3    (*(__IO uint32_t*)0x40020160U) /**< \brief (PWM0) PWM Comparison 3 Value Register */
    198. 

  198.   #define REG_PWM0_CMPVUPD3 (*(__O  uint32_t*)0x40020164U) /**< \brief (PWM0) PWM Comparison 3 Value Update Register */
    199. 

  199.   #define REG_PWM0_CMPM3    (*(__IO uint32_t*)0x40020168U) /**< \brief (PWM0) PWM Comparison 3 Mode Register */
    200. 

  200.   #define REG_PWM0_CMPMUPD3 (*(__O  uint32_t*)0x4002016CU) /**< \brief (PWM0) PWM Comparison 3 Mode Update Register */
    201. 

  201.   #define REG_PWM0_CMPV4    (*(__IO uint32_t*)0x40020170U) /**< \brief (PWM0) PWM Comparison 4 Value Register */
    202. 

  202.   #define REG_PWM0_CMPVUPD4 (*(__O  uint32_t*)0x40020174U) /**< \brief (PWM0) PWM Comparison 4 Value Update Register */
    203. 

  203.   #define REG_PWM0_CMPM4    (*(__IO uint32_t*)0x40020178U) /**< \brief (PWM0) PWM Comparison 4 Mode Register */
    204. 

  204.   #define REG_PWM0_CMPMUPD4 (*(__O  uint32_t*)0x4002017CU) /**< \brief (PWM0) PWM Comparison 4 Mode Update Register */
    205. 

  205.   #define REG_PWM0_CMPV5    (*(__IO uint32_t*)0x40020180U) /**< \brief (PWM0) PWM Comparison 5 Value Register */
    206. 

  206.   #define REG_PWM0_CMPVUPD5 (*(__O  uint32_t*)0x40020184U) /**< \brief (PWM0) PWM Comparison 5 Value Update Register */
    207. 

  207.   #define REG_PWM0_CMPM5    (*(__IO uint32_t*)0x40020188U) /**< \brief (PWM0) PWM Comparison 5 Mode Register */
    208. 

  208.   #define REG_PWM0_CMPMUPD5 (*(__O  uint32_t*)0x4002018CU) /**< \brief (PWM0) PWM Comparison 5 Mode Update Register */
    209. 

  209.   #define REG_PWM0_CMPV6    (*(__IO uint32_t*)0x40020190U) /**< \brief (PWM0) PWM Comparison 6 Value Register */
    210. 

  210.   #define REG_PWM0_CMPVUPD6 (*(__O  uint32_t*)0x40020194U) /**< \brief (PWM0) PWM Comparison 6 Value Update Register */
    211. 

  211.   #define REG_PWM0_CMPM6    (*(__IO uint32_t*)0x40020198U) /**< \brief (PWM0) PWM Comparison 6 Mode Register */
    212. 

  212.   #define REG_PWM0_CMPMUPD6 (*(__O  uint32_t*)0x4002019CU) /**< \brief (PWM0) PWM Comparison 6 Mode Update Register */
    213. 

  213.   #define REG_PWM0_CMPV7    (*(__IO uint32_t*)0x400201A0U) /**< \brief (PWM0) PWM Comparison 7 Value Register */
    214. 

  214.   #define REG_PWM0_CMPVUPD7 (*(__O  uint32_t*)0x400201A4U) /**< \brief (PWM0) PWM Comparison 7 Value Update Register */
    215. 

  215.   #define REG_PWM0_CMPM7    (*(__IO uint32_t*)0x400201A8U) /**< \brief (PWM0) PWM Comparison 7 Mode Register */
    216. 

  216.   #define REG_PWM0_CMPMUPD7 (*(__O  uint32_t*)0x400201ACU) /**< \brief (PWM0) PWM Comparison 7 Mode Update Register */
    217. 

  217.   #define REG_PWM0_CMR0     (*(__IO uint32_t*)0x40020200U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 0) */
    218. 

  218.   #define REG_PWM0_CDTY0    (*(__IO uint32_t*)0x40020204U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 0) */
    219. 

  219.   #define REG_PWM0_CDTYUPD0 (*(__O  uint32_t*)0x40020208U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 0) */
    220. 

  220.   #define REG_PWM0_CPRD0    (*(__IO uint32_t*)0x4002020CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 0) */
    221. 

  221.   #define REG_PWM0_CPRDUPD0 (*(__O  uint32_t*)0x40020210U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 0) */
    222. 

  222.   #define REG_PWM0_CCNT0    (*(__I  uint32_t*)0x40020214U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 0) */
    223. 

  223.   #define REG_PWM0_DT0      (*(__IO uint32_t*)0x40020218U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 0) */
    224. 

  224.   #define REG_PWM0_DTUPD0   (*(__O  uint32_t*)0x4002021CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 0) */
    225. 

  225.   #define REG_PWM0_CMR1     (*(__IO uint32_t*)0x40020220U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 1) */
    226. 

  226.   #define REG_PWM0_CDTY1    (*(__IO uint32_t*)0x40020224U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 1) */
    227. 

  227.   #define REG_PWM0_CDTYUPD1 (*(__O  uint32_t*)0x40020228U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 1) */
    228. 

  228.   #define REG_PWM0_CPRD1    (*(__IO uint32_t*)0x4002022CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 1) */
    229. 

  229.   #define REG_PWM0_CPRDUPD1 (*(__O  uint32_t*)0x40020230U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 1) */
    230. 

  230.   #define REG_PWM0_CCNT1    (*(__I  uint32_t*)0x40020234U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 1) */
    231. 

  231.   #define REG_PWM0_DT1      (*(__IO uint32_t*)0x40020238U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 1) */
    232. 

  232.   #define REG_PWM0_DTUPD1   (*(__O  uint32_t*)0x4002023CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 1) */
    233. 

  233.   #define REG_PWM0_CMR2     (*(__IO uint32_t*)0x40020240U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 2) */
    234. 

  234.   #define REG_PWM0_CDTY2    (*(__IO uint32_t*)0x40020244U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 2) */
    235. 

  235.   #define REG_PWM0_CDTYUPD2 (*(__O  uint32_t*)0x40020248U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 2) */
    236. 

  236.   #define REG_PWM0_CPRD2    (*(__IO uint32_t*)0x4002024CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 2) */
    237. 

  237.   #define REG_PWM0_CPRDUPD2 (*(__O  uint32_t*)0x40020250U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 2) */
    238. 

  238.   #define REG_PWM0_CCNT2    (*(__I  uint32_t*)0x40020254U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 2) */
    239. 

  239.   #define REG_PWM0_DT2      (*(__IO uint32_t*)0x40020258U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 2) */
    240. 

  240.   #define REG_PWM0_DTUPD2   (*(__O  uint32_t*)0x4002025CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 2) */
    241. 

  241.   #define REG_PWM0_CMR3     (*(__IO uint32_t*)0x40020260U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 3) */
    242. 

  242.   #define REG_PWM0_CDTY3    (*(__IO uint32_t*)0x40020264U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 3) */
    243. 

  243.   #define REG_PWM0_CDTYUPD3 (*(__O  uint32_t*)0x40020268U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 3) */
    244. 

  244.   #define REG_PWM0_CPRD3    (*(__IO uint32_t*)0x4002026CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 3) */
    245. 

  245.   #define REG_PWM0_CPRDUPD3 (*(__O  uint32_t*)0x40020270U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 3) */
    246. 

  246.   #define REG_PWM0_CCNT3    (*(__I  uint32_t*)0x40020274U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 3) */
    247. 

  247.   #define REG_PWM0_DT3      (*(__IO uint32_t*)0x40020278U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 3) */
    248. 

  248.   #define REG_PWM0_DTUPD3   (*(__O  uint32_t*)0x4002027CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 3) */
    249. 

  249.   #define REG_PWM0_CMUPD0   (*(__O  uint32_t*)0x40020400U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 0) */
    250. 

  250.   #define REG_PWM0_CMUPD1   (*(__O  uint32_t*)0x40020420U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 1) */
    251. 

  251.   #define REG_PWM0_ETRG1    (*(__IO uint32_t*)0x4002042CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 1) */
    252. 

  252.   #define REG_PWM0_LEBR1    (*(__IO uint32_t*)0x40020430U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 1) */
    253. 

  253.   #define REG_PWM0_CMUPD2   (*(__O  uint32_t*)0x40020440U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 2) */
    254. 

  254.   #define REG_PWM0_ETRG2    (*(__IO uint32_t*)0x4002044CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 2) */
    255. 

  255.   #define REG_PWM0_LEBR2    (*(__IO uint32_t*)0x40020450U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 2) */
    256. 

  256.   #define REG_PWM0_CMUPD3   (*(__O  uint32_t*)0x40020460U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 3) */
    257. 

  257. #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
    258. 

  258. 

  259. #endif /* _SAME70_PWM0_INSTANCE_ */
    260.