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pioa.h

pioa.h 16 KB
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  1. /**
    2. 

  2.  * \file
    3. 

  3.  *
    4. 

  4.  * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
    5. 

  5.  *
    6. 

  6.  * \asf_license_start
    7. 

  7.  *
    8. 

  8.  * \page License
    9. 

  9.  *
    10. 

  10.  * Subject to your compliance with these terms, you may use Microchip
    11. 

  11.  * software and any derivatives exclusively with Microchip products.
    12. 

  12.  * It is your responsibility to comply with third party license terms applicable
    13. 

  13.  * to your use of third party software (including open source software) that
    14. 

  14.  * may accompany Microchip software.
    15. 

  15.  *
    16. 

  16.  * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
    17. 

  17.  * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
    18. 

  18.  * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
    19. 

  19.  * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
    20. 

  20.  * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
    21. 

  21.  * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
    22. 

  22.  * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
    23. 

  23.  * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
    24. 

  24.  * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
    25. 

  25.  * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
    26. 

  26.  * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
    27. 

  27.  *
    28. 

  28.  * \asf_license_stop
    29. 

  29.  *
    30. 

  30.  */
    31. 

  31. /*
    32. 

  32.  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
    33. 

  33.  */
    34. 

  34. 

  35. #ifndef _SAME70_PIOA_INSTANCE_
    36. 

  36. #define _SAME70_PIOA_INSTANCE_
    37. 

  37. 

  38. /* ========== Register definition for PIOA peripheral ========== */
    39. 

  39. #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
    40. 

  40.   #define REG_PIOA_PER                      (0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */
    41. 

  41.   #define REG_PIOA_PDR                      (0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */
    42. 

  42.   #define REG_PIOA_PSR                      (0x400E0E08U) /**< \brief (PIOA) PIO Status Register */
    43. 

  43.   #define REG_PIOA_OER                      (0x400E0E10U) /**< \brief (PIOA) Output Enable Register */
    44. 

  44.   #define REG_PIOA_ODR                      (0x400E0E14U) /**< \brief (PIOA) Output Disable Register */
    45. 

  45.   #define REG_PIOA_OSR                      (0x400E0E18U) /**< \brief (PIOA) Output Status Register */
    46. 

  46.   #define REG_PIOA_IFER                     (0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
    47. 

  47.   #define REG_PIOA_IFDR                     (0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
    48. 

  48.   #define REG_PIOA_IFSR                     (0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
    49. 

  49.   #define REG_PIOA_SODR                     (0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */
    50. 

  50.   #define REG_PIOA_CODR                     (0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */
    51. 

  51.   #define REG_PIOA_ODSR                     (0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */
    52. 

  52.   #define REG_PIOA_PDSR                     (0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */
    53. 

  53.   #define REG_PIOA_IER                      (0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */
    54. 

  54.   #define REG_PIOA_IDR                      (0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */
    55. 

  55.   #define REG_PIOA_IMR                      (0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */
    56. 

  56.   #define REG_PIOA_ISR                      (0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */
    57. 

  57.   #define REG_PIOA_MDER                     (0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */
    58. 

  58.   #define REG_PIOA_MDDR                     (0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */
    59. 

  59.   #define REG_PIOA_MDSR                     (0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */
    60. 

  60.   #define REG_PIOA_PUDR                     (0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */
    61. 

  61.   #define REG_PIOA_PUER                     (0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */
    62. 

  62.   #define REG_PIOA_PUSR                     (0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */
    63. 

  63.   #define REG_PIOA_ABCDSR                   (0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */
    64. 

  64.   #define REG_PIOA_IFSCDR                   (0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */
    65. 

  65.   #define REG_PIOA_IFSCER                   (0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */
    66. 

  66.   #define REG_PIOA_IFSCSR                   (0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */
    67. 

  67.   #define REG_PIOA_SCDR                     (0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
    68. 

  68.   #define REG_PIOA_PPDDR                    (0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */
    69. 

  69.   #define REG_PIOA_PPDER                    (0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */
    70. 

  70.   #define REG_PIOA_PPDSR                    (0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */
    71. 

  71.   #define REG_PIOA_OWER                     (0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */
    72. 

  72.   #define REG_PIOA_OWDR                     (0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */
    73. 

  73.   #define REG_PIOA_OWSR                     (0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */
    74. 

  74.   #define REG_PIOA_AIMER                    (0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
    75. 

  75.   #define REG_PIOA_AIMDR                    (0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disable Register */
    76. 

  76.   #define REG_PIOA_AIMMR                    (0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
    77. 

  77.   #define REG_PIOA_ESR                      (0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */
    78. 

  78.   #define REG_PIOA_LSR                      (0x400E0EC4U) /**< \brief (PIOA) Level Select Register */
    79. 

  79.   #define REG_PIOA_ELSR                     (0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */
    80. 

  80.   #define REG_PIOA_FELLSR                   (0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low-Level Select Register */
    81. 

  81.   #define REG_PIOA_REHLSR                   (0x400E0ED4U) /**< \brief (PIOA) Rising Edge/High-Level Select Register */
    82. 

  82.   #define REG_PIOA_FRLHSR                   (0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
    83. 

  83.   #define REG_PIOA_LOCKSR                   (0x400E0EE0U) /**< \brief (PIOA) Lock Status */
    84. 

  84.   #define REG_PIOA_WPMR                     (0x400E0EE4U) /**< \brief (PIOA) Write Protection Mode Register */
    85. 

  85.   #define REG_PIOA_WPSR                     (0x400E0EE8U) /**< \brief (PIOA) Write Protection Status Register */
    86. 

  86.   #define REG_PIOA_VERSION                  (0x400E0EFCU) /**< \brief (PIOA) Version Register */
    87. 

  87.   #define REG_PIOA_SCHMITT                  (0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */
    88. 

  88.   #define REG_PIOA_DRIVER                   (0x400E0F18U) /**< \brief (PIOA) PIO I/O Drive Register */
    89. 

  89.   #define REG_PIOA_KER                      (0x400E0F20U) /**< \brief (PIOA) Keypad Controller Enable Register */
    90. 

  90.   #define REG_PIOA_KRCR                     (0x400E0F24U) /**< \brief (PIOA) Keypad Controller Row Column Register */
    91. 

  91.   #define REG_PIOA_KDR                      (0x400E0F28U) /**< \brief (PIOA) Keypad Controller Debouncing Register */
    92. 

  92.   #define REG_PIOA_KIER                     (0x400E0F30U) /**< \brief (PIOA) Keypad Controller Interrupt Enable Register */
    93. 

  93.   #define REG_PIOA_KIDR                     (0x400E0F34U) /**< \brief (PIOA) Keypad Controller Interrupt Disable Register */
    94. 

  94.   #define REG_PIOA_KIMR                     (0x400E0F38U) /**< \brief (PIOA) Keypad Controller Interrupt Mask Register */
    95. 

  95.   #define REG_PIOA_KSR                      (0x400E0F3CU) /**< \brief (PIOA) Keypad Controller Status Register */
    96. 

  96.   #define REG_PIOA_KKPR                     (0x400E0F40U) /**< \brief (PIOA) Keypad Controller Key Press Register */
    97. 

  97.   #define REG_PIOA_KKRR                     (0x400E0F44U) /**< \brief (PIOA) Keypad Controller Key Release Register */
    98. 

  98.   #define REG_PIOA_PCMR                     (0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */
    99. 

  99.   #define REG_PIOA_PCIER                    (0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */
    100. 

  100.   #define REG_PIOA_PCIDR                    (0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */
    101. 

  101.   #define REG_PIOA_PCIMR                    (0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */
    102. 

  102.   #define REG_PIOA_PCISR                    (0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */
    103. 

  103.   #define REG_PIOA_PCRHR                    (0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */
    104. 

  104. #else
    105. 

  105.   #define REG_PIOA_PER     (*(__O  uint32_t*)0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */
    106. 

  106.   #define REG_PIOA_PDR     (*(__O  uint32_t*)0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */
    107. 

  107.   #define REG_PIOA_PSR     (*(__I  uint32_t*)0x400E0E08U) /**< \brief (PIOA) PIO Status Register */
    108. 

  108.   #define REG_PIOA_OER     (*(__O  uint32_t*)0x400E0E10U) /**< \brief (PIOA) Output Enable Register */
    109. 

  109.   #define REG_PIOA_ODR     (*(__O  uint32_t*)0x400E0E14U) /**< \brief (PIOA) Output Disable Register */
    110. 

  110.   #define REG_PIOA_OSR     (*(__I  uint32_t*)0x400E0E18U) /**< \brief (PIOA) Output Status Register */
    111. 

  111.   #define REG_PIOA_IFER    (*(__O  uint32_t*)0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
    112. 

  112.   #define REG_PIOA_IFDR    (*(__O  uint32_t*)0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
    113. 

  113.   #define REG_PIOA_IFSR    (*(__I  uint32_t*)0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
    114. 

  114.   #define REG_PIOA_SODR    (*(__O  uint32_t*)0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */
    115. 

  115.   #define REG_PIOA_CODR    (*(__O  uint32_t*)0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */
    116. 

  116.   #define REG_PIOA_ODSR    (*(__IO uint32_t*)0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */
    117. 

  117.   #define REG_PIOA_PDSR    (*(__I  uint32_t*)0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */
    118. 

  118.   #define REG_PIOA_IER     (*(__O  uint32_t*)0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */
    119. 

  119.   #define REG_PIOA_IDR     (*(__O  uint32_t*)0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */
    120. 

  120.   #define REG_PIOA_IMR     (*(__I  uint32_t*)0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */
    121. 

  121.   #define REG_PIOA_ISR     (*(__I  uint32_t*)0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */
    122. 

  122.   #define REG_PIOA_MDER    (*(__O  uint32_t*)0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */
    123. 

  123.   #define REG_PIOA_MDDR    (*(__O  uint32_t*)0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */
    124. 

  124.   #define REG_PIOA_MDSR    (*(__I  uint32_t*)0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */
    125. 

  125.   #define REG_PIOA_PUDR    (*(__O  uint32_t*)0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */
    126. 

  126.   #define REG_PIOA_PUER    (*(__O  uint32_t*)0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */
    127. 

  127.   #define REG_PIOA_PUSR    (*(__I  uint32_t*)0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */
    128. 

  128.   #define REG_PIOA_ABCDSR  (*(__IO uint32_t*)0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */
    129. 

  129.   #define REG_PIOA_IFSCDR  (*(__O  uint32_t*)0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */
    130. 

  130.   #define REG_PIOA_IFSCER  (*(__O  uint32_t*)0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */
    131. 

  131.   #define REG_PIOA_IFSCSR  (*(__I  uint32_t*)0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */
    132. 

  132.   #define REG_PIOA_SCDR    (*(__IO uint32_t*)0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
    133. 

  133.   #define REG_PIOA_PPDDR   (*(__O  uint32_t*)0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */
    134. 

  134.   #define REG_PIOA_PPDER   (*(__O  uint32_t*)0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */
    135. 

  135.   #define REG_PIOA_PPDSR   (*(__I  uint32_t*)0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */
    136. 

  136.   #define REG_PIOA_OWER    (*(__O  uint32_t*)0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */
    137. 

  137.   #define REG_PIOA_OWDR    (*(__O  uint32_t*)0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */
    138. 

  138.   #define REG_PIOA_OWSR    (*(__I  uint32_t*)0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */
    139. 

  139.   #define REG_PIOA_AIMER   (*(__O  uint32_t*)0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
    140. 

  140.   #define REG_PIOA_AIMDR   (*(__O  uint32_t*)0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disable Register */
    141. 

  141.   #define REG_PIOA_AIMMR   (*(__I  uint32_t*)0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
    142. 

  142.   #define REG_PIOA_ESR     (*(__O  uint32_t*)0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */
    143. 

  143.   #define REG_PIOA_LSR     (*(__O  uint32_t*)0x400E0EC4U) /**< \brief (PIOA) Level Select Register */
    144. 

  144.   #define REG_PIOA_ELSR    (*(__I  uint32_t*)0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */
    145. 

  145.   #define REG_PIOA_FELLSR  (*(__O  uint32_t*)0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low-Level Select Register */
    146. 

  146.   #define REG_PIOA_REHLSR  (*(__O  uint32_t*)0x400E0ED4U) /**< \brief (PIOA) Rising Edge/High-Level Select Register */
    147. 

  147.   #define REG_PIOA_FRLHSR  (*(__I  uint32_t*)0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
    148. 

  148.   #define REG_PIOA_LOCKSR  (*(__I  uint32_t*)0x400E0EE0U) /**< \brief (PIOA) Lock Status */
    149. 

  149.   #define REG_PIOA_WPMR    (*(__IO uint32_t*)0x400E0EE4U) /**< \brief (PIOA) Write Protection Mode Register */
    150. 

  150.   #define REG_PIOA_WPSR    (*(__I  uint32_t*)0x400E0EE8U) /**< \brief (PIOA) Write Protection Status Register */
    151. 

  151.   #define REG_PIOA_VERSION (*(__I  uint32_t*)0x400E0EFCU) /**< \brief (PIOA) Version Register */
    152. 

  152.   #define REG_PIOA_SCHMITT (*(__IO uint32_t*)0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */
    153. 

  153.   #define REG_PIOA_DRIVER  (*(__IO uint32_t*)0x400E0F18U) /**< \brief (PIOA) PIO I/O Drive Register */
    154. 

  154.   #define REG_PIOA_KER     (*(__IO uint32_t*)0x400E0F20U) /**< \brief (PIOA) Keypad Controller Enable Register */
    155. 

  155.   #define REG_PIOA_KRCR    (*(__IO uint32_t*)0x400E0F24U) /**< \brief (PIOA) Keypad Controller Row Column Register */
    156. 

  156.   #define REG_PIOA_KDR     (*(__IO uint32_t*)0x400E0F28U) /**< \brief (PIOA) Keypad Controller Debouncing Register */
    157. 

  157.   #define REG_PIOA_KIER    (*(__O  uint32_t*)0x400E0F30U) /**< \brief (PIOA) Keypad Controller Interrupt Enable Register */
    158. 

  158.   #define REG_PIOA_KIDR    (*(__O  uint32_t*)0x400E0F34U) /**< \brief (PIOA) Keypad Controller Interrupt Disable Register */
    159. 

  159.   #define REG_PIOA_KIMR    (*(__I  uint32_t*)0x400E0F38U) /**< \brief (PIOA) Keypad Controller Interrupt Mask Register */
    160. 

  160.   #define REG_PIOA_KSR     (*(__I  uint32_t*)0x400E0F3CU) /**< \brief (PIOA) Keypad Controller Status Register */
    161. 

  161.   #define REG_PIOA_KKPR    (*(__I  uint32_t*)0x400E0F40U) /**< \brief (PIOA) Keypad Controller Key Press Register */
    162. 

  162.   #define REG_PIOA_KKRR    (*(__I  uint32_t*)0x400E0F44U) /**< \brief (PIOA) Keypad Controller Key Release Register */
    163. 

  163.   #define REG_PIOA_PCMR    (*(__IO uint32_t*)0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */
    164. 

  164.   #define REG_PIOA_PCIER   (*(__O  uint32_t*)0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */
    165. 

  165.   #define REG_PIOA_PCIDR   (*(__O  uint32_t*)0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */
    166. 

  166.   #define REG_PIOA_PCIMR   (*(__I  uint32_t*)0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */
    167. 

  167.   #define REG_PIOA_PCISR   (*(__I  uint32_t*)0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */
    168. 

  168.   #define REG_PIOA_PCRHR   (*(__I  uint32_t*)0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */
    169. 

  169. #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
    170. 

  170. 

  171. #endif /* _SAME70_PIOA_INSTANCE_ */
    172.