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Momentum-Apps
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free-dap
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same70
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instance
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mcan0.h

mcan0.h 13 KB
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  1. /**
    2. 

  2.  * \file
    3. 

  3.  *
    4. 

  4.  * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
    5. 

  5.  *
    6. 

  6.  * \asf_license_start
    7. 

  7.  *
    8. 

  8.  * \page License
    9. 

  9.  *
    10. 

  10.  * Subject to your compliance with these terms, you may use Microchip
    11. 

  11.  * software and any derivatives exclusively with Microchip products.
    12. 

  12.  * It is your responsibility to comply with third party license terms applicable
    13. 

  13.  * to your use of third party software (including open source software) that
    14. 

  14.  * may accompany Microchip software.
    15. 

  15.  *
    16. 

  16.  * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
    17. 

  17.  * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
    18. 

  18.  * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
    19. 

  19.  * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
    20. 

  20.  * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
    21. 

  21.  * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
    22. 

  22.  * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
    23. 

  23.  * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
    24. 

  24.  * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
    25. 

  25.  * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
    26. 

  26.  * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
    27. 

  27.  *
    28. 

  28.  * \asf_license_stop
    29. 

  29.  *
    30. 

  30.  */
    31. 

  31. /*
    32. 

  32.  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
    33. 

  33.  */
    34. 

  34. 

  35. #ifndef _SAME70_MCAN0_INSTANCE_
    36. 

  36. #define _SAME70_MCAN0_INSTANCE_
    37. 

  37. 

  38. /* ========== Register definition for MCAN0 peripheral ========== */
    39. 

  39. #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
    40. 

  40.   #define REG_MCAN0_CREL                    (0x40030000U) /**< \brief (MCAN0) Core Release Register */
    41. 

  41.   #define REG_MCAN0_ENDN                    (0x40030004U) /**< \brief (MCAN0) Endian Register */
    42. 

  42.   #define REG_MCAN0_CUST                    (0x40030008U) /**< \brief (MCAN0) Customer Register */
    43. 

  43.   #define REG_MCAN0_FBTP                    (0x4003000CU) /**< \brief (MCAN0) Fast Bit Timing and Prescaler Register */
    44. 

  44.   #define REG_MCAN0_DBTP                    (0x4003000CU) /**< \brief (MCAN0) Data Bit Timing and Prescaler Register */
    45. 

  45.   #define REG_MCAN0_TEST                    (0x40030010U) /**< \brief (MCAN0) Test Register */
    46. 

  46.   #define REG_MCAN0_RWD                     (0x40030014U) /**< \brief (MCAN0) RAM Watchdog Register */
    47. 

  47.   #define REG_MCAN0_CCCR                    (0x40030018U) /**< \brief (MCAN0) CC Control Register */
    48. 

  48.   #define REG_MCAN0_BTP                     (0x4003001CU) /**< \brief (MCAN0) Bit Timing and Prescaler Register */
    49. 

  49.   #define REG_MCAN0_NBTP                    (0x4003001CU) /**< \brief (MCAN0) Nominal Bit Timing and Prescaler Register */
    50. 

  50.   #define REG_MCAN0_TSCC                    (0x40030020U) /**< \brief (MCAN0) Timestamp Counter Configuration Register */
    51. 

  51.   #define REG_MCAN0_TSCV                    (0x40030024U) /**< \brief (MCAN0) Timestamp Counter Value Register */
    52. 

  52.   #define REG_MCAN0_TOCC                    (0x40030028U) /**< \brief (MCAN0) Timeout Counter Configuration Register */
    53. 

  53.   #define REG_MCAN0_TOCV                    (0x4003002CU) /**< \brief (MCAN0) Timeout Counter Value Register */
    54. 

  54.   #define REG_MCAN0_ECR                     (0x40030040U) /**< \brief (MCAN0) Error Counter Register */
    55. 

  55.   #define REG_MCAN0_PSR                     (0x40030044U) /**< \brief (MCAN0) Protocol Status Register */
    56. 

  56.   #define REG_MCAN0_TDCR                    (0x40030048U) /**< \brief (MCAN0) Transmit Delay Compensation Register */
    57. 

  57.   #define REG_MCAN0_IR                      (0x40030050U) /**< \brief (MCAN0) Interrupt Register */
    58. 

  58.   #define REG_MCAN0_IE                      (0x40030054U) /**< \brief (MCAN0) Interrupt Enable Register */
    59. 

  59.   #define REG_MCAN0_ILS                     (0x40030058U) /**< \brief (MCAN0) Interrupt Line Select Register */
    60. 

  60.   #define REG_MCAN0_ILE                     (0x4003005CU) /**< \brief (MCAN0) Interrupt Line Enable Register */
    61. 

  61.   #define REG_MCAN0_GFC                     (0x40030080U) /**< \brief (MCAN0) Global Filter Configuration Register */
    62. 

  62.   #define REG_MCAN0_SIDFC                   (0x40030084U) /**< \brief (MCAN0) Standard ID Filter Configuration Register */
    63. 

  63.   #define REG_MCAN0_XIDFC                   (0x40030088U) /**< \brief (MCAN0) Extended ID Filter Configuration Register */
    64. 

  64.   #define REG_MCAN0_XIDAM                   (0x40030090U) /**< \brief (MCAN0) Extended ID AND Mask Register */
    65. 

  65.   #define REG_MCAN0_HPMS                    (0x40030094U) /**< \brief (MCAN0) High Priority Message Status Register */
    66. 

  66.   #define REG_MCAN0_NDAT1                   (0x40030098U) /**< \brief (MCAN0) New Data 1 Register */
    67. 

  67.   #define REG_MCAN0_NDAT2                   (0x4003009CU) /**< \brief (MCAN0) New Data 2 Register */
    68. 

  68.   #define REG_MCAN0_RXF0C                   (0x400300A0U) /**< \brief (MCAN0) Receive FIFO 0 Configuration Register */
    69. 

  69.   #define REG_MCAN0_RXF0S                   (0x400300A4U) /**< \brief (MCAN0) Receive FIFO 0 Status Register */
    70. 

  70.   #define REG_MCAN0_RXF0A                   (0x400300A8U) /**< \brief (MCAN0) Receive FIFO 0 Acknowledge Register */
    71. 

  71.   #define REG_MCAN0_RXBC                    (0x400300ACU) /**< \brief (MCAN0) Receive Rx Buffer Configuration Register */
    72. 

  72.   #define REG_MCAN0_RXF1C                   (0x400300B0U) /**< \brief (MCAN0) Receive FIFO 1 Configuration Register */
    73. 

  73.   #define REG_MCAN0_RXF1S                   (0x400300B4U) /**< \brief (MCAN0) Receive FIFO 1 Status Register */
    74. 

  74.   #define REG_MCAN0_RXF1A                   (0x400300B8U) /**< \brief (MCAN0) Receive FIFO 1 Acknowledge Register */
    75. 

  75.   #define REG_MCAN0_RXESC                   (0x400300BCU) /**< \brief (MCAN0) Receive Buffer / FIFO Element Size Configuration Register */
    76. 

  76.   #define REG_MCAN0_TXBC                    (0x400300C0U) /**< \brief (MCAN0) Transmit Buffer Configuration Register */
    77. 

  77.   #define REG_MCAN0_TXFQS                   (0x400300C4U) /**< \brief (MCAN0) Transmit FIFO/Queue Status Register */
    78. 

  78.   #define REG_MCAN0_TXESC                   (0x400300C8U) /**< \brief (MCAN0) Transmit Buffer Element Size Configuration Register */
    79. 

  79.   #define REG_MCAN0_TXBRP                   (0x400300CCU) /**< \brief (MCAN0) Transmit Buffer Request Pending Register */
    80. 

  80.   #define REG_MCAN0_TXBAR                   (0x400300D0U) /**< \brief (MCAN0) Transmit Buffer Add Request Register */
    81. 

  81.   #define REG_MCAN0_TXBCR                   (0x400300D4U) /**< \brief (MCAN0) Transmit Buffer Cancellation Request Register */
    82. 

  82.   #define REG_MCAN0_TXBTO                   (0x400300D8U) /**< \brief (MCAN0) Transmit Buffer Transmission Occurred Register */
    83. 

  83.   #define REG_MCAN0_TXBCF                   (0x400300DCU) /**< \brief (MCAN0) Transmit Buffer Cancellation Finished Register */
    84. 

  84.   #define REG_MCAN0_TXBTIE                  (0x400300E0U) /**< \brief (MCAN0) Transmit Buffer Transmission Interrupt Enable Register */
    85. 

  85.   #define REG_MCAN0_TXBCIE                  (0x400300E4U) /**< \brief (MCAN0) Transmit Buffer Cancellation Finished Interrupt Enable Register */
    86. 

  86.   #define REG_MCAN0_TXEFC                   (0x400300F0U) /**< \brief (MCAN0) Transmit Event FIFO Configuration Register */
    87. 

  87.   #define REG_MCAN0_TXEFS                   (0x400300F4U) /**< \brief (MCAN0) Transmit Event FIFO Status Register */
    88. 

  88.   #define REG_MCAN0_TXEFA                   (0x400300F8U) /**< \brief (MCAN0) Transmit Event FIFO Acknowledge Register */
    89. 

  89. #else
    90. 

  90.   #define REG_MCAN0_CREL   (*(__I  uint32_t*)0x40030000U) /**< \brief (MCAN0) Core Release Register */
    91. 

  91.   #define REG_MCAN0_ENDN   (*(__I  uint32_t*)0x40030004U) /**< \brief (MCAN0) Endian Register */
    92. 

  92.   #define REG_MCAN0_CUST   (*(__IO uint32_t*)0x40030008U) /**< \brief (MCAN0) Customer Register */
    93. 

  93.   #define REG_MCAN0_FBTP   (*(__IO uint32_t*)0x4003000CU) /**< \brief (MCAN0) Fast Bit Timing and Prescaler Register */
    94. 

  94.   #define REG_MCAN0_DBTP   (*(__IO uint32_t*)0x4003000CU) /**< \brief (MCAN0) Data Bit Timing and Prescaler Register */
    95. 

  95.   #define REG_MCAN0_TEST   (*(__IO uint32_t*)0x40030010U) /**< \brief (MCAN0) Test Register */
    96. 

  96.   #define REG_MCAN0_RWD    (*(__IO uint32_t*)0x40030014U) /**< \brief (MCAN0) RAM Watchdog Register */
    97. 

  97.   #define REG_MCAN0_CCCR   (*(__IO uint32_t*)0x40030018U) /**< \brief (MCAN0) CC Control Register */
    98. 

  98.   #define REG_MCAN0_BTP    (*(__IO uint32_t*)0x4003001CU) /**< \brief (MCAN0) Bit Timing and Prescaler Register */
    99. 

  99.   #define REG_MCAN0_NBTP   (*(__IO uint32_t*)0x4003001CU) /**< \brief (MCAN0) Nominal Bit Timing and Prescaler Register */
    100. 

  100.   #define REG_MCAN0_TSCC   (*(__IO uint32_t*)0x40030020U) /**< \brief (MCAN0) Timestamp Counter Configuration Register */
    101. 

  101.   #define REG_MCAN0_TSCV   (*(__IO uint32_t*)0x40030024U) /**< \brief (MCAN0) Timestamp Counter Value Register */
    102. 

  102.   #define REG_MCAN0_TOCC   (*(__IO uint32_t*)0x40030028U) /**< \brief (MCAN0) Timeout Counter Configuration Register */
    103. 

  103.   #define REG_MCAN0_TOCV   (*(__IO uint32_t*)0x4003002CU) /**< \brief (MCAN0) Timeout Counter Value Register */
    104. 

  104.   #define REG_MCAN0_ECR    (*(__I  uint32_t*)0x40030040U) /**< \brief (MCAN0) Error Counter Register */
    105. 

  105.   #define REG_MCAN0_PSR    (*(__I  uint32_t*)0x40030044U) /**< \brief (MCAN0) Protocol Status Register */
    106. 

  106.   #define REG_MCAN0_TDCR   (*(__IO uint32_t*)0x40030048U) /**< \brief (MCAN0) Transmit Delay Compensation Register */
    107. 

  107.   #define REG_MCAN0_IR     (*(__IO uint32_t*)0x40030050U) /**< \brief (MCAN0) Interrupt Register */
    108. 

  108.   #define REG_MCAN0_IE     (*(__IO uint32_t*)0x40030054U) /**< \brief (MCAN0) Interrupt Enable Register */
    109. 

  109.   #define REG_MCAN0_ILS    (*(__IO uint32_t*)0x40030058U) /**< \brief (MCAN0) Interrupt Line Select Register */
    110. 

  110.   #define REG_MCAN0_ILE    (*(__IO uint32_t*)0x4003005CU) /**< \brief (MCAN0) Interrupt Line Enable Register */
    111. 

  111.   #define REG_MCAN0_GFC    (*(__IO uint32_t*)0x40030080U) /**< \brief (MCAN0) Global Filter Configuration Register */
    112. 

  112.   #define REG_MCAN0_SIDFC  (*(__IO uint32_t*)0x40030084U) /**< \brief (MCAN0) Standard ID Filter Configuration Register */
    113. 

  113.   #define REG_MCAN0_XIDFC  (*(__IO uint32_t*)0x40030088U) /**< \brief (MCAN0) Extended ID Filter Configuration Register */
    114. 

  114.   #define REG_MCAN0_XIDAM  (*(__IO uint32_t*)0x40030090U) /**< \brief (MCAN0) Extended ID AND Mask Register */
    115. 

  115.   #define REG_MCAN0_HPMS   (*(__I  uint32_t*)0x40030094U) /**< \brief (MCAN0) High Priority Message Status Register */
    116. 

  116.   #define REG_MCAN0_NDAT1  (*(__IO uint32_t*)0x40030098U) /**< \brief (MCAN0) New Data 1 Register */
    117. 

  117.   #define REG_MCAN0_NDAT2  (*(__IO uint32_t*)0x4003009CU) /**< \brief (MCAN0) New Data 2 Register */
    118. 

  118.   #define REG_MCAN0_RXF0C  (*(__IO uint32_t*)0x400300A0U) /**< \brief (MCAN0) Receive FIFO 0 Configuration Register */
    119. 

  119.   #define REG_MCAN0_RXF0S  (*(__I  uint32_t*)0x400300A4U) /**< \brief (MCAN0) Receive FIFO 0 Status Register */
    120. 

  120.   #define REG_MCAN0_RXF0A  (*(__IO uint32_t*)0x400300A8U) /**< \brief (MCAN0) Receive FIFO 0 Acknowledge Register */
    121. 

  121.   #define REG_MCAN0_RXBC   (*(__IO uint32_t*)0x400300ACU) /**< \brief (MCAN0) Receive Rx Buffer Configuration Register */
    122. 

  122.   #define REG_MCAN0_RXF1C  (*(__IO uint32_t*)0x400300B0U) /**< \brief (MCAN0) Receive FIFO 1 Configuration Register */
    123. 

  123.   #define REG_MCAN0_RXF1S  (*(__I  uint32_t*)0x400300B4U) /**< \brief (MCAN0) Receive FIFO 1 Status Register */
    124. 

  124.   #define REG_MCAN0_RXF1A  (*(__IO uint32_t*)0x400300B8U) /**< \brief (MCAN0) Receive FIFO 1 Acknowledge Register */
    125. 

  125.   #define REG_MCAN0_RXESC  (*(__IO uint32_t*)0x400300BCU) /**< \brief (MCAN0) Receive Buffer / FIFO Element Size Configuration Register */
    126. 

  126.   #define REG_MCAN0_TXBC   (*(__IO uint32_t*)0x400300C0U) /**< \brief (MCAN0) Transmit Buffer Configuration Register */
    127. 

  127.   #define REG_MCAN0_TXFQS  (*(__I  uint32_t*)0x400300C4U) /**< \brief (MCAN0) Transmit FIFO/Queue Status Register */
    128. 

  128.   #define REG_MCAN0_TXESC  (*(__IO uint32_t*)0x400300C8U) /**< \brief (MCAN0) Transmit Buffer Element Size Configuration Register */
    129. 

  129.   #define REG_MCAN0_TXBRP  (*(__I  uint32_t*)0x400300CCU) /**< \brief (MCAN0) Transmit Buffer Request Pending Register */
    130. 

  130.   #define REG_MCAN0_TXBAR  (*(__IO uint32_t*)0x400300D0U) /**< \brief (MCAN0) Transmit Buffer Add Request Register */
    131. 

  131.   #define REG_MCAN0_TXBCR  (*(__IO uint32_t*)0x400300D4U) /**< \brief (MCAN0) Transmit Buffer Cancellation Request Register */
    132. 

  132.   #define REG_MCAN0_TXBTO  (*(__I  uint32_t*)0x400300D8U) /**< \brief (MCAN0) Transmit Buffer Transmission Occurred Register */
    133. 

  133.   #define REG_MCAN0_TXBCF  (*(__I  uint32_t*)0x400300DCU) /**< \brief (MCAN0) Transmit Buffer Cancellation Finished Register */
    134. 

  134.   #define REG_MCAN0_TXBTIE (*(__IO uint32_t*)0x400300E0U) /**< \brief (MCAN0) Transmit Buffer Transmission Interrupt Enable Register */
    135. 

  135.   #define REG_MCAN0_TXBCIE (*(__IO uint32_t*)0x400300E4U) /**< \brief (MCAN0) Transmit Buffer Cancellation Finished Interrupt Enable Register */
    136. 

  136.   #define REG_MCAN0_TXEFC  (*(__IO uint32_t*)0x400300F0U) /**< \brief (MCAN0) Transmit Event FIFO Configuration Register */
    137. 

  137.   #define REG_MCAN0_TXEFS  (*(__I  uint32_t*)0x400300F4U) /**< \brief (MCAN0) Transmit Event FIFO Status Register */
    138. 

  138.   #define REG_MCAN0_TXEFA  (*(__IO uint32_t*)0x400300F8U) /**< \brief (MCAN0) Transmit Event FIFO Acknowledge Register */
    139. 

  139. #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
    140. 

  140. 

  141. #endif /* _SAME70_MCAN0_INSTANCE_ */
    142.