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Momentum-Apps
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lib
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free-dap
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same70
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include
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instance
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matrix.h

matrix.h 11 KB
История Исходник

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  1. /**
    2. 

  2.  * \file
    3. 

  3.  *
    4. 

  4.  * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
    5. 

  5.  *
    6. 

  6.  * \asf_license_start
    7. 

  7.  *
    8. 

  8.  * \page License
    9. 

  9.  *
    10. 

  10.  * Subject to your compliance with these terms, you may use Microchip
    11. 

  11.  * software and any derivatives exclusively with Microchip products.
    12. 

  12.  * It is your responsibility to comply with third party license terms applicable
    13. 

  13.  * to your use of third party software (including open source software) that
    14. 

  14.  * may accompany Microchip software.
    15. 

  15.  *
    16. 

  16.  * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
    17. 

  17.  * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
    18. 

  18.  * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
    19. 

  19.  * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
    20. 

  20.  * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
    21. 

  21.  * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
    22. 

  22.  * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
    23. 

  23.  * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
    24. 

  24.  * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
    25. 

  25.  * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
    26. 

  26.  * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
    27. 

  27.  *
    28. 

  28.  * \asf_license_stop
    29. 

  29.  *
    30. 

  30.  */
    31. 

  31. /*
    32. 

  32.  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
    33. 

  33.  */
    34. 

  34. 

  35. #ifndef _SAME70_MATRIX_INSTANCE_
    36. 

  36. #define _SAME70_MATRIX_INSTANCE_
    37. 

  37. 

  38. /* ========== Register definition for MATRIX peripheral ========== */
    39. 

  39. #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
    40. 

  40.   #define REG_MATRIX_MCFG0                    (0x40088000U) /**< \brief (MATRIX) Master Configuration Register 0 */
    41. 

  41.   #define REG_MATRIX_MCFG1                    (0x40088004U) /**< \brief (MATRIX) Master Configuration Register 1 */
    42. 

  42.   #define REG_MATRIX_MCFG2                    (0x40088008U) /**< \brief (MATRIX) Master Configuration Register 2 */
    43. 

  43.   #define REG_MATRIX_MCFG3                    (0x4008800CU) /**< \brief (MATRIX) Master Configuration Register 3 */
    44. 

  44.   #define REG_MATRIX_MCFG4                    (0x40088010U) /**< \brief (MATRIX) Master Configuration Register 4 */
    45. 

  45.   #define REG_MATRIX_MCFG5                    (0x40088014U) /**< \brief (MATRIX) Master Configuration Register 5 */
    46. 

  46.   #define REG_MATRIX_MCFG6                    (0x40088018U) /**< \brief (MATRIX) Master Configuration Register 6 */
    47. 

  47.   #define REG_MATRIX_MCFG8                    (0x40088020U) /**< \brief (MATRIX) Master Configuration Register 8 */
    48. 

  48.   #define REG_MATRIX_MCFG9                    (0x40088024U) /**< \brief (MATRIX) Master Configuration Register 9 */
    49. 

  49.   #define REG_MATRIX_MCFG10                   (0x40088028U) /**< \brief (MATRIX) Master Configuration Register 10 */
    50. 

  50.   #define REG_MATRIX_MCFG11                   (0x4008802CU) /**< \brief (MATRIX) Master Configuration Register 11 */
    51. 

  51.   #define REG_MATRIX_MCFG12                   (0x40088030U) /**< \brief (MATRIX) Master Configuration Register 12 */
    52. 

  52.   #define REG_MATRIX_SCFG                     (0x40088040U) /**< \brief (MATRIX) Slave Configuration Register */
    53. 

  53.   #define REG_MATRIX_PRAS0                    (0x40088080U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
    54. 

  54.   #define REG_MATRIX_PRBS0                    (0x40088084U) /**< \brief (MATRIX) Priority Register B for Slave 0 */
    55. 

  55.   #define REG_MATRIX_PRAS1                    (0x40088088U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
    56. 

  56.   #define REG_MATRIX_PRBS1                    (0x4008808CU) /**< \brief (MATRIX) Priority Register B for Slave 1 */
    57. 

  57.   #define REG_MATRIX_PRAS2                    (0x40088090U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
    58. 

  58.   #define REG_MATRIX_PRBS2                    (0x40088094U) /**< \brief (MATRIX) Priority Register B for Slave 2 */
    59. 

  59.   #define REG_MATRIX_PRAS3                    (0x40088098U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
    60. 

  60.   #define REG_MATRIX_PRBS3                    (0x4008809CU) /**< \brief (MATRIX) Priority Register B for Slave 3 */
    61. 

  61.   #define REG_MATRIX_PRAS4                    (0x400880A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
    62. 

  62.   #define REG_MATRIX_PRBS4                    (0x400880A4U) /**< \brief (MATRIX) Priority Register B for Slave 4 */
    63. 

  63.   #define REG_MATRIX_PRAS5                    (0x400880A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */
    64. 

  64.   #define REG_MATRIX_PRBS5                    (0x400880ACU) /**< \brief (MATRIX) Priority Register B for Slave 5 */
    65. 

  65.   #define REG_MATRIX_PRAS6                    (0x400880B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */
    66. 

  66.   #define REG_MATRIX_PRBS6                    (0x400880B4U) /**< \brief (MATRIX) Priority Register B for Slave 6 */
    67. 

  67.   #define REG_MATRIX_PRAS7                    (0x400880B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */
    68. 

  68.   #define REG_MATRIX_PRBS7                    (0x400880BCU) /**< \brief (MATRIX) Priority Register B for Slave 7 */
    69. 

  69.   #define REG_MATRIX_PRAS8                    (0x400880C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */
    70. 

  70.   #define REG_MATRIX_PRBS8                    (0x400880C4U) /**< \brief (MATRIX) Priority Register B for Slave 8 */
    71. 

  71.   #define REG_MATRIX_MRCR                     (0x40088100U) /**< \brief (MATRIX) Master Remap Control Register */
    72. 

  72.   #define REG_CCFG_CAN0                       (0x40088110U) /**< \brief (MATRIX) CAN0 Configuration Register */
    73. 

  73.   #define REG_CCFG_SYSIO                      (0x40088114U) /**< \brief (MATRIX) System I/O and CAN1 Configuration Register */
    74. 

  74.   #define REG_CCFG_PCCR                       (0x40088118U) /**< \brief (MATRIX) Peripheral Clock Configuration Register */
    75. 

  75.   #define REG_CCFG_DYNCKG                     (0x4008811CU) /**< \brief (MATRIX) Dynamic Clock Gating Register */
    76. 

  76.   #define REG_CCFG_SMCNFCS                    (0x40088124U) /**< \brief (MATRIX) SMC NAND Flash Chip Select Configuration Register */
    77. 

  77.   #define REG_MATRIX_WPMR                     (0x400881E4U) /**< \brief (MATRIX) Write Protection Mode Register */
    78. 

  78.   #define REG_MATRIX_WPSR                     (0x400881E8U) /**< \brief (MATRIX) Write Protection Status Register */
    79. 

  79.   #define REG_MATRIX_VERSION                  (0x400881FCU) /**< \brief (MATRIX) Version Register */
    80. 

  80. #else
    81. 

  81.   #define REG_MATRIX_MCFG0   (*(__IO uint32_t*)0x40088000U) /**< \brief (MATRIX) Master Configuration Register 0 */
    82. 

  82.   #define REG_MATRIX_MCFG1   (*(__IO uint32_t*)0x40088004U) /**< \brief (MATRIX) Master Configuration Register 1 */
    83. 

  83.   #define REG_MATRIX_MCFG2   (*(__IO uint32_t*)0x40088008U) /**< \brief (MATRIX) Master Configuration Register 2 */
    84. 

  84.   #define REG_MATRIX_MCFG3   (*(__IO uint32_t*)0x4008800CU) /**< \brief (MATRIX) Master Configuration Register 3 */
    85. 

  85.   #define REG_MATRIX_MCFG4   (*(__IO uint32_t*)0x40088010U) /**< \brief (MATRIX) Master Configuration Register 4 */
    86. 

  86.   #define REG_MATRIX_MCFG5   (*(__IO uint32_t*)0x40088014U) /**< \brief (MATRIX) Master Configuration Register 5 */
    87. 

  87.   #define REG_MATRIX_MCFG6   (*(__IO uint32_t*)0x40088018U) /**< \brief (MATRIX) Master Configuration Register 6 */
    88. 

  88.   #define REG_MATRIX_MCFG8   (*(__IO uint32_t*)0x40088020U) /**< \brief (MATRIX) Master Configuration Register 8 */
    89. 

  89.   #define REG_MATRIX_MCFG9   (*(__IO uint32_t*)0x40088024U) /**< \brief (MATRIX) Master Configuration Register 9 */
    90. 

  90.   #define REG_MATRIX_MCFG10  (*(__IO uint32_t*)0x40088028U) /**< \brief (MATRIX) Master Configuration Register 10 */
    91. 

  91.   #define REG_MATRIX_MCFG11  (*(__IO uint32_t*)0x4008802CU) /**< \brief (MATRIX) Master Configuration Register 11 */
    92. 

  92.   #define REG_MATRIX_MCFG12  (*(__IO uint32_t*)0x40088030U) /**< \brief (MATRIX) Master Configuration Register 12 */
    93. 

  93.   #define REG_MATRIX_SCFG    (*(__IO uint32_t*)0x40088040U) /**< \brief (MATRIX) Slave Configuration Register */
    94. 

  94.   #define REG_MATRIX_PRAS0   (*(__IO uint32_t*)0x40088080U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
    95. 

  95.   #define REG_MATRIX_PRBS0   (*(__IO uint32_t*)0x40088084U) /**< \brief (MATRIX) Priority Register B for Slave 0 */
    96. 

  96.   #define REG_MATRIX_PRAS1   (*(__IO uint32_t*)0x40088088U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
    97. 

  97.   #define REG_MATRIX_PRBS1   (*(__IO uint32_t*)0x4008808CU) /**< \brief (MATRIX) Priority Register B for Slave 1 */
    98. 

  98.   #define REG_MATRIX_PRAS2   (*(__IO uint32_t*)0x40088090U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
    99. 

  99.   #define REG_MATRIX_PRBS2   (*(__IO uint32_t*)0x40088094U) /**< \brief (MATRIX) Priority Register B for Slave 2 */
    100. 

  100.   #define REG_MATRIX_PRAS3   (*(__IO uint32_t*)0x40088098U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
    101. 

  101.   #define REG_MATRIX_PRBS3   (*(__IO uint32_t*)0x4008809CU) /**< \brief (MATRIX) Priority Register B for Slave 3 */
    102. 

  102.   #define REG_MATRIX_PRAS4   (*(__IO uint32_t*)0x400880A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
    103. 

  103.   #define REG_MATRIX_PRBS4   (*(__IO uint32_t*)0x400880A4U) /**< \brief (MATRIX) Priority Register B for Slave 4 */
    104. 

  104.   #define REG_MATRIX_PRAS5   (*(__IO uint32_t*)0x400880A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */
    105. 

  105.   #define REG_MATRIX_PRBS5   (*(__IO uint32_t*)0x400880ACU) /**< \brief (MATRIX) Priority Register B for Slave 5 */
    106. 

  106.   #define REG_MATRIX_PRAS6   (*(__IO uint32_t*)0x400880B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */
    107. 

  107.   #define REG_MATRIX_PRBS6   (*(__IO uint32_t*)0x400880B4U) /**< \brief (MATRIX) Priority Register B for Slave 6 */
    108. 

  108.   #define REG_MATRIX_PRAS7   (*(__IO uint32_t*)0x400880B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */
    109. 

  109.   #define REG_MATRIX_PRBS7   (*(__IO uint32_t*)0x400880BCU) /**< \brief (MATRIX) Priority Register B for Slave 7 */
    110. 

  110.   #define REG_MATRIX_PRAS8   (*(__IO uint32_t*)0x400880C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */
    111. 

  111.   #define REG_MATRIX_PRBS8   (*(__IO uint32_t*)0x400880C4U) /**< \brief (MATRIX) Priority Register B for Slave 8 */
    112. 

  112.   #define REG_MATRIX_MRCR    (*(__IO uint32_t*)0x40088100U) /**< \brief (MATRIX) Master Remap Control Register */
    113. 

  113.   #define REG_CCFG_CAN0      (*(__IO uint32_t*)0x40088110U) /**< \brief (MATRIX) CAN0 Configuration Register */
    114. 

  114.   #define REG_CCFG_SYSIO     (*(__IO uint32_t*)0x40088114U) /**< \brief (MATRIX) System I/O and CAN1 Configuration Register */
    115. 

  115.   #define REG_CCFG_PCCR      (*(__IO uint32_t*)0x40088118U) /**< \brief (MATRIX) Peripheral Clock Configuration Register */
    116. 

  116.   #define REG_CCFG_DYNCKG    (*(__IO uint32_t*)0x4008811CU) /**< \brief (MATRIX) Dynamic Clock Gating Register */
    117. 

  117.   #define REG_CCFG_SMCNFCS   (*(__IO uint32_t*)0x40088124U) /**< \brief (MATRIX) SMC NAND Flash Chip Select Configuration Register */
    118. 

  118.   #define REG_MATRIX_WPMR    (*(__IO uint32_t*)0x400881E4U) /**< \brief (MATRIX) Write Protection Mode Register */
    119. 

  119.   #define REG_MATRIX_WPSR    (*(__I  uint32_t*)0x400881E8U) /**< \brief (MATRIX) Write Protection Status Register */
    120. 

  120.   #define REG_MATRIX_VERSION (*(__I  uint32_t*)0x400881FCU) /**< \brief (MATRIX) Version Register */
    121. 

  121. #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
    122. 

  122. 

  123. #endif /* _SAME70_MATRIX_INSTANCE_ */
    124.