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Momentum-Apps
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free-dap
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same70
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gmac.h

gmac.h 43 KB
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  1. /**
    2. 

  2.  * \file
    3. 

  3.  *
    4. 

  4.  * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
    5. 

  5.  *
    6. 

  6.  * \asf_license_start
    7. 

  7.  *
    8. 

  8.  * \page License
    9. 

  9.  *
    10. 

  10.  * Subject to your compliance with these terms, you may use Microchip
    11. 

  11.  * software and any derivatives exclusively with Microchip products.
    12. 

  12.  * It is your responsibility to comply with third party license terms applicable
    13. 

  13.  * to your use of third party software (including open source software) that
    14. 

  14.  * may accompany Microchip software.
    15. 

  15.  *
    16. 

  16.  * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
    17. 

  17.  * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
    18. 

  18.  * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
    19. 

  19.  * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
    20. 

  20.  * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
    21. 

  21.  * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
    22. 

  22.  * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
    23. 

  23.  * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
    24. 

  24.  * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
    25. 

  25.  * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
    26. 

  26.  * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
    27. 

  27.  *
    28. 

  28.  * \asf_license_stop
    29. 

  29.  *
    30. 

  30.  */
    31. 

  31. /*
    32. 

  32.  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
    33. 

  33.  */
    34. 

  34. 

  35. #ifndef _SAME70_GMAC_INSTANCE_
    36. 

  36. #define _SAME70_GMAC_INSTANCE_
    37. 

  37. 

  38. /* ========== Register definition for GMAC peripheral ========== */
    39. 

  39. #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
    40. 

  40.   #define REG_GMAC_NCR                        (0x40050000U) /**< \brief (GMAC) Network Control Register */
    41. 

  41.   #define REG_GMAC_NCFGR                      (0x40050004U) /**< \brief (GMAC) Network Configuration Register */
    42. 

  42.   #define REG_GMAC_NSR                        (0x40050008U) /**< \brief (GMAC) Network Status Register */
    43. 

  43.   #define REG_GMAC_UR                         (0x4005000CU) /**< \brief (GMAC) User Register */
    44. 

  44.   #define REG_GMAC_DCFGR                      (0x40050010U) /**< \brief (GMAC) DMA Configuration Register */
    45. 

  45.   #define REG_GMAC_TSR                        (0x40050014U) /**< \brief (GMAC) Transmit Status Register */
    46. 

  46.   #define REG_GMAC_RBQB                       (0x40050018U) /**< \brief (GMAC) Receive Buffer Queue Base Address Register */
    47. 

  47.   #define REG_GMAC_TBQB                       (0x4005001CU) /**< \brief (GMAC) Transmit Buffer Queue Base Address Register */
    48. 

  48.   #define REG_GMAC_RSR                        (0x40050020U) /**< \brief (GMAC) Receive Status Register */
    49. 

  49.   #define REG_GMAC_ISR                        (0x40050024U) /**< \brief (GMAC) Interrupt Status Register */
    50. 

  50.   #define REG_GMAC_IER                        (0x40050028U) /**< \brief (GMAC) Interrupt Enable Register */
    51. 

  51.   #define REG_GMAC_IDR                        (0x4005002CU) /**< \brief (GMAC) Interrupt Disable Register */
    52. 

  52.   #define REG_GMAC_IMR                        (0x40050030U) /**< \brief (GMAC) Interrupt Mask Register */
    53. 

  53.   #define REG_GMAC_MAN                        (0x40050034U) /**< \brief (GMAC) PHY Maintenance Register */
    54. 

  54.   #define REG_GMAC_RPQ                        (0x40050038U) /**< \brief (GMAC) Received Pause Quantum Register */
    55. 

  55.   #define REG_GMAC_TPQ                        (0x4005003CU) /**< \brief (GMAC) Transmit Pause Quantum Register */
    56. 

  56.   #define REG_GMAC_TPSF                       (0x40050040U) /**< \brief (GMAC) TX Partial Store and Forward Register */
    57. 

  57.   #define REG_GMAC_RPSF                       (0x40050044U) /**< \brief (GMAC) RX Partial Store and Forward Register */
    58. 

  58.   #define REG_GMAC_RJFML                      (0x40050048U) /**< \brief (GMAC) RX Jumbo Frame Max Length Register */
    59. 

  59.   #define REG_GMAC_HRB                        (0x40050080U) /**< \brief (GMAC) Hash Register Bottom */
    60. 

  60.   #define REG_GMAC_HRT                        (0x40050084U) /**< \brief (GMAC) Hash Register Top */
    61. 

  61.   #define REG_GMAC_SAB1                       (0x40050088U) /**< \brief (GMAC) Specific Address 1 Bottom Register */
    62. 

  62.   #define REG_GMAC_SAT1                       (0x4005008CU) /**< \brief (GMAC) Specific Address 1 Top Register */
    63. 

  63.   #define REG_GMAC_SAB2                       (0x40050090U) /**< \brief (GMAC) Specific Address 2 Bottom Register */
    64. 

  64.   #define REG_GMAC_SAT2                       (0x40050094U) /**< \brief (GMAC) Specific Address 2 Top Register */
    65. 

  65.   #define REG_GMAC_SAB3                       (0x40050098U) /**< \brief (GMAC) Specific Address 3 Bottom Register */
    66. 

  66.   #define REG_GMAC_SAT3                       (0x4005009CU) /**< \brief (GMAC) Specific Address 3 Top Register */
    67. 

  67.   #define REG_GMAC_SAB4                       (0x400500A0U) /**< \brief (GMAC) Specific Address 4 Bottom Register */
    68. 

  68.   #define REG_GMAC_SAT4                       (0x400500A4U) /**< \brief (GMAC) Specific Address 4 Top Register */
    69. 

  69.   #define REG_GMAC_TIDM1                      (0x400500A8U) /**< \brief (GMAC) Type ID Match 1 Register */
    70. 

  70.   #define REG_GMAC_TIDM2                      (0x400500ACU) /**< \brief (GMAC) Type ID Match 2 Register */
    71. 

  71.   #define REG_GMAC_TIDM3                      (0x400500B0U) /**< \brief (GMAC) Type ID Match 3 Register */
    72. 

  72.   #define REG_GMAC_TIDM4                      (0x400500B4U) /**< \brief (GMAC) Type ID Match 4 Register */
    73. 

  73.   #define REG_GMAC_WOL                        (0x400500B8U) /**< \brief (GMAC) Wake on LAN Register */
    74. 

  74.   #define REG_GMAC_IPGS                       (0x400500BCU) /**< \brief (GMAC) IPG Stretch Register */
    75. 

  75.   #define REG_GMAC_SVLAN                      (0x400500C0U) /**< \brief (GMAC) Stacked VLAN Register */
    76. 

  76.   #define REG_GMAC_TPFCP                      (0x400500C4U) /**< \brief (GMAC) Transmit PFC Pause Register */
    77. 

  77.   #define REG_GMAC_SAMB1                      (0x400500C8U) /**< \brief (GMAC) Specific Address 1 Mask Bottom Register */
    78. 

  78.   #define REG_GMAC_SAMT1                      (0x400500CCU) /**< \brief (GMAC) Specific Address 1 Mask Top Register */
    79. 

  79.   #define REG_GMAC_NSC                        (0x400500DCU) /**< \brief (GMAC) 1588 Timer Nanosecond Comparison Register */
    80. 

  80.   #define REG_GMAC_SCL                        (0x400500E0U) /**< \brief (GMAC) 1588 Timer Second Comparison Low Register */
    81. 

  81.   #define REG_GMAC_SCH                        (0x400500E4U) /**< \brief (GMAC) 1588 Timer Second Comparison High Register */
    82. 

  82.   #define REG_GMAC_EFTSH                      (0x400500E8U) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds High Register */
    83. 

  83.   #define REG_GMAC_EFRSH                      (0x400500ECU) /**< \brief (GMAC) PTP Event Frame Received Seconds High Register */
    84. 

  84.   #define REG_GMAC_PEFTSH                     (0x400500F0U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds High Register */
    85. 

  85.   #define REG_GMAC_PEFRSH                     (0x400500F4U) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds High Register */
    86. 

  86.   #define REG_GMAC_MID                        (0x400500FCU) /**< \brief (GMAC) Module ID Register */
    87. 

  87.   #define REG_GMAC_OTLO                       (0x40050100U) /**< \brief (GMAC) Octets Transmitted Low Register */
    88. 

  88.   #define REG_GMAC_OTHI                       (0x40050104U) /**< \brief (GMAC) Octets Transmitted High Register */
    89. 

  89.   #define REG_GMAC_FT                         (0x40050108U) /**< \brief (GMAC) Frames Transmitted Register */
    90. 

  90.   #define REG_GMAC_BCFT                       (0x4005010CU) /**< \brief (GMAC) Broadcast Frames Transmitted Register */
    91. 

  91.   #define REG_GMAC_MFT                        (0x40050110U) /**< \brief (GMAC) Multicast Frames Transmitted Register */
    92. 

  92.   #define REG_GMAC_PFT                        (0x40050114U) /**< \brief (GMAC) Pause Frames Transmitted Register */
    93. 

  93.   #define REG_GMAC_BFT64                      (0x40050118U) /**< \brief (GMAC) 64 Byte Frames Transmitted Register */
    94. 

  94.   #define REG_GMAC_TBFT127                    (0x4005011CU) /**< \brief (GMAC) 65 to 127 Byte Frames Transmitted Register */
    95. 

  95.   #define REG_GMAC_TBFT255                    (0x40050120U) /**< \brief (GMAC) 128 to 255 Byte Frames Transmitted Register */
    96. 

  96.   #define REG_GMAC_TBFT511                    (0x40050124U) /**< \brief (GMAC) 256 to 511 Byte Frames Transmitted Register */
    97. 

  97.   #define REG_GMAC_TBFT1023                   (0x40050128U) /**< \brief (GMAC) 512 to 1023 Byte Frames Transmitted Register */
    98. 

  98.   #define REG_GMAC_TBFT1518                   (0x4005012CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Transmitted Register */
    99. 

  99.   #define REG_GMAC_GTBFT1518                  (0x40050130U) /**< \brief (GMAC) Greater Than 1518 Byte Frames Transmitted Register */
    100. 

  100.   #define REG_GMAC_TUR                        (0x40050134U) /**< \brief (GMAC) Transmit Underruns Register */
    101. 

  101.   #define REG_GMAC_SCF                        (0x40050138U) /**< \brief (GMAC) Single Collision Frames Register */
    102. 

  102.   #define REG_GMAC_MCF                        (0x4005013CU) /**< \brief (GMAC) Multiple Collision Frames Register */
    103. 

  103.   #define REG_GMAC_EC                         (0x40050140U) /**< \brief (GMAC) Excessive Collisions Register */
    104. 

  104.   #define REG_GMAC_LC                         (0x40050144U) /**< \brief (GMAC) Late Collisions Register */
    105. 

  105.   #define REG_GMAC_DTF                        (0x40050148U) /**< \brief (GMAC) Deferred Transmission Frames Register */
    106. 

  106.   #define REG_GMAC_CSE                        (0x4005014CU) /**< \brief (GMAC) Carrier Sense Errors Register */
    107. 

  107.   #define REG_GMAC_ORLO                       (0x40050150U) /**< \brief (GMAC) Octets Received Low Received Register */
    108. 

  108.   #define REG_GMAC_ORHI                       (0x40050154U) /**< \brief (GMAC) Octets Received High Received Register */
    109. 

  109.   #define REG_GMAC_FR                         (0x40050158U) /**< \brief (GMAC) Frames Received Register */
    110. 

  110.   #define REG_GMAC_BCFR                       (0x4005015CU) /**< \brief (GMAC) Broadcast Frames Received Register */
    111. 

  111.   #define REG_GMAC_MFR                        (0x40050160U) /**< \brief (GMAC) Multicast Frames Received Register */
    112. 

  112.   #define REG_GMAC_PFR                        (0x40050164U) /**< \brief (GMAC) Pause Frames Received Register */
    113. 

  113.   #define REG_GMAC_BFR64                      (0x40050168U) /**< \brief (GMAC) 64 Byte Frames Received Register */
    114. 

  114.   #define REG_GMAC_TBFR127                    (0x4005016CU) /**< \brief (GMAC) 65 to 127 Byte Frames Received Register */
    115. 

  115.   #define REG_GMAC_TBFR255                    (0x40050170U) /**< \brief (GMAC) 128 to 255 Byte Frames Received Register */
    116. 

  116.   #define REG_GMAC_TBFR511                    (0x40050174U) /**< \brief (GMAC) 256 to 511 Byte Frames Received Register */
    117. 

  117.   #define REG_GMAC_TBFR1023                   (0x40050178U) /**< \brief (GMAC) 512 to 1023 Byte Frames Received Register */
    118. 

  118.   #define REG_GMAC_TBFR1518                   (0x4005017CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Received Register */
    119. 

  119.   #define REG_GMAC_TMXBFR                     (0x40050180U) /**< \brief (GMAC) 1519 to Maximum Byte Frames Received Register */
    120. 

  120.   #define REG_GMAC_UFR                        (0x40050184U) /**< \brief (GMAC) Undersize Frames Received Register */
    121. 

  121.   #define REG_GMAC_OFR                        (0x40050188U) /**< \brief (GMAC) Oversize Frames Received Register */
    122. 

  122.   #define REG_GMAC_JR                         (0x4005018CU) /**< \brief (GMAC) Jabbers Received Register */
    123. 

  123.   #define REG_GMAC_FCSE                       (0x40050190U) /**< \brief (GMAC) Frame Check Sequence Errors Register */
    124. 

  124.   #define REG_GMAC_LFFE                       (0x40050194U) /**< \brief (GMAC) Length Field Frame Errors Register */
    125. 

  125.   #define REG_GMAC_RSE                        (0x40050198U) /**< \brief (GMAC) Receive Symbol Errors Register */
    126. 

  126.   #define REG_GMAC_AE                         (0x4005019CU) /**< \brief (GMAC) Alignment Errors Register */
    127. 

  127.   #define REG_GMAC_RRE                        (0x400501A0U) /**< \brief (GMAC) Receive Resource Errors Register */
    128. 

  128.   #define REG_GMAC_ROE                        (0x400501A4U) /**< \brief (GMAC) Receive Overrun Register */
    129. 

  129.   #define REG_GMAC_IHCE                       (0x400501A8U) /**< \brief (GMAC) IP Header Checksum Errors Register */
    130. 

  130.   #define REG_GMAC_TCE                        (0x400501ACU) /**< \brief (GMAC) TCP Checksum Errors Register */
    131. 

  131.   #define REG_GMAC_UCE                        (0x400501B0U) /**< \brief (GMAC) UDP Checksum Errors Register */
    132. 

  132.   #define REG_GMAC_TISUBN                     (0x400501BCU) /**< \brief (GMAC) 1588 Timer Increment Sub-nanoseconds Register */
    133. 

  133.   #define REG_GMAC_TSH                        (0x400501C0U) /**< \brief (GMAC) 1588 Timer Seconds High Register */
    134. 

  134.   #define REG_GMAC_TSL                        (0x400501D0U) /**< \brief (GMAC) 1588 Timer Seconds Low Register */
    135. 

  135.   #define REG_GMAC_TN                         (0x400501D4U) /**< \brief (GMAC) 1588 Timer Nanoseconds Register */
    136. 

  136.   #define REG_GMAC_TA                         (0x400501D8U) /**< \brief (GMAC) 1588 Timer Adjust Register */
    137. 

  137.   #define REG_GMAC_TI                         (0x400501DCU) /**< \brief (GMAC) 1588 Timer Increment Register */
    138. 

  138.   #define REG_GMAC_EFTSL                      (0x400501E0U) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds Low Register */
    139. 

  139.   #define REG_GMAC_EFTN                       (0x400501E4U) /**< \brief (GMAC) PTP Event Frame Transmitted Nanoseconds Register */
    140. 

  140.   #define REG_GMAC_EFRSL                      (0x400501E8U) /**< \brief (GMAC) PTP Event Frame Received Seconds Low Register */
    141. 

  141.   #define REG_GMAC_EFRN                       (0x400501ECU) /**< \brief (GMAC) PTP Event Frame Received Nanoseconds Register */
    142. 

  142.   #define REG_GMAC_PEFTSL                     (0x400501F0U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds Low Register */
    143. 

  143.   #define REG_GMAC_PEFTN                      (0x400501F4U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Nanoseconds Register */
    144. 

  144.   #define REG_GMAC_PEFRSL                     (0x400501F8U) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds Low Register */
    145. 

  145.   #define REG_GMAC_PEFRN                      (0x400501FCU) /**< \brief (GMAC) PTP Peer Event Frame Received Nanoseconds Register */
    146. 

  146.   #define REG_GMAC_RXLPI                      (0x40050270U) /**< \brief (GMAC) Received LPI Transitions */
    147. 

  147.   #define REG_GMAC_RXLPITIME                  (0x40050274U) /**< \brief (GMAC) Received LPI Time */
    148. 

  148.   #define REG_GMAC_TXLPI                      (0x40050278U) /**< \brief (GMAC) Transmit LPI Transitions */
    149. 

  149.   #define REG_GMAC_TXLPITIME                  (0x4005027CU) /**< \brief (GMAC) Transmit LPI Time */
    150. 

  150.   #define REG_GMAC_ISRPQ                      (0x400503FCU) /**< \brief (GMAC) Interrupt Status Register Priority Queue (index = 1) */
    151. 

  151.   #define REG_GMAC_TBQBAPQ                    (0x4005043CU) /**< \brief (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) */
    152. 

  152.   #define REG_GMAC_RBQBAPQ                    (0x4005047CU) /**< \brief (GMAC) Receive Buffer Queue Base Address Register Priority Queue (index = 1) */
    153. 

  153.   #define REG_GMAC_RBSRPQ                     (0x4005049CU) /**< \brief (GMAC) Receive Buffer Size Register Priority Queue (index = 1) */
    154. 

  154.   #define REG_GMAC_CBSCR                      (0x400504BCU) /**< \brief (GMAC) Credit-Based Shaping Control Register */
    155. 

  155.   #define REG_GMAC_CBSISQA                    (0x400504C0U) /**< \brief (GMAC) Credit-Based Shaping IdleSlope Register for Queue A */
    156. 

  156.   #define REG_GMAC_CBSISQB                    (0x400504C4U) /**< \brief (GMAC) Credit-Based Shaping IdleSlope Register for Queue B */
    157. 

  157.   #define REG_GMAC_ST1RPQ                     (0x40050500U) /**< \brief (GMAC) Screening Type 1 Register Priority Queue (index = 0) */
    158. 

  158.   #define REG_GMAC_ST2RPQ                     (0x40050540U) /**< \brief (GMAC) Screening Type 2 Register Priority Queue (index = 0) */
    159. 

  159.   #define REG_GMAC_IERPQ                      (0x400505FCU) /**< \brief (GMAC) Interrupt Enable Register Priority Queue (index = 1) */
    160. 

  160.   #define REG_GMAC_IDRPQ                      (0x4005061CU) /**< \brief (GMAC) Interrupt Disable Register Priority Queue (index = 1) */
    161. 

  161.   #define REG_GMAC_IMRPQ                      (0x4005063CU) /**< \brief (GMAC) Interrupt Mask Register Priority Queue (index = 1) */
    162. 

  162.   #define REG_GMAC_ST2ER                      (0x400506E0U) /**< \brief (GMAC) Screening Type 2 Ethertype Register (index = 0) */
    163. 

  163.   #define REG_GMAC_ST2CW00                    (0x40050700U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 0) */
    164. 

  164.   #define REG_GMAC_ST2CW10                    (0x40050704U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 0) */
    165. 

  165.   #define REG_GMAC_ST2CW01                    (0x40050708U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 1) */
    166. 

  166.   #define REG_GMAC_ST2CW11                    (0x4005070CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 1) */
    167. 

  167.   #define REG_GMAC_ST2CW02                    (0x40050710U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 2) */
    168. 

  168.   #define REG_GMAC_ST2CW12                    (0x40050714U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 2) */
    169. 

  169.   #define REG_GMAC_ST2CW03                    (0x40050718U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 3) */
    170. 

  170.   #define REG_GMAC_ST2CW13                    (0x4005071CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 3) */
    171. 

  171.   #define REG_GMAC_ST2CW04                    (0x40050720U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 4) */
    172. 

  172.   #define REG_GMAC_ST2CW14                    (0x40050724U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 4) */
    173. 

  173.   #define REG_GMAC_ST2CW05                    (0x40050728U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 5) */
    174. 

  174.   #define REG_GMAC_ST2CW15                    (0x4005072CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 5) */
    175. 

  175.   #define REG_GMAC_ST2CW06                    (0x40050730U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 6) */
    176. 

  176.   #define REG_GMAC_ST2CW16                    (0x40050734U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 6) */
    177. 

  177.   #define REG_GMAC_ST2CW07                    (0x40050738U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 7) */
    178. 

  178.   #define REG_GMAC_ST2CW17                    (0x4005073CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 7) */
    179. 

  179.   #define REG_GMAC_ST2CW08                    (0x40050740U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 8) */
    180. 

  180.   #define REG_GMAC_ST2CW18                    (0x40050744U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 8) */
    181. 

  181.   #define REG_GMAC_ST2CW09                    (0x40050748U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 9) */
    182. 

  182.   #define REG_GMAC_ST2CW19                    (0x4005074CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 9) */
    183. 

  183.   #define REG_GMAC_ST2CW010                   (0x40050750U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 10) */
    184. 

  184.   #define REG_GMAC_ST2CW110                   (0x40050754U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 10) */
    185. 

  185.   #define REG_GMAC_ST2CW011                   (0x40050758U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 11) */
    186. 

  186.   #define REG_GMAC_ST2CW111                   (0x4005075CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 11) */
    187. 

  187.   #define REG_GMAC_ST2CW012                   (0x40050760U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 12) */
    188. 

  188.   #define REG_GMAC_ST2CW112                   (0x40050764U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 12) */
    189. 

  189.   #define REG_GMAC_ST2CW013                   (0x40050768U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 13) */
    190. 

  190.   #define REG_GMAC_ST2CW113                   (0x4005076CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 13) */
    191. 

  191.   #define REG_GMAC_ST2CW014                   (0x40050770U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 14) */
    192. 

  192.   #define REG_GMAC_ST2CW114                   (0x40050774U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 14) */
    193. 

  193.   #define REG_GMAC_ST2CW015                   (0x40050778U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 15) */
    194. 

  194.   #define REG_GMAC_ST2CW115                   (0x4005077CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 15) */
    195. 

  195.   #define REG_GMAC_ST2CW016                   (0x40050780U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 16) */
    196. 

  196.   #define REG_GMAC_ST2CW116                   (0x40050784U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 16) */
    197. 

  197.   #define REG_GMAC_ST2CW017                   (0x40050788U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 17) */
    198. 

  198.   #define REG_GMAC_ST2CW117                   (0x4005078CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 17) */
    199. 

  199.   #define REG_GMAC_ST2CW018                   (0x40050790U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 18) */
    200. 

  200.   #define REG_GMAC_ST2CW118                   (0x40050794U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 18) */
    201. 

  201.   #define REG_GMAC_ST2CW019                   (0x40050798U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 19) */
    202. 

  202.   #define REG_GMAC_ST2CW119                   (0x4005079CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 19) */
    203. 

  203.   #define REG_GMAC_ST2CW020                   (0x400507A0U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 20) */
    204. 

  204.   #define REG_GMAC_ST2CW120                   (0x400507A4U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 20) */
    205. 

  205.   #define REG_GMAC_ST2CW021                   (0x400507A8U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 21) */
    206. 

  206.   #define REG_GMAC_ST2CW121                   (0x400507ACU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 21) */
    207. 

  207.   #define REG_GMAC_ST2CW022                   (0x400507B0U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 22) */
    208. 

  208.   #define REG_GMAC_ST2CW122                   (0x400507B4U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 22) */
    209. 

  209.   #define REG_GMAC_ST2CW023                   (0x400507B8U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 23) */
    210. 

  210.   #define REG_GMAC_ST2CW123                   (0x400507BCU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 23) */
    211. 

  211. #else
    212. 

  212.   #define REG_GMAC_NCR       (*(__IO uint32_t*)0x40050000U) /**< \brief (GMAC) Network Control Register */
    213. 

  213.   #define REG_GMAC_NCFGR     (*(__IO uint32_t*)0x40050004U) /**< \brief (GMAC) Network Configuration Register */
    214. 

  214.   #define REG_GMAC_NSR       (*(__I  uint32_t*)0x40050008U) /**< \brief (GMAC) Network Status Register */
    215. 

  215.   #define REG_GMAC_UR        (*(__IO uint32_t*)0x4005000CU) /**< \brief (GMAC) User Register */
    216. 

  216.   #define REG_GMAC_DCFGR     (*(__IO uint32_t*)0x40050010U) /**< \brief (GMAC) DMA Configuration Register */
    217. 

  217.   #define REG_GMAC_TSR       (*(__IO uint32_t*)0x40050014U) /**< \brief (GMAC) Transmit Status Register */
    218. 

  218.   #define REG_GMAC_RBQB      (*(__IO uint32_t*)0x40050018U) /**< \brief (GMAC) Receive Buffer Queue Base Address Register */
    219. 

  219.   #define REG_GMAC_TBQB      (*(__IO uint32_t*)0x4005001CU) /**< \brief (GMAC) Transmit Buffer Queue Base Address Register */
    220. 

  220.   #define REG_GMAC_RSR       (*(__IO uint32_t*)0x40050020U) /**< \brief (GMAC) Receive Status Register */
    221. 

  221.   #define REG_GMAC_ISR       (*(__I  uint32_t*)0x40050024U) /**< \brief (GMAC) Interrupt Status Register */
    222. 

  222.   #define REG_GMAC_IER       (*(__O  uint32_t*)0x40050028U) /**< \brief (GMAC) Interrupt Enable Register */
    223. 

  223.   #define REG_GMAC_IDR       (*(__O  uint32_t*)0x4005002CU) /**< \brief (GMAC) Interrupt Disable Register */
    224. 

  224.   #define REG_GMAC_IMR       (*(__IO uint32_t*)0x40050030U) /**< \brief (GMAC) Interrupt Mask Register */
    225. 

  225.   #define REG_GMAC_MAN       (*(__IO uint32_t*)0x40050034U) /**< \brief (GMAC) PHY Maintenance Register */
    226. 

  226.   #define REG_GMAC_RPQ       (*(__I  uint32_t*)0x40050038U) /**< \brief (GMAC) Received Pause Quantum Register */
    227. 

  227.   #define REG_GMAC_TPQ       (*(__IO uint32_t*)0x4005003CU) /**< \brief (GMAC) Transmit Pause Quantum Register */
    228. 

  228.   #define REG_GMAC_TPSF      (*(__IO uint32_t*)0x40050040U) /**< \brief (GMAC) TX Partial Store and Forward Register */
    229. 

  229.   #define REG_GMAC_RPSF      (*(__IO uint32_t*)0x40050044U) /**< \brief (GMAC) RX Partial Store and Forward Register */
    230. 

  230.   #define REG_GMAC_RJFML     (*(__IO uint32_t*)0x40050048U) /**< \brief (GMAC) RX Jumbo Frame Max Length Register */
    231. 

  231.   #define REG_GMAC_HRB       (*(__IO uint32_t*)0x40050080U) /**< \brief (GMAC) Hash Register Bottom */
    232. 

  232.   #define REG_GMAC_HRT       (*(__IO uint32_t*)0x40050084U) /**< \brief (GMAC) Hash Register Top */
    233. 

  233.   #define REG_GMAC_SAB1      (*(__IO uint32_t*)0x40050088U) /**< \brief (GMAC) Specific Address 1 Bottom Register */
    234. 

  234.   #define REG_GMAC_SAT1      (*(__IO uint32_t*)0x4005008CU) /**< \brief (GMAC) Specific Address 1 Top Register */
    235. 

  235.   #define REG_GMAC_SAB2      (*(__IO uint32_t*)0x40050090U) /**< \brief (GMAC) Specific Address 2 Bottom Register */
    236. 

  236.   #define REG_GMAC_SAT2      (*(__IO uint32_t*)0x40050094U) /**< \brief (GMAC) Specific Address 2 Top Register */
    237. 

  237.   #define REG_GMAC_SAB3      (*(__IO uint32_t*)0x40050098U) /**< \brief (GMAC) Specific Address 3 Bottom Register */
    238. 

  238.   #define REG_GMAC_SAT3      (*(__IO uint32_t*)0x4005009CU) /**< \brief (GMAC) Specific Address 3 Top Register */
    239. 

  239.   #define REG_GMAC_SAB4      (*(__IO uint32_t*)0x400500A0U) /**< \brief (GMAC) Specific Address 4 Bottom Register */
    240. 

  240.   #define REG_GMAC_SAT4      (*(__IO uint32_t*)0x400500A4U) /**< \brief (GMAC) Specific Address 4 Top Register */
    241. 

  241.   #define REG_GMAC_TIDM1     (*(__IO uint32_t*)0x400500A8U) /**< \brief (GMAC) Type ID Match 1 Register */
    242. 

  242.   #define REG_GMAC_TIDM2     (*(__IO uint32_t*)0x400500ACU) /**< \brief (GMAC) Type ID Match 2 Register */
    243. 

  243.   #define REG_GMAC_TIDM3     (*(__IO uint32_t*)0x400500B0U) /**< \brief (GMAC) Type ID Match 3 Register */
    244. 

  244.   #define REG_GMAC_TIDM4     (*(__IO uint32_t*)0x400500B4U) /**< \brief (GMAC) Type ID Match 4 Register */
    245. 

  245.   #define REG_GMAC_WOL       (*(__IO uint32_t*)0x400500B8U) /**< \brief (GMAC) Wake on LAN Register */
    246. 

  246.   #define REG_GMAC_IPGS      (*(__IO uint32_t*)0x400500BCU) /**< \brief (GMAC) IPG Stretch Register */
    247. 

  247.   #define REG_GMAC_SVLAN     (*(__IO uint32_t*)0x400500C0U) /**< \brief (GMAC) Stacked VLAN Register */
    248. 

  248.   #define REG_GMAC_TPFCP     (*(__IO uint32_t*)0x400500C4U) /**< \brief (GMAC) Transmit PFC Pause Register */
    249. 

  249.   #define REG_GMAC_SAMB1     (*(__IO uint32_t*)0x400500C8U) /**< \brief (GMAC) Specific Address 1 Mask Bottom Register */
    250. 

  250.   #define REG_GMAC_SAMT1     (*(__IO uint32_t*)0x400500CCU) /**< \brief (GMAC) Specific Address 1 Mask Top Register */
    251. 

  251.   #define REG_GMAC_NSC       (*(__IO uint32_t*)0x400500DCU) /**< \brief (GMAC) 1588 Timer Nanosecond Comparison Register */
    252. 

  252.   #define REG_GMAC_SCL       (*(__IO uint32_t*)0x400500E0U) /**< \brief (GMAC) 1588 Timer Second Comparison Low Register */
    253. 

  253.   #define REG_GMAC_SCH       (*(__IO uint32_t*)0x400500E4U) /**< \brief (GMAC) 1588 Timer Second Comparison High Register */
    254. 

  254.   #define REG_GMAC_EFTSH     (*(__I  uint32_t*)0x400500E8U) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds High Register */
    255. 

  255.   #define REG_GMAC_EFRSH     (*(__I  uint32_t*)0x400500ECU) /**< \brief (GMAC) PTP Event Frame Received Seconds High Register */
    256. 

  256.   #define REG_GMAC_PEFTSH    (*(__I  uint32_t*)0x400500F0U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds High Register */
    257. 

  257.   #define REG_GMAC_PEFRSH    (*(__I  uint32_t*)0x400500F4U) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds High Register */
    258. 

  258.   #define REG_GMAC_MID       (*(__I  uint32_t*)0x400500FCU) /**< \brief (GMAC) Module ID Register */
    259. 

  259.   #define REG_GMAC_OTLO      (*(__I  uint32_t*)0x40050100U) /**< \brief (GMAC) Octets Transmitted Low Register */
    260. 

  260.   #define REG_GMAC_OTHI      (*(__I  uint32_t*)0x40050104U) /**< \brief (GMAC) Octets Transmitted High Register */
    261. 

  261.   #define REG_GMAC_FT        (*(__I  uint32_t*)0x40050108U) /**< \brief (GMAC) Frames Transmitted Register */
    262. 

  262.   #define REG_GMAC_BCFT      (*(__I  uint32_t*)0x4005010CU) /**< \brief (GMAC) Broadcast Frames Transmitted Register */
    263. 

  263.   #define REG_GMAC_MFT       (*(__I  uint32_t*)0x40050110U) /**< \brief (GMAC) Multicast Frames Transmitted Register */
    264. 

  264.   #define REG_GMAC_PFT       (*(__I  uint32_t*)0x40050114U) /**< \brief (GMAC) Pause Frames Transmitted Register */
    265. 

  265.   #define REG_GMAC_BFT64     (*(__I  uint32_t*)0x40050118U) /**< \brief (GMAC) 64 Byte Frames Transmitted Register */
    266. 

  266.   #define REG_GMAC_TBFT127   (*(__I  uint32_t*)0x4005011CU) /**< \brief (GMAC) 65 to 127 Byte Frames Transmitted Register */
    267. 

  267.   #define REG_GMAC_TBFT255   (*(__I  uint32_t*)0x40050120U) /**< \brief (GMAC) 128 to 255 Byte Frames Transmitted Register */
    268. 

  268.   #define REG_GMAC_TBFT511   (*(__I  uint32_t*)0x40050124U) /**< \brief (GMAC) 256 to 511 Byte Frames Transmitted Register */
    269. 

  269.   #define REG_GMAC_TBFT1023  (*(__I  uint32_t*)0x40050128U) /**< \brief (GMAC) 512 to 1023 Byte Frames Transmitted Register */
    270. 

  270.   #define REG_GMAC_TBFT1518  (*(__I  uint32_t*)0x4005012CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Transmitted Register */
    271. 

  271.   #define REG_GMAC_GTBFT1518 (*(__I  uint32_t*)0x40050130U) /**< \brief (GMAC) Greater Than 1518 Byte Frames Transmitted Register */
    272. 

  272.   #define REG_GMAC_TUR       (*(__I  uint32_t*)0x40050134U) /**< \brief (GMAC) Transmit Underruns Register */
    273. 

  273.   #define REG_GMAC_SCF       (*(__I  uint32_t*)0x40050138U) /**< \brief (GMAC) Single Collision Frames Register */
    274. 

  274.   #define REG_GMAC_MCF       (*(__I  uint32_t*)0x4005013CU) /**< \brief (GMAC) Multiple Collision Frames Register */
    275. 

  275.   #define REG_GMAC_EC        (*(__I  uint32_t*)0x40050140U) /**< \brief (GMAC) Excessive Collisions Register */
    276. 

  276.   #define REG_GMAC_LC        (*(__I  uint32_t*)0x40050144U) /**< \brief (GMAC) Late Collisions Register */
    277. 

  277.   #define REG_GMAC_DTF       (*(__I  uint32_t*)0x40050148U) /**< \brief (GMAC) Deferred Transmission Frames Register */
    278. 

  278.   #define REG_GMAC_CSE       (*(__I  uint32_t*)0x4005014CU) /**< \brief (GMAC) Carrier Sense Errors Register */
    279. 

  279.   #define REG_GMAC_ORLO      (*(__I  uint32_t*)0x40050150U) /**< \brief (GMAC) Octets Received Low Received Register */
    280. 

  280.   #define REG_GMAC_ORHI      (*(__I  uint32_t*)0x40050154U) /**< \brief (GMAC) Octets Received High Received Register */
    281. 

  281.   #define REG_GMAC_FR        (*(__I  uint32_t*)0x40050158U) /**< \brief (GMAC) Frames Received Register */
    282. 

  282.   #define REG_GMAC_BCFR      (*(__I  uint32_t*)0x4005015CU) /**< \brief (GMAC) Broadcast Frames Received Register */
    283. 

  283.   #define REG_GMAC_MFR       (*(__I  uint32_t*)0x40050160U) /**< \brief (GMAC) Multicast Frames Received Register */
    284. 

  284.   #define REG_GMAC_PFR       (*(__I  uint32_t*)0x40050164U) /**< \brief (GMAC) Pause Frames Received Register */
    285. 

  285.   #define REG_GMAC_BFR64     (*(__I  uint32_t*)0x40050168U) /**< \brief (GMAC) 64 Byte Frames Received Register */
    286. 

  286.   #define REG_GMAC_TBFR127   (*(__I  uint32_t*)0x4005016CU) /**< \brief (GMAC) 65 to 127 Byte Frames Received Register */
    287. 

  287.   #define REG_GMAC_TBFR255   (*(__I  uint32_t*)0x40050170U) /**< \brief (GMAC) 128 to 255 Byte Frames Received Register */
    288. 

  288.   #define REG_GMAC_TBFR511   (*(__I  uint32_t*)0x40050174U) /**< \brief (GMAC) 256 to 511 Byte Frames Received Register */
    289. 

  289.   #define REG_GMAC_TBFR1023  (*(__I  uint32_t*)0x40050178U) /**< \brief (GMAC) 512 to 1023 Byte Frames Received Register */
    290. 

  290.   #define REG_GMAC_TBFR1518  (*(__I  uint32_t*)0x4005017CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Received Register */
    291. 

  291.   #define REG_GMAC_TMXBFR    (*(__I  uint32_t*)0x40050180U) /**< \brief (GMAC) 1519 to Maximum Byte Frames Received Register */
    292. 

  292.   #define REG_GMAC_UFR       (*(__I  uint32_t*)0x40050184U) /**< \brief (GMAC) Undersize Frames Received Register */
    293. 

  293.   #define REG_GMAC_OFR       (*(__I  uint32_t*)0x40050188U) /**< \brief (GMAC) Oversize Frames Received Register */
    294. 

  294.   #define REG_GMAC_JR        (*(__I  uint32_t*)0x4005018CU) /**< \brief (GMAC) Jabbers Received Register */
    295. 

  295.   #define REG_GMAC_FCSE      (*(__I  uint32_t*)0x40050190U) /**< \brief (GMAC) Frame Check Sequence Errors Register */
    296. 

  296.   #define REG_GMAC_LFFE      (*(__I  uint32_t*)0x40050194U) /**< \brief (GMAC) Length Field Frame Errors Register */
    297. 

  297.   #define REG_GMAC_RSE       (*(__I  uint32_t*)0x40050198U) /**< \brief (GMAC) Receive Symbol Errors Register */
    298. 

  298.   #define REG_GMAC_AE        (*(__I  uint32_t*)0x4005019CU) /**< \brief (GMAC) Alignment Errors Register */
    299. 

  299.   #define REG_GMAC_RRE       (*(__I  uint32_t*)0x400501A0U) /**< \brief (GMAC) Receive Resource Errors Register */
    300. 

  300.   #define REG_GMAC_ROE       (*(__I  uint32_t*)0x400501A4U) /**< \brief (GMAC) Receive Overrun Register */
    301. 

  301.   #define REG_GMAC_IHCE      (*(__I  uint32_t*)0x400501A8U) /**< \brief (GMAC) IP Header Checksum Errors Register */
    302. 

  302.   #define REG_GMAC_TCE       (*(__I  uint32_t*)0x400501ACU) /**< \brief (GMAC) TCP Checksum Errors Register */
    303. 

  303.   #define REG_GMAC_UCE       (*(__I  uint32_t*)0x400501B0U) /**< \brief (GMAC) UDP Checksum Errors Register */
    304. 

  304.   #define REG_GMAC_TISUBN    (*(__IO uint32_t*)0x400501BCU) /**< \brief (GMAC) 1588 Timer Increment Sub-nanoseconds Register */
    305. 

  305.   #define REG_GMAC_TSH       (*(__IO uint32_t*)0x400501C0U) /**< \brief (GMAC) 1588 Timer Seconds High Register */
    306. 

  306.   #define REG_GMAC_TSL       (*(__IO uint32_t*)0x400501D0U) /**< \brief (GMAC) 1588 Timer Seconds Low Register */
    307. 

  307.   #define REG_GMAC_TN        (*(__IO uint32_t*)0x400501D4U) /**< \brief (GMAC) 1588 Timer Nanoseconds Register */
    308. 

  308.   #define REG_GMAC_TA        (*(__O  uint32_t*)0x400501D8U) /**< \brief (GMAC) 1588 Timer Adjust Register */
    309. 

  309.   #define REG_GMAC_TI        (*(__IO uint32_t*)0x400501DCU) /**< \brief (GMAC) 1588 Timer Increment Register */
    310. 

  310.   #define REG_GMAC_EFTSL     (*(__I  uint32_t*)0x400501E0U) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds Low Register */
    311. 

  311.   #define REG_GMAC_EFTN      (*(__I  uint32_t*)0x400501E4U) /**< \brief (GMAC) PTP Event Frame Transmitted Nanoseconds Register */
    312. 

  312.   #define REG_GMAC_EFRSL     (*(__I  uint32_t*)0x400501E8U) /**< \brief (GMAC) PTP Event Frame Received Seconds Low Register */
    313. 

  313.   #define REG_GMAC_EFRN      (*(__I  uint32_t*)0x400501ECU) /**< \brief (GMAC) PTP Event Frame Received Nanoseconds Register */
    314. 

  314.   #define REG_GMAC_PEFTSL    (*(__I  uint32_t*)0x400501F0U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds Low Register */
    315. 

  315.   #define REG_GMAC_PEFTN     (*(__I  uint32_t*)0x400501F4U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Nanoseconds Register */
    316. 

  316.   #define REG_GMAC_PEFRSL    (*(__I  uint32_t*)0x400501F8U) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds Low Register */
    317. 

  317.   #define REG_GMAC_PEFRN     (*(__I  uint32_t*)0x400501FCU) /**< \brief (GMAC) PTP Peer Event Frame Received Nanoseconds Register */
    318. 

  318.   #define REG_GMAC_RXLPI     (*(__I  uint32_t*)0x40050270U) /**< \brief (GMAC) Received LPI Transitions */
    319. 

  319.   #define REG_GMAC_RXLPITIME (*(__I  uint32_t*)0x40050274U) /**< \brief (GMAC) Received LPI Time */
    320. 

  320.   #define REG_GMAC_TXLPI     (*(__I  uint32_t*)0x40050278U) /**< \brief (GMAC) Transmit LPI Transitions */
    321. 

  321.   #define REG_GMAC_TXLPITIME (*(__I  uint32_t*)0x4005027CU) /**< \brief (GMAC) Transmit LPI Time */
    322. 

  322.   #define REG_GMAC_ISRPQ     (*(__I  uint32_t*)0x400503FCU) /**< \brief (GMAC) Interrupt Status Register Priority Queue (index = 1) 0 */
    323. 

  323.   #define REG_GMAC_TBQBAPQ   (*(__IO uint32_t*)0x4005043CU) /**< \brief (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) */
    324. 

  324.   #define REG_GMAC_RBQBAPQ   (*(__IO uint32_t*)0x4005047CU) /**< \brief (GMAC) Receive Buffer Queue Base Address Register Priority Queue (index = 1) */
    325. 

  325.   #define REG_GMAC_RBSRPQ    (*(__IO uint32_t*)0x4005049CU) /**< \brief (GMAC) Receive Buffer Size Register Priority Queue (index = 1) */
    326. 

  326.   #define REG_GMAC_CBSCR     (*(__IO uint32_t*)0x400504BCU) /**< \brief (GMAC) Credit-Based Shaping Control Register */
    327. 

  327.   #define REG_GMAC_CBSISQA   (*(__IO uint32_t*)0x400504C0U) /**< \brief (GMAC) Credit-Based Shaping IdleSlope Register for Queue A */
    328. 

  328.   #define REG_GMAC_CBSISQB   (*(__IO uint32_t*)0x400504C4U) /**< \brief (GMAC) Credit-Based Shaping IdleSlope Register for Queue B */
    329. 

  329.   #define REG_GMAC_ST1RPQ    (*(__IO uint32_t*)0x40050500U) /**< \brief (GMAC) Screening Type 1 Register Priority Queue (index = 0) */
    330. 

  330.   #define REG_GMAC_ST2RPQ    (*(__IO uint32_t*)0x40050540U) /**< \brief (GMAC) Screening Type 2 Register Priority Queue (index = 0) */
    331. 

  331.   #define REG_GMAC_IERPQ     (*(__O  uint32_t*)0x400505FCU) /**< \brief (GMAC) Interrupt Enable Register Priority Queue (index = 1) */
    332. 

  332.   #define REG_GMAC_IDRPQ     (*(__O  uint32_t*)0x4005061CU) /**< \brief (GMAC) Interrupt Disable Register Priority Queue (index = 1) */
    333. 

  333.   #define REG_GMAC_IMRPQ     (*(__IO uint32_t*)0x4005063CU) /**< \brief (GMAC) Interrupt Mask Register Priority Queue (index = 1) */
    334. 

  334.   #define REG_GMAC_ST2ER     (*(__IO uint32_t*)0x400506E0U) /**< \brief (GMAC) Screening Type 2 Ethertype Register (index = 0) */
    335. 

  335.   #define REG_GMAC_ST2CW00   (*(__IO uint32_t*)0x40050700U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 0) */
    336. 

  336.   #define REG_GMAC_ST2CW10   (*(__IO uint32_t*)0x40050704U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 0) */
    337. 

  337.   #define REG_GMAC_ST2CW01   (*(__IO uint32_t*)0x40050708U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 1) */
    338. 

  338.   #define REG_GMAC_ST2CW11   (*(__IO uint32_t*)0x4005070CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 1) */
    339. 

  339.   #define REG_GMAC_ST2CW02   (*(__IO uint32_t*)0x40050710U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 2) */
    340. 

  340.   #define REG_GMAC_ST2CW12   (*(__IO uint32_t*)0x40050714U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 2) */
    341. 

  341.   #define REG_GMAC_ST2CW03   (*(__IO uint32_t*)0x40050718U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 3) */
    342. 

  342.   #define REG_GMAC_ST2CW13   (*(__IO uint32_t*)0x4005071CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 3) */
    343. 

  343.   #define REG_GMAC_ST2CW04   (*(__IO uint32_t*)0x40050720U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 4) */
    344. 

  344.   #define REG_GMAC_ST2CW14   (*(__IO uint32_t*)0x40050724U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 4) */
    345. 

  345.   #define REG_GMAC_ST2CW05   (*(__IO uint32_t*)0x40050728U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 5) */
    346. 

  346.   #define REG_GMAC_ST2CW15   (*(__IO uint32_t*)0x4005072CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 5) */
    347. 

  347.   #define REG_GMAC_ST2CW06   (*(__IO uint32_t*)0x40050730U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 6) */
    348. 

  348.   #define REG_GMAC_ST2CW16   (*(__IO uint32_t*)0x40050734U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 6) */
    349. 

  349.   #define REG_GMAC_ST2CW07   (*(__IO uint32_t*)0x40050738U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 7) */
    350. 

  350.   #define REG_GMAC_ST2CW17   (*(__IO uint32_t*)0x4005073CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 7) */
    351. 

  351.   #define REG_GMAC_ST2CW08   (*(__IO uint32_t*)0x40050740U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 8) */
    352. 

  352.   #define REG_GMAC_ST2CW18   (*(__IO uint32_t*)0x40050744U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 8) */
    353. 

  353.   #define REG_GMAC_ST2CW09   (*(__IO uint32_t*)0x40050748U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 9) */
    354. 

  354.   #define REG_GMAC_ST2CW19   (*(__IO uint32_t*)0x4005074CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 9) */
    355. 

  355.   #define REG_GMAC_ST2CW010  (*(__IO uint32_t*)0x40050750U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 10) */
    356. 

  356.   #define REG_GMAC_ST2CW110  (*(__IO uint32_t*)0x40050754U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 10) */
    357. 

  357.   #define REG_GMAC_ST2CW011  (*(__IO uint32_t*)0x40050758U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 11) */
    358. 

  358.   #define REG_GMAC_ST2CW111  (*(__IO uint32_t*)0x4005075CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 11) */
    359. 

  359.   #define REG_GMAC_ST2CW012  (*(__IO uint32_t*)0x40050760U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 12) */
    360. 

  360.   #define REG_GMAC_ST2CW112  (*(__IO uint32_t*)0x40050764U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 12) */
    361. 

  361.   #define REG_GMAC_ST2CW013  (*(__IO uint32_t*)0x40050768U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 13) */
    362. 

  362.   #define REG_GMAC_ST2CW113  (*(__IO uint32_t*)0x4005076CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 13) */
    363. 

  363.   #define REG_GMAC_ST2CW014  (*(__IO uint32_t*)0x40050770U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 14) */
    364. 

  364.   #define REG_GMAC_ST2CW114  (*(__IO uint32_t*)0x40050774U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 14) */
    365. 

  365.   #define REG_GMAC_ST2CW015  (*(__IO uint32_t*)0x40050778U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 15) */
    366. 

  366.   #define REG_GMAC_ST2CW115  (*(__IO uint32_t*)0x4005077CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 15) */
    367. 

  367.   #define REG_GMAC_ST2CW016  (*(__IO uint32_t*)0x40050780U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 16) */
    368. 

  368.   #define REG_GMAC_ST2CW116  (*(__IO uint32_t*)0x40050784U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 16) */
    369. 

  369.   #define REG_GMAC_ST2CW017  (*(__IO uint32_t*)0x40050788U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 17) */
    370. 

  370.   #define REG_GMAC_ST2CW117  (*(__IO uint32_t*)0x4005078CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 17) */
    371. 

  371.   #define REG_GMAC_ST2CW018  (*(__IO uint32_t*)0x40050790U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 18) */
    372. 

  372.   #define REG_GMAC_ST2CW118  (*(__IO uint32_t*)0x40050794U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 18) */
    373. 

  373.   #define REG_GMAC_ST2CW019  (*(__IO uint32_t*)0x40050798U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 19) */
    374. 

  374.   #define REG_GMAC_ST2CW119  (*(__IO uint32_t*)0x4005079CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 19) */
    375. 

  375.   #define REG_GMAC_ST2CW020  (*(__IO uint32_t*)0x400507A0U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 20) */
    376. 

  376.   #define REG_GMAC_ST2CW120  (*(__IO uint32_t*)0x400507A4U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 20) */
    377. 

  377.   #define REG_GMAC_ST2CW021  (*(__IO uint32_t*)0x400507A8U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 21) */
    378. 

  378.   #define REG_GMAC_ST2CW121  (*(__IO uint32_t*)0x400507ACU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 21) */
    379. 

  379.   #define REG_GMAC_ST2CW022  (*(__IO uint32_t*)0x400507B0U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 22) */
    380. 

  380.   #define REG_GMAC_ST2CW122  (*(__IO uint32_t*)0x400507B4U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 22) */
    381. 

  381.   #define REG_GMAC_ST2CW023  (*(__IO uint32_t*)0x400507B8U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 23) */
    382. 

  382.   #define REG_GMAC_ST2CW123  (*(__IO uint32_t*)0x400507BCU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 23) */
    383. 

  383. #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
    384. 

  384. 

  385. #endif /* _SAME70_GMAC_INSTANCE_ */
    386.