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tcc0.h

tcc0.h 9.0 KB
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  1. /**
    2. 

  2.  * \file
    3. 

  3.  *
    4. 

  4.  * \brief Instance description for TCC0
    5. 

  5.  *
    6. 

  6.  * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
    7. 

  7.  *
    8. 

  8.  * \asf_license_start
    9. 

  9.  *
    10. 

  10.  * \page License
    11. 

  11.  *
    12. 

  12.  * Redistribution and use in source and binary forms, with or without
    13. 

  13.  * modification, are permitted provided that the following conditions are met:
    14. 

  14.  *
    15. 

  15.  * 1. Redistributions of source code must retain the above copyright notice,
    16. 

  16.  *    this list of conditions and the following disclaimer.
    17. 

  17.  *
    18. 

  18.  * 2. Redistributions in binary form must reproduce the above copyright notice,
    19. 

  19.  *    this list of conditions and the following disclaimer in the documentation
    20. 

  20.  *    and/or other materials provided with the distribution.
    21. 

  21.  *
    22. 

  22.  * 3. The name of Atmel may not be used to endorse or promote products derived
    23. 

  23.  *    from this software without specific prior written permission.
    24. 

  24.  *
    25. 

  25.  * 4. This software may only be redistributed and used in connection with an
    26. 

  26.  *    Atmel microcontroller product.
    27. 

  27.  *
    28. 

  28.  * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
    29. 

  29.  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
    30. 

  30.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
    31. 

  31.  * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
    32. 

  32.  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
    33. 

  33.  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
    34. 

  34.  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
    35. 

  35.  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
    36. 

  36.  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
    37. 

  37.  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
    38. 

  38.  * POSSIBILITY OF SUCH DAMAGE.
    39. 

  39.  *
    40. 

  40.  * \asf_license_stop
    41. 

  41.  *
    42. 

  42.  */
    43. 

  43. /*
    44. 

  44.  * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
    45. 

  45.  */
    46. 

  46. 

  47. #ifndef _SAMD21_TCC0_INSTANCE_
    48. 

  48. #define _SAMD21_TCC0_INSTANCE_
    49. 

  49. 

  50. /* ========== Register definition for TCC0 peripheral ========== */
    51. 

  51. #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
    52. 

  52. #define REG_TCC0_CTRLA             (0x42002000U) /**< \brief (TCC0) Control A */
    53. 

  53. #define REG_TCC0_CTRLBCLR          (0x42002004U) /**< \brief (TCC0) Control B Clear */
    54. 

  54. #define REG_TCC0_CTRLBSET          (0x42002005U) /**< \brief (TCC0) Control B Set */
    55. 

  55. #define REG_TCC0_SYNCBUSY          (0x42002008U) /**< \brief (TCC0) Synchronization Busy */
    56. 

  56. #define REG_TCC0_FCTRLA            (0x4200200CU) /**< \brief (TCC0) Recoverable Fault A Configuration */
    57. 

  57. #define REG_TCC0_FCTRLB            (0x42002010U) /**< \brief (TCC0) Recoverable Fault B Configuration */
    58. 

  58. #define REG_TCC0_WEXCTRL           (0x42002014U) /**< \brief (TCC0) Waveform Extension Configuration */
    59. 

  59. #define REG_TCC0_DRVCTRL           (0x42002018U) /**< \brief (TCC0) Driver Control */
    60. 

  60. #define REG_TCC0_DBGCTRL           (0x4200201EU) /**< \brief (TCC0) Debug Control */
    61. 

  61. #define REG_TCC0_EVCTRL            (0x42002020U) /**< \brief (TCC0) Event Control */
    62. 

  62. #define REG_TCC0_INTENCLR          (0x42002024U) /**< \brief (TCC0) Interrupt Enable Clear */
    63. 

  63. #define REG_TCC0_INTENSET          (0x42002028U) /**< \brief (TCC0) Interrupt Enable Set */
    64. 

  64. #define REG_TCC0_INTFLAG           (0x4200202CU) /**< \brief (TCC0) Interrupt Flag Status and Clear */
    65. 

  65. #define REG_TCC0_STATUS            (0x42002030U) /**< \brief (TCC0) Status */
    66. 

  66. #define REG_TCC0_COUNT             (0x42002034U) /**< \brief (TCC0) Count */
    67. 

  67. #define REG_TCC0_PATT              (0x42002038U) /**< \brief (TCC0) Pattern */
    68. 

  68. #define REG_TCC0_WAVE              (0x4200203CU) /**< \brief (TCC0) Waveform Control */
    69. 

  69. #define REG_TCC0_PER               (0x42002040U) /**< \brief (TCC0) Period */
    70. 

  70. #define REG_TCC0_CC0               (0x42002044U) /**< \brief (TCC0) Compare and Capture 0 */
    71. 

  71. #define REG_TCC0_CC1               (0x42002048U) /**< \brief (TCC0) Compare and Capture 1 */
    72. 

  72. #define REG_TCC0_CC2               (0x4200204CU) /**< \brief (TCC0) Compare and Capture 2 */
    73. 

  73. #define REG_TCC0_CC3               (0x42002050U) /**< \brief (TCC0) Compare and Capture 3 */
    74. 

  74. #define REG_TCC0_PATTB             (0x42002064U) /**< \brief (TCC0) Pattern Buffer */
    75. 

  75. #define REG_TCC0_WAVEB             (0x42002068U) /**< \brief (TCC0) Waveform Control Buffer */
    76. 

  76. #define REG_TCC0_PERB              (0x4200206CU) /**< \brief (TCC0) Period Buffer */
    77. 

  77. #define REG_TCC0_CCB0              (0x42002070U) /**< \brief (TCC0) Compare and Capture Buffer 0 */
    78. 

  78. #define REG_TCC0_CCB1              (0x42002074U) /**< \brief (TCC0) Compare and Capture Buffer 1 */
    79. 

  79. #define REG_TCC0_CCB2              (0x42002078U) /**< \brief (TCC0) Compare and Capture Buffer 2 */
    80. 

  80. #define REG_TCC0_CCB3              (0x4200207CU) /**< \brief (TCC0) Compare and Capture Buffer 3 */
    81. 

  81. #else
    82. 

  82. #define REG_TCC0_CTRLA             (*(RwReg  *)0x42002000U) /**< \brief (TCC0) Control A */
    83. 

  83. #define REG_TCC0_CTRLBCLR          (*(RwReg8 *)0x42002004U) /**< \brief (TCC0) Control B Clear */
    84. 

  84. #define REG_TCC0_CTRLBSET          (*(RwReg8 *)0x42002005U) /**< \brief (TCC0) Control B Set */
    85. 

  85. #define REG_TCC0_SYNCBUSY          (*(RoReg  *)0x42002008U) /**< \brief (TCC0) Synchronization Busy */
    86. 

  86. #define REG_TCC0_FCTRLA            (*(RwReg  *)0x4200200CU) /**< \brief (TCC0) Recoverable Fault A Configuration */
    87. 

  87. #define REG_TCC0_FCTRLB            (*(RwReg  *)0x42002010U) /**< \brief (TCC0) Recoverable Fault B Configuration */
    88. 

  88. #define REG_TCC0_WEXCTRL           (*(RwReg  *)0x42002014U) /**< \brief (TCC0) Waveform Extension Configuration */
    89. 

  89. #define REG_TCC0_DRVCTRL           (*(RwReg  *)0x42002018U) /**< \brief (TCC0) Driver Control */
    90. 

  90. #define REG_TCC0_DBGCTRL           (*(RwReg8 *)0x4200201EU) /**< \brief (TCC0) Debug Control */
    91. 

  91. #define REG_TCC0_EVCTRL            (*(RwReg  *)0x42002020U) /**< \brief (TCC0) Event Control */
    92. 

  92. #define REG_TCC0_INTENCLR          (*(RwReg  *)0x42002024U) /**< \brief (TCC0) Interrupt Enable Clear */
    93. 

  93. #define REG_TCC0_INTENSET          (*(RwReg  *)0x42002028U) /**< \brief (TCC0) Interrupt Enable Set */
    94. 

  94. #define REG_TCC0_INTFLAG           (*(RwReg  *)0x4200202CU) /**< \brief (TCC0) Interrupt Flag Status and Clear */
    95. 

  95. #define REG_TCC0_STATUS            (*(RwReg  *)0x42002030U) /**< \brief (TCC0) Status */
    96. 

  96. #define REG_TCC0_COUNT             (*(RwReg  *)0x42002034U) /**< \brief (TCC0) Count */
    97. 

  97. #define REG_TCC0_PATT              (*(RwReg16*)0x42002038U) /**< \brief (TCC0) Pattern */
    98. 

  98. #define REG_TCC0_WAVE              (*(RwReg  *)0x4200203CU) /**< \brief (TCC0) Waveform Control */
    99. 

  99. #define REG_TCC0_PER               (*(RwReg  *)0x42002040U) /**< \brief (TCC0) Period */
    100. 

  100. #define REG_TCC0_CC0               (*(RwReg  *)0x42002044U) /**< \brief (TCC0) Compare and Capture 0 */
    101. 

  101. #define REG_TCC0_CC1               (*(RwReg  *)0x42002048U) /**< \brief (TCC0) Compare and Capture 1 */
    102. 

  102. #define REG_TCC0_CC2               (*(RwReg  *)0x4200204CU) /**< \brief (TCC0) Compare and Capture 2 */
    103. 

  103. #define REG_TCC0_CC3               (*(RwReg  *)0x42002050U) /**< \brief (TCC0) Compare and Capture 3 */
    104. 

  104. #define REG_TCC0_PATTB             (*(RwReg16*)0x42002064U) /**< \brief (TCC0) Pattern Buffer */
    105. 

  105. #define REG_TCC0_WAVEB             (*(RwReg  *)0x42002068U) /**< \brief (TCC0) Waveform Control Buffer */
    106. 

  106. #define REG_TCC0_PERB              (*(RwReg  *)0x4200206CU) /**< \brief (TCC0) Period Buffer */
    107. 

  107. #define REG_TCC0_CCB0              (*(RwReg  *)0x42002070U) /**< \brief (TCC0) Compare and Capture Buffer 0 */
    108. 

  108. #define REG_TCC0_CCB1              (*(RwReg  *)0x42002074U) /**< \brief (TCC0) Compare and Capture Buffer 1 */
    109. 

  109. #define REG_TCC0_CCB2              (*(RwReg  *)0x42002078U) /**< \brief (TCC0) Compare and Capture Buffer 2 */
    110. 

  110. #define REG_TCC0_CCB3              (*(RwReg  *)0x4200207CU) /**< \brief (TCC0) Compare and Capture Buffer 3 */
    111. 

  111. #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
    112. 

  112. 

  113. /* ========== Instance parameters for TCC0 peripheral ========== */
    114. 

  114. #define TCC0_CC_NUM                 4        // Number of Compare/Capture units
    115. 

  115. #define TCC0_DITHERING              1        // Dithering feature implemented
    116. 

  116. #define TCC0_DMAC_ID_MC_0           14
    117. 

  117. #define TCC0_DMAC_ID_MC_1           15
    118. 

  118. #define TCC0_DMAC_ID_MC_2           16
    119. 

  119. #define TCC0_DMAC_ID_MC_3           17
    120. 

  120. #define TCC0_DMAC_ID_MC_LSB         14
    121. 

  121. #define TCC0_DMAC_ID_MC_MSB         17
    122. 

  122. #define TCC0_DMAC_ID_MC_SIZE        4
    123. 

  123. #define TCC0_DMAC_ID_OVF            13       // DMA overflow/underflow/retrigger trigger
    124. 

  124. #define TCC0_DTI                    1        // Dead-Time-Insertion feature implemented
    125. 

  125. #define TCC0_EXT                    31       // (@_DITHERING*16+@_PG*8+@_SWAP*4+@_DTI*2+@_OTMX*1)
    126. 

  126. #define TCC0_GCLK_ID                26       // Index of Generic Clock
    127. 

  127. #define TCC0_MASTER                 0       
    128. 

  128. #define TCC0_OTMX                   1        // Output Matrix feature implemented
    129. 

  129. #define TCC0_OW_NUM                 8        // Number of Output Waveforms
    130. 

  130. #define TCC0_PG                     1        // Pattern Generation feature implemented
    131. 

  131. #define TCC0_SIZE                   24      
    132. 

  132. #define TCC0_SWAP                   1        // DTI outputs swap feature implemented
    133. 

  133. #define TCC0_TYPE                   1        // TCC type 0 : NA, 1 : Master, 2 : Slave
    134. 

  134. 

  135. #endif /* _SAMD21_TCC0_INSTANCE_ */
    136.