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Momentum-Apps
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lib
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free-dap
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platform
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samd21
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include
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instance
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port.h

port.h 10 KB
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  1. /**
    2. 

  2.  * \file
    3. 

  3.  *
    4. 

  4.  * \brief Instance description for PORT
    5. 

  5.  *
    6. 

  6.  * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
    7. 

  7.  *
    8. 

  8.  * \asf_license_start
    9. 

  9.  *
    10. 

  10.  * \page License
    11. 

  11.  *
    12. 

  12.  * Redistribution and use in source and binary forms, with or without
    13. 

  13.  * modification, are permitted provided that the following conditions are met:
    14. 

  14.  *
    15. 

  15.  * 1. Redistributions of source code must retain the above copyright notice,
    16. 

  16.  *    this list of conditions and the following disclaimer.
    17. 

  17.  *
    18. 

  18.  * 2. Redistributions in binary form must reproduce the above copyright notice,
    19. 

  19.  *    this list of conditions and the following disclaimer in the documentation
    20. 

  20.  *    and/or other materials provided with the distribution.
    21. 

  21.  *
    22. 

  22.  * 3. The name of Atmel may not be used to endorse or promote products derived
    23. 

  23.  *    from this software without specific prior written permission.
    24. 

  24.  *
    25. 

  25.  * 4. This software may only be redistributed and used in connection with an
    26. 

  26.  *    Atmel microcontroller product.
    27. 

  27.  *
    28. 

  28.  * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
    29. 

  29.  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
    30. 

  30.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
    31. 

  31.  * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
    32. 

  32.  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
    33. 

  33.  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
    34. 

  34.  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
    35. 

  35.  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
    36. 

  36.  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
    37. 

  37.  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
    38. 

  38.  * POSSIBILITY OF SUCH DAMAGE.
    39. 

  39.  *
    40. 

  40.  * \asf_license_stop
    41. 

  41.  *
    42. 

  42.  */
    43. 

  43. /*
    44. 

  44.  * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
    45. 

  45.  */
    46. 

  46. 

  47. #ifndef _SAMD21_PORT_INSTANCE_
    48. 

  48. #define _SAMD21_PORT_INSTANCE_
    49. 

  49. 

  50. /* ========== Register definition for PORT peripheral ========== */
    51. 

  51. #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
    52. 

  52. #define REG_PORT_DIR0              (0x41004400U) /**< \brief (PORT) Data Direction 0 */
    53. 

  53. #define REG_PORT_DIRCLR0           (0x41004404U) /**< \brief (PORT) Data Direction Clear 0 */
    54. 

  54. #define REG_PORT_DIRSET0           (0x41004408U) /**< \brief (PORT) Data Direction Set 0 */
    55. 

  55. #define REG_PORT_DIRTGL0           (0x4100440CU) /**< \brief (PORT) Data Direction Toggle 0 */
    56. 

  56. #define REG_PORT_OUT0              (0x41004410U) /**< \brief (PORT) Data Output Value 0 */
    57. 

  57. #define REG_PORT_OUTCLR0           (0x41004414U) /**< \brief (PORT) Data Output Value Clear 0 */
    58. 

  58. #define REG_PORT_OUTSET0           (0x41004418U) /**< \brief (PORT) Data Output Value Set 0 */
    59. 

  59. #define REG_PORT_OUTTGL0           (0x4100441CU) /**< \brief (PORT) Data Output Value Toggle 0 */
    60. 

  60. #define REG_PORT_IN0               (0x41004420U) /**< \brief (PORT) Data Input Value 0 */
    61. 

  61. #define REG_PORT_CTRL0             (0x41004424U) /**< \brief (PORT) Control 0 */
    62. 

  62. #define REG_PORT_WRCONFIG0         (0x41004428U) /**< \brief (PORT) Write Configuration 0 */
    63. 

  63. #define REG_PORT_PMUX0             (0x41004430U) /**< \brief (PORT) Peripheral Multiplexing 0 */
    64. 

  64. #define REG_PORT_PINCFG0           (0x41004440U) /**< \brief (PORT) Pin Configuration 0 */
    65. 

  65. #define REG_PORT_DIR1              (0x41004480U) /**< \brief (PORT) Data Direction 1 */
    66. 

  66. #define REG_PORT_DIRCLR1           (0x41004484U) /**< \brief (PORT) Data Direction Clear 1 */
    67. 

  67. #define REG_PORT_DIRSET1           (0x41004488U) /**< \brief (PORT) Data Direction Set 1 */
    68. 

  68. #define REG_PORT_DIRTGL1           (0x4100448CU) /**< \brief (PORT) Data Direction Toggle 1 */
    69. 

  69. #define REG_PORT_OUT1              (0x41004490U) /**< \brief (PORT) Data Output Value 1 */
    70. 

  70. #define REG_PORT_OUTCLR1           (0x41004494U) /**< \brief (PORT) Data Output Value Clear 1 */
    71. 

  71. #define REG_PORT_OUTSET1           (0x41004498U) /**< \brief (PORT) Data Output Value Set 1 */
    72. 

  72. #define REG_PORT_OUTTGL1           (0x4100449CU) /**< \brief (PORT) Data Output Value Toggle 1 */
    73. 

  73. #define REG_PORT_IN1               (0x410044A0U) /**< \brief (PORT) Data Input Value 1 */
    74. 

  74. #define REG_PORT_CTRL1             (0x410044A4U) /**< \brief (PORT) Control 1 */
    75. 

  75. #define REG_PORT_WRCONFIG1         (0x410044A8U) /**< \brief (PORT) Write Configuration 1 */
    76. 

  76. #define REG_PORT_PMUX1             (0x410044B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */
    77. 

  77. #define REG_PORT_PINCFG1           (0x410044C0U) /**< \brief (PORT) Pin Configuration 1 */
    78. 

  78. #else
    79. 

  79. #define REG_PORT_DIR0              (*(RwReg  *)0x41004400U) /**< \brief (PORT) Data Direction 0 */
    80. 

  80. #define REG_PORT_DIRCLR0           (*(RwReg  *)0x41004404U) /**< \brief (PORT) Data Direction Clear 0 */
    81. 

  81. #define REG_PORT_DIRSET0           (*(RwReg  *)0x41004408U) /**< \brief (PORT) Data Direction Set 0 */
    82. 

  82. #define REG_PORT_DIRTGL0           (*(RwReg  *)0x4100440CU) /**< \brief (PORT) Data Direction Toggle 0 */
    83. 

  83. #define REG_PORT_OUT0              (*(RwReg  *)0x41004410U) /**< \brief (PORT) Data Output Value 0 */
    84. 

  84. #define REG_PORT_OUTCLR0           (*(RwReg  *)0x41004414U) /**< \brief (PORT) Data Output Value Clear 0 */
    85. 

  85. #define REG_PORT_OUTSET0           (*(RwReg  *)0x41004418U) /**< \brief (PORT) Data Output Value Set 0 */
    86. 

  86. #define REG_PORT_OUTTGL0           (*(RwReg  *)0x4100441CU) /**< \brief (PORT) Data Output Value Toggle 0 */
    87. 

  87. #define REG_PORT_IN0               (*(RoReg  *)0x41004420U) /**< \brief (PORT) Data Input Value 0 */
    88. 

  88. #define REG_PORT_CTRL0             (*(RwReg  *)0x41004424U) /**< \brief (PORT) Control 0 */
    89. 

  89. #define REG_PORT_WRCONFIG0         (*(WoReg  *)0x41004428U) /**< \brief (PORT) Write Configuration 0 */
    90. 

  90. #define REG_PORT_PMUX0             (*(RwReg  *)0x41004430U) /**< \brief (PORT) Peripheral Multiplexing 0 */
    91. 

  91. #define REG_PORT_PINCFG0           (*(RwReg  *)0x41004440U) /**< \brief (PORT) Pin Configuration 0 */
    92. 

  92. #define REG_PORT_DIR1              (*(RwReg  *)0x41004480U) /**< \brief (PORT) Data Direction 1 */
    93. 

  93. #define REG_PORT_DIRCLR1           (*(RwReg  *)0x41004484U) /**< \brief (PORT) Data Direction Clear 1 */
    94. 

  94. #define REG_PORT_DIRSET1           (*(RwReg  *)0x41004488U) /**< \brief (PORT) Data Direction Set 1 */
    95. 

  95. #define REG_PORT_DIRTGL1           (*(RwReg  *)0x4100448CU) /**< \brief (PORT) Data Direction Toggle 1 */
    96. 

  96. #define REG_PORT_OUT1              (*(RwReg  *)0x41004490U) /**< \brief (PORT) Data Output Value 1 */
    97. 

  97. #define REG_PORT_OUTCLR1           (*(RwReg  *)0x41004494U) /**< \brief (PORT) Data Output Value Clear 1 */
    98. 

  98. #define REG_PORT_OUTSET1           (*(RwReg  *)0x41004498U) /**< \brief (PORT) Data Output Value Set 1 */
    99. 

  99. #define REG_PORT_OUTTGL1           (*(RwReg  *)0x4100449CU) /**< \brief (PORT) Data Output Value Toggle 1 */
    100. 

  100. #define REG_PORT_IN1               (*(RoReg  *)0x410044A0U) /**< \brief (PORT) Data Input Value 1 */
    101. 

  101. #define REG_PORT_CTRL1             (*(RwReg  *)0x410044A4U) /**< \brief (PORT) Control 1 */
    102. 

  102. #define REG_PORT_WRCONFIG1         (*(WoReg  *)0x410044A8U) /**< \brief (PORT) Write Configuration 1 */
    103. 

  103. #define REG_PORT_PMUX1             (*(RwReg  *)0x410044B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */
    104. 

  104. #define REG_PORT_PINCFG1           (*(RwReg  *)0x410044C0U) /**< \brief (PORT) Pin Configuration 1 */
    105. 

  105. #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
    106. 

  106. 

  107. /* ========== Instance parameters for PORT peripheral ========== */
    108. 

  108. #define PORT_BITS                   64       // Number of PORT pins
    109. 

  109. #define PORT_DIR_DEFAULT_VAL        { 0x00000000, 0x00000000 } // Default value for DIR of all pins
    110. 

  110. #define PORT_DIR_IMPLEMENTED        { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for DIR of all pins
    111. 

  111. #define PORT_DRVSTR                 1        // DRVSTR supported
    112. 

  112. #define PORT_DRVSTR_DEFAULT_VAL     { 0xD8FFFFFF, 0xC0C3FFFF } // Default value for DRVSTR of all pins
    113. 

  113. #define PORT_DRVSTR_IMPLEMENTED     { 0xD8FFFFFF, 0xC0C3FFFF } // Implementation mask for DRVSTR of all pins
    114. 

  114. #define PORT_EVENT_IMPLEMENTED      { 0x00000000, 0x00000000 }
    115. 

  115. #define PORT_INEN_DEFAULT_VAL       { 0x00000000, 0x00000000 } // Default value for INEN of all pins
    116. 

  116. #define PORT_INEN_IMPLEMENTED       { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for INEN of all pins
    117. 

  117. #define PORT_ODRAIN                 0        // ODRAIN supported
    118. 

  118. #define PORT_ODRAIN_DEFAULT_VAL     { 0x00000000, 0x00000000 } // Default value for ODRAIN of all pins
    119. 

  119. #define PORT_ODRAIN_IMPLEMENTED     { 0x00000000, 0x00000000 } // Implementation mask for ODRAIN of all pins
    120. 

  120. #define PORT_OUT_DEFAULT_VAL        { 0x00000000, 0x00000000 } // Default value for OUT of all pins
    121. 

  121. #define PORT_OUT_IMPLEMENTED        { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for OUT of all pins
    122. 

  122. #define PORT_PIN_IMPLEMENTED        { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for all PORT pins
    123. 

  123. #define PORT_PMUXBIT0_DEFAULT_VAL   { 0x00000000, 0x00000000 } // Default value for PMUX[0] of all pins
    124. 

  124. #define PORT_PMUXBIT0_IMPLEMENTED   { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for PMUX[0] of all pins
    125. 

  125. #define PORT_PMUXBIT1_DEFAULT_VAL   { 0x40000000, 0x00000000 } // Default value for PMUX[1] of all pins
    126. 

  126. #define PORT_PMUXBIT1_IMPLEMENTED   { 0xDBFFFFF3, 0xC0C3FF0F } // Implementation mask for PMUX[1] of all pins
    127. 

  127. #define PORT_PMUXBIT2_DEFAULT_VAL   { 0x40000000, 0x00000000 } // Default value for PMUX[2] of all pins
    128. 

  128. #define PORT_PMUXBIT2_IMPLEMENTED   { 0xDBFFFFF7, 0xC0C3FF0F } // Implementation mask for PMUX[2] of all pins
    129. 

  129. #define PORT_PMUXBIT3_DEFAULT_VAL   { 0x00000000, 0x00000000 } // Default value for PMUX[3] of all pins
    130. 

  130. #define PORT_PMUXBIT3_IMPLEMENTED   { 0x00000000, 0x00000000 } // Implementation mask for PMUX[3] of all pins
    131. 

  131. #define PORT_PMUXEN_DEFAULT_VAL     { 0x64000000, 0x3F3C0000 } // Default value for PMUXEN of all pins
    132. 

  132. #define PORT_PMUXEN_IMPLEMENTED     { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for PMUXEN of all pins
    133. 

  133. #define PORT_PULLEN_DEFAULT_VAL     { 0x00000000, 0x00000000 } // Default value for PULLEN of all pins
    134. 

  134. #define PORT_PULLEN_IMPLEMENTED     { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for PULLEN of all pins
    135. 

  135. #define PORT_SLEWLIM                0        // SLEWLIM supported
    136. 

  136. #define PORT_SLEWLIM_DEFAULT_VAL    { 0x00000000, 0x00000000 } // Default value for SLEWLIM of all pins
    137. 

  137. #define PORT_SLEWLIM_IMPLEMENTED    { 0x00000000, 0x00000000 } // Implementation mask for SLEWLIM of all pins
    138. 

  138. 

  139. #endif /* _SAMD21_PORT_INSTANCE_ */
    140.