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Momentum-Apps
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evsys.h

evsys.h 47 KB
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  1. /**
    2. 

  2.  * \file
    3. 

  3.  *
    4. 

  4.  * \brief Component description for EVSYS
    5. 

  5.  *
    6. 

  6.  * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
    7. 

  7.  *
    8. 

  8.  * \asf_license_start
    9. 

  9.  *
    10. 

  10.  * \page License
    11. 

  11.  *
    12. 

  12.  * Redistribution and use in source and binary forms, with or without
    13. 

  13.  * modification, are permitted provided that the following conditions are met:
    14. 

  14.  *
    15. 

  15.  * 1. Redistributions of source code must retain the above copyright notice,
    16. 

  16.  *    this list of conditions and the following disclaimer.
    17. 

  17.  *
    18. 

  18.  * 2. Redistributions in binary form must reproduce the above copyright notice,
    19. 

  19.  *    this list of conditions and the following disclaimer in the documentation
    20. 

  20.  *    and/or other materials provided with the distribution.
    21. 

  21.  *
    22. 

  22.  * 3. The name of Atmel may not be used to endorse or promote products derived
    23. 

  23.  *    from this software without specific prior written permission.
    24. 

  24.  *
    25. 

  25.  * 4. This software may only be redistributed and used in connection with an
    26. 

  26.  *    Atmel microcontroller product.
    27. 

  27.  *
    28. 

  28.  * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
    29. 

  29.  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
    30. 

  30.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
    31. 

  31.  * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
    32. 

  32.  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
    33. 

  33.  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
    34. 

  34.  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
    35. 

  35.  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
    36. 

  36.  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
    37. 

  37.  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
    38. 

  38.  * POSSIBILITY OF SUCH DAMAGE.
    39. 

  39.  *
    40. 

  40.  * \asf_license_stop
    41. 

  41.  *
    42. 

  42.  */
    43. 

  43. /*
    44. 

  44.  * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
    45. 

  45.  */
    46. 

  46. 

  47. #ifndef _SAMD21_EVSYS_COMPONENT_
    48. 

  48. #define _SAMD21_EVSYS_COMPONENT_
    49. 

  49. 

  50. /* ========================================================================== */
    51. 

  51. /**  SOFTWARE API DEFINITION FOR EVSYS */
    52. 

  52. /* ========================================================================== */
    53. 

  53. /** \addtogroup SAMD21_EVSYS Event System Interface */
    54. 

  54. /*@{*/
    55. 

  55. 

  56. #define EVSYS_U2208
    57. 

  57. #define REV_EVSYS                   0x101
    58. 

  58. 

  59. /* -------- EVSYS_CTRL : (EVSYS Offset: 0x00) ( /W  8) Control -------- */
    60. 

  60. #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
    61. 

  61. typedef union {
    62. 

  62.   struct {
    63. 

  63.     uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
    64. 

  64.     uint8_t  :3;               /*!< bit:  1.. 3  Reserved                           */
    65. 

  65.     uint8_t  GCLKREQ:1;        /*!< bit:      4  Generic Clock Requests             */
    66. 

  66.     uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
    67. 

  67.   } bit;                       /*!< Structure used for bit  access                  */
    68. 

  68.   uint8_t reg;                 /*!< Type      used for register access              */
    69. 

  69. } EVSYS_CTRL_Type;
    70. 

  70. #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
    71. 

  71. 

  72. #define EVSYS_CTRL_OFFSET           0x00         /**< \brief (EVSYS_CTRL offset) Control */
    73. 

  73. #define EVSYS_CTRL_RESETVALUE       0x00ul       /**< \brief (EVSYS_CTRL reset_value) Control */
    74. 

  74. 

  75. #define EVSYS_CTRL_SWRST_Pos        0            /**< \brief (EVSYS_CTRL) Software Reset */
    76. 

  76. #define EVSYS_CTRL_SWRST            (0x1ul << EVSYS_CTRL_SWRST_Pos)
    77. 

  77. #define EVSYS_CTRL_GCLKREQ_Pos      4            /**< \brief (EVSYS_CTRL) Generic Clock Requests */
    78. 

  78. #define EVSYS_CTRL_GCLKREQ          (0x1ul << EVSYS_CTRL_GCLKREQ_Pos)
    79. 

  79. #define EVSYS_CTRL_MASK             0x11ul       /**< \brief (EVSYS_CTRL) MASK Register */
    80. 

  80. 

  81. /* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x04) (R/W 32) Channel -------- */
    82. 

  82. #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
    83. 

  83. typedef union {
    84. 

  84.   struct {
    85. 

  85.     uint32_t CHANNEL:4;        /*!< bit:  0.. 3  Channel Selection                  */
    86. 

  86.     uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
    87. 

  87.     uint32_t SWEVT:1;          /*!< bit:      8  Software Event                     */
    88. 

  88.     uint32_t :7;               /*!< bit:  9..15  Reserved                           */
    89. 

  89.     uint32_t EVGEN:7;          /*!< bit: 16..22  Event Generator Selection          */
    90. 

  90.     uint32_t :1;               /*!< bit:     23  Reserved                           */
    91. 

  91.     uint32_t PATH:2;           /*!< bit: 24..25  Path Selection                     */
    92. 

  92.     uint32_t EDGSEL:2;         /*!< bit: 26..27  Edge Detection Selection           */
    93. 

  93.     uint32_t :4;               /*!< bit: 28..31  Reserved                           */
    94. 

  94.   } bit;                       /*!< Structure used for bit  access                  */
    95. 

  95.   uint32_t reg;                /*!< Type      used for register access              */
    96. 

  96. } EVSYS_CHANNEL_Type;
    97. 

  97. #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
    98. 

  98. 

  99. #define EVSYS_CHANNEL_OFFSET        0x04         /**< \brief (EVSYS_CHANNEL offset) Channel */
    100. 

  100. #define EVSYS_CHANNEL_RESETVALUE    0x00000000ul /**< \brief (EVSYS_CHANNEL reset_value) Channel */
    101. 

  101. 

  102. #define EVSYS_CHANNEL_CHANNEL_Pos   0            /**< \brief (EVSYS_CHANNEL) Channel Selection */
    103. 

  103. #define EVSYS_CHANNEL_CHANNEL_Msk   (0xFul << EVSYS_CHANNEL_CHANNEL_Pos)
    104. 

  104. #define EVSYS_CHANNEL_CHANNEL(value) ((EVSYS_CHANNEL_CHANNEL_Msk & ((value) << EVSYS_CHANNEL_CHANNEL_Pos)))
    105. 

  105. #define EVSYS_CHANNEL_SWEVT_Pos     8            /**< \brief (EVSYS_CHANNEL) Software Event */
    106. 

  106. #define EVSYS_CHANNEL_SWEVT         (0x1ul << EVSYS_CHANNEL_SWEVT_Pos)
    107. 

  107. #define EVSYS_CHANNEL_EVGEN_Pos     16           /**< \brief (EVSYS_CHANNEL) Event Generator Selection */
    108. 

  108. #define EVSYS_CHANNEL_EVGEN_Msk     (0x7Ful << EVSYS_CHANNEL_EVGEN_Pos)
    109. 

  109. #define EVSYS_CHANNEL_EVGEN(value)  ((EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos)))
    110. 

  110. #define EVSYS_CHANNEL_PATH_Pos      24           /**< \brief (EVSYS_CHANNEL) Path Selection */
    111. 

  111. #define EVSYS_CHANNEL_PATH_Msk      (0x3ul << EVSYS_CHANNEL_PATH_Pos)
    112. 

  112. #define EVSYS_CHANNEL_PATH(value)   ((EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos)))
    113. 

  113. #define   EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val 0x0ul  /**< \brief (EVSYS_CHANNEL) Synchronous path */
    114. 

  114. #define   EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val 0x1ul  /**< \brief (EVSYS_CHANNEL) Resynchronized path */
    115. 

  115. #define   EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val 0x2ul  /**< \brief (EVSYS_CHANNEL) Asynchronous path */
    116. 

  116. #define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
    117. 

  117. #define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos)
    118. 

  118. #define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
    119. 

  119. #define EVSYS_CHANNEL_EDGSEL_Pos    26           /**< \brief (EVSYS_CHANNEL) Edge Detection Selection */
    120. 

  120. #define EVSYS_CHANNEL_EDGSEL_Msk    (0x3ul << EVSYS_CHANNEL_EDGSEL_Pos)
    121. 

  121. #define EVSYS_CHANNEL_EDGSEL(value) ((EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos)))
    122. 

  122. #define   EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val 0x0ul  /**< \brief (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */
    123. 

  123. #define   EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val 0x1ul  /**< \brief (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */
    124. 

  124. #define   EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val 0x2ul  /**< \brief (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */
    125. 

  125. #define   EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val 0x3ul  /**< \brief (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path */
    126. 

  126. #define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos)
    127. 

  127. #define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
    128. 

  128. #define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
    129. 

  129. #define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos)
    130. 

  130. #define EVSYS_CHANNEL_MASK          0x0F7F010Ful /**< \brief (EVSYS_CHANNEL) MASK Register */
    131. 

  131. 

  132. /* -------- EVSYS_USER : (EVSYS Offset: 0x08) (R/W 16) User Multiplexer -------- */
    133. 

  133. #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
    134. 

  134. typedef union {
    135. 

  135.   struct {
    136. 

  136.     uint16_t USER:5;           /*!< bit:  0.. 4  User Multiplexer Selection         */
    137. 

  137.     uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
    138. 

  138.     uint16_t CHANNEL:5;        /*!< bit:  8..12  Channel Event Selection            */
    139. 

  139.     uint16_t :3;               /*!< bit: 13..15  Reserved                           */
    140. 

  140.   } bit;                       /*!< Structure used for bit  access                  */
    141. 

  141.   uint16_t reg;                /*!< Type      used for register access              */
    142. 

  142. } EVSYS_USER_Type;
    143. 

  143. #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
    144. 

  144. 

  145. #define EVSYS_USER_OFFSET           0x08         /**< \brief (EVSYS_USER offset) User Multiplexer */
    146. 

  146. #define EVSYS_USER_RESETVALUE       0x0000ul     /**< \brief (EVSYS_USER reset_value) User Multiplexer */
    147. 

  147. 

  148. #define EVSYS_USER_USER_Pos         0            /**< \brief (EVSYS_USER) User Multiplexer Selection */
    149. 

  149. #define EVSYS_USER_USER_Msk         (0x1Ful << EVSYS_USER_USER_Pos)
    150. 

  150. #define EVSYS_USER_USER(value)      ((EVSYS_USER_USER_Msk & ((value) << EVSYS_USER_USER_Pos)))
    151. 

  151. #define EVSYS_USER_CHANNEL_Pos      8            /**< \brief (EVSYS_USER) Channel Event Selection */
    152. 

  152. #define EVSYS_USER_CHANNEL_Msk      (0x1Ful << EVSYS_USER_CHANNEL_Pos)
    153. 

  153. #define EVSYS_USER_CHANNEL(value)   ((EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos)))
    154. 

  154. #define   EVSYS_USER_CHANNEL_0_Val        0x0ul  /**< \brief (EVSYS_USER) No Channel Output Selected */
    155. 

  155. #define EVSYS_USER_CHANNEL_0        (EVSYS_USER_CHANNEL_0_Val      << EVSYS_USER_CHANNEL_Pos)
    156. 

  156. #define EVSYS_USER_MASK             0x1F1Ful     /**< \brief (EVSYS_USER) MASK Register */
    157. 

  157. 

  158. /* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/  32) Channel Status -------- */
    159. 

  159. #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
    160. 

  160. typedef union {
    161. 

  161.   struct {
    162. 

  162.     uint32_t USRRDY0:1;        /*!< bit:      0  Channel 0 User Ready               */
    163. 

  163.     uint32_t USRRDY1:1;        /*!< bit:      1  Channel 1 User Ready               */
    164. 

  164.     uint32_t USRRDY2:1;        /*!< bit:      2  Channel 2 User Ready               */
    165. 

  165.     uint32_t USRRDY3:1;        /*!< bit:      3  Channel 3 User Ready               */
    166. 

  166.     uint32_t USRRDY4:1;        /*!< bit:      4  Channel 4 User Ready               */
    167. 

  167.     uint32_t USRRDY5:1;        /*!< bit:      5  Channel 5 User Ready               */
    168. 

  168.     uint32_t USRRDY6:1;        /*!< bit:      6  Channel 6 User Ready               */
    169. 

  169.     uint32_t USRRDY7:1;        /*!< bit:      7  Channel 7 User Ready               */
    170. 

  170.     uint32_t CHBUSY0:1;        /*!< bit:      8  Channel 0 Busy                     */
    171. 

  171.     uint32_t CHBUSY1:1;        /*!< bit:      9  Channel 1 Busy                     */
    172. 

  172.     uint32_t CHBUSY2:1;        /*!< bit:     10  Channel 2 Busy                     */
    173. 

  173.     uint32_t CHBUSY3:1;        /*!< bit:     11  Channel 3 Busy                     */
    174. 

  174.     uint32_t CHBUSY4:1;        /*!< bit:     12  Channel 4 Busy                     */
    175. 

  175.     uint32_t CHBUSY5:1;        /*!< bit:     13  Channel 5 Busy                     */
    176. 

  176.     uint32_t CHBUSY6:1;        /*!< bit:     14  Channel 6 Busy                     */
    177. 

  177.     uint32_t CHBUSY7:1;        /*!< bit:     15  Channel 7 Busy                     */
    178. 

  178.     uint32_t USRRDY8:1;        /*!< bit:     16  Channel 8 User Ready               */
    179. 

  179.     uint32_t USRRDY9:1;        /*!< bit:     17  Channel 9 User Ready               */
    180. 

  180.     uint32_t USRRDY10:1;       /*!< bit:     18  Channel 10 User Ready              */
    181. 

  181.     uint32_t USRRDY11:1;       /*!< bit:     19  Channel 11 User Ready              */
    182. 

  182.     uint32_t :4;               /*!< bit: 20..23  Reserved                           */
    183. 

  183.     uint32_t CHBUSY8:1;        /*!< bit:     24  Channel 8 Busy                     */
    184. 

  184.     uint32_t CHBUSY9:1;        /*!< bit:     25  Channel 9 Busy                     */
    185. 

  185.     uint32_t CHBUSY10:1;       /*!< bit:     26  Channel 10 Busy                    */
    186. 

  186.     uint32_t CHBUSY11:1;       /*!< bit:     27  Channel 11 Busy                    */
    187. 

  187.     uint32_t :4;               /*!< bit: 28..31  Reserved                           */
    188. 

  188.   } bit;                       /*!< Structure used for bit  access                  */
    189. 

  189.   struct {
    190. 

  190.     uint32_t USRRDY:8;         /*!< bit:  0.. 7  Channel x User Ready               */
    191. 

  191.     uint32_t CHBUSY:8;         /*!< bit:  8..15  Channel x Busy                     */
    192. 

  192.     uint32_t USRRDYp8:4;       /*!< bit: 16..19  Channel x+8 User Ready             */
    193. 

  193.     uint32_t :4;               /*!< bit: 20..23  Reserved                           */
    194. 

  194.     uint32_t CHBUSYp8:4;       /*!< bit: 24..27  Channel x+8 Busy                   */
    195. 

  195.     uint32_t :4;               /*!< bit: 28..31  Reserved                           */
    196. 

  196.   } vec;                       /*!< Structure used for vec  access                  */
    197. 

  197.   uint32_t reg;                /*!< Type      used for register access              */
    198. 

  198. } EVSYS_CHSTATUS_Type;
    199. 

  199. #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
    200. 

  200. 

  201. #define EVSYS_CHSTATUS_OFFSET       0x0C         /**< \brief (EVSYS_CHSTATUS offset) Channel Status */
    202. 

  202. #define EVSYS_CHSTATUS_RESETVALUE   0x000F00FFul /**< \brief (EVSYS_CHSTATUS reset_value) Channel Status */
    203. 

  203. 

  204. #define EVSYS_CHSTATUS_USRRDY0_Pos  0            /**< \brief (EVSYS_CHSTATUS) Channel 0 User Ready */
    205. 

  205. #define EVSYS_CHSTATUS_USRRDY0      (1 << EVSYS_CHSTATUS_USRRDY0_Pos)
    206. 

  206. #define EVSYS_CHSTATUS_USRRDY1_Pos  1            /**< \brief (EVSYS_CHSTATUS) Channel 1 User Ready */
    207. 

  207. #define EVSYS_CHSTATUS_USRRDY1      (1 << EVSYS_CHSTATUS_USRRDY1_Pos)
    208. 

  208. #define EVSYS_CHSTATUS_USRRDY2_Pos  2            /**< \brief (EVSYS_CHSTATUS) Channel 2 User Ready */
    209. 

  209. #define EVSYS_CHSTATUS_USRRDY2      (1 << EVSYS_CHSTATUS_USRRDY2_Pos)
    210. 

  210. #define EVSYS_CHSTATUS_USRRDY3_Pos  3            /**< \brief (EVSYS_CHSTATUS) Channel 3 User Ready */
    211. 

  211. #define EVSYS_CHSTATUS_USRRDY3      (1 << EVSYS_CHSTATUS_USRRDY3_Pos)
    212. 

  212. #define EVSYS_CHSTATUS_USRRDY4_Pos  4            /**< \brief (EVSYS_CHSTATUS) Channel 4 User Ready */
    213. 

  213. #define EVSYS_CHSTATUS_USRRDY4      (1 << EVSYS_CHSTATUS_USRRDY4_Pos)
    214. 

  214. #define EVSYS_CHSTATUS_USRRDY5_Pos  5            /**< \brief (EVSYS_CHSTATUS) Channel 5 User Ready */
    215. 

  215. #define EVSYS_CHSTATUS_USRRDY5      (1 << EVSYS_CHSTATUS_USRRDY5_Pos)
    216. 

  216. #define EVSYS_CHSTATUS_USRRDY6_Pos  6            /**< \brief (EVSYS_CHSTATUS) Channel 6 User Ready */
    217. 

  217. #define EVSYS_CHSTATUS_USRRDY6      (1 << EVSYS_CHSTATUS_USRRDY6_Pos)
    218. 

  218. #define EVSYS_CHSTATUS_USRRDY7_Pos  7            /**< \brief (EVSYS_CHSTATUS) Channel 7 User Ready */
    219. 

  219. #define EVSYS_CHSTATUS_USRRDY7      (1 << EVSYS_CHSTATUS_USRRDY7_Pos)
    220. 

  220. #define EVSYS_CHSTATUS_USRRDY_Pos   0            /**< \brief (EVSYS_CHSTATUS) Channel x User Ready */
    221. 

  221. #define EVSYS_CHSTATUS_USRRDY_Msk   (0xFFul << EVSYS_CHSTATUS_USRRDY_Pos)
    222. 

  222. #define EVSYS_CHSTATUS_USRRDY(value) ((EVSYS_CHSTATUS_USRRDY_Msk & ((value) << EVSYS_CHSTATUS_USRRDY_Pos)))
    223. 

  223. #define EVSYS_CHSTATUS_CHBUSY0_Pos  8            /**< \brief (EVSYS_CHSTATUS) Channel 0 Busy */
    224. 

  224. #define EVSYS_CHSTATUS_CHBUSY0      (1 << EVSYS_CHSTATUS_CHBUSY0_Pos)
    225. 

  225. #define EVSYS_CHSTATUS_CHBUSY1_Pos  9            /**< \brief (EVSYS_CHSTATUS) Channel 1 Busy */
    226. 

  226. #define EVSYS_CHSTATUS_CHBUSY1      (1 << EVSYS_CHSTATUS_CHBUSY1_Pos)
    227. 

  227. #define EVSYS_CHSTATUS_CHBUSY2_Pos  10           /**< \brief (EVSYS_CHSTATUS) Channel 2 Busy */
    228. 

  228. #define EVSYS_CHSTATUS_CHBUSY2      (1 << EVSYS_CHSTATUS_CHBUSY2_Pos)
    229. 

  229. #define EVSYS_CHSTATUS_CHBUSY3_Pos  11           /**< \brief (EVSYS_CHSTATUS) Channel 3 Busy */
    230. 

  230. #define EVSYS_CHSTATUS_CHBUSY3      (1 << EVSYS_CHSTATUS_CHBUSY3_Pos)
    231. 

  231. #define EVSYS_CHSTATUS_CHBUSY4_Pos  12           /**< \brief (EVSYS_CHSTATUS) Channel 4 Busy */
    232. 

  232. #define EVSYS_CHSTATUS_CHBUSY4      (1 << EVSYS_CHSTATUS_CHBUSY4_Pos)
    233. 

  233. #define EVSYS_CHSTATUS_CHBUSY5_Pos  13           /**< \brief (EVSYS_CHSTATUS) Channel 5 Busy */
    234. 

  234. #define EVSYS_CHSTATUS_CHBUSY5      (1 << EVSYS_CHSTATUS_CHBUSY5_Pos)
    235. 

  235. #define EVSYS_CHSTATUS_CHBUSY6_Pos  14           /**< \brief (EVSYS_CHSTATUS) Channel 6 Busy */
    236. 

  236. #define EVSYS_CHSTATUS_CHBUSY6      (1 << EVSYS_CHSTATUS_CHBUSY6_Pos)
    237. 

  237. #define EVSYS_CHSTATUS_CHBUSY7_Pos  15           /**< \brief (EVSYS_CHSTATUS) Channel 7 Busy */
    238. 

  238. #define EVSYS_CHSTATUS_CHBUSY7      (1 << EVSYS_CHSTATUS_CHBUSY7_Pos)
    239. 

  239. #define EVSYS_CHSTATUS_CHBUSY_Pos   8            /**< \brief (EVSYS_CHSTATUS) Channel x Busy */
    240. 

  240. #define EVSYS_CHSTATUS_CHBUSY_Msk   (0xFFul << EVSYS_CHSTATUS_CHBUSY_Pos)
    241. 

  241. #define EVSYS_CHSTATUS_CHBUSY(value) ((EVSYS_CHSTATUS_CHBUSY_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY_Pos)))
    242. 

  242. #define EVSYS_CHSTATUS_USRRDY8_Pos  16           /**< \brief (EVSYS_CHSTATUS) Channel 8 User Ready */
    243. 

  243. #define EVSYS_CHSTATUS_USRRDY8      (1 << EVSYS_CHSTATUS_USRRDY8_Pos)
    244. 

  244. #define EVSYS_CHSTATUS_USRRDY9_Pos  17           /**< \brief (EVSYS_CHSTATUS) Channel 9 User Ready */
    245. 

  245. #define EVSYS_CHSTATUS_USRRDY9      (1 << EVSYS_CHSTATUS_USRRDY9_Pos)
    246. 

  246. #define EVSYS_CHSTATUS_USRRDY10_Pos 18           /**< \brief (EVSYS_CHSTATUS) Channel 10 User Ready */
    247. 

  247. #define EVSYS_CHSTATUS_USRRDY10     (1 << EVSYS_CHSTATUS_USRRDY10_Pos)
    248. 

  248. #define EVSYS_CHSTATUS_USRRDY11_Pos 19           /**< \brief (EVSYS_CHSTATUS) Channel 11 User Ready */
    249. 

  249. #define EVSYS_CHSTATUS_USRRDY11     (1 << EVSYS_CHSTATUS_USRRDY11_Pos)
    250. 

  250. #define EVSYS_CHSTATUS_USRRDYp8_Pos 16           /**< \brief (EVSYS_CHSTATUS) Channel x+8 User Ready */
    251. 

  251. #define EVSYS_CHSTATUS_USRRDYp8_Msk (0xFul << EVSYS_CHSTATUS_USRRDYp8_Pos)
    252. 

  252. #define EVSYS_CHSTATUS_USRRDYp8(value) ((EVSYS_CHSTATUS_USRRDYp8_Msk & ((value) << EVSYS_CHSTATUS_USRRDYp8_Pos)))
    253. 

  253. #define EVSYS_CHSTATUS_CHBUSY8_Pos  24           /**< \brief (EVSYS_CHSTATUS) Channel 8 Busy */
    254. 

  254. #define EVSYS_CHSTATUS_CHBUSY8      (1 << EVSYS_CHSTATUS_CHBUSY8_Pos)
    255. 

  255. #define EVSYS_CHSTATUS_CHBUSY9_Pos  25           /**< \brief (EVSYS_CHSTATUS) Channel 9 Busy */
    256. 

  256. #define EVSYS_CHSTATUS_CHBUSY9      (1 << EVSYS_CHSTATUS_CHBUSY9_Pos)
    257. 

  257. #define EVSYS_CHSTATUS_CHBUSY10_Pos 26           /**< \brief (EVSYS_CHSTATUS) Channel 10 Busy */
    258. 

  258. #define EVSYS_CHSTATUS_CHBUSY10     (1 << EVSYS_CHSTATUS_CHBUSY10_Pos)
    259. 

  259. #define EVSYS_CHSTATUS_CHBUSY11_Pos 27           /**< \brief (EVSYS_CHSTATUS) Channel 11 Busy */
    260. 

  260. #define EVSYS_CHSTATUS_CHBUSY11     (1 << EVSYS_CHSTATUS_CHBUSY11_Pos)
    261. 

  261. #define EVSYS_CHSTATUS_CHBUSYp8_Pos 24           /**< \brief (EVSYS_CHSTATUS) Channel x+8 Busy */
    262. 

  262. #define EVSYS_CHSTATUS_CHBUSYp8_Msk (0xFul << EVSYS_CHSTATUS_CHBUSYp8_Pos)
    263. 

  263. #define EVSYS_CHSTATUS_CHBUSYp8(value) ((EVSYS_CHSTATUS_CHBUSYp8_Msk & ((value) << EVSYS_CHSTATUS_CHBUSYp8_Pos)))
    264. 

  264. #define EVSYS_CHSTATUS_MASK         0x0F0FFFFFul /**< \brief (EVSYS_CHSTATUS) MASK Register */
    265. 

  265. 

  266. /* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */
    267. 

  267. #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
    268. 

  268. typedef union {
    269. 

  269.   struct {
    270. 

  270.     uint32_t OVR0:1;           /*!< bit:      0  Channel 0 Overrun Interrupt Enable */
    271. 

  271.     uint32_t OVR1:1;           /*!< bit:      1  Channel 1 Overrun Interrupt Enable */
    272. 

  272.     uint32_t OVR2:1;           /*!< bit:      2  Channel 2 Overrun Interrupt Enable */
    273. 

  273.     uint32_t OVR3:1;           /*!< bit:      3  Channel 3 Overrun Interrupt Enable */
    274. 

  274.     uint32_t OVR4:1;           /*!< bit:      4  Channel 4 Overrun Interrupt Enable */
    275. 

  275.     uint32_t OVR5:1;           /*!< bit:      5  Channel 5 Overrun Interrupt Enable */
    276. 

  276.     uint32_t OVR6:1;           /*!< bit:      6  Channel 6 Overrun Interrupt Enable */
    277. 

  277.     uint32_t OVR7:1;           /*!< bit:      7  Channel 7 Overrun Interrupt Enable */
    278. 

  278.     uint32_t EVD0:1;           /*!< bit:      8  Channel 0 Event Detection Interrupt Enable */
    279. 

  279.     uint32_t EVD1:1;           /*!< bit:      9  Channel 1 Event Detection Interrupt Enable */
    280. 

  280.     uint32_t EVD2:1;           /*!< bit:     10  Channel 2 Event Detection Interrupt Enable */
    281. 

  281.     uint32_t EVD3:1;           /*!< bit:     11  Channel 3 Event Detection Interrupt Enable */
    282. 

  282.     uint32_t EVD4:1;           /*!< bit:     12  Channel 4 Event Detection Interrupt Enable */
    283. 

  283.     uint32_t EVD5:1;           /*!< bit:     13  Channel 5 Event Detection Interrupt Enable */
    284. 

  284.     uint32_t EVD6:1;           /*!< bit:     14  Channel 6 Event Detection Interrupt Enable */
    285. 

  285.     uint32_t EVD7:1;           /*!< bit:     15  Channel 7 Event Detection Interrupt Enable */
    286. 

  286.     uint32_t OVR8:1;           /*!< bit:     16  Channel 8 Overrun Interrupt Enable */
    287. 

  287.     uint32_t OVR9:1;           /*!< bit:     17  Channel 9 Overrun Interrupt Enable */
    288. 

  288.     uint32_t OVR10:1;          /*!< bit:     18  Channel 10 Overrun Interrupt Enable */
    289. 

  289.     uint32_t OVR11:1;          /*!< bit:     19  Channel 11 Overrun Interrupt Enable */
    290. 

  290.     uint32_t :4;               /*!< bit: 20..23  Reserved                           */
    291. 

  291.     uint32_t EVD8:1;           /*!< bit:     24  Channel 8 Event Detection Interrupt Enable */
    292. 

  292.     uint32_t EVD9:1;           /*!< bit:     25  Channel 9 Event Detection Interrupt Enable */
    293. 

  293.     uint32_t EVD10:1;          /*!< bit:     26  Channel 10 Event Detection Interrupt Enable */
    294. 

  294.     uint32_t EVD11:1;          /*!< bit:     27  Channel 11 Event Detection Interrupt Enable */
    295. 

  295.     uint32_t :4;               /*!< bit: 28..31  Reserved                           */
    296. 

  296.   } bit;                       /*!< Structure used for bit  access                  */
    297. 

  297.   struct {
    298. 

  298.     uint32_t OVR:8;            /*!< bit:  0.. 7  Channel x Overrun Interrupt Enable */
    299. 

  299.     uint32_t EVD:8;            /*!< bit:  8..15  Channel x Event Detection Interrupt Enable */
    300. 

  300.     uint32_t OVRp8:4;          /*!< bit: 16..19  Channel x+8 Overrun Interrupt Enable */
    301. 

  301.     uint32_t :4;               /*!< bit: 20..23  Reserved                           */
    302. 

  302.     uint32_t EVDp8:4;          /*!< bit: 24..27  Channel x+8 Event Detection Interrupt Enable */
    303. 

  303.     uint32_t :4;               /*!< bit: 28..31  Reserved                           */
    304. 

  304.   } vec;                       /*!< Structure used for vec  access                  */
    305. 

  305.   uint32_t reg;                /*!< Type      used for register access              */
    306. 

  306. } EVSYS_INTENCLR_Type;
    307. 

  307. #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
    308. 

  308. 

  309. #define EVSYS_INTENCLR_OFFSET       0x10         /**< \brief (EVSYS_INTENCLR offset) Interrupt Enable Clear */
    310. 

  310. #define EVSYS_INTENCLR_RESETVALUE   0x00000000ul /**< \brief (EVSYS_INTENCLR reset_value) Interrupt Enable Clear */
    311. 

  311. 

  312. #define EVSYS_INTENCLR_OVR0_Pos     0            /**< \brief (EVSYS_INTENCLR) Channel 0 Overrun Interrupt Enable */
    313. 

  313. #define EVSYS_INTENCLR_OVR0         (1 << EVSYS_INTENCLR_OVR0_Pos)
    314. 

  314. #define EVSYS_INTENCLR_OVR1_Pos     1            /**< \brief (EVSYS_INTENCLR) Channel 1 Overrun Interrupt Enable */
    315. 

  315. #define EVSYS_INTENCLR_OVR1         (1 << EVSYS_INTENCLR_OVR1_Pos)
    316. 

  316. #define EVSYS_INTENCLR_OVR2_Pos     2            /**< \brief (EVSYS_INTENCLR) Channel 2 Overrun Interrupt Enable */
    317. 

  317. #define EVSYS_INTENCLR_OVR2         (1 << EVSYS_INTENCLR_OVR2_Pos)
    318. 

  318. #define EVSYS_INTENCLR_OVR3_Pos     3            /**< \brief (EVSYS_INTENCLR) Channel 3 Overrun Interrupt Enable */
    319. 

  319. #define EVSYS_INTENCLR_OVR3         (1 << EVSYS_INTENCLR_OVR3_Pos)
    320. 

  320. #define EVSYS_INTENCLR_OVR4_Pos     4            /**< \brief (EVSYS_INTENCLR) Channel 4 Overrun Interrupt Enable */
    321. 

  321. #define EVSYS_INTENCLR_OVR4         (1 << EVSYS_INTENCLR_OVR4_Pos)
    322. 

  322. #define EVSYS_INTENCLR_OVR5_Pos     5            /**< \brief (EVSYS_INTENCLR) Channel 5 Overrun Interrupt Enable */
    323. 

  323. #define EVSYS_INTENCLR_OVR5         (1 << EVSYS_INTENCLR_OVR5_Pos)
    324. 

  324. #define EVSYS_INTENCLR_OVR6_Pos     6            /**< \brief (EVSYS_INTENCLR) Channel 6 Overrun Interrupt Enable */
    325. 

  325. #define EVSYS_INTENCLR_OVR6         (1 << EVSYS_INTENCLR_OVR6_Pos)
    326. 

  326. #define EVSYS_INTENCLR_OVR7_Pos     7            /**< \brief (EVSYS_INTENCLR) Channel 7 Overrun Interrupt Enable */
    327. 

  327. #define EVSYS_INTENCLR_OVR7         (1 << EVSYS_INTENCLR_OVR7_Pos)
    328. 

  328. #define EVSYS_INTENCLR_OVR_Pos      0            /**< \brief (EVSYS_INTENCLR) Channel x Overrun Interrupt Enable */
    329. 

  329. #define EVSYS_INTENCLR_OVR_Msk      (0xFFul << EVSYS_INTENCLR_OVR_Pos)
    330. 

  330. #define EVSYS_INTENCLR_OVR(value)   ((EVSYS_INTENCLR_OVR_Msk & ((value) << EVSYS_INTENCLR_OVR_Pos)))
    331. 

  331. #define EVSYS_INTENCLR_EVD0_Pos     8            /**< \brief (EVSYS_INTENCLR) Channel 0 Event Detection Interrupt Enable */
    332. 

  332. #define EVSYS_INTENCLR_EVD0         (1 << EVSYS_INTENCLR_EVD0_Pos)
    333. 

  333. #define EVSYS_INTENCLR_EVD1_Pos     9            /**< \brief (EVSYS_INTENCLR) Channel 1 Event Detection Interrupt Enable */
    334. 

  334. #define EVSYS_INTENCLR_EVD1         (1 << EVSYS_INTENCLR_EVD1_Pos)
    335. 

  335. #define EVSYS_INTENCLR_EVD2_Pos     10           /**< \brief (EVSYS_INTENCLR) Channel 2 Event Detection Interrupt Enable */
    336. 

  336. #define EVSYS_INTENCLR_EVD2         (1 << EVSYS_INTENCLR_EVD2_Pos)
    337. 

  337. #define EVSYS_INTENCLR_EVD3_Pos     11           /**< \brief (EVSYS_INTENCLR) Channel 3 Event Detection Interrupt Enable */
    338. 

  338. #define EVSYS_INTENCLR_EVD3         (1 << EVSYS_INTENCLR_EVD3_Pos)
    339. 

  339. #define EVSYS_INTENCLR_EVD4_Pos     12           /**< \brief (EVSYS_INTENCLR) Channel 4 Event Detection Interrupt Enable */
    340. 

  340. #define EVSYS_INTENCLR_EVD4         (1 << EVSYS_INTENCLR_EVD4_Pos)
    341. 

  341. #define EVSYS_INTENCLR_EVD5_Pos     13           /**< \brief (EVSYS_INTENCLR) Channel 5 Event Detection Interrupt Enable */
    342. 

  342. #define EVSYS_INTENCLR_EVD5         (1 << EVSYS_INTENCLR_EVD5_Pos)
    343. 

  343. #define EVSYS_INTENCLR_EVD6_Pos     14           /**< \brief (EVSYS_INTENCLR) Channel 6 Event Detection Interrupt Enable */
    344. 

  344. #define EVSYS_INTENCLR_EVD6         (1 << EVSYS_INTENCLR_EVD6_Pos)
    345. 

  345. #define EVSYS_INTENCLR_EVD7_Pos     15           /**< \brief (EVSYS_INTENCLR) Channel 7 Event Detection Interrupt Enable */
    346. 

  346. #define EVSYS_INTENCLR_EVD7         (1 << EVSYS_INTENCLR_EVD7_Pos)
    347. 

  347. #define EVSYS_INTENCLR_EVD_Pos      8            /**< \brief (EVSYS_INTENCLR) Channel x Event Detection Interrupt Enable */
    348. 

  348. #define EVSYS_INTENCLR_EVD_Msk      (0xFFul << EVSYS_INTENCLR_EVD_Pos)
    349. 

  349. #define EVSYS_INTENCLR_EVD(value)   ((EVSYS_INTENCLR_EVD_Msk & ((value) << EVSYS_INTENCLR_EVD_Pos)))
    350. 

  350. #define EVSYS_INTENCLR_OVR8_Pos     16           /**< \brief (EVSYS_INTENCLR) Channel 8 Overrun Interrupt Enable */
    351. 

  351. #define EVSYS_INTENCLR_OVR8         (1 << EVSYS_INTENCLR_OVR8_Pos)
    352. 

  352. #define EVSYS_INTENCLR_OVR9_Pos     17           /**< \brief (EVSYS_INTENCLR) Channel 9 Overrun Interrupt Enable */
    353. 

  353. #define EVSYS_INTENCLR_OVR9         (1 << EVSYS_INTENCLR_OVR9_Pos)
    354. 

  354. #define EVSYS_INTENCLR_OVR10_Pos    18           /**< \brief (EVSYS_INTENCLR) Channel 10 Overrun Interrupt Enable */
    355. 

  355. #define EVSYS_INTENCLR_OVR10        (1 << EVSYS_INTENCLR_OVR10_Pos)
    356. 

  356. #define EVSYS_INTENCLR_OVR11_Pos    19           /**< \brief (EVSYS_INTENCLR) Channel 11 Overrun Interrupt Enable */
    357. 

  357. #define EVSYS_INTENCLR_OVR11        (1 << EVSYS_INTENCLR_OVR11_Pos)
    358. 

  358. #define EVSYS_INTENCLR_OVRp8_Pos    16           /**< \brief (EVSYS_INTENCLR) Channel x+8 Overrun Interrupt Enable */
    359. 

  359. #define EVSYS_INTENCLR_OVRp8_Msk    (0xFul << EVSYS_INTENCLR_OVRp8_Pos)
    360. 

  360. #define EVSYS_INTENCLR_OVRp8(value) ((EVSYS_INTENCLR_OVRp8_Msk & ((value) << EVSYS_INTENCLR_OVRp8_Pos)))
    361. 

  361. #define EVSYS_INTENCLR_EVD8_Pos     24           /**< \brief (EVSYS_INTENCLR) Channel 8 Event Detection Interrupt Enable */
    362. 

  362. #define EVSYS_INTENCLR_EVD8         (1 << EVSYS_INTENCLR_EVD8_Pos)
    363. 

  363. #define EVSYS_INTENCLR_EVD9_Pos     25           /**< \brief (EVSYS_INTENCLR) Channel 9 Event Detection Interrupt Enable */
    364. 

  364. #define EVSYS_INTENCLR_EVD9         (1 << EVSYS_INTENCLR_EVD9_Pos)
    365. 

  365. #define EVSYS_INTENCLR_EVD10_Pos    26           /**< \brief (EVSYS_INTENCLR) Channel 10 Event Detection Interrupt Enable */
    366. 

  366. #define EVSYS_INTENCLR_EVD10        (1 << EVSYS_INTENCLR_EVD10_Pos)
    367. 

  367. #define EVSYS_INTENCLR_EVD11_Pos    27           /**< \brief (EVSYS_INTENCLR) Channel 11 Event Detection Interrupt Enable */
    368. 

  368. #define EVSYS_INTENCLR_EVD11        (1 << EVSYS_INTENCLR_EVD11_Pos)
    369. 

  369. #define EVSYS_INTENCLR_EVDp8_Pos    24           /**< \brief (EVSYS_INTENCLR) Channel x+8 Event Detection Interrupt Enable */
    370. 

  370. #define EVSYS_INTENCLR_EVDp8_Msk    (0xFul << EVSYS_INTENCLR_EVDp8_Pos)
    371. 

  371. #define EVSYS_INTENCLR_EVDp8(value) ((EVSYS_INTENCLR_EVDp8_Msk & ((value) << EVSYS_INTENCLR_EVDp8_Pos)))
    372. 

  372. #define EVSYS_INTENCLR_MASK         0x0F0FFFFFul /**< \brief (EVSYS_INTENCLR) MASK Register */
    373. 

  373. 

  374. /* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */
    375. 

  375. #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
    376. 

  376. typedef union {
    377. 

  377.   struct {
    378. 

  378.     uint32_t OVR0:1;           /*!< bit:      0  Channel 0 Overrun Interrupt Enable */
    379. 

  379.     uint32_t OVR1:1;           /*!< bit:      1  Channel 1 Overrun Interrupt Enable */
    380. 

  380.     uint32_t OVR2:1;           /*!< bit:      2  Channel 2 Overrun Interrupt Enable */
    381. 

  381.     uint32_t OVR3:1;           /*!< bit:      3  Channel 3 Overrun Interrupt Enable */
    382. 

  382.     uint32_t OVR4:1;           /*!< bit:      4  Channel 4 Overrun Interrupt Enable */
    383. 

  383.     uint32_t OVR5:1;           /*!< bit:      5  Channel 5 Overrun Interrupt Enable */
    384. 

  384.     uint32_t OVR6:1;           /*!< bit:      6  Channel 6 Overrun Interrupt Enable */
    385. 

  385.     uint32_t OVR7:1;           /*!< bit:      7  Channel 7 Overrun Interrupt Enable */
    386. 

  386.     uint32_t EVD0:1;           /*!< bit:      8  Channel 0 Event Detection Interrupt Enable */
    387. 

  387.     uint32_t EVD1:1;           /*!< bit:      9  Channel 1 Event Detection Interrupt Enable */
    388. 

  388.     uint32_t EVD2:1;           /*!< bit:     10  Channel 2 Event Detection Interrupt Enable */
    389. 

  389.     uint32_t EVD3:1;           /*!< bit:     11  Channel 3 Event Detection Interrupt Enable */
    390. 

  390.     uint32_t EVD4:1;           /*!< bit:     12  Channel 4 Event Detection Interrupt Enable */
    391. 

  391.     uint32_t EVD5:1;           /*!< bit:     13  Channel 5 Event Detection Interrupt Enable */
    392. 

  392.     uint32_t EVD6:1;           /*!< bit:     14  Channel 6 Event Detection Interrupt Enable */
    393. 

  393.     uint32_t EVD7:1;           /*!< bit:     15  Channel 7 Event Detection Interrupt Enable */
    394. 

  394.     uint32_t OVR8:1;           /*!< bit:     16  Channel 8 Overrun Interrupt Enable */
    395. 

  395.     uint32_t OVR9:1;           /*!< bit:     17  Channel 9 Overrun Interrupt Enable */
    396. 

  396.     uint32_t OVR10:1;          /*!< bit:     18  Channel 10 Overrun Interrupt Enable */
    397. 

  397.     uint32_t OVR11:1;          /*!< bit:     19  Channel 11 Overrun Interrupt Enable */
    398. 

  398.     uint32_t :4;               /*!< bit: 20..23  Reserved                           */
    399. 

  399.     uint32_t EVD8:1;           /*!< bit:     24  Channel 8 Event Detection Interrupt Enable */
    400. 

  400.     uint32_t EVD9:1;           /*!< bit:     25  Channel 9 Event Detection Interrupt Enable */
    401. 

  401.     uint32_t EVD10:1;          /*!< bit:     26  Channel 10 Event Detection Interrupt Enable */
    402. 

  402.     uint32_t EVD11:1;          /*!< bit:     27  Channel 11 Event Detection Interrupt Enable */
    403. 

  403.     uint32_t :4;               /*!< bit: 28..31  Reserved                           */
    404. 

  404.   } bit;                       /*!< Structure used for bit  access                  */
    405. 

  405.   struct {
    406. 

  406.     uint32_t OVR:8;            /*!< bit:  0.. 7  Channel x Overrun Interrupt Enable */
    407. 

  407.     uint32_t EVD:8;            /*!< bit:  8..15  Channel x Event Detection Interrupt Enable */
    408. 

  408.     uint32_t OVRp8:4;          /*!< bit: 16..19  Channel x+8 Overrun Interrupt Enable */
    409. 

  409.     uint32_t :4;               /*!< bit: 20..23  Reserved                           */
    410. 

  410.     uint32_t EVDp8:4;          /*!< bit: 24..27  Channel x+8 Event Detection Interrupt Enable */
    411. 

  411.     uint32_t :4;               /*!< bit: 28..31  Reserved                           */
    412. 

  412.   } vec;                       /*!< Structure used for vec  access                  */
    413. 

  413.   uint32_t reg;                /*!< Type      used for register access              */
    414. 

  414. } EVSYS_INTENSET_Type;
    415. 

  415. #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
    416. 

  416. 

  417. #define EVSYS_INTENSET_OFFSET       0x14         /**< \brief (EVSYS_INTENSET offset) Interrupt Enable Set */
    418. 

  418. #define EVSYS_INTENSET_RESETVALUE   0x00000000ul /**< \brief (EVSYS_INTENSET reset_value) Interrupt Enable Set */
    419. 

  419. 

  420. #define EVSYS_INTENSET_OVR0_Pos     0            /**< \brief (EVSYS_INTENSET) Channel 0 Overrun Interrupt Enable */
    421. 

  421. #define EVSYS_INTENSET_OVR0         (1 << EVSYS_INTENSET_OVR0_Pos)
    422. 

  422. #define EVSYS_INTENSET_OVR1_Pos     1            /**< \brief (EVSYS_INTENSET) Channel 1 Overrun Interrupt Enable */
    423. 

  423. #define EVSYS_INTENSET_OVR1         (1 << EVSYS_INTENSET_OVR1_Pos)
    424. 

  424. #define EVSYS_INTENSET_OVR2_Pos     2            /**< \brief (EVSYS_INTENSET) Channel 2 Overrun Interrupt Enable */
    425. 

  425. #define EVSYS_INTENSET_OVR2         (1 << EVSYS_INTENSET_OVR2_Pos)
    426. 

  426. #define EVSYS_INTENSET_OVR3_Pos     3            /**< \brief (EVSYS_INTENSET) Channel 3 Overrun Interrupt Enable */
    427. 

  427. #define EVSYS_INTENSET_OVR3         (1 << EVSYS_INTENSET_OVR3_Pos)
    428. 

  428. #define EVSYS_INTENSET_OVR4_Pos     4            /**< \brief (EVSYS_INTENSET) Channel 4 Overrun Interrupt Enable */
    429. 

  429. #define EVSYS_INTENSET_OVR4         (1 << EVSYS_INTENSET_OVR4_Pos)
    430. 

  430. #define EVSYS_INTENSET_OVR5_Pos     5            /**< \brief (EVSYS_INTENSET) Channel 5 Overrun Interrupt Enable */
    431. 

  431. #define EVSYS_INTENSET_OVR5         (1 << EVSYS_INTENSET_OVR5_Pos)
    432. 

  432. #define EVSYS_INTENSET_OVR6_Pos     6            /**< \brief (EVSYS_INTENSET) Channel 6 Overrun Interrupt Enable */
    433. 

  433. #define EVSYS_INTENSET_OVR6         (1 << EVSYS_INTENSET_OVR6_Pos)
    434. 

  434. #define EVSYS_INTENSET_OVR7_Pos     7            /**< \brief (EVSYS_INTENSET) Channel 7 Overrun Interrupt Enable */
    435. 

  435. #define EVSYS_INTENSET_OVR7         (1 << EVSYS_INTENSET_OVR7_Pos)
    436. 

  436. #define EVSYS_INTENSET_OVR_Pos      0            /**< \brief (EVSYS_INTENSET) Channel x Overrun Interrupt Enable */
    437. 

  437. #define EVSYS_INTENSET_OVR_Msk      (0xFFul << EVSYS_INTENSET_OVR_Pos)
    438. 

  438. #define EVSYS_INTENSET_OVR(value)   ((EVSYS_INTENSET_OVR_Msk & ((value) << EVSYS_INTENSET_OVR_Pos)))
    439. 

  439. #define EVSYS_INTENSET_EVD0_Pos     8            /**< \brief (EVSYS_INTENSET) Channel 0 Event Detection Interrupt Enable */
    440. 

  440. #define EVSYS_INTENSET_EVD0         (1 << EVSYS_INTENSET_EVD0_Pos)
    441. 

  441. #define EVSYS_INTENSET_EVD1_Pos     9            /**< \brief (EVSYS_INTENSET) Channel 1 Event Detection Interrupt Enable */
    442. 

  442. #define EVSYS_INTENSET_EVD1         (1 << EVSYS_INTENSET_EVD1_Pos)
    443. 

  443. #define EVSYS_INTENSET_EVD2_Pos     10           /**< \brief (EVSYS_INTENSET) Channel 2 Event Detection Interrupt Enable */
    444. 

  444. #define EVSYS_INTENSET_EVD2         (1 << EVSYS_INTENSET_EVD2_Pos)
    445. 

  445. #define EVSYS_INTENSET_EVD3_Pos     11           /**< \brief (EVSYS_INTENSET) Channel 3 Event Detection Interrupt Enable */
    446. 

  446. #define EVSYS_INTENSET_EVD3         (1 << EVSYS_INTENSET_EVD3_Pos)
    447. 

  447. #define EVSYS_INTENSET_EVD4_Pos     12           /**< \brief (EVSYS_INTENSET) Channel 4 Event Detection Interrupt Enable */
    448. 

  448. #define EVSYS_INTENSET_EVD4         (1 << EVSYS_INTENSET_EVD4_Pos)
    449. 

  449. #define EVSYS_INTENSET_EVD5_Pos     13           /**< \brief (EVSYS_INTENSET) Channel 5 Event Detection Interrupt Enable */
    450. 

  450. #define EVSYS_INTENSET_EVD5         (1 << EVSYS_INTENSET_EVD5_Pos)
    451. 

  451. #define EVSYS_INTENSET_EVD6_Pos     14           /**< \brief (EVSYS_INTENSET) Channel 6 Event Detection Interrupt Enable */
    452. 

  452. #define EVSYS_INTENSET_EVD6         (1 << EVSYS_INTENSET_EVD6_Pos)
    453. 

  453. #define EVSYS_INTENSET_EVD7_Pos     15           /**< \brief (EVSYS_INTENSET) Channel 7 Event Detection Interrupt Enable */
    454. 

  454. #define EVSYS_INTENSET_EVD7         (1 << EVSYS_INTENSET_EVD7_Pos)
    455. 

  455. #define EVSYS_INTENSET_EVD_Pos      8            /**< \brief (EVSYS_INTENSET) Channel x Event Detection Interrupt Enable */
    456. 

  456. #define EVSYS_INTENSET_EVD_Msk      (0xFFul << EVSYS_INTENSET_EVD_Pos)
    457. 

  457. #define EVSYS_INTENSET_EVD(value)   ((EVSYS_INTENSET_EVD_Msk & ((value) << EVSYS_INTENSET_EVD_Pos)))
    458. 

  458. #define EVSYS_INTENSET_OVR8_Pos     16           /**< \brief (EVSYS_INTENSET) Channel 8 Overrun Interrupt Enable */
    459. 

  459. #define EVSYS_INTENSET_OVR8         (1 << EVSYS_INTENSET_OVR8_Pos)
    460. 

  460. #define EVSYS_INTENSET_OVR9_Pos     17           /**< \brief (EVSYS_INTENSET) Channel 9 Overrun Interrupt Enable */
    461. 

  461. #define EVSYS_INTENSET_OVR9         (1 << EVSYS_INTENSET_OVR9_Pos)
    462. 

  462. #define EVSYS_INTENSET_OVR10_Pos    18           /**< \brief (EVSYS_INTENSET) Channel 10 Overrun Interrupt Enable */
    463. 

  463. #define EVSYS_INTENSET_OVR10        (1 << EVSYS_INTENSET_OVR10_Pos)
    464. 

  464. #define EVSYS_INTENSET_OVR11_Pos    19           /**< \brief (EVSYS_INTENSET) Channel 11 Overrun Interrupt Enable */
    465. 

  465. #define EVSYS_INTENSET_OVR11        (1 << EVSYS_INTENSET_OVR11_Pos)
    466. 

  466. #define EVSYS_INTENSET_OVRp8_Pos    16           /**< \brief (EVSYS_INTENSET) Channel x+8 Overrun Interrupt Enable */
    467. 

  467. #define EVSYS_INTENSET_OVRp8_Msk    (0xFul << EVSYS_INTENSET_OVRp8_Pos)
    468. 

  468. #define EVSYS_INTENSET_OVRp8(value) ((EVSYS_INTENSET_OVRp8_Msk & ((value) << EVSYS_INTENSET_OVRp8_Pos)))
    469. 

  469. #define EVSYS_INTENSET_EVD8_Pos     24           /**< \brief (EVSYS_INTENSET) Channel 8 Event Detection Interrupt Enable */
    470. 

  470. #define EVSYS_INTENSET_EVD8         (1 << EVSYS_INTENSET_EVD8_Pos)
    471. 

  471. #define EVSYS_INTENSET_EVD9_Pos     25           /**< \brief (EVSYS_INTENSET) Channel 9 Event Detection Interrupt Enable */
    472. 

  472. #define EVSYS_INTENSET_EVD9         (1 << EVSYS_INTENSET_EVD9_Pos)
    473. 

  473. #define EVSYS_INTENSET_EVD10_Pos    26           /**< \brief (EVSYS_INTENSET) Channel 10 Event Detection Interrupt Enable */
    474. 

  474. #define EVSYS_INTENSET_EVD10        (1 << EVSYS_INTENSET_EVD10_Pos)
    475. 

  475. #define EVSYS_INTENSET_EVD11_Pos    27           /**< \brief (EVSYS_INTENSET) Channel 11 Event Detection Interrupt Enable */
    476. 

  476. #define EVSYS_INTENSET_EVD11        (1 << EVSYS_INTENSET_EVD11_Pos)
    477. 

  477. #define EVSYS_INTENSET_EVDp8_Pos    24           /**< \brief (EVSYS_INTENSET) Channel x+8 Event Detection Interrupt Enable */
    478. 

  478. #define EVSYS_INTENSET_EVDp8_Msk    (0xFul << EVSYS_INTENSET_EVDp8_Pos)
    479. 

  479. #define EVSYS_INTENSET_EVDp8(value) ((EVSYS_INTENSET_EVDp8_Msk & ((value) << EVSYS_INTENSET_EVDp8_Pos)))
    480. 

  480. #define EVSYS_INTENSET_MASK         0x0F0FFFFFul /**< \brief (EVSYS_INTENSET) MASK Register */
    481. 

  481. 

  482. /* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */
    483. 

  483. #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
    484. 

  484. typedef union {
    485. 

  485.   struct {
    486. 

  486.     uint32_t OVR0:1;           /*!< bit:      0  Channel 0 Overrun                  */
    487. 

  487.     uint32_t OVR1:1;           /*!< bit:      1  Channel 1 Overrun                  */
    488. 

  488.     uint32_t OVR2:1;           /*!< bit:      2  Channel 2 Overrun                  */
    489. 

  489.     uint32_t OVR3:1;           /*!< bit:      3  Channel 3 Overrun                  */
    490. 

  490.     uint32_t OVR4:1;           /*!< bit:      4  Channel 4 Overrun                  */
    491. 

  491.     uint32_t OVR5:1;           /*!< bit:      5  Channel 5 Overrun                  */
    492. 

  492.     uint32_t OVR6:1;           /*!< bit:      6  Channel 6 Overrun                  */
    493. 

  493.     uint32_t OVR7:1;           /*!< bit:      7  Channel 7 Overrun                  */
    494. 

  494.     uint32_t EVD0:1;           /*!< bit:      8  Channel 0 Event Detection          */
    495. 

  495.     uint32_t EVD1:1;           /*!< bit:      9  Channel 1 Event Detection          */
    496. 

  496.     uint32_t EVD2:1;           /*!< bit:     10  Channel 2 Event Detection          */
    497. 

  497.     uint32_t EVD3:1;           /*!< bit:     11  Channel 3 Event Detection          */
    498. 

  498.     uint32_t EVD4:1;           /*!< bit:     12  Channel 4 Event Detection          */
    499. 

  499.     uint32_t EVD5:1;           /*!< bit:     13  Channel 5 Event Detection          */
    500. 

  500.     uint32_t EVD6:1;           /*!< bit:     14  Channel 6 Event Detection          */
    501. 

  501.     uint32_t EVD7:1;           /*!< bit:     15  Channel 7 Event Detection          */
    502. 

  502.     uint32_t OVR8:1;           /*!< bit:     16  Channel 8 Overrun                  */
    503. 

  503.     uint32_t OVR9:1;           /*!< bit:     17  Channel 9 Overrun                  */
    504. 

  504.     uint32_t OVR10:1;          /*!< bit:     18  Channel 10 Overrun                 */
    505. 

  505.     uint32_t OVR11:1;          /*!< bit:     19  Channel 11 Overrun                 */
    506. 

  506.     uint32_t :4;               /*!< bit: 20..23  Reserved                           */
    507. 

  507.     uint32_t EVD8:1;           /*!< bit:     24  Channel 8 Event Detection          */
    508. 

  508.     uint32_t EVD9:1;           /*!< bit:     25  Channel 9 Event Detection          */
    509. 

  509.     uint32_t EVD10:1;          /*!< bit:     26  Channel 10 Event Detection         */
    510. 

  510.     uint32_t EVD11:1;          /*!< bit:     27  Channel 11 Event Detection         */
    511. 

  511.     uint32_t :4;               /*!< bit: 28..31  Reserved                           */
    512. 

  512.   } bit;                       /*!< Structure used for bit  access                  */
    513. 

  513.   struct {
    514. 

  514.     uint32_t OVR:8;            /*!< bit:  0.. 7  Channel x Overrun                  */
    515. 

  515.     uint32_t EVD:8;            /*!< bit:  8..15  Channel x Event Detection          */
    516. 

  516.     uint32_t OVRp8:4;          /*!< bit: 16..19  Channel x+8 Overrun                */
    517. 

  517.     uint32_t :4;               /*!< bit: 20..23  Reserved                           */
    518. 

  518.     uint32_t EVDp8:4;          /*!< bit: 24..27  Channel x+8 Event Detection        */
    519. 

  519.     uint32_t :4;               /*!< bit: 28..31  Reserved                           */
    520. 

  520.   } vec;                       /*!< Structure used for vec  access                  */
    521. 

  521.   uint32_t reg;                /*!< Type      used for register access              */
    522. 

  522. } EVSYS_INTFLAG_Type;
    523. 

  523. #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
    524. 

  524. 

  525. #define EVSYS_INTFLAG_OFFSET        0x18         /**< \brief (EVSYS_INTFLAG offset) Interrupt Flag Status and Clear */
    526. 

  526. #define EVSYS_INTFLAG_RESETVALUE    0x00000000ul /**< \brief (EVSYS_INTFLAG reset_value) Interrupt Flag Status and Clear */
    527. 

  527. 

  528. #define EVSYS_INTFLAG_OVR0_Pos      0            /**< \brief (EVSYS_INTFLAG) Channel 0 Overrun */
    529. 

  529. #define EVSYS_INTFLAG_OVR0          (1 << EVSYS_INTFLAG_OVR0_Pos)
    530. 

  530. #define EVSYS_INTFLAG_OVR1_Pos      1            /**< \brief (EVSYS_INTFLAG) Channel 1 Overrun */
    531. 

  531. #define EVSYS_INTFLAG_OVR1          (1 << EVSYS_INTFLAG_OVR1_Pos)
    532. 

  532. #define EVSYS_INTFLAG_OVR2_Pos      2            /**< \brief (EVSYS_INTFLAG) Channel 2 Overrun */
    533. 

  533. #define EVSYS_INTFLAG_OVR2          (1 << EVSYS_INTFLAG_OVR2_Pos)
    534. 

  534. #define EVSYS_INTFLAG_OVR3_Pos      3            /**< \brief (EVSYS_INTFLAG) Channel 3 Overrun */
    535. 

  535. #define EVSYS_INTFLAG_OVR3          (1 << EVSYS_INTFLAG_OVR3_Pos)
    536. 

  536. #define EVSYS_INTFLAG_OVR4_Pos      4            /**< \brief (EVSYS_INTFLAG) Channel 4 Overrun */
    537. 

  537. #define EVSYS_INTFLAG_OVR4          (1 << EVSYS_INTFLAG_OVR4_Pos)
    538. 

  538. #define EVSYS_INTFLAG_OVR5_Pos      5            /**< \brief (EVSYS_INTFLAG) Channel 5 Overrun */
    539. 

  539. #define EVSYS_INTFLAG_OVR5          (1 << EVSYS_INTFLAG_OVR5_Pos)
    540. 

  540. #define EVSYS_INTFLAG_OVR6_Pos      6            /**< \brief (EVSYS_INTFLAG) Channel 6 Overrun */
    541. 

  541. #define EVSYS_INTFLAG_OVR6          (1 << EVSYS_INTFLAG_OVR6_Pos)
    542. 

  542. #define EVSYS_INTFLAG_OVR7_Pos      7            /**< \brief (EVSYS_INTFLAG) Channel 7 Overrun */
    543. 

  543. #define EVSYS_INTFLAG_OVR7          (1 << EVSYS_INTFLAG_OVR7_Pos)
    544. 

  544. #define EVSYS_INTFLAG_OVR_Pos       0            /**< \brief (EVSYS_INTFLAG) Channel x Overrun */
    545. 

  545. #define EVSYS_INTFLAG_OVR_Msk       (0xFFul << EVSYS_INTFLAG_OVR_Pos)
    546. 

  546. #define EVSYS_INTFLAG_OVR(value)    ((EVSYS_INTFLAG_OVR_Msk & ((value) << EVSYS_INTFLAG_OVR_Pos)))
    547. 

  547. #define EVSYS_INTFLAG_EVD0_Pos      8            /**< \brief (EVSYS_INTFLAG) Channel 0 Event Detection */
    548. 

  548. #define EVSYS_INTFLAG_EVD0          (1 << EVSYS_INTFLAG_EVD0_Pos)
    549. 

  549. #define EVSYS_INTFLAG_EVD1_Pos      9            /**< \brief (EVSYS_INTFLAG) Channel 1 Event Detection */
    550. 

  550. #define EVSYS_INTFLAG_EVD1          (1 << EVSYS_INTFLAG_EVD1_Pos)
    551. 

  551. #define EVSYS_INTFLAG_EVD2_Pos      10           /**< \brief (EVSYS_INTFLAG) Channel 2 Event Detection */
    552. 

  552. #define EVSYS_INTFLAG_EVD2          (1 << EVSYS_INTFLAG_EVD2_Pos)
    553. 

  553. #define EVSYS_INTFLAG_EVD3_Pos      11           /**< \brief (EVSYS_INTFLAG) Channel 3 Event Detection */
    554. 

  554. #define EVSYS_INTFLAG_EVD3          (1 << EVSYS_INTFLAG_EVD3_Pos)
    555. 

  555. #define EVSYS_INTFLAG_EVD4_Pos      12           /**< \brief (EVSYS_INTFLAG) Channel 4 Event Detection */
    556. 

  556. #define EVSYS_INTFLAG_EVD4          (1 << EVSYS_INTFLAG_EVD4_Pos)
    557. 

  557. #define EVSYS_INTFLAG_EVD5_Pos      13           /**< \brief (EVSYS_INTFLAG) Channel 5 Event Detection */
    558. 

  558. #define EVSYS_INTFLAG_EVD5          (1 << EVSYS_INTFLAG_EVD5_Pos)
    559. 

  559. #define EVSYS_INTFLAG_EVD6_Pos      14           /**< \brief (EVSYS_INTFLAG) Channel 6 Event Detection */
    560. 

  560. #define EVSYS_INTFLAG_EVD6          (1 << EVSYS_INTFLAG_EVD6_Pos)
    561. 

  561. #define EVSYS_INTFLAG_EVD7_Pos      15           /**< \brief (EVSYS_INTFLAG) Channel 7 Event Detection */
    562. 

  562. #define EVSYS_INTFLAG_EVD7          (1 << EVSYS_INTFLAG_EVD7_Pos)
    563. 

  563. #define EVSYS_INTFLAG_EVD_Pos       8            /**< \brief (EVSYS_INTFLAG) Channel x Event Detection */
    564. 

  564. #define EVSYS_INTFLAG_EVD_Msk       (0xFFul << EVSYS_INTFLAG_EVD_Pos)
    565. 

  565. #define EVSYS_INTFLAG_EVD(value)    ((EVSYS_INTFLAG_EVD_Msk & ((value) << EVSYS_INTFLAG_EVD_Pos)))
    566. 

  566. #define EVSYS_INTFLAG_OVR8_Pos      16           /**< \brief (EVSYS_INTFLAG) Channel 8 Overrun */
    567. 

  567. #define EVSYS_INTFLAG_OVR8          (1 << EVSYS_INTFLAG_OVR8_Pos)
    568. 

  568. #define EVSYS_INTFLAG_OVR9_Pos      17           /**< \brief (EVSYS_INTFLAG) Channel 9 Overrun */
    569. 

  569. #define EVSYS_INTFLAG_OVR9          (1 << EVSYS_INTFLAG_OVR9_Pos)
    570. 

  570. #define EVSYS_INTFLAG_OVR10_Pos     18           /**< \brief (EVSYS_INTFLAG) Channel 10 Overrun */
    571. 

  571. #define EVSYS_INTFLAG_OVR10         (1 << EVSYS_INTFLAG_OVR10_Pos)
    572. 

  572. #define EVSYS_INTFLAG_OVR11_Pos     19           /**< \brief (EVSYS_INTFLAG) Channel 11 Overrun */
    573. 

  573. #define EVSYS_INTFLAG_OVR11         (1 << EVSYS_INTFLAG_OVR11_Pos)
    574. 

  574. #define EVSYS_INTFLAG_OVRp8_Pos     16           /**< \brief (EVSYS_INTFLAG) Channel x+8 Overrun */
    575. 

  575. #define EVSYS_INTFLAG_OVRp8_Msk     (0xFul << EVSYS_INTFLAG_OVRp8_Pos)
    576. 

  576. #define EVSYS_INTFLAG_OVRp8(value)  ((EVSYS_INTFLAG_OVRp8_Msk & ((value) << EVSYS_INTFLAG_OVRp8_Pos)))
    577. 

  577. #define EVSYS_INTFLAG_EVD8_Pos      24           /**< \brief (EVSYS_INTFLAG) Channel 8 Event Detection */
    578. 

  578. #define EVSYS_INTFLAG_EVD8          (1 << EVSYS_INTFLAG_EVD8_Pos)
    579. 

  579. #define EVSYS_INTFLAG_EVD9_Pos      25           /**< \brief (EVSYS_INTFLAG) Channel 9 Event Detection */
    580. 

  580. #define EVSYS_INTFLAG_EVD9          (1 << EVSYS_INTFLAG_EVD9_Pos)
    581. 

  581. #define EVSYS_INTFLAG_EVD10_Pos     26           /**< \brief (EVSYS_INTFLAG) Channel 10 Event Detection */
    582. 

  582. #define EVSYS_INTFLAG_EVD10         (1 << EVSYS_INTFLAG_EVD10_Pos)
    583. 

  583. #define EVSYS_INTFLAG_EVD11_Pos     27           /**< \brief (EVSYS_INTFLAG) Channel 11 Event Detection */
    584. 

  584. #define EVSYS_INTFLAG_EVD11         (1 << EVSYS_INTFLAG_EVD11_Pos)
    585. 

  585. #define EVSYS_INTFLAG_EVDp8_Pos     24           /**< \brief (EVSYS_INTFLAG) Channel x+8 Event Detection */
    586. 

  586. #define EVSYS_INTFLAG_EVDp8_Msk     (0xFul << EVSYS_INTFLAG_EVDp8_Pos)
    587. 

  587. #define EVSYS_INTFLAG_EVDp8(value)  ((EVSYS_INTFLAG_EVDp8_Msk & ((value) << EVSYS_INTFLAG_EVDp8_Pos)))
    588. 

  588. #define EVSYS_INTFLAG_MASK          0x0F0FFFFFul /**< \brief (EVSYS_INTFLAG) MASK Register */
    589. 

  589. 

  590. /** \brief EVSYS hardware registers */
    591. 

  591. #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
    592. 

  592. typedef struct {
    593. 

  593.   __O  EVSYS_CTRL_Type           CTRL;        /**< \brief Offset: 0x00 ( /W  8) Control */
    594. 

  594.        RoReg8                    Reserved1[0x3];
    595. 

  595.   __IO EVSYS_CHANNEL_Type        CHANNEL;     /**< \brief Offset: 0x04 (R/W 32) Channel */
    596. 

  596.   __IO EVSYS_USER_Type           USER;        /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */
    597. 

  597.        RoReg8                    Reserved2[0x2];
    598. 

  598.   __I  EVSYS_CHSTATUS_Type       CHSTATUS;    /**< \brief Offset: 0x0C (R/  32) Channel Status */
    599. 

  599.   __IO EVSYS_INTENCLR_Type       INTENCLR;    /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */
    600. 

  600.   __IO EVSYS_INTENSET_Type       INTENSET;    /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */
    601. 

  601.   __IO EVSYS_INTFLAG_Type        INTFLAG;     /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */
    602. 

  602. } Evsys;
    603. 

  603. #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
    604. 

  604. 

  605. /*@}*/
    606. 

  606. 

  607. #endif /* _SAMD21_EVSYS_COMPONENT_ */
    608.