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Momentum-Apps
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free-dap
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samd11
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instance
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sercom2.h

sercom2.h 9.7 KB
История Исходник

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  1. /**
    2. 

  2.  * \file
    3. 

  3.  *
    4. 

  4.  * \brief Instance description for SERCOM2
    5. 

  5.  *
    6. 

  6.  * Copyright (c) 2018 Microchip Technology Inc.
    7. 

  7.  *
    8. 

  8.  * \asf_license_start
    9. 

  9.  *
    10. 

  10.  * \page License
    11. 

  11.  *
    12. 

  12.  * SPDX-License-Identifier: Apache-2.0
    13. 

  13.  *
    14. 

  14.  * Licensed under the Apache License, Version 2.0 (the "License"); you may
    15. 

  15.  * not use this file except in compliance with the License.
    16. 

  16.  * You may obtain a copy of the Licence at
    17. 

  17.  * 
    18. 

  18.  * http://www.apache.org/licenses/LICENSE-2.0
    19. 

  19.  * 
    20. 

  20.  * Unless required by applicable law or agreed to in writing, software
    21. 

  21.  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
    22. 

  22.  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    23. 

  23.  * See the License for the specific language governing permissions and
    24. 

  24.  * limitations under the License.
    25. 

  25.  *
    26. 

  26.  * \asf_license_stop
    27. 

  27.  *
    28. 

  28.  */
    29. 

  29. 

  30. #ifndef _SAMD11_SERCOM2_INSTANCE_
    31. 

  31. #define _SAMD11_SERCOM2_INSTANCE_
    32. 

  32. 

  33. /* ========== Register definition for SERCOM2 peripheral ========== */
    34. 

  34. #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
    35. 

  35. #define REG_SERCOM2_I2CM_CTRLA     (0x42001000) /**< \brief (SERCOM2) I2CM Control A */
    36. 

  36. #define REG_SERCOM2_I2CM_CTRLB     (0x42001004) /**< \brief (SERCOM2) I2CM Control B */
    37. 

  37. #define REG_SERCOM2_I2CM_BAUD      (0x4200100C) /**< \brief (SERCOM2) I2CM Baud Rate */
    38. 

  38. #define REG_SERCOM2_I2CM_INTENCLR  (0x42001014) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */
    39. 

  39. #define REG_SERCOM2_I2CM_INTENSET  (0x42001016) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
    40. 

  40. #define REG_SERCOM2_I2CM_INTFLAG   (0x42001018) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
    41. 

  41. #define REG_SERCOM2_I2CM_STATUS    (0x4200101A) /**< \brief (SERCOM2) I2CM Status */
    42. 

  42. #define REG_SERCOM2_I2CM_SYNCBUSY  (0x4200101C) /**< \brief (SERCOM2) I2CM Syncbusy */
    43. 

  43. #define REG_SERCOM2_I2CM_ADDR      (0x42001024) /**< \brief (SERCOM2) I2CM Address */
    44. 

  44. #define REG_SERCOM2_I2CM_DATA      (0x42001028) /**< \brief (SERCOM2) I2CM Data */
    45. 

  45. #define REG_SERCOM2_I2CM_DBGCTRL   (0x42001030) /**< \brief (SERCOM2) I2CM Debug Control */
    46. 

  46. #define REG_SERCOM2_I2CS_CTRLA     (0x42001000) /**< \brief (SERCOM2) I2CS Control A */
    47. 

  47. #define REG_SERCOM2_I2CS_CTRLB     (0x42001004) /**< \brief (SERCOM2) I2CS Control B */
    48. 

  48. #define REG_SERCOM2_I2CS_INTENCLR  (0x42001014) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */
    49. 

  49. #define REG_SERCOM2_I2CS_INTENSET  (0x42001016) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
    50. 

  50. #define REG_SERCOM2_I2CS_INTFLAG   (0x42001018) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
    51. 

  51. #define REG_SERCOM2_I2CS_STATUS    (0x4200101A) /**< \brief (SERCOM2) I2CS Status */
    52. 

  52. #define REG_SERCOM2_I2CS_SYNCBUSY  (0x4200101C) /**< \brief (SERCOM2) I2CS Syncbusy */
    53. 

  53. #define REG_SERCOM2_I2CS_ADDR      (0x42001024) /**< \brief (SERCOM2) I2CS Address */
    54. 

  54. #define REG_SERCOM2_I2CS_DATA      (0x42001028) /**< \brief (SERCOM2) I2CS Data */
    55. 

  55. #define REG_SERCOM2_SPI_CTRLA      (0x42001000) /**< \brief (SERCOM2) SPI Control A */
    56. 

  56. #define REG_SERCOM2_SPI_CTRLB      (0x42001004) /**< \brief (SERCOM2) SPI Control B */
    57. 

  57. #define REG_SERCOM2_SPI_BAUD       (0x4200100C) /**< \brief (SERCOM2) SPI Baud Rate */
    58. 

  58. #define REG_SERCOM2_SPI_INTENCLR   (0x42001014) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */
    59. 

  59. #define REG_SERCOM2_SPI_INTENSET   (0x42001016) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
    60. 

  60. #define REG_SERCOM2_SPI_INTFLAG    (0x42001018) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
    61. 

  61. #define REG_SERCOM2_SPI_STATUS     (0x4200101A) /**< \brief (SERCOM2) SPI Status */
    62. 

  62. #define REG_SERCOM2_SPI_SYNCBUSY   (0x4200101C) /**< \brief (SERCOM2) SPI Syncbusy */
    63. 

  63. #define REG_SERCOM2_SPI_ADDR       (0x42001024) /**< \brief (SERCOM2) SPI Address */
    64. 

  64. #define REG_SERCOM2_SPI_DATA       (0x42001028) /**< \brief (SERCOM2) SPI Data */
    65. 

  65. #define REG_SERCOM2_SPI_DBGCTRL    (0x42001030) /**< \brief (SERCOM2) SPI Debug Control */
    66. 

  66. #define REG_SERCOM2_USART_CTRLA    (0x42001000) /**< \brief (SERCOM2) USART Control A */
    67. 

  67. #define REG_SERCOM2_USART_CTRLB    (0x42001004) /**< \brief (SERCOM2) USART Control B */
    68. 

  68. #define REG_SERCOM2_USART_BAUD     (0x4200100C) /**< \brief (SERCOM2) USART Baud Rate */
    69. 

  69. #define REG_SERCOM2_USART_RXPL     (0x4200100E) /**< \brief (SERCOM2) USART Receive Pulse Length */
    70. 

  70. #define REG_SERCOM2_USART_INTENCLR (0x42001014) /**< \brief (SERCOM2) USART Interrupt Enable Clear */
    71. 

  71. #define REG_SERCOM2_USART_INTENSET (0x42001016) /**< \brief (SERCOM2) USART Interrupt Enable Set */
    72. 

  72. #define REG_SERCOM2_USART_INTFLAG  (0x42001018) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
    73. 

  73. #define REG_SERCOM2_USART_STATUS   (0x4200101A) /**< \brief (SERCOM2) USART Status */
    74. 

  74. #define REG_SERCOM2_USART_SYNCBUSY (0x4200101C) /**< \brief (SERCOM2) USART Syncbusy */
    75. 

  75. #define REG_SERCOM2_USART_DATA     (0x42001028) /**< \brief (SERCOM2) USART Data */
    76. 

  76. #define REG_SERCOM2_USART_DBGCTRL  (0x42001030) /**< \brief (SERCOM2) USART Debug Control */
    77. 

  77. #else
    78. 

  78. #define REG_SERCOM2_I2CM_CTRLA     (*(RwReg  *)0x42001000UL) /**< \brief (SERCOM2) I2CM Control A */
    79. 

  79. #define REG_SERCOM2_I2CM_CTRLB     (*(RwReg  *)0x42001004UL) /**< \brief (SERCOM2) I2CM Control B */
    80. 

  80. #define REG_SERCOM2_I2CM_BAUD      (*(RwReg  *)0x4200100CUL) /**< \brief (SERCOM2) I2CM Baud Rate */
    81. 

  81. #define REG_SERCOM2_I2CM_INTENCLR  (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */
    82. 

  82. #define REG_SERCOM2_I2CM_INTENSET  (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
    83. 

  83. #define REG_SERCOM2_I2CM_INTFLAG   (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
    84. 

  84. #define REG_SERCOM2_I2CM_STATUS    (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM2) I2CM Status */
    85. 

  85. #define REG_SERCOM2_I2CM_SYNCBUSY  (*(RoReg  *)0x4200101CUL) /**< \brief (SERCOM2) I2CM Syncbusy */
    86. 

  86. #define REG_SERCOM2_I2CM_ADDR      (*(RwReg  *)0x42001024UL) /**< \brief (SERCOM2) I2CM Address */
    87. 

  87. #define REG_SERCOM2_I2CM_DATA      (*(RwReg8 *)0x42001028UL) /**< \brief (SERCOM2) I2CM Data */
    88. 

  88. #define REG_SERCOM2_I2CM_DBGCTRL   (*(RwReg8 *)0x42001030UL) /**< \brief (SERCOM2) I2CM Debug Control */
    89. 

  89. #define REG_SERCOM2_I2CS_CTRLA     (*(RwReg  *)0x42001000UL) /**< \brief (SERCOM2) I2CS Control A */
    90. 

  90. #define REG_SERCOM2_I2CS_CTRLB     (*(RwReg  *)0x42001004UL) /**< \brief (SERCOM2) I2CS Control B */
    91. 

  91. #define REG_SERCOM2_I2CS_INTENCLR  (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */
    92. 

  92. #define REG_SERCOM2_I2CS_INTENSET  (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
    93. 

  93. #define REG_SERCOM2_I2CS_INTFLAG   (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
    94. 

  94. #define REG_SERCOM2_I2CS_STATUS    (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM2) I2CS Status */
    95. 

  95. #define REG_SERCOM2_I2CS_SYNCBUSY  (*(RoReg  *)0x4200101CUL) /**< \brief (SERCOM2) I2CS Syncbusy */
    96. 

  96. #define REG_SERCOM2_I2CS_ADDR      (*(RwReg  *)0x42001024UL) /**< \brief (SERCOM2) I2CS Address */
    97. 

  97. #define REG_SERCOM2_I2CS_DATA      (*(RwReg8 *)0x42001028UL) /**< \brief (SERCOM2) I2CS Data */
    98. 

  98. #define REG_SERCOM2_SPI_CTRLA      (*(RwReg  *)0x42001000UL) /**< \brief (SERCOM2) SPI Control A */
    99. 

  99. #define REG_SERCOM2_SPI_CTRLB      (*(RwReg  *)0x42001004UL) /**< \brief (SERCOM2) SPI Control B */
    100. 

  100. #define REG_SERCOM2_SPI_BAUD       (*(RwReg8 *)0x4200100CUL) /**< \brief (SERCOM2) SPI Baud Rate */
    101. 

  101. #define REG_SERCOM2_SPI_INTENCLR   (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */
    102. 

  102. #define REG_SERCOM2_SPI_INTENSET   (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
    103. 

  103. #define REG_SERCOM2_SPI_INTFLAG    (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
    104. 

  104. #define REG_SERCOM2_SPI_STATUS     (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM2) SPI Status */
    105. 

  105. #define REG_SERCOM2_SPI_SYNCBUSY   (*(RoReg  *)0x4200101CUL) /**< \brief (SERCOM2) SPI Syncbusy */
    106. 

  106. #define REG_SERCOM2_SPI_ADDR       (*(RwReg  *)0x42001024UL) /**< \brief (SERCOM2) SPI Address */
    107. 

  107. #define REG_SERCOM2_SPI_DATA       (*(RwReg  *)0x42001028UL) /**< \brief (SERCOM2) SPI Data */
    108. 

  108. #define REG_SERCOM2_SPI_DBGCTRL    (*(RwReg8 *)0x42001030UL) /**< \brief (SERCOM2) SPI Debug Control */
    109. 

  109. #define REG_SERCOM2_USART_CTRLA    (*(RwReg  *)0x42001000UL) /**< \brief (SERCOM2) USART Control A */
    110. 

  110. #define REG_SERCOM2_USART_CTRLB    (*(RwReg  *)0x42001004UL) /**< \brief (SERCOM2) USART Control B */
    111. 

  111. #define REG_SERCOM2_USART_BAUD     (*(RwReg16*)0x4200100CUL) /**< \brief (SERCOM2) USART Baud Rate */
    112. 

  112. #define REG_SERCOM2_USART_RXPL     (*(RwReg8 *)0x4200100EUL) /**< \brief (SERCOM2) USART Receive Pulse Length */
    113. 

  113. #define REG_SERCOM2_USART_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM2) USART Interrupt Enable Clear */
    114. 

  114. #define REG_SERCOM2_USART_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM2) USART Interrupt Enable Set */
    115. 

  115. #define REG_SERCOM2_USART_INTFLAG  (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
    116. 

  116. #define REG_SERCOM2_USART_STATUS   (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM2) USART Status */
    117. 

  117. #define REG_SERCOM2_USART_SYNCBUSY (*(RoReg  *)0x4200101CUL) /**< \brief (SERCOM2) USART Syncbusy */
    118. 

  118. #define REG_SERCOM2_USART_DATA     (*(RwReg16*)0x42001028UL) /**< \brief (SERCOM2) USART Data */
    119. 

  119. #define REG_SERCOM2_USART_DBGCTRL  (*(RwReg8 *)0x42001030UL) /**< \brief (SERCOM2) USART Debug Control */
    120. 

  120. #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
    121. 

  121. 

  122. /* ========== Instance parameters for SERCOM2 peripheral ========== */
    123. 

  123. #define SERCOM2_DMAC_ID_RX          5        // Index of DMA RX trigger
    124. 

  124. #define SERCOM2_DMAC_ID_TX          6        // Index of DMA TX trigger
    125. 

  125. #define SERCOM2_GCLK_ID_CORE        16       // Index of Generic Clock for Core
    126. 

  126. #define SERCOM2_GCLK_ID_SLOW        13       // Index of Generic Clock for SMbus Timeout
    127. 

  127. #define SERCOM2_INT_MSB             6       
    128. 

  128. 

  129. #endif /* _SAMD11_SERCOM2_INSTANCE_ */
    130.