gclk.h 3.0 KB

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  1. /**
  2. * \file
  3. *
  4. * \brief Instance description for GCLK
  5. *
  6. * Copyright (c) 2018 Microchip Technology Inc.
  7. *
  8. * \asf_license_start
  9. *
  10. * \page License
  11. *
  12. * SPDX-License-Identifier: Apache-2.0
  13. *
  14. * Licensed under the Apache License, Version 2.0 (the "License"); you may
  15. * not use this file except in compliance with the License.
  16. * You may obtain a copy of the Licence at
  17. *
  18. * http://www.apache.org/licenses/LICENSE-2.0
  19. *
  20. * Unless required by applicable law or agreed to in writing, software
  21. * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  22. * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  23. * See the License for the specific language governing permissions and
  24. * limitations under the License.
  25. *
  26. * \asf_license_stop
  27. *
  28. */
  29. #ifndef _SAMD11_GCLK_INSTANCE_
  30. #define _SAMD11_GCLK_INSTANCE_
  31. /* ========== Register definition for GCLK peripheral ========== */
  32. #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
  33. #define REG_GCLK_CTRL (0x40000C00) /**< \brief (GCLK) Control */
  34. #define REG_GCLK_STATUS (0x40000C01) /**< \brief (GCLK) Status */
  35. #define REG_GCLK_CLKCTRL (0x40000C02) /**< \brief (GCLK) Generic Clock Control */
  36. #define REG_GCLK_GENCTRL (0x40000C04) /**< \brief (GCLK) Generic Clock Generator Control */
  37. #define REG_GCLK_GENDIV (0x40000C08) /**< \brief (GCLK) Generic Clock Generator Division */
  38. #else
  39. #define REG_GCLK_CTRL (*(RwReg8 *)0x40000C00UL) /**< \brief (GCLK) Control */
  40. #define REG_GCLK_STATUS (*(RoReg8 *)0x40000C01UL) /**< \brief (GCLK) Status */
  41. #define REG_GCLK_CLKCTRL (*(RwReg16*)0x40000C02UL) /**< \brief (GCLK) Generic Clock Control */
  42. #define REG_GCLK_GENCTRL (*(RwReg *)0x40000C04UL) /**< \brief (GCLK) Generic Clock Generator Control */
  43. #define REG_GCLK_GENDIV (*(RwReg *)0x40000C08UL) /**< \brief (GCLK) Generic Clock Generator Division */
  44. #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
  45. /* ========== Instance parameters for GCLK peripheral ========== */
  46. #define GCLK_GENDIV_BITS 16
  47. #define GCLK_GEN_NUM 6 // Number of Generic Clock Generators
  48. #define GCLK_GEN_NUM_MSB 5 // Number of Generic Clock Generators - 1
  49. #define GCLK_GEN_SOURCE_NUM_MSB 8 // Number of Generic Clock Sources - 1
  50. #define GCLK_NUM 24 // Number of Generic Clock Users
  51. #define GCLK_SOURCE_DFLL48M 7
  52. #define GCLK_SOURCE_DPLL96M 8
  53. #define GCLK_SOURCE_GCLKGEN1 2
  54. #define GCLK_SOURCE_GCLKIN 1
  55. #define GCLK_SOURCE_NUM 9 // Number of Generic Clock Sources
  56. #define GCLK_SOURCE_OSCULP32K 3
  57. #define GCLK_SOURCE_OSC8M 6
  58. #define GCLK_SOURCE_OSC32K 4
  59. #define GCLK_SOURCE_XOSC 0
  60. #define GCLK_SOURCE_XOSC32K 5
  61. #endif /* _SAMD11_GCLK_INSTANCE_ */