dac.h 2.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960
  1. /**
  2. * \file
  3. *
  4. * \brief Instance description for DAC
  5. *
  6. * Copyright (c) 2018 Microchip Technology Inc.
  7. *
  8. * \asf_license_start
  9. *
  10. * \page License
  11. *
  12. * SPDX-License-Identifier: Apache-2.0
  13. *
  14. * Licensed under the Apache License, Version 2.0 (the "License"); you may
  15. * not use this file except in compliance with the License.
  16. * You may obtain a copy of the Licence at
  17. *
  18. * http://www.apache.org/licenses/LICENSE-2.0
  19. *
  20. * Unless required by applicable law or agreed to in writing, software
  21. * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  22. * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  23. * See the License for the specific language governing permissions and
  24. * limitations under the License.
  25. *
  26. * \asf_license_stop
  27. *
  28. */
  29. #ifndef _SAMD11_DAC_INSTANCE_
  30. #define _SAMD11_DAC_INSTANCE_
  31. /* ========== Register definition for DAC peripheral ========== */
  32. #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
  33. #define REG_DAC_CTRLA (0x42002800) /**< \brief (DAC) Control A */
  34. #define REG_DAC_CTRLB (0x42002801) /**< \brief (DAC) Control B */
  35. #define REG_DAC_EVCTRL (0x42002802) /**< \brief (DAC) Event Control */
  36. #define REG_DAC_INTENCLR (0x42002804) /**< \brief (DAC) Interrupt Enable Clear */
  37. #define REG_DAC_INTENSET (0x42002805) /**< \brief (DAC) Interrupt Enable Set */
  38. #define REG_DAC_INTFLAG (0x42002806) /**< \brief (DAC) Interrupt Flag Status and Clear */
  39. #define REG_DAC_STATUS (0x42002807) /**< \brief (DAC) Status */
  40. #define REG_DAC_DATA (0x42002808) /**< \brief (DAC) Data */
  41. #define REG_DAC_DATABUF (0x4200280C) /**< \brief (DAC) Data Buffer */
  42. #else
  43. #define REG_DAC_CTRLA (*(RwReg8 *)0x42002800UL) /**< \brief (DAC) Control A */
  44. #define REG_DAC_CTRLB (*(RwReg8 *)0x42002801UL) /**< \brief (DAC) Control B */
  45. #define REG_DAC_EVCTRL (*(RwReg8 *)0x42002802UL) /**< \brief (DAC) Event Control */
  46. #define REG_DAC_INTENCLR (*(RwReg8 *)0x42002804UL) /**< \brief (DAC) Interrupt Enable Clear */
  47. #define REG_DAC_INTENSET (*(RwReg8 *)0x42002805UL) /**< \brief (DAC) Interrupt Enable Set */
  48. #define REG_DAC_INTFLAG (*(RwReg8 *)0x42002806UL) /**< \brief (DAC) Interrupt Flag Status and Clear */
  49. #define REG_DAC_STATUS (*(RoReg8 *)0x42002807UL) /**< \brief (DAC) Status */
  50. #define REG_DAC_DATA (*(RwReg16*)0x42002808UL) /**< \brief (DAC) Data */
  51. #define REG_DAC_DATABUF (*(RwReg16*)0x4200280CUL) /**< \brief (DAC) Data Buffer */
  52. #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
  53. /* ========== Instance parameters for DAC peripheral ========== */
  54. #define DAC_DMAC_ID_EMPTY 19 // Index of DMAC EMPTY trigger
  55. #define DAC_GCLK_ID 22 // Index of Generic Clock
  56. #endif /* _SAMD11_DAC_INSTANCE_ */