nrf24.c 11 KB

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  1. // Modified by vad7, 24.02.2023
  2. //
  3. #include "nrf24.h"
  4. #include <furi.h>
  5. #include <furi_hal.h>
  6. #include <furi_hal_resources.h>
  7. #include <assert.h>
  8. #include <string.h>
  9. void nrf24_init() {
  10. furi_hal_spi_bus_handle_init(nrf24_HANDLE);
  11. furi_hal_spi_acquire(nrf24_HANDLE);
  12. furi_hal_gpio_init(nrf24_CE_PIN, GpioModeOutputPushPull, GpioPullUp, GpioSpeedVeryHigh);
  13. furi_hal_gpio_write(nrf24_CE_PIN, false);
  14. }
  15. void nrf24_deinit() {
  16. furi_hal_spi_release(nrf24_HANDLE);
  17. furi_hal_spi_bus_handle_deinit(nrf24_HANDLE);
  18. furi_hal_gpio_write(nrf24_CE_PIN, false);
  19. furi_hal_gpio_init(nrf24_CE_PIN, GpioModeAnalog, GpioPullNo, GpioSpeedLow);
  20. }
  21. void nrf24_spi_trx(
  22. FuriHalSpiBusHandle* handle,
  23. uint8_t* tx,
  24. uint8_t* rx,
  25. uint8_t size) {
  26. furi_hal_gpio_write(handle->cs, false);
  27. furi_hal_spi_bus_trx(handle, tx, rx, size, nrf24_TIMEOUT);
  28. furi_hal_gpio_write(handle->cs, true);
  29. }
  30. uint8_t nrf24_write_reg(FuriHalSpiBusHandle* handle, uint8_t reg, uint8_t data) {
  31. uint8_t buf[] = {W_REGISTER | (REGISTER_MASK & reg), data};
  32. nrf24_spi_trx(handle, buf, buf, 2);
  33. //FURI_LOG_D("NRF_WR", " #%02X=%02X", reg, data);
  34. return buf[0];
  35. }
  36. uint8_t nrf24_write_buf_reg(FuriHalSpiBusHandle* handle, uint8_t reg, uint8_t* data, uint8_t size) {
  37. uint8_t buf[size + 1];
  38. buf[0] = W_REGISTER | (REGISTER_MASK & reg);
  39. memcpy(&buf[1], data, size);
  40. nrf24_spi_trx(handle, buf, buf, size + 1);
  41. //FURI_LOG_D("NRF_WR", " #%02X(%02X)=0x%02X%02X%02X%02X%02X", reg, size, data[0], data[1], data[2], data[3], data[4] );
  42. return buf[0];
  43. }
  44. uint8_t nrf24_read_reg(FuriHalSpiBusHandle* handle, uint8_t reg, uint8_t* data, uint8_t size) {
  45. uint8_t buf[size + 1];
  46. memset(buf, 0, size + 1);
  47. buf[0] = R_REGISTER | (REGISTER_MASK & reg);
  48. nrf24_spi_trx(handle, buf, buf, size + 1);
  49. memcpy(data, &buf[1], size);
  50. return buf[0];
  51. }
  52. uint8_t nrf24_read_register(FuriHalSpiBusHandle* handle, uint8_t reg) {
  53. uint8_t buf[] = { R_REGISTER | (REGISTER_MASK & reg), 0xFF };
  54. nrf24_spi_trx(handle, buf, buf, 2);
  55. return buf[1];
  56. }
  57. uint8_t nrf24_flush_rx(FuriHalSpiBusHandle* handle) {
  58. uint8_t tx[] = {FLUSH_RX};
  59. uint8_t rx[] = {0};
  60. nrf24_spi_trx(handle, tx, rx, 1);
  61. return rx[0];
  62. }
  63. uint8_t nrf24_flush_tx(FuriHalSpiBusHandle* handle) {
  64. uint8_t tx[] = {FLUSH_TX};
  65. uint8_t rx[] = {0};
  66. nrf24_spi_trx(handle, tx, rx, 1);
  67. return rx[0];
  68. }
  69. uint8_t nrf24_get_maclen(FuriHalSpiBusHandle* handle) {
  70. uint8_t maclen;
  71. nrf24_read_reg(handle, REG_SETUP_AW, &maclen, 1);
  72. maclen &= 3;
  73. return maclen + 2;
  74. }
  75. uint8_t nrf24_set_maclen(FuriHalSpiBusHandle* handle, uint8_t maclen) {
  76. assert(maclen > 1 && maclen < 6);
  77. uint8_t status = 0;
  78. status = nrf24_write_reg(handle, REG_SETUP_AW, maclen - 2);
  79. return status;
  80. }
  81. uint8_t nrf24_status(FuriHalSpiBusHandle* handle) {
  82. uint8_t tx = RF24_NOP;
  83. nrf24_spi_trx(handle, &tx, &tx, 1);
  84. return tx;
  85. }
  86. uint32_t nrf24_get_rate(FuriHalSpiBusHandle* handle) {
  87. uint8_t setup = 0;
  88. uint32_t rate = 0;
  89. nrf24_read_reg(handle, REG_RF_SETUP, &setup, 1);
  90. setup &= 0x28;
  91. if(setup == 0x20)
  92. rate = 250000; // 250kbps
  93. else if(setup == 0x08)
  94. rate = 2000000; // 2Mbps
  95. else if(setup == 0x00)
  96. rate = 1000000; // 1Mbps
  97. return rate;
  98. }
  99. uint8_t nrf24_set_rate(FuriHalSpiBusHandle* handle, uint32_t rate) {
  100. uint8_t r6 = 0;
  101. uint8_t status = 0;
  102. if(!rate) rate = 2000000;
  103. nrf24_read_reg(handle, REG_RF_SETUP, &r6, 1); // RF_SETUP register
  104. r6 = r6 & (~0x28); // Clear rate fields.
  105. if(rate == 2000000)
  106. r6 = r6 | 0x08;
  107. else if(rate == 1000000)
  108. r6 = r6;
  109. else if(rate == 250000)
  110. r6 = r6 | 0x20;
  111. status = nrf24_write_reg(handle, REG_RF_SETUP, r6); // Write new rate.
  112. return status;
  113. }
  114. uint8_t nrf24_get_chan(FuriHalSpiBusHandle* handle) {
  115. uint8_t channel = 0;
  116. nrf24_read_reg(handle, REG_RF_CH, &channel, 1);
  117. return channel;
  118. }
  119. uint8_t nrf24_set_chan(FuriHalSpiBusHandle* handle, uint8_t chan) {
  120. uint8_t status;
  121. status = nrf24_write_reg(handle, REG_RF_CH, chan);
  122. return status;
  123. }
  124. uint8_t nrf24_get_src_mac(FuriHalSpiBusHandle* handle, uint8_t* mac) {
  125. uint8_t size = 0;
  126. uint8_t status = 0;
  127. size = nrf24_get_maclen(handle);
  128. status = nrf24_read_reg(handle, REG_RX_ADDR_P0, mac, size);
  129. return status;
  130. }
  131. uint8_t nrf24_set_src_mac(FuriHalSpiBusHandle* handle, uint8_t* mac, uint8_t size) {
  132. uint8_t status = 0;
  133. uint8_t clearmac[] = {0, 0, 0, 0, 0};
  134. nrf24_set_maclen(handle, size);
  135. nrf24_write_buf_reg(handle, REG_RX_ADDR_P0, clearmac, 5);
  136. status = nrf24_write_buf_reg(handle, REG_RX_ADDR_P0, mac, size);
  137. return status;
  138. }
  139. uint8_t nrf24_get_dst_mac(FuriHalSpiBusHandle* handle, uint8_t* mac) {
  140. uint8_t size = 0;
  141. uint8_t status = 0;
  142. size = nrf24_get_maclen(handle);
  143. status = nrf24_read_reg(handle, REG_TX_ADDR, mac, size);
  144. return status;
  145. }
  146. uint8_t nrf24_set_dst_mac(FuriHalSpiBusHandle* handle, uint8_t* mac, uint8_t size) {
  147. uint8_t status = 0;
  148. uint8_t clearmac[] = {0, 0, 0, 0, 0};
  149. nrf24_set_maclen(handle, size);
  150. nrf24_write_buf_reg(handle, REG_TX_ADDR, clearmac, 5);
  151. status = nrf24_write_buf_reg(handle, REG_TX_ADDR, mac, size);
  152. return status;
  153. }
  154. uint8_t nrf24_get_packetlen(FuriHalSpiBusHandle* handle, uint8_t pipe) {
  155. uint8_t len = 0;
  156. if(pipe > 5) pipe = 0;
  157. nrf24_read_reg(handle, RX_PW_P0 + pipe, &len, 1);
  158. return len;
  159. }
  160. uint8_t nrf24_set_packetlen(FuriHalSpiBusHandle* handle, uint8_t len) {
  161. uint8_t status = 0;
  162. status = nrf24_write_reg(handle, RX_PW_P0, len);
  163. return status;
  164. }
  165. // packet_size: 0 - dyn payload (read from PL_WID), 1 - read from pipe size, >1 - override
  166. uint8_t nrf24_rxpacket(FuriHalSpiBusHandle* handle, uint8_t* packet, uint8_t* ret_packetsize, uint8_t packet_size) {
  167. uint8_t status = 0;
  168. uint8_t buf[33]; // 32 max payload size + 1 for command
  169. status = nrf24_status(handle);
  170. if(!(status & RX_DR)) {
  171. if((nrf24_read_register(handle, REG_FIFO_STATUS) & 1) == 0) {
  172. FURI_LOG_D("NRF", "FIFO PKT");
  173. status |= RX_DR; // packet in FIFO buffer
  174. }
  175. }
  176. if(status & RX_DR) {
  177. if(packet_size == 1)
  178. packet_size = nrf24_get_packetlen(handle, (status >> 1) & 7);
  179. else if(packet_size == 0){
  180. buf[0] = R_RX_PL_WID; buf[1] = 0xFF;
  181. nrf24_spi_trx(handle, buf, buf, 2);
  182. packet_size = buf[1];
  183. }
  184. if(packet_size > 32 || packet_size == 0) packet_size = 32;
  185. memset(buf, 0, packet_size + 1);
  186. buf[0] = R_RX_PAYLOAD;
  187. nrf24_spi_trx(handle, buf, buf, packet_size + 1);
  188. memcpy(packet, &buf[1], packet_size);
  189. nrf24_write_reg(handle, REG_STATUS, RX_DR); // clear RX_DR
  190. }
  191. // if(status & (TX_DS | MAX_RT)) { // MAX_RT, TX_DS
  192. // nrf24_write_reg(handle, REG_STATUS, (TX_DS | MAX_RT)); // clear RX_DR, MAX_RT.
  193. // }
  194. *ret_packetsize = packet_size;
  195. return status;
  196. }
  197. // Return 0 when error
  198. uint8_t nrf24_txpacket(FuriHalSpiBusHandle* handle, uint8_t* payload, uint8_t size, bool ack) {
  199. uint8_t status = 0;
  200. uint8_t buf[size + 1];
  201. buf[0] = ack ? W_TX_PAYLOAD : W_TX_PAYLOAD_NOACK;
  202. memcpy(&buf[1], payload, size);
  203. nrf24_set_tx_mode(handle);
  204. nrf24_spi_trx(handle, buf, buf, size + 1);
  205. uint32_t start_time = furi_get_tick();
  206. do {
  207. furi_delay_us(100);
  208. status = nrf24_status(handle);
  209. } while(!(status & (TX_DS | MAX_RT)) && furi_get_tick() - start_time < 100UL);
  210. if(status & MAX_RT) {
  211. if(furi_log_get_level() == FuriLogLevelDebug) FURI_LOG_D("NRF", "MAX RT: %X (%X)", nrf24_read_register(handle, REG_OBSERVE_TX), status);
  212. nrf24_flush_tx(handle);
  213. }
  214. furi_hal_gpio_write(nrf24_CE_PIN, false);
  215. //nrf24_set_idle(handle);
  216. if(status & (TX_DS | MAX_RT)) nrf24_write_reg(handle, REG_STATUS, TX_DS | MAX_RT);
  217. return status & TX_DS;
  218. }
  219. uint8_t nrf24_power_up(FuriHalSpiBusHandle* handle) {
  220. uint8_t status = 0;
  221. uint8_t cfg = 0;
  222. nrf24_read_reg(handle, REG_CONFIG, &cfg, 1);
  223. cfg = cfg | 2;
  224. status = nrf24_write_reg(handle, REG_CONFIG, cfg);
  225. //furi_delay_ms(1000);
  226. return status;
  227. }
  228. uint8_t nrf24_set_idle(FuriHalSpiBusHandle* handle) {
  229. uint8_t status = 0;
  230. uint8_t cfg = 0;
  231. nrf24_read_reg(handle, REG_CONFIG, &cfg, 1);
  232. cfg &= 0xfc; // clear bottom two bits to power down the radio
  233. status = nrf24_write_reg(handle, REG_CONFIG, cfg);
  234. furi_hal_gpio_write(nrf24_CE_PIN, false);
  235. return status;
  236. }
  237. uint8_t nrf24_set_rx_mode(FuriHalSpiBusHandle* handle) {
  238. uint8_t cfg = 0;
  239. cfg = nrf24_read_register(handle, REG_CONFIG);
  240. cfg |= 0x03; // PWR_UP, and PRIM_RX
  241. cfg = nrf24_write_reg(handle, REG_CONFIG, cfg);
  242. furi_hal_gpio_write(nrf24_CE_PIN, true);
  243. return cfg;
  244. }
  245. uint8_t nrf24_set_tx_mode(FuriHalSpiBusHandle* handle) {
  246. uint8_t reg;
  247. furi_hal_gpio_write(nrf24_CE_PIN, false);
  248. //nrf24_write_reg(handle, REG_STATUS, TX_DS | MAX_RT);
  249. reg = nrf24_read_register(handle, REG_CONFIG);
  250. reg &= ~0x01; // disable PRIM_RX
  251. reg |= 0x02; // PWR_UP
  252. reg = nrf24_write_reg(handle, REG_CONFIG, reg);
  253. furi_hal_gpio_write(nrf24_CE_PIN, true);
  254. return reg;
  255. }
  256. void hexlify(uint8_t* in, uint8_t size, char* out) {
  257. memset(out, 0, size * 2);
  258. for(int i = 0; i < size; i++)
  259. snprintf(out + strlen(out), sizeof(out + strlen(out)), "%02X", in[i]);
  260. }
  261. uint64_t bytes_to_int64(uint8_t* bytes, uint8_t size, bool bigendian) {
  262. uint64_t ret = 0;
  263. for(int i = 0; i < size; i++)
  264. if(bigendian)
  265. ret |= bytes[i] << ((size - 1 - i) * 8);
  266. else
  267. ret |= bytes[i] << (i * 8);
  268. return ret;
  269. }
  270. void int64_to_bytes(uint64_t val, uint8_t* out, bool bigendian) {
  271. for(int i = 0; i < 8; i++) {
  272. if(bigendian)
  273. out[i] = (val >> ((7 - i) * 8)) & 0xff;
  274. else
  275. out[i] = (val >> (i * 8)) & 0xff;
  276. }
  277. }
  278. uint32_t bytes_to_int32(uint8_t* bytes, bool bigendian) {
  279. uint32_t ret = 0;
  280. for(int i = 0; i < 4; i++)
  281. if(bigendian)
  282. ret |= bytes[i] << ((3 - i) * 8);
  283. else
  284. ret |= bytes[i] << (i * 8);
  285. return ret;
  286. }
  287. void int32_to_bytes(uint32_t val, uint8_t* out, bool bigendian) {
  288. for(int i = 0; i < 4; i++) {
  289. if(bigendian)
  290. out[i] = (val >> ((3 - i) * 8)) & 0xff;
  291. else
  292. out[i] = (val >> (i * 8)) & 0xff;
  293. }
  294. }
  295. uint64_t bytes_to_int16(uint8_t* bytes, bool bigendian) {
  296. uint16_t ret = 0;
  297. for(int i = 0; i < 2; i++)
  298. if(bigendian)
  299. ret |= bytes[i] << ((1 - i) * 8);
  300. else
  301. ret |= bytes[i] << (i * 8);
  302. return ret;
  303. }
  304. void int16_to_bytes(uint16_t val, uint8_t* out, bool bigendian) {
  305. for(int i = 0; i < 2; i++) {
  306. if(bigendian)
  307. out[i] = (val >> ((1 - i) * 8)) & 0xff;
  308. else
  309. out[i] = (val >> (i * 8)) & 0xff;
  310. }
  311. }
  312. uint8_t nrf24_set_mac(uint8_t mac_addr, uint8_t *mac, uint8_t mlen)
  313. {
  314. uint8_t addr[5];
  315. for(int i = 0; i < mlen; i++) addr[i] = mac[mlen - i - 1];
  316. return nrf24_write_buf_reg(nrf24_HANDLE, mac_addr, addr, mlen);
  317. }