api-hal-subghz.c 18 KB

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  1. #include "api-hal-subghz.h"
  2. #include <api-hal-gpio.h>
  3. #include <api-hal-spi.h>
  4. #include <api-hal-interrupt.h>
  5. #include <api-hal-resources.h>
  6. #include <furi.h>
  7. #include <cc1101.h>
  8. #include <stdio.h>
  9. static volatile SubGhzState api_hal_subghz_state = SubGhzStateInit;
  10. static const uint8_t api_hal_subghz_preset_ook_async_regs[][2] = {
  11. // https://e2e.ti.com/support/wireless-connectivity/sub-1-ghz-group/sub-1-ghz/f/sub-1-ghz-forum/382066/cc1101---don-t-know-the-correct-registers-configuration
  12. /* GPIO GD0 */
  13. { CC1101_IOCFG0, 0x0D }, // GD0 as async serial data output/input
  14. /* FIFO and internals */
  15. { CC1101_FIFOTHR, 0x47 }, // The only important bit is ADC_RETENTION
  16. /* Packet engine */
  17. { CC1101_PKTCTRL0, 0x32 }, // Async, continious, no whitening
  18. /* Frequency Synthesizer Control */
  19. { CC1101_FSCTRL1, 0x06 }, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
  20. // Modem Configuration
  21. { CC1101_MDMCFG0, 0x00 }, // Channel spacing is 25kHz
  22. { CC1101_MDMCFG1, 0x00 }, // Channel spacing is 25kHz
  23. { CC1101_MDMCFG2, 0x30 }, // Format ASK/OOK, No preamble/sync
  24. { CC1101_MDMCFG3, 0x32 }, // Data rate is 3.79372 kBaud
  25. { CC1101_MDMCFG4, 0x67 }, // Rx BW filter is 270.833333kHz
  26. /* Main Radio Control State Machine */
  27. { CC1101_MCSM0, 0x18 }, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
  28. /* Frequency Offset Compensation Configuration */
  29. { CC1101_FOCCFG, 0x18 }, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
  30. /* Automatic Gain Control */
  31. { CC1101_AGCTRL1, 0x00 }, // LNA 2 gain is decreased to minimum before decreasing LNA gain
  32. { CC1101_AGCTRL2, 0x07 }, // MAGN_TARGET is 42 dB
  33. /* Wake on radio and timeouts control */
  34. { CC1101_WORCTRL, 0xFB }, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
  35. /* Frontend configuration */
  36. { CC1101_FREND0, 0x11 }, // Adjusts current TX LO buffer + high is PATABLE[1]
  37. { CC1101_FREND1, 0xB6 }, //
  38. /* Frequency Synthesizer Calibration, valid for 433.92 */
  39. { CC1101_FSCAL3, 0xE9 },
  40. { CC1101_FSCAL2, 0x2A },
  41. { CC1101_FSCAL1, 0x00 },
  42. { CC1101_FSCAL0, 0x1F },
  43. /* Magic f4ckery */
  44. { CC1101_TEST2, 0x81 }, // FIFOTHR ADC_RETENTION=1 matched value
  45. { CC1101_TEST1, 0x35 }, // FIFOTHR ADC_RETENTION=1 matched value
  46. { CC1101_TEST0, 0x09 }, // VCO selection calibration stage is disabled
  47. /* End */
  48. { 0, 0 },
  49. };
  50. static const uint8_t api_hal_subghz_preset_ook_async_patable[8] = {
  51. 0x00,
  52. 0xC0, // 10dBm 0xC0, 7dBm 0xC8, 5dBm 0x84, 0dBm 0x60, -10dBm 0x34, -15dBm 0x1D, -20dBm 0x0E, -30dBm 0x12
  53. 0x00,
  54. 0x00,
  55. 0x00,
  56. 0x00,
  57. 0x00,
  58. 0x00
  59. };
  60. void api_hal_subghz_init() {
  61. furi_assert(api_hal_subghz_state == SubGhzStateInit);
  62. api_hal_subghz_state = SubGhzStateIdle;
  63. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  64. #ifdef API_HAL_SUBGHZ_TX_GPIO
  65. hal_gpio_init(&API_HAL_SUBGHZ_TX_GPIO, GpioModeOutputPushPull, GpioPullNo, GpioSpeedLow);
  66. #endif
  67. // Reset
  68. hal_gpio_init(&gpio_cc1101_g0, GpioModeAnalog, GpioPullNo, GpioSpeedLow);
  69. cc1101_reset(device);
  70. cc1101_write_reg(device, CC1101_IOCFG0, CC1101IocfgHighImpedance);
  71. // Prepare GD0 for power on self test
  72. hal_gpio_init(&gpio_cc1101_g0, GpioModeInput, GpioPullNo, GpioSpeedLow);
  73. // GD0 low
  74. cc1101_write_reg(device, CC1101_IOCFG0, CC1101IocfgHW);
  75. while(hal_gpio_read(&gpio_cc1101_g0) != false);
  76. // GD0 high
  77. cc1101_write_reg(device, CC1101_IOCFG0, CC1101IocfgHW | CC1101_IOCFG_INV);
  78. while(hal_gpio_read(&gpio_cc1101_g0) != true);
  79. // Reset GD0 to floating state
  80. cc1101_write_reg(device, CC1101_IOCFG0, CC1101IocfgHighImpedance);
  81. hal_gpio_init(&gpio_cc1101_g0, GpioModeAnalog, GpioPullNo, GpioSpeedLow);
  82. // RF switches
  83. hal_gpio_init(&gpio_rf_sw_0, GpioModeOutputPushPull, GpioPullNo, GpioSpeedLow);
  84. cc1101_write_reg(device, CC1101_IOCFG2, CC1101IocfgHW);
  85. // Go to sleep
  86. cc1101_shutdown(device);
  87. api_hal_spi_device_return(device);
  88. FURI_LOG_I("FuriHalSubGhz", "Init OK");
  89. }
  90. void api_hal_subghz_sleep() {
  91. furi_assert(api_hal_subghz_state == SubGhzStateIdle);
  92. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  93. cc1101_switch_to_idle(device);
  94. cc1101_write_reg(device, CC1101_IOCFG0, CC1101IocfgHighImpedance);
  95. hal_gpio_init(&gpio_cc1101_g0, GpioModeAnalog, GpioPullNo, GpioSpeedLow);
  96. cc1101_shutdown(device);
  97. api_hal_spi_device_return(device);
  98. }
  99. void api_hal_subghz_dump_state() {
  100. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  101. printf(
  102. "[api_hal_subghz] cc1101 chip %d, version %d\r\n",
  103. cc1101_get_partnumber(device),
  104. cc1101_get_version(device)
  105. );
  106. api_hal_spi_device_return(device);
  107. }
  108. void api_hal_subghz_load_preset(ApiHalSubGhzPreset preset) {
  109. if(preset == ApiHalSubGhzPresetOokAsync) {
  110. api_hal_subghz_load_registers(api_hal_subghz_preset_ook_async_regs);
  111. api_hal_subghz_load_patable(api_hal_subghz_preset_ook_async_patable);
  112. } else {
  113. furi_check(0);
  114. }
  115. }
  116. uint8_t api_hal_subghz_get_status() {
  117. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  118. CC1101StatusRaw st;
  119. st.status = cc1101_get_status(device);
  120. api_hal_spi_device_return(device);
  121. return st.status_raw;
  122. }
  123. void api_hal_subghz_load_registers(const uint8_t data[][2]) {
  124. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  125. cc1101_reset(device);
  126. uint32_t i = 0;
  127. while (data[i][0]) {
  128. cc1101_write_reg(device, data[i][0], data[i][1]);
  129. i++;
  130. }
  131. api_hal_spi_device_return(device);
  132. }
  133. void api_hal_subghz_load_patable(const uint8_t data[8]) {
  134. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  135. cc1101_set_pa_table(device, data);
  136. api_hal_spi_device_return(device);
  137. }
  138. void api_hal_subghz_write_packet(const uint8_t* data, uint8_t size) {
  139. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  140. cc1101_flush_tx(device);
  141. cc1101_write_fifo(device, data, size);
  142. api_hal_spi_device_return(device);
  143. }
  144. void api_hal_subghz_flush_rx() {
  145. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  146. cc1101_flush_rx(device);
  147. api_hal_spi_device_return(device);
  148. }
  149. void api_hal_subghz_read_packet(uint8_t* data, uint8_t* size) {
  150. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  151. cc1101_read_fifo(device, data, size);
  152. api_hal_spi_device_return(device);
  153. }
  154. void api_hal_subghz_shutdown() {
  155. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  156. // Reset and shutdown
  157. cc1101_shutdown(device);
  158. api_hal_spi_device_return(device);
  159. }
  160. void api_hal_subghz_reset() {
  161. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  162. hal_gpio_init(&gpio_cc1101_g0, GpioModeAnalog, GpioPullNo, GpioSpeedLow);
  163. cc1101_switch_to_idle(device);
  164. cc1101_reset(device);
  165. cc1101_write_reg(device, CC1101_IOCFG0, CC1101IocfgHighImpedance);
  166. api_hal_spi_device_return(device);
  167. }
  168. void api_hal_subghz_idle() {
  169. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  170. cc1101_switch_to_idle(device);
  171. api_hal_spi_device_return(device);
  172. }
  173. void api_hal_subghz_rx() {
  174. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  175. cc1101_switch_to_rx(device);
  176. api_hal_spi_device_return(device);
  177. }
  178. void api_hal_subghz_tx() {
  179. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  180. cc1101_switch_to_tx(device);
  181. api_hal_spi_device_return(device);
  182. }
  183. float api_hal_subghz_get_rssi() {
  184. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  185. int32_t rssi_dec = cc1101_get_rssi(device);
  186. api_hal_spi_device_return(device);
  187. float rssi = rssi_dec;
  188. if(rssi_dec >= 128) {
  189. rssi = ((rssi - 256.0f) / 2.0f) - 74.0f;
  190. } else {
  191. rssi = (rssi / 2.0f) - 74.0f;
  192. }
  193. return rssi;
  194. }
  195. bool api_hal_subghz_is_frequency_valid(uint32_t value) {
  196. if(!(value >= 299999755 && value <= 348000335) &&
  197. !(value >= 386999938 && value <= 464000000) &&
  198. !(value >= 778999847 && value <= 928000000)) {
  199. return false;
  200. }
  201. return true;
  202. }
  203. uint32_t api_hal_subghz_set_frequency_and_path(uint32_t value) {
  204. value = api_hal_subghz_set_frequency(value);
  205. if(value >= 299999755 && value <= 348000335) {
  206. api_hal_subghz_set_path(ApiHalSubGhzPath315);
  207. } else if(value >= 386999938 && value <= 464000000) {
  208. api_hal_subghz_set_path(ApiHalSubGhzPath433);
  209. } else if(value >= 778999847 && value <= 928000000) {
  210. api_hal_subghz_set_path(ApiHalSubGhzPath868);
  211. } else {
  212. furi_check(0);
  213. }
  214. return value;
  215. }
  216. uint32_t api_hal_subghz_set_frequency(uint32_t value) {
  217. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  218. uint32_t real_frequency = cc1101_set_frequency(device, value);
  219. cc1101_calibrate(device);
  220. api_hal_spi_device_return(device);
  221. return real_frequency;
  222. }
  223. void api_hal_subghz_set_path(ApiHalSubGhzPath path) {
  224. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  225. if (path == ApiHalSubGhzPath433) {
  226. hal_gpio_write(&gpio_rf_sw_0, 0);
  227. cc1101_write_reg(device, CC1101_IOCFG2, CC1101IocfgHW | CC1101_IOCFG_INV);
  228. } else if (path == ApiHalSubGhzPath315) {
  229. hal_gpio_write(&gpio_rf_sw_0, 1);
  230. cc1101_write_reg(device, CC1101_IOCFG2, CC1101IocfgHW);
  231. } else if (path == ApiHalSubGhzPath868) {
  232. hal_gpio_write(&gpio_rf_sw_0, 1);
  233. cc1101_write_reg(device, CC1101_IOCFG2, CC1101IocfgHW | CC1101_IOCFG_INV);
  234. } else if (path == ApiHalSubGhzPathIsolate) {
  235. hal_gpio_write(&gpio_rf_sw_0, 0);
  236. cc1101_write_reg(device, CC1101_IOCFG2, CC1101IocfgHW);
  237. } else {
  238. furi_check(0);
  239. }
  240. api_hal_spi_device_return(device);
  241. }
  242. volatile uint32_t api_hal_subghz_capture_delta_duration = 0;
  243. volatile ApiHalSubGhzCaptureCallback api_hal_subghz_capture_callback = NULL;
  244. volatile void* api_hal_subghz_capture_callback_context = NULL;
  245. static void api_hal_subghz_capture_ISR() {
  246. // Channel 1
  247. if(LL_TIM_IsActiveFlag_CC1(TIM2)) {
  248. LL_TIM_ClearFlag_CC1(TIM2);
  249. api_hal_subghz_capture_delta_duration = LL_TIM_IC_GetCaptureCH1(TIM2);
  250. if (api_hal_subghz_capture_callback) {
  251. api_hal_subghz_capture_callback(true, api_hal_subghz_capture_delta_duration,
  252. (void*)api_hal_subghz_capture_callback_context
  253. );
  254. }
  255. }
  256. // Channel 2
  257. if(LL_TIM_IsActiveFlag_CC2(TIM2)) {
  258. LL_TIM_ClearFlag_CC2(TIM2);
  259. if (api_hal_subghz_capture_callback) {
  260. api_hal_subghz_capture_callback(false, LL_TIM_IC_GetCaptureCH2(TIM2) - api_hal_subghz_capture_delta_duration,
  261. (void*)api_hal_subghz_capture_callback_context
  262. );
  263. }
  264. }
  265. }
  266. void api_hal_subghz_set_async_rx_callback(ApiHalSubGhzCaptureCallback callback, void* context) {
  267. api_hal_subghz_capture_callback = callback;
  268. api_hal_subghz_capture_callback_context = context;
  269. }
  270. void api_hal_subghz_start_async_rx() {
  271. furi_assert(api_hal_subghz_state == SubGhzStateIdle);
  272. api_hal_subghz_state = SubGhzStateAsyncRx;
  273. hal_gpio_init_ex(&gpio_cc1101_g0, GpioModeAltFunctionPushPull, GpioPullNo, GpioSpeedLow, GpioAltFn1TIM2);
  274. // Timer: base
  275. LL_TIM_InitTypeDef TIM_InitStruct = {0};
  276. TIM_InitStruct.Prescaler = 64-1;
  277. TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;
  278. TIM_InitStruct.Autoreload = 0x7FFFFFFE;
  279. TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
  280. LL_TIM_Init(TIM2, &TIM_InitStruct);
  281. // Timer: advanced
  282. LL_TIM_SetClockSource(TIM2, LL_TIM_CLOCKSOURCE_INTERNAL);
  283. LL_TIM_DisableARRPreload(TIM2);
  284. LL_TIM_SetTriggerInput(TIM2, LL_TIM_TS_TI2FP2);
  285. LL_TIM_SetSlaveMode(TIM2, LL_TIM_SLAVEMODE_RESET);
  286. LL_TIM_SetTriggerOutput(TIM2, LL_TIM_TRGO_RESET);
  287. LL_TIM_EnableMasterSlaveMode(TIM2);
  288. LL_TIM_DisableDMAReq_TRIG(TIM2);
  289. LL_TIM_DisableIT_TRIG(TIM2);
  290. // Timer: channel 1 indirect
  291. LL_TIM_IC_SetActiveInput(TIM2, LL_TIM_CHANNEL_CH1, LL_TIM_ACTIVEINPUT_INDIRECTTI);
  292. LL_TIM_IC_SetPrescaler(TIM2, LL_TIM_CHANNEL_CH1, LL_TIM_ICPSC_DIV1);
  293. LL_TIM_IC_SetPolarity(TIM2, LL_TIM_CHANNEL_CH1, LL_TIM_IC_POLARITY_FALLING);
  294. LL_TIM_IC_SetFilter(TIM2, LL_TIM_CHANNEL_CH1, LL_TIM_IC_FILTER_FDIV1);
  295. // Timer: channel 2 direct
  296. LL_TIM_IC_SetActiveInput(TIM2, LL_TIM_CHANNEL_CH2, LL_TIM_ACTIVEINPUT_DIRECTTI);
  297. LL_TIM_IC_SetPrescaler(TIM2, LL_TIM_CHANNEL_CH2, LL_TIM_ICPSC_DIV1);
  298. LL_TIM_IC_SetPolarity(TIM2, LL_TIM_CHANNEL_CH2, LL_TIM_IC_POLARITY_RISING);
  299. LL_TIM_IC_SetFilter(TIM2, LL_TIM_CHANNEL_CH2, LL_TIM_IC_FILTER_FDIV1);
  300. // ISR setup
  301. api_hal_interrupt_set_timer_isr(TIM2, api_hal_subghz_capture_ISR);
  302. NVIC_SetPriority(TIM2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),5, 0));
  303. NVIC_EnableIRQ(TIM2_IRQn);
  304. // Interrupts and channels
  305. LL_TIM_EnableIT_CC1(TIM2);
  306. LL_TIM_EnableIT_CC2(TIM2);
  307. LL_TIM_CC_EnableChannel(TIM2, LL_TIM_CHANNEL_CH1);
  308. LL_TIM_CC_EnableChannel(TIM2, LL_TIM_CHANNEL_CH2);
  309. // Start timer
  310. LL_TIM_SetCounter(TIM2, 0);
  311. LL_TIM_EnableCounter(TIM2);
  312. // Switch to RX
  313. api_hal_subghz_rx();
  314. }
  315. void api_hal_subghz_stop_async_rx() {
  316. furi_assert(api_hal_subghz_state == SubGhzStateAsyncRx);
  317. api_hal_subghz_state = SubGhzStateIdle;
  318. // Shutdown radio
  319. api_hal_subghz_idle();
  320. LL_TIM_DeInit(TIM2);
  321. api_hal_interrupt_set_timer_isr(TIM2, NULL);
  322. hal_gpio_init(&gpio_cc1101_g0, GpioModeAnalog, GpioPullNo, GpioSpeedLow);
  323. }
  324. volatile size_t api_hal_subghz_tx_repeat = 0;
  325. static void api_hal_subghz_tx_dma_isr() {
  326. if (LL_DMA_IsActiveFlag_TC1(DMA1)) {
  327. LL_DMA_ClearFlag_TC1(DMA1);
  328. furi_assert(api_hal_subghz_state == SubGhzStateAsyncTx);
  329. if (--api_hal_subghz_tx_repeat == 0) {
  330. api_hal_subghz_state = SubGhzStateAsyncTxLast;
  331. LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_1);
  332. }
  333. }
  334. }
  335. static void api_hal_subghz_tx_timer_isr() {
  336. if(LL_TIM_IsActiveFlag_UPDATE(TIM2)) {
  337. LL_TIM_ClearFlag_UPDATE(TIM2);
  338. if (api_hal_subghz_state == SubGhzStateAsyncTxLast) {
  339. LL_TIM_DisableCounter(TIM2);
  340. api_hal_subghz_state = SubGhzStateAsyncTxEnd;
  341. }
  342. }
  343. }
  344. void api_hal_subghz_start_async_tx(uint32_t* buffer, size_t buffer_size, size_t repeat) {
  345. furi_assert(api_hal_subghz_state == SubGhzStateIdle);
  346. api_hal_subghz_state = SubGhzStateAsyncTx;
  347. api_hal_subghz_tx_repeat = repeat;
  348. // Connect CC1101_GD0 to TIM2 as output
  349. hal_gpio_init_ex(&gpio_cc1101_g0, GpioModeAltFunctionPushPull, GpioPullDown, GpioSpeedLow, GpioAltFn1TIM2);
  350. // Configure DMA
  351. LL_DMA_InitTypeDef dma_config = {0};
  352. dma_config.PeriphOrM2MSrcAddress = (uint32_t)&(TIM2->ARR);
  353. dma_config.MemoryOrM2MDstAddress = (uint32_t)buffer;
  354. dma_config.Direction = LL_DMA_DIRECTION_MEMORY_TO_PERIPH;
  355. dma_config.Mode = LL_DMA_MODE_CIRCULAR;
  356. dma_config.PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
  357. dma_config.MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT;
  358. dma_config.PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_WORD;
  359. dma_config.MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_WORD;
  360. dma_config.NbData = buffer_size / sizeof(uint32_t);
  361. dma_config.PeriphRequest = LL_DMAMUX_REQ_TIM2_UP;
  362. dma_config.Priority = LL_DMA_MODE_NORMAL;
  363. LL_DMA_Init(DMA1, LL_DMA_CHANNEL_1, &dma_config);
  364. api_hal_interrupt_set_dma_channel_isr(DMA1, LL_DMA_CHANNEL_1, api_hal_subghz_tx_dma_isr);
  365. LL_DMA_EnableIT_TC(DMA1, LL_DMA_CHANNEL_1);
  366. LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_1);
  367. // Configure TIM2
  368. LL_TIM_InitTypeDef TIM_InitStruct = {0};
  369. TIM_InitStruct.Prescaler = 64-1;
  370. TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;
  371. TIM_InitStruct.Autoreload = 1000;
  372. TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
  373. LL_TIM_Init(TIM2, &TIM_InitStruct);
  374. LL_TIM_SetClockSource(TIM2, LL_TIM_CLOCKSOURCE_INTERNAL);
  375. LL_TIM_EnableARRPreload(TIM2);
  376. // Configure TIM2 CH2
  377. LL_TIM_OC_InitTypeDef TIM_OC_InitStruct = {0};
  378. TIM_OC_InitStruct.OCMode = LL_TIM_OCMODE_TOGGLE;
  379. TIM_OC_InitStruct.OCState = LL_TIM_OCSTATE_DISABLE;
  380. TIM_OC_InitStruct.OCNState = LL_TIM_OCSTATE_DISABLE;
  381. TIM_OC_InitStruct.CompareValue = 0;
  382. TIM_OC_InitStruct.OCPolarity = LL_TIM_OCPOLARITY_HIGH;
  383. LL_TIM_OC_Init(TIM2, LL_TIM_CHANNEL_CH2, &TIM_OC_InitStruct);
  384. LL_TIM_OC_DisableFast(TIM2, LL_TIM_CHANNEL_CH2);
  385. LL_TIM_DisableMasterSlaveMode(TIM2);
  386. api_hal_interrupt_set_timer_isr(TIM2, api_hal_subghz_tx_timer_isr);
  387. LL_TIM_EnableIT_UPDATE(TIM2);
  388. LL_TIM_EnableDMAReq_UPDATE(TIM2);
  389. LL_TIM_CC_EnableChannel(TIM2, LL_TIM_CHANNEL_CH2);
  390. // Start counter
  391. LL_TIM_GenerateEvent_UPDATE(TIM2);
  392. #ifdef API_HAL_SUBGHZ_TX_GPIO
  393. hal_gpio_write(&API_HAL_SUBGHZ_TX_GPIO, true);
  394. #endif
  395. api_hal_subghz_tx();
  396. LL_TIM_SetCounter(TIM2, 0);
  397. LL_TIM_EnableCounter(TIM2);
  398. }
  399. size_t api_hal_subghz_get_async_tx_repeat_left() {
  400. return api_hal_subghz_tx_repeat;
  401. }
  402. void api_hal_subghz_wait_async_tx() {
  403. while(api_hal_subghz_state != SubGhzStateAsyncTxEnd) osDelay(1);
  404. }
  405. void api_hal_subghz_stop_async_tx() {
  406. furi_assert(
  407. api_hal_subghz_state == SubGhzStateAsyncTx
  408. || api_hal_subghz_state == SubGhzStateAsyncTxLast
  409. || api_hal_subghz_state == SubGhzStateAsyncTxEnd
  410. );
  411. // Shutdown radio
  412. api_hal_subghz_idle();
  413. #ifdef API_HAL_SUBGHZ_TX_GPIO
  414. hal_gpio_write(&API_HAL_SUBGHZ_TX_GPIO, false);
  415. #endif
  416. // Deinitialize Timer
  417. LL_TIM_DeInit(TIM2);
  418. api_hal_interrupt_set_timer_isr(TIM2, NULL);
  419. // Deinitialize DMA
  420. LL_DMA_DeInit(DMA1, LL_DMA_CHANNEL_1);
  421. api_hal_interrupt_set_dma_channel_isr(DMA1, LL_DMA_CHANNEL_1, NULL);
  422. // Deinitialize GPIO
  423. hal_gpio_init(&gpio_cc1101_g0, GpioModeAnalog, GpioPullNo, GpioSpeedLow);
  424. api_hal_subghz_state = SubGhzStateIdle;
  425. }