cc1101-workaround.cpp 19 KB

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  1. #include "cc1101.h"
  2. #include <furi.h>
  3. #include <gui/gui.h>
  4. #include <input/input.h>
  5. #define RSSI_DELAY 5000 //rssi delay in micro second
  6. #define CHAN_SPA 0.05 // channel spacing
  7. int16_t rssi_to_dbm(uint8_t rssi_dec, uint8_t rssiOffset) {
  8. int16_t rssi;
  9. if(rssi_dec >= 128) {
  10. rssi = (int16_t)((int16_t)(rssi_dec - 256) / 2) - rssiOffset;
  11. } else {
  12. rssi = (rssi_dec / 2) - rssiOffset;
  13. }
  14. return rssi;
  15. }
  16. typedef struct {
  17. float base_freq;
  18. uint8_t reg[3]; // FREQ2, FREQ1, FREQ0
  19. uint8_t first_channel;
  20. uint8_t last_channel;
  21. uint8_t rssi_offset;
  22. } Band;
  23. typedef struct {
  24. const Band* band;
  25. uint16_t channel;
  26. } FreqConfig;
  27. void setup_freq(CC1101* cc1101, float freq) {
  28. // cc1101->SpiWriteReg(CC1101_MCSM0, 0x08); // disalbe FS_AUTOCAL
  29. // cc1101->SpiWriteReg(CC1101_AGCCTRL2, 0x43 | 0x0C); // MAX_DVGA_GAIN to 11 for fast rssi
  30. // cc1101->SpiWriteReg(CC1101_AGCCTRL0, 0xB0); // max AGC WAIT_TIME; 0 filter_length
  31. // cc1101->SetMod(GFSK); // set to GFSK for fast rssi measurement | +8 is dcfilter off
  32. uint32_t freq_reg = freq * 1e6 / (F_OSC / 65536);
  33. cc1101->SetFreq((freq_reg >> 16) & 0xFF, (freq_reg >> 8) & 0xFF, (freq_reg)&0xFF);
  34. cc1101->SetChannel(0);
  35. /*
  36. //set test0 to 0x09
  37. cc1101->SpiWriteReg(CC1101_TEST0, 0x09);
  38. //set FSCAL2 to 0x2A to force VCO HIGH
  39. cc1101->SpiWriteReg(CC1101_FSCAL2, 0x2A);
  40. // perform a manual calibration by issuing SCAL command
  41. cc1101->SpiStrobe(CC1101_SCAL);
  42. */
  43. }
  44. static GpioPin debug_0 = {GPIOB, GPIO_PIN_2};
  45. int16_t rx_rssi(CC1101* cc1101, const FreqConfig* config) {
  46. // cc1101->SpiStrobe(CC1101_SFRX);
  47. // cc1101->SetReceive();
  48. // uint8_t begin_size = cc1101->SpiReadStatus(CC1101_RXBYTES);
  49. // uint8_t rx_status = cc1101->SpiReadStatus(CC1101_MARCSTATE);
  50. // delay_us(RSSI_DELAY);
  51. // osDelay(15);
  52. // uint8_t end_size = cc1101->SpiReadStatus(CC1101_RXBYTES);
  53. // 1.4.8) read PKTSTATUS register while the radio is in RX state
  54. /*uint8_t _pkt_status = */ // cc1101->SpiReadStatus(CC1101_PKTSTATUS);
  55. // 1.4.9) enter IDLE state by issuing a SIDLE command
  56. // cc1101->SpiStrobe(CC1101_SIDLE);
  57. // //read rssi value and converto to dBm form
  58. uint8_t rssi_dec = (uint8_t)cc1101->SpiReadStatus(CC1101_RSSI);
  59. int16_t rssi_dBm = rssi_to_dbm(rssi_dec, config->band->rssi_offset);
  60. /*
  61. char buf[256];
  62. sprintf(buf, "status: %d -> %d, rssi: %d\n", rx_status, cc1101->SpiReadStatus(CC1101_MARCSTATE), rssi_dBm);
  63. printf(buf);
  64. sprintf(buf, "begin: %d, end: %d\n", begin_size, end_size);
  65. printf(buf);
  66. */
  67. // uint8_t rx_data[64];
  68. // uint8_t fifo_length = end_size - begin_size;
  69. /*
  70. if(fifo_length < 64) {
  71. // cc1101->SpiReadBurstReg(CC1101_RXFIFO, rx_data, fifo_length);
  72. *
  73. printf("FIFO:");
  74. for(uint8_t i = 0; i < fifo_length; i++) {
  75. for(uint8_t bit = 0; bit < 8; bit++) {
  76. printf("%s", (rx_data[i] & (1 << bit)) > 0 ? "1" : "0");
  77. }
  78. printf(" ");
  79. }
  80. printf("\r\n");
  81. *
  82. for(uint8_t i = 0; i < fifo_length; i++) {
  83. for(uint8_t bit = 0; bit < 8; bit++) {
  84. gpio_write((GpioPin*)&debug_0, (rx_data[i] & (1 << bit)) > 0);
  85. delay_us(5);
  86. }
  87. }
  88. } else {
  89. printf("fifo size over\r\n");
  90. }
  91. */
  92. return rssi_dBm;
  93. }
  94. /*
  95. void flp_config(CC1101* cc1101) {
  96. cc1101->SpiWriteReg(
  97. CC1101_MCSM0, 0x18); // calibrate when going from IDLE to RX or TX ; 149 - 155 μs timeout
  98. // MCSM0.FS_AUTOCAL[1:0] = 1
  99. cc1101->SpiWriteReg(CC1101_AGCCTRL2, 0x43);
  100. cc1101->SpiWriteReg(CC1101_AGCCTRL1, 0x49);
  101. cc1101->SpiWriteReg(CC1101_AGCCTRL0, 0x91);
  102. //freq synthesizer calibration
  103. cc1101->SpiWriteReg(CC1101_FSCAL3, 0xEA);
  104. cc1101->SpiWriteReg(CC1101_FSCAL2, 0x2A);
  105. cc1101->SpiWriteReg(CC1101_FSCAL1, 0x00);
  106. cc1101->SpiWriteReg(CC1101_FSCAL0, 0x1F);
  107. // async data out
  108. cc1101->SpiSetRegValue(CC1101_IOCFG0, 13, 5, 0); // GDO0 Output Pin Configuration
  109. cc1101->SpiSetRegValue(CC1101_IOCFG0, 13, 5, 0); // WAT
  110. // FIFOTHR.ADC_RETENTION = 1
  111. cc1101->SpiSetRegValue(CC1101_FIFOTHR, 1, 6, 6);
  112. // PKTCTRL1.APPEND_STATUS = 0
  113. cc1101->SpiSetRegValue(CC1101_PKTCTRL1, 0, 2, 2);
  114. // PKTCTRL0.WHITE_DATA = 0
  115. cc1101->SpiSetRegValue(CC1101_PKTCTRL0, 0, 6, 6);
  116. // PKTCTRL0.LENGTH_CONFIG = 2 // Infinite packet length mode
  117. cc1101->SpiSetRegValue(CC1101_PKTCTRL0, 2, 1, 0);
  118. // PKTCTRL0.CRC_EN = 0
  119. cc1101->SpiSetRegValue(CC1101_PKTCTRL0, 0, 2, 2);
  120. // PKTCTRL0.PKT_FORMAT = 3
  121. cc1101->SpiSetRegValue(CC1101_PKTCTRL0, 3, 5, 4);
  122. // bandwidth 50-100 kHz
  123. if(!cc1101->setRxBandwidth(75.0)) {
  124. printf("wrong rx bw\r\n");
  125. }
  126. // datarate ~30 kbps
  127. if(!cc1101->setBitRate(100.)) {
  128. printf("wrong bitrate\r\n");
  129. }
  130. // mod
  131. // MDMCFG2.MOD_FORMAT = 3 (3: OOK, 0: 2-FSK)
  132. cc1101->SpiSetRegValue(CC1101_MDMCFG2, 3, 6, 4);
  133. // MDMCFG2.SYNC_MODE = 0
  134. cc1101->SpiSetRegValue(CC1101_MDMCFG2, 0, 2, 0);
  135. }
  136. */
  137. void tx_config(CC1101* cc1101) {
  138. // cc1101->SpiWriteReg(CC1101_IOCFG2,0x0B); //GDO2 Output Pin Configuration
  139. // cc1101->SpiWriteReg(CC1101_IOCFG0,0x0C); //GDO0 Output Pin Configuration
  140. cc1101->SpiSetRegValue(CC1101_IOCFG0, 13, 5, 0); // GDO0 Output Pin Configuration
  141. cc1101->SpiWriteReg(CC1101_FIFOTHR, 0x47); //RX FIFO and TX FIFO Thresholds
  142. cc1101->SpiWriteReg(CC1101_PKTCTRL0, 0x32); //Packet Automation Control
  143. cc1101->SpiWriteReg(CC1101_FSCTRL1, 0x06); //Frequency Synthesizer Control
  144. cc1101->SpiWriteReg(CC1101_FREQ2, 0x10); //Frequency Control Word, High Byte
  145. cc1101->SpiWriteReg(CC1101_FREQ1, 0xB0); //Frequency Control Word, Middle Byte
  146. cc1101->SpiWriteReg(CC1101_FREQ0, 0x71); //Frequency Control Word, Low Byte
  147. cc1101->SpiWriteReg(CC1101_MDMCFG4, 0x6A); //Modem Configuration
  148. cc1101->SpiWriteReg(CC1101_MDMCFG3, 0x2E); //Modem Configuration
  149. cc1101->SpiWriteReg(CC1101_MDMCFG2, 0x30); //Modem Configuration
  150. cc1101->SpiWriteReg(CC1101_DEVIATN, 0x15); //Modem Deviation Setting
  151. cc1101->SpiWriteReg(CC1101_MCSM0, 0x18); //Main Radio Control State Machine Configuration
  152. cc1101->SpiWriteReg(CC1101_FOCCFG, 0x16); //Frequency Offset Compensation Configuration
  153. cc1101->SpiWriteReg(CC1101_WORCTRL, 0xFB); //Wake On Radio Control
  154. cc1101->SpiWriteReg(CC1101_FREND0, 0x11); //Front End TX Configuration
  155. cc1101->SpiWriteReg(CC1101_FSCAL3, 0xE9); //Frequency Synthesizer Calibration
  156. cc1101->SpiWriteReg(CC1101_FSCAL2, 0x2A); //Frequency Synthesizer Calibration
  157. cc1101->SpiWriteReg(CC1101_FSCAL1, 0x00); //Frequency Synthesizer Calibration
  158. cc1101->SpiWriteReg(CC1101_FSCAL0, 0x1F); //Frequency Synthesizer Calibration
  159. /*
  160. cc1101->SpiWriteReg(CC1101_TEST2, 0x81); //Various Test Settings
  161. cc1101->SpiWriteReg(CC1101_TEST1, 0x35); //Various Test Settings
  162. cc1101->SpiWriteReg(CC1101_TEST0, 0x09); //Various Test Settings
  163. */
  164. }
  165. // f = (f_osc/65536) * (FREQ + CHAN * (256 + CH_SP_M) * 2^(CH_SP_E - 2))
  166. // FREQ = f / (f_osc/65536)
  167. // CHAN = 0
  168. // TODO: CHAN number not implemented!
  169. // TODO: reg values not affetcts
  170. const Band bands[] = {
  171. {300., {0x00, 0x00, 0x00}, 0, 255, 74},
  172. {315., {0x00, 0x00, 0x00}, 0, 255, 74},
  173. {348., {0x00, 0x00, 0x00}, 0, 255, 74},
  174. {386., {0x00, 0x00, 0x00}, 0, 255, 74},
  175. {433.92, {0x00, 0x00, 0x00}, 0, 255, 74},
  176. {438.9, {0x00, 0x00, 0x00}, 0, 255, 74},
  177. {464., {0x00, 0x00, 0x00}, 0, 255, 74},
  178. {779., {0x00, 0x00, 0x00}, 0, 255, 74},
  179. {868., {0x00, 0x00, 0x00}, 0, 255, 74},
  180. {915., {0x00, 0x00, 0x00}, 0, 255, 74},
  181. {928., {0x00, 0x00, 0x00}, 0, 255, 74},
  182. };
  183. const FreqConfig FREQ_LIST[] = {
  184. {&bands[0], 0},
  185. {&bands[1], 0},
  186. {&bands[2], 0},
  187. {&bands[3], 0},
  188. {&bands[4], 0},
  189. {&bands[5], 0},
  190. {&bands[6], 0},
  191. {&bands[7], 0},
  192. {&bands[8], 0},
  193. {&bands[9], 0},
  194. {&bands[10], 0},
  195. };
  196. extern "C" void cc1101_isr(void* _pin, void* _ctx) {
  197. uint32_t pin = (uint32_t)_pin;
  198. if(pin == CC1101_G0_Pin) {
  199. gpio_write((GpioPin*)&debug_0, gpio_read(&cc1101_g0_gpio));
  200. }
  201. }
  202. typedef enum {
  203. EventTypeTick,
  204. EventTypeKey,
  205. } EventType;
  206. typedef struct {
  207. union {
  208. InputEvent input;
  209. } value;
  210. EventType type;
  211. } AppEvent;
  212. typedef enum { ModeRx, ModeTx } Mode;
  213. typedef struct {
  214. int16_t dbm;
  215. uint8_t reg;
  216. } TxLevel;
  217. const TxLevel TX_LEVELS[] = {
  218. {-10, 0},
  219. {-5, 0},
  220. {0, 0},
  221. {5, 0},
  222. };
  223. typedef struct {
  224. Mode mode;
  225. size_t active_freq_idx;
  226. float active_freq;
  227. int16_t last_rssi;
  228. size_t tx_level;
  229. bool need_cc1101_conf;
  230. } State;
  231. static void render_callback(Canvas* canvas, void* ctx) {
  232. State* state = (State*)acquire_mutex((ValueMutex*)ctx, 25);
  233. if(!state) return;
  234. canvas_clear(canvas);
  235. canvas_set_color(canvas, ColorBlack);
  236. canvas_set_font(canvas, FontPrimary);
  237. canvas_draw_str(canvas, 2, 12, "cc1101 workaround");
  238. {
  239. char buf[24];
  240. sprintf(
  241. buf,
  242. "freq: %ld.%02ld MHz",
  243. (uint32_t)state->active_freq,
  244. (uint32_t)(state->active_freq * 100.) % 100);
  245. canvas_set_font(canvas, FontSecondary);
  246. canvas_draw_str(canvas, 2, 25, buf);
  247. }
  248. {
  249. canvas_set_font(canvas, FontSecondary);
  250. if(state->need_cc1101_conf) {
  251. canvas_draw_str(canvas, 2, 36, "mode: configuring...");
  252. } else if(state->mode == ModeRx) {
  253. canvas_draw_str(canvas, 2, 36, "mode: RX");
  254. } else if(state->mode == ModeTx) {
  255. canvas_draw_str(canvas, 2, 36, "mode: TX");
  256. } else {
  257. canvas_draw_str(canvas, 2, 36, "mode: unknown");
  258. }
  259. }
  260. {
  261. if(!state->need_cc1101_conf && state->mode == ModeRx) {
  262. char buf[24];
  263. sprintf(buf, "RSSI: %d dBm", state->last_rssi);
  264. canvas_set_font(canvas, FontSecondary);
  265. canvas_draw_str(canvas, 2, 48, buf);
  266. }
  267. }
  268. {
  269. char buf[24];
  270. sprintf(buf, "tx level: %d dBm", TX_LEVELS[state->tx_level].dbm);
  271. canvas_set_font(canvas, FontSecondary);
  272. canvas_draw_str(canvas, 2, 63, buf);
  273. }
  274. release_mutex((ValueMutex*)ctx, state);
  275. }
  276. static void input_callback(InputEvent* input_event, void* ctx) {
  277. osMessageQueueId_t event_queue = ctx;
  278. AppEvent event;
  279. event.type = EventTypeKey;
  280. event.value.input = *input_event;
  281. osMessageQueuePut(event_queue, &event, 0, 0);
  282. }
  283. extern "C" void cc1101_workaround(void* p) {
  284. osMessageQueueId_t event_queue = osMessageQueueNew(8, sizeof(AppEvent), NULL);
  285. furi_check(event_queue);
  286. State _state;
  287. _state.mode = ModeRx;
  288. _state.active_freq_idx = 4;
  289. FreqConfig conf = FREQ_LIST[_state.active_freq_idx];
  290. _state.active_freq = conf.band->base_freq + CHAN_SPA * conf.channel;
  291. _state.need_cc1101_conf = true;
  292. _state.last_rssi = 0;
  293. _state.tx_level = 0;
  294. ValueMutex state_mutex;
  295. if(!init_mutex(&state_mutex, &_state, sizeof(State))) {
  296. printf("[cc1101] cannot create mutex\r\n");
  297. furiac_exit(NULL);
  298. }
  299. ViewPort* view_port = view_port_alloc();
  300. view_port_draw_callback_set(view_port, render_callback, &state_mutex);
  301. view_port_input_callback_set(view_port, input_callback, event_queue);
  302. // Open GUI and register view_port
  303. Gui* gui = (Gui*)furi_record_open("gui");
  304. if(gui == NULL) {
  305. printf("[cc1101] gui is not available\r\n");
  306. furiac_exit(NULL);
  307. }
  308. gui_add_view_port(gui, view_port, GuiLayerFullscreen);
  309. gpio_init(&debug_0, GpioModeOutputPushPull);
  310. gpio_write((GpioPin*)&debug_0, false);
  311. printf("[cc1101] creating device\r\n");
  312. GpioPin cs_pin = {CC1101_CS_GPIO_Port, CC1101_CS_Pin};
  313. gpio_init(&cc1101_g0_gpio, GpioModeInput);
  314. api_interrupt_add(cc1101_isr, InterruptTypeExternalInterrupt, NULL);
  315. // TODO open record
  316. GpioPin* cs_pin_record = &cs_pin;
  317. CC1101 cc1101(cs_pin_record);
  318. printf("[cc1101] init device\r\n");
  319. uint8_t address = cc1101.Init();
  320. if(address > 0) {
  321. printf("[cc1101] init done: %d\r\n", address);
  322. } else {
  323. printf("[cc1101] init fail\r\n");
  324. furiac_exit(NULL);
  325. }
  326. cc1101.SpiStrobe(CC1101_SIDLE);
  327. // flp_config(&cc1101);
  328. tx_config(&cc1101);
  329. // setup_freq(&cc1101, &FREQ_LIST[4]);
  330. // enable_cc1101_irq();
  331. printf("init ok\r\n");
  332. // TODO open record
  333. GpioPin* led_record = (GpioPin*)&led_gpio[1];
  334. // configure pin
  335. gpio_init(led_record, GpioModeOutputOpenDrain);
  336. const int16_t RSSI_THRESHOLD = -60;
  337. // setup_freq(&cc1101, &FREQ_LIST[1]);
  338. cc1101.SetReceive();
  339. AppEvent event;
  340. while(1) {
  341. osStatus_t event_status = osMessageQueueGet(event_queue, &event, NULL, 100);
  342. State* state = (State*)acquire_mutex_block(&state_mutex);
  343. if(event_status == osOK) {
  344. if(event.type == EventTypeKey) {
  345. if(event.value.input.type == InputTypeShort &&
  346. event.value.input.key == InputKeyBack) {
  347. printf("[cc1101] bye!\r\n");
  348. cc1101.SpiStrobe(CC1101_SIDLE);
  349. cc1101.SpiStrobe(CC1101_SPWD);
  350. printf("[cc1101] go to power down\r\n");
  351. // TODO remove all view_ports create by app
  352. view_port_enabled_set(view_port, false);
  353. furiac_exit(NULL);
  354. }
  355. if(event.value.input.type == InputTypeShort &&
  356. event.value.input.key == InputKeyDown) {
  357. if(state->active_freq_idx > 0) {
  358. state->active_freq_idx--;
  359. }
  360. FreqConfig conf = FREQ_LIST[state->active_freq_idx];
  361. state->active_freq = conf.band->base_freq + CHAN_SPA * conf.channel;
  362. state->need_cc1101_conf = true;
  363. }
  364. if(event.value.input.type == InputTypeShort &&
  365. event.value.input.key == InputKeyUp) {
  366. if(state->active_freq_idx < (sizeof(FREQ_LIST) / sizeof(FREQ_LIST[0]) - 1)) {
  367. state->active_freq_idx++;
  368. }
  369. FreqConfig conf = FREQ_LIST[state->active_freq_idx];
  370. state->active_freq = conf.band->base_freq + CHAN_SPA * conf.channel;
  371. state->need_cc1101_conf = true;
  372. }
  373. if(event.value.input.type == InputTypeShort &&
  374. event.value.input.key == InputKeyRight) {
  375. /*
  376. if(state->tx_level < (sizeof(TX_LEVELS) / sizeof(TX_LEVELS[0]) - 1)) {
  377. state->tx_level++;
  378. } else {
  379. state->tx_level = 0;
  380. }
  381. */
  382. state->active_freq += 0.25;
  383. state->need_cc1101_conf = true;
  384. }
  385. if(event.value.input.type == InputTypeShort &&
  386. event.value.input.key == InputKeyLeft) {
  387. /*
  388. if(state->tx_level < (sizeof(TX_LEVELS) / sizeof(TX_LEVELS[0]) - 1)) {
  389. state->tx_level++;
  390. } else {
  391. state->tx_level = 0;
  392. }
  393. */
  394. state->active_freq -= 0.25;
  395. state->need_cc1101_conf = true;
  396. }
  397. if(event.value.input.key == InputKeyOk) {
  398. if(event.value.input.type == InputTypePress) {
  399. state->mode = ModeTx;
  400. state->need_cc1101_conf = true;
  401. } else if(event.value.input.type == InputTypeRelease) {
  402. state->mode = ModeRx;
  403. state->need_cc1101_conf = true;
  404. }
  405. }
  406. }
  407. } else {
  408. }
  409. if(state->need_cc1101_conf) {
  410. if(state->mode == ModeRx) {
  411. cc1101.SpiStrobe(CC1101_SIDLE);
  412. gpio_init(&cc1101_g0_gpio, GpioModeInput);
  413. setup_freq(&cc1101, state->active_freq);
  414. cc1101.SetReceive();
  415. state->last_rssi = rx_rssi(&cc1101, &FREQ_LIST[state->active_freq_idx]);
  416. } else if(state->mode == ModeTx) {
  417. cc1101.SpiStrobe(CC1101_SIDLE);
  418. setup_freq(&cc1101, state->active_freq);
  419. cc1101.SetTransmit();
  420. gpio_init(&cc1101_g0_gpio, GpioModeOutputPushPull);
  421. gpio_write(&cc1101_g0_gpio, false);
  422. }
  423. state->need_cc1101_conf = false;
  424. }
  425. if(!state->need_cc1101_conf && state->mode == ModeRx) {
  426. // TOOD what about rssi offset
  427. state->last_rssi = rx_rssi(&cc1101, &FREQ_LIST[state->active_freq_idx]);
  428. gpio_write(led_record, state->last_rssi < RSSI_THRESHOLD);
  429. } else if(!state->need_cc1101_conf && state->mode == ModeTx) {
  430. /*
  431. const uint8_t data = 0xA5;
  432. for(uint8_t i = 0; i < 8; i++) {
  433. gpio_write(&cc1101_g0_gpio, (data & (1 << i)) > 0);
  434. osDelay(1);
  435. }
  436. gpio_write(&cc1101_g0_gpio, false);
  437. */
  438. /*
  439. // BELL UDB-Q022-0000
  440. const uint16_t HALF_PERIOD = 500;
  441. for(uint8_t n = 0; n < 4; n++) {
  442. for(uint8_t i = 0; i < 4; i++) {
  443. gpio_write(&cc1101_g0_gpio, true);
  444. delay_us(3 * HALF_PERIOD);
  445. gpio_write(&cc1101_g0_gpio, false);
  446. delay_us(HALF_PERIOD);
  447. }
  448. for(uint8_t i = 0; i < 40; i++) {
  449. gpio_write(&cc1101_g0_gpio, true);
  450. delay_us(HALF_PERIOD);
  451. gpio_write(&cc1101_g0_gpio, false);
  452. delay_us(HALF_PERIOD);
  453. }
  454. }
  455. */
  456. // BELL ERA C61, static code
  457. const uint16_t ONE_ON = 150;
  458. const uint16_t ONE_OFF = 400;
  459. const uint16_t ZERO_ON = 420;
  460. const uint16_t ZERO_OFF = 130;
  461. const bool SEQ[] = {true, true, false, false, true, false, true, false, true,
  462. false, true, true, true, false, true, false, true, true,
  463. true, true, true, false, true, false, true};
  464. for(uint8_t n = 0; n < 10; n++) {
  465. for(uint8_t i = 0; i < sizeof(SEQ) / sizeof(SEQ[0]); i++) {
  466. if(SEQ[i]) {
  467. gpio_write(&cc1101_g0_gpio, false);
  468. delay_us(ONE_ON);
  469. gpio_write(&cc1101_g0_gpio, true);
  470. delay_us(ONE_OFF);
  471. } else {
  472. gpio_write(&cc1101_g0_gpio, false);
  473. delay_us(ZERO_ON);
  474. gpio_write(&cc1101_g0_gpio, true);
  475. delay_us(ZERO_OFF);
  476. }
  477. }
  478. osDelay(4);
  479. }
  480. gpio_write(&cc1101_g0_gpio, false);
  481. }
  482. release_mutex(&state_mutex, state);
  483. view_port_update(view_port);
  484. }
  485. }