api-hal-subghz.c 18 KB

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  1. #include "api-hal-subghz.h"
  2. #include <api-hal-gpio.h>
  3. #include <api-hal-spi.h>
  4. #include <api-hal-interrupt.h>
  5. #include <api-hal-resources.h>
  6. #include <furi.h>
  7. #include <cc1101.h>
  8. #include <stdio.h>
  9. static volatile SubGhzState api_hal_subghz_state = SubGhzStateInit;
  10. static const uint8_t api_hal_subghz_preset_ook_async_regs[][2] = {
  11. /* Base setting */
  12. { CC1101_IOCFG0, 0x0D }, // GD0 as async serial data output/input
  13. { CC1101_MCSM0, 0x18 }, // Autocalibrate on idle to TRX, ~150us OSC guard time
  14. /* Async OOK Specific things */
  15. { CC1101_MDMCFG2, 0x30 }, // ASK/OOK, No preamble/sync
  16. { CC1101_PKTCTRL0, 0x32 }, // Async, no CRC, Infinite
  17. { CC1101_FREND0, 0x01 }, // OOK/ASK PATABLE
  18. /* End */
  19. { 0, 0 },
  20. };
  21. static const uint8_t api_hal_subghz_preset_ook_async_patable[8] = {
  22. 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  23. };
  24. static const uint8_t api_hal_subghz_preset_mp_regs[][2] = {
  25. { CC1101_IOCFG0, 0x0D },
  26. { CC1101_FIFOTHR, 0x07 },
  27. { CC1101_PKTCTRL0, 0x32 },
  28. //{ CC1101_FSCTRL1, 0x0E },
  29. { CC1101_FSCTRL1, 0x06 },
  30. { CC1101_FREQ2, 0x10 },
  31. { CC1101_FREQ1, 0xB0 },
  32. { CC1101_FREQ0, 0x7F },
  33. { CC1101_MDMCFG4, 0x17 },
  34. { CC1101_MDMCFG3, 0x32 },
  35. { CC1101_MDMCFG2, 0x30 }, //<---OOK/ASK
  36. { CC1101_MDMCFG1, 0x23 },
  37. { CC1101_MDMCFG0, 0xF8 },
  38. { CC1101_MCSM0, 0x18 },
  39. { CC1101_FOCCFG, 0x18 },
  40. { CC1101_AGCTRL2, 0x07 },
  41. { CC1101_AGCTRL1, 0x00 },
  42. { CC1101_AGCTRL0, 0x91 },
  43. { CC1101_WORCTRL, 0xFB },
  44. { CC1101_FREND1, 0xB6 },
  45. //{ CC1101_FREND0, 0x11 },
  46. { CC1101_FREND0, 0x01 },
  47. { CC1101_FSCAL3, 0xE9 },
  48. { CC1101_FSCAL2, 0x2A },
  49. { CC1101_FSCAL1, 0x00 },
  50. { CC1101_FSCAL0, 0x1F },
  51. { CC1101_TEST2, 0x88 },
  52. { CC1101_TEST1, 0x31 },
  53. { CC1101_TEST0, 0x09 },
  54. /* End */
  55. { 0, 0 },
  56. };
  57. static const uint8_t api_hal_subghz_preset_mp_patable[8] = {
  58. 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  59. };
  60. static const uint8_t api_hal_subghz_preset_2fsk_packet_regs[][2] = {
  61. /* Base setting */
  62. { CC1101_IOCFG0, 0x06 }, // GD0 as async serial data output/input
  63. { CC1101_MCSM0, 0x18 }, // Autocalibrate on idle to TRX, ~150us OSC guard time
  64. /* Magic */
  65. { CC1101_TEST2, 0x81},
  66. { CC1101_TEST1, 0x35},
  67. { CC1101_TEST0, 0x09},
  68. /* End */
  69. { 0, 0 },
  70. };
  71. static const uint8_t api_hal_subghz_preset_2fsk_packet_patable[8] = {
  72. 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  73. };
  74. void api_hal_subghz_init() {
  75. furi_assert(api_hal_subghz_state == SubGhzStateInit);
  76. api_hal_subghz_state = SubGhzStateIdle;
  77. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  78. #ifdef API_HAL_SUBGHZ_TX_GPIO
  79. hal_gpio_init(&API_HAL_SUBGHZ_TX_GPIO, GpioModeOutputPushPull, GpioPullNo, GpioSpeedLow);
  80. #endif
  81. // Reset
  82. hal_gpio_init(&gpio_cc1101_g0, GpioModeAnalog, GpioPullNo, GpioSpeedLow);
  83. cc1101_reset(device);
  84. cc1101_write_reg(device, CC1101_IOCFG0, CC1101IocfgHighImpedance);
  85. // Prepare GD0 for power on self test
  86. hal_gpio_init(&gpio_cc1101_g0, GpioModeInput, GpioPullNo, GpioSpeedLow);
  87. // GD0 low
  88. cc1101_write_reg(device, CC1101_IOCFG0, CC1101IocfgHW);
  89. while(hal_gpio_read(&gpio_cc1101_g0) != false);
  90. // GD0 high
  91. cc1101_write_reg(device, CC1101_IOCFG0, CC1101IocfgHW | CC1101_IOCFG_INV);
  92. while(hal_gpio_read(&gpio_cc1101_g0) != true);
  93. // Reset GD0 to floating state
  94. cc1101_write_reg(device, CC1101_IOCFG0, CC1101IocfgHighImpedance);
  95. hal_gpio_init(&gpio_cc1101_g0, GpioModeAnalog, GpioPullNo, GpioSpeedLow);
  96. // RF switches
  97. hal_gpio_init(&gpio_rf_sw_0, GpioModeOutputPushPull, GpioPullNo, GpioSpeedLow);
  98. cc1101_write_reg(device, CC1101_IOCFG2, CC1101IocfgHW);
  99. // Go to sleep
  100. cc1101_shutdown(device);
  101. api_hal_spi_device_return(device);
  102. }
  103. void api_hal_subghz_sleep() {
  104. furi_assert(api_hal_subghz_state == SubGhzStateIdle);
  105. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  106. cc1101_switch_to_idle(device);
  107. cc1101_write_reg(device, CC1101_IOCFG0, CC1101IocfgHighImpedance);
  108. hal_gpio_init(&gpio_cc1101_g0, GpioModeAnalog, GpioPullNo, GpioSpeedLow);
  109. cc1101_shutdown(device);
  110. api_hal_spi_device_return(device);
  111. }
  112. void api_hal_subghz_dump_state() {
  113. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  114. printf(
  115. "[api_hal_subghz] cc1101 chip %d, version %d\r\n",
  116. cc1101_get_partnumber(device),
  117. cc1101_get_version(device)
  118. );
  119. api_hal_spi_device_return(device);
  120. }
  121. void api_hal_subghz_load_preset(ApiHalSubGhzPreset preset) {
  122. if(preset == ApiHalSubGhzPresetOokAsync) {
  123. api_hal_subghz_load_registers(api_hal_subghz_preset_ook_async_regs);
  124. api_hal_subghz_load_patable(api_hal_subghz_preset_ook_async_patable);
  125. } else if(preset == ApiHalSubGhzPreset2FskPacket) {
  126. api_hal_subghz_load_registers(api_hal_subghz_preset_2fsk_packet_regs);
  127. api_hal_subghz_load_patable(api_hal_subghz_preset_2fsk_packet_patable);
  128. } else if(preset == ApiHalSubGhzPresetMP) {
  129. api_hal_subghz_load_registers(api_hal_subghz_preset_mp_regs);
  130. api_hal_subghz_load_patable(api_hal_subghz_preset_mp_patable);
  131. }
  132. }
  133. uint8_t api_hal_subghz_get_status() {
  134. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  135. CC1101StatusRaw st;
  136. st.status = cc1101_get_status(device);
  137. api_hal_spi_device_return(device);
  138. return st.status_raw;
  139. }
  140. void api_hal_subghz_load_registers(const uint8_t data[][2]) {
  141. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  142. cc1101_reset(device);
  143. uint32_t i = 0;
  144. while (data[i][0]) {
  145. cc1101_write_reg(device, data[i][0], data[i][1]);
  146. i++;
  147. }
  148. api_hal_spi_device_return(device);
  149. }
  150. void api_hal_subghz_load_patable(const uint8_t data[8]) {
  151. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  152. cc1101_set_pa_table(device, data);
  153. api_hal_spi_device_return(device);
  154. }
  155. void api_hal_subghz_write_packet(const uint8_t* data, uint8_t size) {
  156. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  157. cc1101_flush_tx(device);
  158. cc1101_write_fifo(device, data, size);
  159. api_hal_spi_device_return(device);
  160. }
  161. void api_hal_subghz_flush_rx() {
  162. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  163. cc1101_flush_rx(device);
  164. api_hal_spi_device_return(device);
  165. }
  166. void api_hal_subghz_read_packet(uint8_t* data, uint8_t* size) {
  167. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  168. cc1101_read_fifo(device, data, size);
  169. api_hal_spi_device_return(device);
  170. }
  171. void api_hal_subghz_shutdown() {
  172. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  173. // Reset and shutdown
  174. cc1101_shutdown(device);
  175. api_hal_spi_device_return(device);
  176. }
  177. void api_hal_subghz_reset() {
  178. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  179. hal_gpio_init(&gpio_cc1101_g0, GpioModeAnalog, GpioPullNo, GpioSpeedLow);
  180. cc1101_switch_to_idle(device);
  181. cc1101_reset(device);
  182. cc1101_write_reg(device, CC1101_IOCFG0, CC1101IocfgHighImpedance);
  183. api_hal_spi_device_return(device);
  184. }
  185. void api_hal_subghz_idle() {
  186. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  187. cc1101_switch_to_idle(device);
  188. api_hal_spi_device_return(device);
  189. }
  190. void api_hal_subghz_rx() {
  191. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  192. cc1101_switch_to_rx(device);
  193. api_hal_spi_device_return(device);
  194. }
  195. void api_hal_subghz_tx() {
  196. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  197. cc1101_switch_to_tx(device);
  198. api_hal_spi_device_return(device);
  199. }
  200. float api_hal_subghz_get_rssi() {
  201. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  202. int32_t rssi_dec = cc1101_get_rssi(device);
  203. api_hal_spi_device_return(device);
  204. float rssi = rssi_dec;
  205. if(rssi_dec >= 128) {
  206. rssi = ((rssi - 256.0f) / 2.0f) - 74.0f;
  207. } else {
  208. rssi = (rssi / 2.0f) - 74.0f;
  209. }
  210. return rssi;
  211. }
  212. uint32_t api_hal_subghz_set_frequency_and_path(uint32_t value) {
  213. value = api_hal_subghz_set_frequency(value);
  214. if(value >= 300000000 && value <= 348000335) {
  215. api_hal_subghz_set_path(ApiHalSubGhzPath315);
  216. } else if(value >= 387000000 && value <= 464000000) {
  217. api_hal_subghz_set_path(ApiHalSubGhzPath433);
  218. } else if(value >= 779000000 && value <= 928000000) {
  219. api_hal_subghz_set_path(ApiHalSubGhzPath868);
  220. } else {
  221. furi_check(0);
  222. }
  223. return value;
  224. }
  225. uint32_t api_hal_subghz_set_frequency(uint32_t value) {
  226. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  227. // Compensate rounding
  228. if (value % cc1101_get_frequency_step(device) > (cc1101_get_frequency_step(device) / 2)) {
  229. value += cc1101_get_frequency_step(device);
  230. }
  231. uint32_t real_frequency = cc1101_set_frequency(device, value);
  232. cc1101_calibrate(device);
  233. api_hal_spi_device_return(device);
  234. return real_frequency;
  235. }
  236. void api_hal_subghz_set_path(ApiHalSubGhzPath path) {
  237. const ApiHalSpiDevice* device = api_hal_spi_device_get(ApiHalSpiDeviceIdSubGhz);
  238. if (path == ApiHalSubGhzPath433) {
  239. hal_gpio_write(&gpio_rf_sw_0, 0);
  240. cc1101_write_reg(device, CC1101_IOCFG2, CC1101IocfgHW | CC1101_IOCFG_INV);
  241. } else if (path == ApiHalSubGhzPath315) {
  242. hal_gpio_write(&gpio_rf_sw_0, 1);
  243. cc1101_write_reg(device, CC1101_IOCFG2, CC1101IocfgHW);
  244. } else if (path == ApiHalSubGhzPath868) {
  245. hal_gpio_write(&gpio_rf_sw_0, 1);
  246. cc1101_write_reg(device, CC1101_IOCFG2, CC1101IocfgHW | CC1101_IOCFG_INV);
  247. } else if (path == ApiHalSubGhzPathIsolate) {
  248. hal_gpio_write(&gpio_rf_sw_0, 0);
  249. cc1101_write_reg(device, CC1101_IOCFG2, CC1101IocfgHW);
  250. } else {
  251. furi_check(0);
  252. }
  253. api_hal_spi_device_return(device);
  254. }
  255. volatile uint32_t api_hal_subghz_capture_delta_duration = 0;
  256. volatile ApiHalSubGhzCaptureCallback api_hal_subghz_capture_callback = NULL;
  257. volatile void* api_hal_subghz_capture_callback_context = NULL;
  258. static void api_hal_subghz_capture_ISR() {
  259. // Channel 1
  260. if(LL_TIM_IsActiveFlag_CC1(TIM2)) {
  261. LL_TIM_ClearFlag_CC1(TIM2);
  262. api_hal_subghz_capture_delta_duration = LL_TIM_IC_GetCaptureCH1(TIM2);
  263. if (api_hal_subghz_capture_callback) {
  264. api_hal_subghz_capture_callback(true, api_hal_subghz_capture_delta_duration,
  265. (void*)api_hal_subghz_capture_callback_context
  266. );
  267. }
  268. }
  269. // Channel 2
  270. if(LL_TIM_IsActiveFlag_CC2(TIM2)) {
  271. LL_TIM_ClearFlag_CC2(TIM2);
  272. if (api_hal_subghz_capture_callback) {
  273. api_hal_subghz_capture_callback(false, LL_TIM_IC_GetCaptureCH2(TIM2) - api_hal_subghz_capture_delta_duration,
  274. (void*)api_hal_subghz_capture_callback_context
  275. );
  276. }
  277. }
  278. }
  279. void api_hal_subghz_set_async_rx_callback(ApiHalSubGhzCaptureCallback callback, void* context) {
  280. api_hal_subghz_capture_callback = callback;
  281. api_hal_subghz_capture_callback_context = context;
  282. }
  283. void api_hal_subghz_start_async_rx() {
  284. furi_assert(api_hal_subghz_state == SubGhzStateIdle);
  285. api_hal_subghz_state = SubGhzStateAsyncRx;
  286. hal_gpio_init_ex(&gpio_cc1101_g0, GpioModeAltFunctionPushPull, GpioPullNo, GpioSpeedLow, GpioAltFn1TIM2);
  287. // Timer: base
  288. LL_TIM_InitTypeDef TIM_InitStruct = {0};
  289. TIM_InitStruct.Prescaler = 64-1;
  290. TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;
  291. TIM_InitStruct.Autoreload = 0x7FFFFFFE;
  292. TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
  293. LL_TIM_Init(TIM2, &TIM_InitStruct);
  294. // Timer: advanced
  295. LL_TIM_SetClockSource(TIM2, LL_TIM_CLOCKSOURCE_INTERNAL);
  296. LL_TIM_DisableARRPreload(TIM2);
  297. LL_TIM_SetTriggerInput(TIM2, LL_TIM_TS_TI2FP2);
  298. LL_TIM_SetSlaveMode(TIM2, LL_TIM_SLAVEMODE_RESET);
  299. LL_TIM_SetTriggerOutput(TIM2, LL_TIM_TRGO_RESET);
  300. LL_TIM_EnableMasterSlaveMode(TIM2);
  301. LL_TIM_DisableDMAReq_TRIG(TIM2);
  302. LL_TIM_DisableIT_TRIG(TIM2);
  303. // Timer: channel 1 indirect
  304. LL_TIM_IC_SetActiveInput(TIM2, LL_TIM_CHANNEL_CH1, LL_TIM_ACTIVEINPUT_INDIRECTTI);
  305. LL_TIM_IC_SetPrescaler(TIM2, LL_TIM_CHANNEL_CH1, LL_TIM_ICPSC_DIV1);
  306. LL_TIM_IC_SetPolarity(TIM2, LL_TIM_CHANNEL_CH1, LL_TIM_IC_POLARITY_FALLING);
  307. LL_TIM_IC_SetFilter(TIM2, LL_TIM_CHANNEL_CH1, LL_TIM_IC_FILTER_FDIV1);
  308. // Timer: channel 2 direct
  309. LL_TIM_IC_SetActiveInput(TIM2, LL_TIM_CHANNEL_CH2, LL_TIM_ACTIVEINPUT_DIRECTTI);
  310. LL_TIM_IC_SetPrescaler(TIM2, LL_TIM_CHANNEL_CH2, LL_TIM_ICPSC_DIV1);
  311. LL_TIM_IC_SetPolarity(TIM2, LL_TIM_CHANNEL_CH2, LL_TIM_IC_POLARITY_RISING);
  312. LL_TIM_IC_SetFilter(TIM2, LL_TIM_CHANNEL_CH2, LL_TIM_IC_FILTER_FDIV1);
  313. // ISR setup
  314. api_hal_interrupt_set_timer_isr(TIM2, api_hal_subghz_capture_ISR);
  315. NVIC_SetPriority(TIM2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),5, 0));
  316. NVIC_EnableIRQ(TIM2_IRQn);
  317. // Interrupts and channels
  318. LL_TIM_EnableIT_CC1(TIM2);
  319. LL_TIM_EnableIT_CC2(TIM2);
  320. LL_TIM_CC_EnableChannel(TIM2, LL_TIM_CHANNEL_CH1);
  321. LL_TIM_CC_EnableChannel(TIM2, LL_TIM_CHANNEL_CH2);
  322. // Start timer
  323. LL_TIM_SetCounter(TIM2, 0);
  324. LL_TIM_EnableCounter(TIM2);
  325. // Switch to RX
  326. api_hal_subghz_rx();
  327. }
  328. void api_hal_subghz_stop_async_rx() {
  329. furi_assert(api_hal_subghz_state == SubGhzStateAsyncRx);
  330. api_hal_subghz_state = SubGhzStateIdle;
  331. // Shutdown radio
  332. api_hal_subghz_idle();
  333. LL_TIM_DeInit(TIM2);
  334. api_hal_interrupt_set_timer_isr(TIM2, NULL);
  335. hal_gpio_init(&gpio_cc1101_g0, GpioModeAnalog, GpioPullNo, GpioSpeedLow);
  336. }
  337. volatile size_t api_hal_subghz_tx_repeat = 0;
  338. static void api_hal_subghz_tx_dma_isr() {
  339. if (LL_DMA_IsActiveFlag_TC1(DMA1)) {
  340. LL_DMA_ClearFlag_TC1(DMA1);
  341. furi_assert(api_hal_subghz_state == SubGhzStateAsyncTx);
  342. if (--api_hal_subghz_tx_repeat == 0) {
  343. api_hal_subghz_state = SubGhzStateAsyncTxLast;
  344. LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_1);
  345. }
  346. }
  347. }
  348. static void api_hal_subghz_tx_timer_isr() {
  349. if(LL_TIM_IsActiveFlag_UPDATE(TIM2)) {
  350. LL_TIM_ClearFlag_UPDATE(TIM2);
  351. if (api_hal_subghz_state == SubGhzStateAsyncTxLast) {
  352. LL_TIM_DisableCounter(TIM2);
  353. api_hal_subghz_state = SubGhzStateAsyncTxEnd;
  354. }
  355. }
  356. }
  357. void api_hal_subghz_start_async_tx(uint32_t* buffer, size_t buffer_size, size_t repeat) {
  358. furi_assert(api_hal_subghz_state == SubGhzStateIdle);
  359. api_hal_subghz_state = SubGhzStateAsyncTx;
  360. api_hal_subghz_tx_repeat = repeat;
  361. // Connect CC1101_GD0 to TIM2 as output
  362. hal_gpio_init_ex(&gpio_cc1101_g0, GpioModeAltFunctionPushPull, GpioPullDown, GpioSpeedLow, GpioAltFn1TIM2);
  363. // Configure DMA
  364. LL_DMA_InitTypeDef dma_config = {0};
  365. dma_config.PeriphOrM2MSrcAddress = (uint32_t)&(TIM2->ARR);
  366. dma_config.MemoryOrM2MDstAddress = (uint32_t)buffer;
  367. dma_config.Direction = LL_DMA_DIRECTION_MEMORY_TO_PERIPH;
  368. dma_config.Mode = LL_DMA_MODE_CIRCULAR;
  369. dma_config.PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
  370. dma_config.MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT;
  371. dma_config.PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_WORD;
  372. dma_config.MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_WORD;
  373. dma_config.NbData = buffer_size / sizeof(uint32_t);
  374. dma_config.PeriphRequest = LL_DMAMUX_REQ_TIM2_UP;
  375. dma_config.Priority = LL_DMA_MODE_NORMAL;
  376. LL_DMA_Init(DMA1, LL_DMA_CHANNEL_1, &dma_config);
  377. api_hal_interrupt_set_dma_channel_isr(DMA1, LL_DMA_CHANNEL_1, api_hal_subghz_tx_dma_isr);
  378. LL_DMA_EnableIT_TC(DMA1, LL_DMA_CHANNEL_1);
  379. LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_1);
  380. // Configure TIM2
  381. LL_TIM_InitTypeDef TIM_InitStruct = {0};
  382. TIM_InitStruct.Prescaler = 64-1;
  383. TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;
  384. TIM_InitStruct.Autoreload = 1000;
  385. TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
  386. LL_TIM_Init(TIM2, &TIM_InitStruct);
  387. LL_TIM_SetClockSource(TIM2, LL_TIM_CLOCKSOURCE_INTERNAL);
  388. LL_TIM_EnableARRPreload(TIM2);
  389. // Configure TIM2 CH2
  390. LL_TIM_OC_InitTypeDef TIM_OC_InitStruct = {0};
  391. TIM_OC_InitStruct.OCMode = LL_TIM_OCMODE_TOGGLE;
  392. TIM_OC_InitStruct.OCState = LL_TIM_OCSTATE_DISABLE;
  393. TIM_OC_InitStruct.OCNState = LL_TIM_OCSTATE_DISABLE;
  394. TIM_OC_InitStruct.CompareValue = 0;
  395. TIM_OC_InitStruct.OCPolarity = LL_TIM_OCPOLARITY_HIGH;
  396. LL_TIM_OC_Init(TIM2, LL_TIM_CHANNEL_CH2, &TIM_OC_InitStruct);
  397. LL_TIM_OC_DisableFast(TIM2, LL_TIM_CHANNEL_CH2);
  398. LL_TIM_DisableMasterSlaveMode(TIM2);
  399. api_hal_interrupt_set_timer_isr(TIM2, api_hal_subghz_tx_timer_isr);
  400. LL_TIM_EnableIT_UPDATE(TIM2);
  401. LL_TIM_EnableDMAReq_UPDATE(TIM2);
  402. LL_TIM_CC_EnableChannel(TIM2, LL_TIM_CHANNEL_CH2);
  403. // Start counter
  404. LL_TIM_GenerateEvent_UPDATE(TIM2);
  405. #ifdef API_HAL_SUBGHZ_TX_GPIO
  406. hal_gpio_write(&API_HAL_SUBGHZ_TX_GPIO, true);
  407. #endif
  408. api_hal_subghz_tx();
  409. LL_TIM_SetCounter(TIM2, 0);
  410. LL_TIM_EnableCounter(TIM2);
  411. }
  412. void api_hal_subghz_wait_async_tx() {
  413. while(api_hal_subghz_state != SubGhzStateAsyncTxEnd) osDelay(1);
  414. }
  415. void api_hal_subghz_stop_async_tx() {
  416. furi_assert(api_hal_subghz_state == SubGhzStateAsyncTxEnd);
  417. api_hal_subghz_state = SubGhzStateIdle;
  418. // Shutdown radio
  419. api_hal_subghz_idle();
  420. #ifdef API_HAL_SUBGHZ_TX_GPIO
  421. hal_gpio_write(&API_HAL_SUBGHZ_TX_GPIO, false);
  422. #endif
  423. // Deinitialize Timer
  424. LL_TIM_DeInit(TIM2);
  425. api_hal_interrupt_set_timer_isr(TIM2, NULL);
  426. // Deinitialize DMA
  427. LL_DMA_DeInit(DMA1, LL_DMA_CHANNEL_1);
  428. api_hal_interrupt_set_dma_channel_isr(DMA1, LL_DMA_CHANNEL_1, NULL);
  429. // Deinitialize GPIO
  430. hal_gpio_init(&gpio_cc1101_g0, GpioModeAnalog, GpioPullNo, GpioSpeedLow);
  431. }