furi-hal-bt.c 3.5 KB

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  1. #include <furi-hal-bt.h>
  2. #include <app_entry.h>
  3. #include <ble.h>
  4. #include <stm32wbxx.h>
  5. #include <shci.h>
  6. #include <cmsis_os2.h>
  7. #include <app_ble.h>
  8. #include <gap.h>
  9. void furi_hal_bt_init() {
  10. // Explicitly tell that we are in charge of CLK48 domain
  11. HAL_HSEM_FastTake(CFG_HW_CLK48_CONFIG_SEMID);
  12. // Start Core2, init HCI and start GAP/GATT
  13. APPE_Init();
  14. }
  15. bool furi_hal_bt_start_app() {
  16. return gap_init();
  17. }
  18. void furi_hal_bt_dump_state(string_t buffer) {
  19. BleGlueStatus status = APPE_Status();
  20. if (status == BleGlueStatusStarted) {
  21. uint8_t HCI_Version;
  22. uint16_t HCI_Revision;
  23. uint8_t LMP_PAL_Version;
  24. uint16_t Manufacturer_Name;
  25. uint16_t LMP_PAL_Subversion;
  26. tBleStatus ret = hci_read_local_version_information(
  27. &HCI_Version, &HCI_Revision, &LMP_PAL_Version, &Manufacturer_Name, &LMP_PAL_Subversion
  28. );
  29. string_cat_printf(buffer,
  30. "Ret: %d, HCI_Version: %d, HCI_Revision: %d, LMP_PAL_Version: %d, Manufacturer_Name: %d, LMP_PAL_Subversion: %d",
  31. ret, HCI_Version, HCI_Revision, LMP_PAL_Version, Manufacturer_Name, LMP_PAL_Subversion
  32. );
  33. } else {
  34. string_cat_printf(buffer, "BLE not ready");
  35. }
  36. }
  37. bool furi_hal_bt_is_alive() {
  38. return APPE_Status() == BleGlueStatusStarted;
  39. }
  40. bool furi_hal_bt_wait_startup() {
  41. uint8_t counter = 0;
  42. while (!(APPE_Status() == BleGlueStatusStarted || APPE_Status() == BleGlueStatusBroken)) {
  43. osDelay(10);
  44. counter++;
  45. if (counter > 1000) {
  46. return false;
  47. }
  48. }
  49. return true;
  50. }
  51. bool furi_hal_bt_lock_flash() {
  52. if (!furi_hal_bt_wait_startup()) {
  53. return false;
  54. }
  55. while (HAL_HSEM_FastTake(CFG_HW_FLASH_SEMID) != HAL_OK) {
  56. osDelay(1);
  57. }
  58. SHCI_C2_FLASH_EraseActivity(ERASE_ACTIVITY_ON);
  59. HAL_FLASH_Unlock();
  60. while(LL_FLASH_IsOperationSuspended()) {};
  61. return true;
  62. }
  63. void furi_hal_bt_unlock_flash() {
  64. SHCI_C2_FLASH_EraseActivity(ERASE_ACTIVITY_OFF);
  65. HAL_FLASH_Lock();
  66. HAL_HSEM_Release(CFG_HW_FLASH_SEMID, HSEM_CPU1_COREID);
  67. }
  68. void furi_hal_bt_start_tone_tx(uint8_t channel, uint8_t power) {
  69. aci_hal_set_tx_power_level(0, power);
  70. aci_hal_tone_start(channel, 0);
  71. }
  72. void furi_hal_bt_stop_tone_tx() {
  73. aci_hal_tone_stop();
  74. }
  75. void furi_hal_bt_start_packet_tx(uint8_t channel, uint8_t pattern, uint8_t datarate) {
  76. hci_le_enhanced_transmitter_test(channel, 0x25, pattern, datarate);
  77. }
  78. void furi_hal_bt_start_packet_rx(uint8_t channel, uint8_t datarate) {
  79. hci_le_enhanced_receiver_test(channel, datarate, 0);
  80. }
  81. uint16_t furi_hal_bt_stop_packet_test() {
  82. uint16_t num_of_packets = 0;
  83. hci_le_test_end(&num_of_packets);
  84. return num_of_packets;
  85. }
  86. void furi_hal_bt_start_rx(uint8_t channel) {
  87. aci_hal_rx_start(channel);
  88. }
  89. float furi_hal_bt_get_rssi() {
  90. float val;
  91. uint8_t rssi_raw[3];
  92. if (aci_hal_read_raw_rssi(rssi_raw) != BLE_STATUS_SUCCESS) {
  93. return 0.0f;
  94. }
  95. // Some ST magic with rssi
  96. uint8_t agc = rssi_raw[2] & 0xFF;
  97. int rssi = (((int)rssi_raw[1] << 8) & 0xFF00) + (rssi_raw[0] & 0xFF);
  98. if(rssi == 0 || agc > 11) {
  99. val = -127.0;
  100. } else {
  101. val = agc * 6.0f - 127.0f;
  102. while(rssi > 30) {
  103. val += 6.0;
  104. rssi >>=1;
  105. }
  106. val += (417 * rssi + 18080) >> 10;
  107. }
  108. return val;
  109. }
  110. uint32_t furi_hal_bt_get_transmitted_packets() {
  111. uint32_t packets = 0;
  112. aci_hal_le_tx_test_packet_number(&packets);
  113. return packets;
  114. }
  115. void furi_hal_bt_stop_rx() {
  116. aci_hal_rx_stop();
  117. }