rw1990.c 2.5 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495
  1. #include "rw1990.h"
  2. #include <core/kernel.h>
  3. #define RW1990_1_CMD_WRITE_RECORD_FLAG 0xD1
  4. #define RW1990_1_CMD_READ_RECORD_FLAG 0xB5
  5. #define RW1990_1_CMD_WRITE_ROM 0xD5
  6. #define RW1990_2_CMD_WRITE_RECORD_FLAG 0x1D
  7. #define RW1990_2_CMD_READ_RECORD_FLAG 0x1E
  8. #define RW1990_2_CMD_WRITE_ROM 0xD5
  9. #define DS1990_CMD_READ_ROM 0x33
  10. static void rw1990_write_byte(OneWireHost* host, uint8_t value) {
  11. for(uint8_t bitMask = 0x01; bitMask; bitMask <<= 1) {
  12. onewire_host_write_bit(host, (bool)(bitMask & value));
  13. furi_delay_us(5000);
  14. }
  15. }
  16. static bool rw1990_read_and_compare(OneWireHost* host, const uint8_t* data, size_t data_size) {
  17. bool success = false;
  18. if(onewire_host_reset(host)) {
  19. success = true;
  20. onewire_host_write(host, DS1990_CMD_READ_ROM);
  21. for(size_t i = 0; i < data_size; ++i) {
  22. if(data[i] != onewire_host_read(host)) {
  23. success = false;
  24. break;
  25. }
  26. }
  27. }
  28. return success;
  29. }
  30. bool rw1990_write_v1(OneWireHost* host, const uint8_t* data, size_t data_size) {
  31. // Unlock sequence
  32. onewire_host_reset(host);
  33. onewire_host_write(host, RW1990_1_CMD_WRITE_RECORD_FLAG);
  34. furi_delay_us(10);
  35. onewire_host_write_bit(host, false);
  36. furi_delay_us(5000);
  37. // Write data
  38. onewire_host_reset(host);
  39. onewire_host_write(host, RW1990_1_CMD_WRITE_ROM);
  40. for(size_t i = 0; i < data_size; ++i) {
  41. // inverted key for RW1990.1
  42. rw1990_write_byte(host, ~(data[i]));
  43. furi_delay_us(30000);
  44. }
  45. // Lock sequence
  46. onewire_host_write(host, RW1990_1_CMD_WRITE_RECORD_FLAG);
  47. onewire_host_write_bit(host, true);
  48. furi_delay_us(10000);
  49. // TODO: Better error handling
  50. return rw1990_read_and_compare(host, data, data_size);
  51. }
  52. bool rw1990_write_v2(OneWireHost* host, const uint8_t* data, size_t data_size) {
  53. // Unlock sequence
  54. onewire_host_reset(host);
  55. onewire_host_write(host, RW1990_2_CMD_WRITE_RECORD_FLAG);
  56. furi_delay_us(10);
  57. onewire_host_write_bit(host, true);
  58. furi_delay_us(5000);
  59. // Write data
  60. onewire_host_reset(host);
  61. onewire_host_write(host, RW1990_2_CMD_WRITE_ROM);
  62. for(size_t i = 0; i < data_size; ++i) {
  63. rw1990_write_byte(host, data[i]);
  64. furi_delay_us(30000);
  65. }
  66. // Lock sequence
  67. onewire_host_write(host, RW1990_2_CMD_WRITE_RECORD_FLAG);
  68. onewire_host_write_bit(host, false);
  69. furi_delay_us(10000);
  70. // TODO: Better error handling
  71. return rw1990_read_and_compare(host, data, data_size);
  72. }