custom_presets.h 4.7 KB

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  1. #include <cc1101.h>
  2. /* This is how to configure registers MDMCFG3 and MDMCFG4.
  3. *
  4. * Data rate kBaud setting:
  5. *
  6. * MDMCFG3 is the data rate mantissa, the exponent is in MDMCFG4,
  7. * last 4 bits of the register.
  8. *
  9. * The rate (assuming 26Mhz crystal) is calculated as follows:
  10. *
  11. * ((256+MDMCFG3)*(2^MDMCFG4:0..3bits)) / 2^28 * 26000000.
  12. *
  13. * For instance for the default values of MDMCFG3 (34) and MDMCFG4 (12):
  14. *
  15. * ((256+34)*(2^12))/(2^28)*26000000 = 115051.2688000000, that is 115KBaud
  16. *
  17. * Bandwidth filter setting:
  18. *
  19. * BW filter as just 16 possibilities depending on how the first nibble
  20. * (first 4 bits) of the MDMCFG4 bits are set. Instead of providing the
  21. * formula, it is simpler to show all the values of the nibble and the
  22. * corresponding bandwidth filter.
  23. *
  24. * 0 812khz
  25. * 1 650khz
  26. * 2 541khz
  27. * 3 464khz
  28. * 4 406khz
  29. * 5 325khz
  30. * 6 270khz
  31. * 7 232khz
  32. * 8 203khz
  33. * 9 162khz
  34. * a 135khz
  35. * b 116khz
  36. * c 102khz
  37. * d 82 khz
  38. * e 68 khz
  39. * f 58 khz
  40. */
  41. /* 20 KBaud, 2FSK, 28.56 kHz deviation, 325 Khz bandwidth filter. */
  42. static uint8_t protoview_subghz_tpms1_async_regs[][2] = {
  43. /* GPIO GD0 */
  44. {CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input
  45. /* Frequency Synthesizer Control */
  46. {CC1101_FSCTRL1, 0x06}, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
  47. /* Packet engine */
  48. {CC1101_PKTCTRL0, 0x32}, // Async, continious, no whitening
  49. {CC1101_PKTCTRL1, 0x04},
  50. // // Modem Configuration
  51. {CC1101_MDMCFG0, 0x00},
  52. {CC1101_MDMCFG1, 0x02},
  53. {CC1101_MDMCFG2, 0x04}, // Format 2-FSK/FM, No preamble/sync, Disable (current optimized). Other code reading TPMS uses GFSK, but should be the same when in RX mode.
  54. {CC1101_MDMCFG3, 0x93}, // Data rate is 20kBaud
  55. {CC1101_MDMCFG4, 0x59}, // Rx bandwidth filter is 325 kHz
  56. {CC1101_DEVIATN, 0x41}, // Deviation 28.56 kHz
  57. /* Main Radio Control State Machine */
  58. {CC1101_MCSM0, 0x18}, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
  59. /* Frequency Offset Compensation Configuration */
  60. {CC1101_FOCCFG,
  61. 0x16}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
  62. /* Automatic Gain Control */
  63. {CC1101_AGCCTRL0,
  64. 0x91}, //10 - Medium hysteresis, medium asymmetric dead zone, medium gain ; 01 - 16 samples agc; 00 - Normal AGC, 01 - 8dB boundary
  65. {CC1101_AGCCTRL1,
  66. 0x00}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
  67. {CC1101_AGCCTRL2, 0x07}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 111 - MAIN_TARGET 42 dB
  68. /* Wake on radio and timeouts control */
  69. {CC1101_WORCTRL, 0xFB}, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
  70. /* Frontend configuration */
  71. {CC1101_FREND0, 0x10}, // Adjusts current TX LO buffer
  72. {CC1101_FREND1, 0x56},
  73. /* End */
  74. {0, 0},
  75. };
  76. /* 40 KBaud, 2FSK, 19 kHz deviation, 102 Khz bandwidth filter. */
  77. static uint8_t protoview_subghz_tpms2_async_regs[][2] = {
  78. /* GPIO GD0 */
  79. {CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input
  80. /* Frequency Synthesizer Control */
  81. {CC1101_FSCTRL1, 0x06}, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
  82. /* Packet engine */
  83. {CC1101_PKTCTRL0, 0x32}, // Async, continious, no whitening
  84. {CC1101_PKTCTRL1, 0x04},
  85. // // Modem Configuration
  86. {CC1101_MDMCFG0, 0x00},
  87. {CC1101_MDMCFG1, 0x02},
  88. {CC1101_MDMCFG2, 0x04}, // Format 2-FSK/FM, No preamble/sync, Disable (current optimized). Other code reading TPMS uses GFSK, but should be the same when in RX mode.
  89. {CC1101_MDMCFG3, 0x93}, // Data rate is 40kBaud
  90. {CC1101_MDMCFG4, 0x6A}, // 6 = BW filter 270kHz, A = Data rate exp
  91. {CC1101_DEVIATN, 0x41}, // Deviation 19.042 kHz
  92. /* Main Radio Control State Machine */
  93. {CC1101_MCSM0, 0x18}, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
  94. /* Frequency Offset Compensation Configuration */
  95. {CC1101_FOCCFG,
  96. 0x16}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
  97. /* Automatic Gain Control */
  98. {CC1101_AGCCTRL0,
  99. 0x91}, //10 - Medium hysteresis, medium asymmetric dead zone, medium gain ; 01 - 16 samples agc; 00 - Normal AGC, 01 - 8dB boundary
  100. {CC1101_AGCCTRL1,
  101. 0x00}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
  102. {CC1101_AGCCTRL2, 0x07}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 111 - MAIN_TARGET 42 dB
  103. /* Wake on radio and timeouts control */
  104. {CC1101_WORCTRL, 0xFB}, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
  105. /* Frontend configuration */
  106. {CC1101_FREND0, 0x10}, // Adjusts current TX LO buffer
  107. {CC1101_FREND1, 0x56},
  108. /* End */
  109. {0, 0},
  110. };