custom_presets.h 8.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240
  1. #include <cc1101.h>
  2. /* This is how to configure registers MDMCFG3 and MDMCFG4.
  3. *
  4. * Data rate kBaud setting:
  5. *
  6. * MDMCFG3 is the data rate mantissa, the exponent is in MDMCFG4,
  7. * last 4 bits of the register.
  8. *
  9. * The rate (assuming 26Mhz crystal) is calculated as follows:
  10. *
  11. * ((256+MDMCFG3)*(2^MDMCFG4:0..3bits)) / 2^28 * 26000000.
  12. *
  13. * For instance for the default values of MDMCFG3[0..3] (34) and MDMCFG4 (12):
  14. *
  15. * ((256+34)*(2^12))/(2^28)*26000000 = 115051.2688000000, that is 115KBaud
  16. *
  17. * Bandwidth filter setting:
  18. *
  19. * BW filter as just 16 possibilities depending on how the first nibble
  20. * (first 4 bits) of the MDMCFG4 bits are set. Instead of providing the
  21. * formula, it is simpler to show all the values of the nibble and the
  22. * corresponding bandwidth filter.
  23. *
  24. * 0 812khz
  25. * 1 650khz
  26. * 2 541khz
  27. * 3 464khz
  28. * 4 406khz
  29. * 5 325khz
  30. * 6 270khz
  31. * 7 232khz
  32. * 8 203khz
  33. * 9 162khz
  34. * a 135khz
  35. * b 116khz
  36. * c 102khz
  37. * d 82 khz
  38. * e 68 khz
  39. * f 58 khz
  40. *
  41. * FSK deviation is controlled by the DEVIATION register. In Ruby:
  42. *
  43. * dev = (26000000.0/2**17)*(8+(deviation&7))*(2**(deviation>>4&7))
  44. *
  45. * deviation&7 (last three bits) is the deviation mantissa, while
  46. * deviation>>4&7 (bits 6,5,4) are the exponent.
  47. *
  48. * Deviations values according to certain configuration of DEVIATION:
  49. *
  50. * 0x04 -> 2.380371 kHz
  51. * 0x24 -> 9.521484 kHz
  52. * 0x34 -> 19.042969 Khz
  53. * 0x40 -> 25.390625 Khz
  54. * 0x43 -> 34.912109 Khz
  55. * 0x45 -> 41.259765 Khz
  56. * 0x47 -> 47.607422 kHz
  57. */
  58. /* 20 KBaud, 2FSK, 28.56 kHz deviation, 325 Khz bandwidth filter. */
  59. static uint8_t protoview_subghz_tpms1_fsk_async_regs[][2] = {
  60. /* GPIO GD0 */
  61. {CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input
  62. /* Frequency Synthesizer Control */
  63. {CC1101_FSCTRL1, 0x06}, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
  64. /* Packet engine */
  65. {CC1101_PKTCTRL0, 0x32}, // Async, continious, no whitening
  66. {CC1101_PKTCTRL1, 0x04},
  67. // // Modem Configuration
  68. {CC1101_MDMCFG0, 0x00},
  69. {CC1101_MDMCFG1, 0x02},
  70. {CC1101_MDMCFG2, 0x04}, // Format 2-FSK/FM, No preamble/sync, Disable (current optimized). Other code reading TPMS uses GFSK, but should be the same when in RX mode.
  71. {CC1101_MDMCFG3, 0x93}, // Data rate is 20kBaud
  72. {CC1101_MDMCFG4, 0x59}, // Rx bandwidth filter is 325 kHz
  73. {CC1101_DEVIATN, 0x41}, // Deviation 28.56 kHz
  74. /* Main Radio Control State Machine */
  75. {CC1101_MCSM0, 0x18}, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
  76. /* Frequency Offset Compensation Configuration */
  77. {CC1101_FOCCFG,
  78. 0x16}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
  79. /* Automatic Gain Control */
  80. {CC1101_AGCCTRL0,
  81. 0x91}, //10 - Medium hysteresis, medium asymmetric dead zone, medium gain ; 01 - 16 samples agc; 00 - Normal AGC, 01 - 8dB boundary
  82. {CC1101_AGCCTRL1,
  83. 0x00}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
  84. {CC1101_AGCCTRL2, 0x07}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 111 - MAIN_TARGET 42 dB
  85. /* Wake on radio and timeouts control */
  86. {CC1101_WORCTRL, 0xFB}, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
  87. /* Frontend configuration */
  88. {CC1101_FREND0, 0x10}, // Adjusts current TX LO buffer
  89. {CC1101_FREND1, 0x56},
  90. /* End */
  91. {0, 0},
  92. };
  93. /* This is like the default Flipper OOK 640Khz bandwidth preset, but
  94. * the bandwidth is changed to 10kBaud to accomodate TPMS frequency. */
  95. static const uint8_t protoview_subghz_tpms2_ook_async_regs[][2] = {
  96. /* GPIO GD0 */
  97. {CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input
  98. /* FIFO and internals */
  99. {CC1101_FIFOTHR, 0x07}, // The only important bit is ADC_RETENTION
  100. /* Packet engine */
  101. {CC1101_PKTCTRL0, 0x32}, // Async, continious, no whitening
  102. /* Frequency Synthesizer Control */
  103. {CC1101_FSCTRL1, 0x06}, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
  104. // Modem Configuration
  105. {CC1101_MDMCFG0, 0x00}, // Channel spacing is 25kHz
  106. {CC1101_MDMCFG1, 0x00}, // Channel spacing is 25kHz
  107. {CC1101_MDMCFG2, 0x30}, // Format ASK/OOK, No preamble/sync
  108. {CC1101_MDMCFG3, 0x93}, // Data rate is 10kBaud
  109. {CC1101_MDMCFG4, 0x18}, // Rx BW filter is 650.000kHz
  110. /* Main Radio Control State Machine */
  111. {CC1101_MCSM0, 0x18}, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
  112. /* Frequency Offset Compensation Configuration */
  113. {CC1101_FOCCFG,
  114. 0x18}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
  115. /* Automatic Gain Control */
  116. {CC1101_AGCCTRL0,
  117. 0x91}, // 10 - Medium hysteresis, medium asymmetric dead zone, medium gain ; 01 - 16 samples agc; 00 - Normal AGC, 01 - 8dB boundary
  118. {CC1101_AGCCTRL1,
  119. 0x0}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
  120. {CC1101_AGCCTRL2, 0x07}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 111 - MAIN_TARGET 42 dB
  121. /* Wake on radio and timeouts control */
  122. {CC1101_WORCTRL, 0xFB}, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
  123. /* Frontend configuration */
  124. {CC1101_FREND0, 0x11}, // Adjusts current TX LO buffer + high is PATABLE[1]
  125. {CC1101_FREND1, 0xB6}, //
  126. /* End */
  127. {0, 0},
  128. };
  129. /* 40 KBaud, 2FSK, 19 kHz deviation, 102 Khz bandwidth filter. */
  130. static uint8_t protoview_subghz_tpms3_fsk_async_regs[][2] = {
  131. /* GPIO GD0 */
  132. {CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input
  133. /* Frequency Synthesizer Control */
  134. {CC1101_FSCTRL1, 0x06}, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
  135. /* Packet engine */
  136. {CC1101_PKTCTRL0, 0x32}, // Async, continious, no whitening
  137. {CC1101_PKTCTRL1, 0x04},
  138. // // Modem Configuration
  139. {CC1101_MDMCFG0, 0x00},
  140. {CC1101_MDMCFG1, 0x02},
  141. {CC1101_MDMCFG2, 0x04}, // Format 2-FSK/FM, No preamble/sync, Disable (current optimized). Other code reading TPMS uses GFSK, but should be the same when in RX mode.
  142. {CC1101_MDMCFG3, 0x93}, // Data rate is 40kBaud
  143. {CC1101_MDMCFG4, 0x6A}, // 6 = BW filter 270kHz, A = Data rate exp
  144. {CC1101_DEVIATN, 0x41}, // Deviation 19.042 kHz
  145. /* Main Radio Control State Machine */
  146. {CC1101_MCSM0, 0x18}, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
  147. /* Frequency Offset Compensation Configuration */
  148. {CC1101_FOCCFG,
  149. 0x16}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
  150. /* Automatic Gain Control */
  151. {CC1101_AGCCTRL0,
  152. 0x91}, //10 - Medium hysteresis, medium asymmetric dead zone, medium gain ; 01 - 16 samples agc; 00 - Normal AGC, 01 - 8dB boundary
  153. {CC1101_AGCCTRL1,
  154. 0x00}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
  155. {CC1101_AGCCTRL2, 0x07}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 111 - MAIN_TARGET 42 dB
  156. /* Wake on radio and timeouts control */
  157. {CC1101_WORCTRL, 0xFB}, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
  158. /* Frontend configuration */
  159. {CC1101_FREND0, 0x10}, // Adjusts current TX LO buffer
  160. {CC1101_FREND1, 0x56},
  161. /* End */
  162. {0, 0},
  163. };
  164. /* Parameters that should work well for the TPMS PVM C210 sensor. */
  165. static uint8_t protoview_subghz_tpms4_fsk_async_regs[][2] = {
  166. /* GPIO GD0 */
  167. {CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input
  168. /* Frequency Synthesizer Control */
  169. {CC1101_FSCTRL1, 0x06}, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
  170. /* Packet engine */
  171. {CC1101_PKTCTRL0, 0x32}, // Async, continious, no whitening
  172. {CC1101_PKTCTRL1, 0x04},
  173. // // Modem Configuration
  174. {CC1101_MDMCFG0, 0x00},
  175. {CC1101_MDMCFG1, 0x02}, // 2 is the channel spacing exponet: not used
  176. {CC1101_MDMCFG2, 0x10}, // GFSK without any other check
  177. {CC1101_MDMCFG3, 0x93}, // Data rate is 20kBaud
  178. {CC1101_MDMCFG4, 0x59}, // Rx bandwidth filter is 325 kHz
  179. {CC1101_DEVIATN, 0x34}, // Deviation 19.04 Khz, works well with TPMS
  180. /* Main Radio Control State Machine */
  181. {CC1101_MCSM0, 0x18}, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
  182. /* Frequency Offset Compensation Configuration */
  183. {CC1101_FOCCFG,
  184. 0x16}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
  185. /* Automatic Gain Control */
  186. {CC1101_AGCCTRL0, 0x80},
  187. {CC1101_AGCCTRL1, 0x58},
  188. {CC1101_AGCCTRL2, 0x87},
  189. /* Wake on radio and timeouts control */
  190. {CC1101_WORCTRL, 0xFB}, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
  191. /* Frontend configuration */
  192. {CC1101_FREND0, 0x10}, // Adjusts current TX LO buffer
  193. {CC1101_FREND1, 0x56},
  194. /* End */
  195. {0, 0},
  196. };