cc1101-workaround.cpp 18 KB

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  1. #include "cc1101.h"
  2. #include <furi.h>
  3. #include <gui/gui.h>
  4. #include <input/input.h>
  5. extern "C" void cli_print(const char* str);
  6. #define RSSI_DELAY 5000 //rssi delay in micro second
  7. #define CHAN_SPA 0.05 // channel spacing
  8. int16_t rssi_to_dbm(uint8_t rssi_dec, uint8_t rssiOffset) {
  9. int16_t rssi;
  10. if(rssi_dec >= 128) {
  11. rssi = (int16_t)((int16_t)(rssi_dec - 256) / 2) - rssiOffset;
  12. } else {
  13. rssi = (rssi_dec / 2) - rssiOffset;
  14. }
  15. return rssi;
  16. }
  17. typedef struct {
  18. float base_freq;
  19. uint8_t reg[3]; // FREQ2, FREQ1, FREQ0
  20. uint8_t first_channel;
  21. uint8_t last_channel;
  22. uint8_t rssi_offset;
  23. } Band;
  24. typedef struct {
  25. const Band* band;
  26. uint16_t channel;
  27. } FreqConfig;
  28. void setup_freq(CC1101* cc1101, float freq) {
  29. // cc1101->SpiWriteReg(CC1101_MCSM0, 0x08); // disalbe FS_AUTOCAL
  30. // cc1101->SpiWriteReg(CC1101_AGCCTRL2, 0x43 | 0x0C); // MAX_DVGA_GAIN to 11 for fast rssi
  31. // cc1101->SpiWriteReg(CC1101_AGCCTRL0, 0xB0); // max AGC WAIT_TIME; 0 filter_length
  32. // cc1101->SetMod(GFSK); // set to GFSK for fast rssi measurement | +8 is dcfilter off
  33. uint32_t freq_reg = freq * 1e6 / (F_OSC / 65536);
  34. cc1101->SetFreq((freq_reg >> 16) & 0xFF, (freq_reg >> 8) & 0xFF, (freq_reg)&0xFF);
  35. cc1101->SetChannel(0);
  36. /*
  37. //set test0 to 0x09
  38. cc1101->SpiWriteReg(CC1101_TEST0, 0x09);
  39. //set FSCAL2 to 0x2A to force VCO HIGH
  40. cc1101->SpiWriteReg(CC1101_FSCAL2, 0x2A);
  41. // perform a manual calibration by issuing SCAL command
  42. cc1101->SpiStrobe(CC1101_SCAL);
  43. */
  44. }
  45. static GpioPin debug_0 = {GPIOB, GPIO_PIN_2};
  46. int16_t rx_rssi(CC1101* cc1101, const FreqConfig* config) {
  47. // cc1101->SpiStrobe(CC1101_SFRX);
  48. // cc1101->SetReceive();
  49. // uint8_t begin_size = cc1101->SpiReadStatus(CC1101_RXBYTES);
  50. // uint8_t rx_status = cc1101->SpiReadStatus(CC1101_MARCSTATE);
  51. // delay_us(RSSI_DELAY);
  52. // osDelay(15);
  53. // uint8_t end_size = cc1101->SpiReadStatus(CC1101_RXBYTES);
  54. // 1.4.8) read PKTSTATUS register while the radio is in RX state
  55. /*uint8_t _pkt_status = */ // cc1101->SpiReadStatus(CC1101_PKTSTATUS);
  56. // 1.4.9) enter IDLE state by issuing a SIDLE command
  57. // cc1101->SpiStrobe(CC1101_SIDLE);
  58. // //read rssi value and converto to dBm form
  59. uint8_t rssi_dec = (uint8_t)cc1101->SpiReadStatus(CC1101_RSSI);
  60. int16_t rssi_dBm = rssi_to_dbm(rssi_dec, config->band->rssi_offset);
  61. /*
  62. char buf[256];
  63. sprintf(buf, "status: %d -> %d, rssi: %d\n", rx_status, cc1101->SpiReadStatus(CC1101_MARCSTATE), rssi_dBm);
  64. cli_print(buf);
  65. sprintf(buf, "begin: %d, end: %d\n", begin_size, end_size);
  66. cli_print(buf);
  67. */
  68. // uint8_t rx_data[64];
  69. // uint8_t fifo_length = end_size - begin_size;
  70. /*
  71. if(fifo_length < 64) {
  72. // cc1101->SpiReadBurstReg(CC1101_RXFIFO, rx_data, fifo_length);
  73. *
  74. printf("FIFO:");
  75. for(uint8_t i = 0; i < fifo_length; i++) {
  76. for(uint8_t bit = 0; bit < 8; bit++) {
  77. printf("%s", (rx_data[i] & (1 << bit)) > 0 ? "1" : "0");
  78. }
  79. printf(" ");
  80. }
  81. printf("\n");
  82. *
  83. for(uint8_t i = 0; i < fifo_length; i++) {
  84. for(uint8_t bit = 0; bit < 8; bit++) {
  85. gpio_write((GpioPin*)&debug_0, (rx_data[i] & (1 << bit)) > 0);
  86. delay_us(5);
  87. }
  88. }
  89. } else {
  90. cli_print("fifo size over\n");
  91. }
  92. */
  93. return rssi_dBm;
  94. }
  95. /*
  96. void flp_config(CC1101* cc1101) {
  97. cc1101->SpiWriteReg(
  98. CC1101_MCSM0, 0x18); // calibrate when going from IDLE to RX or TX ; 149 - 155 μs timeout
  99. // MCSM0.FS_AUTOCAL[1:0] = 1
  100. cc1101->SpiWriteReg(CC1101_AGCCTRL2, 0x43);
  101. cc1101->SpiWriteReg(CC1101_AGCCTRL1, 0x49);
  102. cc1101->SpiWriteReg(CC1101_AGCCTRL0, 0x91);
  103. //freq synthesizer calibration
  104. cc1101->SpiWriteReg(CC1101_FSCAL3, 0xEA);
  105. cc1101->SpiWriteReg(CC1101_FSCAL2, 0x2A);
  106. cc1101->SpiWriteReg(CC1101_FSCAL1, 0x00);
  107. cc1101->SpiWriteReg(CC1101_FSCAL0, 0x1F);
  108. // async data out
  109. cc1101->SpiSetRegValue(CC1101_IOCFG0, 13, 5, 0); // GDO0 Output Pin Configuration
  110. cc1101->SpiSetRegValue(CC1101_IOCFG0, 13, 5, 0); // WAT
  111. // FIFOTHR.ADC_RETENTION = 1
  112. cc1101->SpiSetRegValue(CC1101_FIFOTHR, 1, 6, 6);
  113. // PKTCTRL1.APPEND_STATUS = 0
  114. cc1101->SpiSetRegValue(CC1101_PKTCTRL1, 0, 2, 2);
  115. // PKTCTRL0.WHITE_DATA = 0
  116. cc1101->SpiSetRegValue(CC1101_PKTCTRL0, 0, 6, 6);
  117. // PKTCTRL0.LENGTH_CONFIG = 2 // Infinite packet length mode
  118. cc1101->SpiSetRegValue(CC1101_PKTCTRL0, 2, 1, 0);
  119. // PKTCTRL0.CRC_EN = 0
  120. cc1101->SpiSetRegValue(CC1101_PKTCTRL0, 0, 2, 2);
  121. // PKTCTRL0.PKT_FORMAT = 3
  122. cc1101->SpiSetRegValue(CC1101_PKTCTRL0, 3, 5, 4);
  123. // bandwidth 50-100 kHz
  124. if(!cc1101->setRxBandwidth(75.0)) {
  125. printf("wrong rx bw\n");
  126. }
  127. // datarate ~30 kbps
  128. if(!cc1101->setBitRate(100.)) {
  129. printf("wrong bitrate\n");
  130. }
  131. // mod
  132. // MDMCFG2.MOD_FORMAT = 3 (3: OOK, 0: 2-FSK)
  133. cc1101->SpiSetRegValue(CC1101_MDMCFG2, 3, 6, 4);
  134. // MDMCFG2.SYNC_MODE = 0
  135. cc1101->SpiSetRegValue(CC1101_MDMCFG2, 0, 2, 0);
  136. }
  137. */
  138. void tx_config(CC1101* cc1101) {
  139. // cc1101->SpiWriteReg(CC1101_IOCFG2,0x0B); //GDO2 Output Pin Configuration
  140. // cc1101->SpiWriteReg(CC1101_IOCFG0,0x0C); //GDO0 Output Pin Configuration
  141. cc1101->SpiSetRegValue(CC1101_IOCFG0, 13, 5, 0); // GDO0 Output Pin Configuration
  142. cc1101->SpiWriteReg(CC1101_FIFOTHR, 0x47); //RX FIFO and TX FIFO Thresholds
  143. cc1101->SpiWriteReg(CC1101_PKTCTRL0, 0x32); //Packet Automation Control
  144. cc1101->SpiWriteReg(CC1101_FSCTRL1, 0x06); //Frequency Synthesizer Control
  145. cc1101->SpiWriteReg(CC1101_FREQ2, 0x10); //Frequency Control Word, High Byte
  146. cc1101->SpiWriteReg(CC1101_FREQ1, 0xB0); //Frequency Control Word, Middle Byte
  147. cc1101->SpiWriteReg(CC1101_FREQ0, 0x71); //Frequency Control Word, Low Byte
  148. cc1101->SpiWriteReg(CC1101_MDMCFG4, 0x6A); //Modem Configuration
  149. cc1101->SpiWriteReg(CC1101_MDMCFG3, 0x2E); //Modem Configuration
  150. cc1101->SpiWriteReg(CC1101_MDMCFG2, 0x30); //Modem Configuration
  151. cc1101->SpiWriteReg(CC1101_DEVIATN, 0x15); //Modem Deviation Setting
  152. cc1101->SpiWriteReg(CC1101_MCSM0, 0x18); //Main Radio Control State Machine Configuration
  153. cc1101->SpiWriteReg(CC1101_FOCCFG, 0x16); //Frequency Offset Compensation Configuration
  154. cc1101->SpiWriteReg(CC1101_WORCTRL, 0xFB); //Wake On Radio Control
  155. cc1101->SpiWriteReg(CC1101_FREND0, 0x11); //Front End TX Configuration
  156. cc1101->SpiWriteReg(CC1101_FSCAL3, 0xE9); //Frequency Synthesizer Calibration
  157. cc1101->SpiWriteReg(CC1101_FSCAL2, 0x2A); //Frequency Synthesizer Calibration
  158. cc1101->SpiWriteReg(CC1101_FSCAL1, 0x00); //Frequency Synthesizer Calibration
  159. cc1101->SpiWriteReg(CC1101_FSCAL0, 0x1F); //Frequency Synthesizer Calibration
  160. /*
  161. cc1101->SpiWriteReg(CC1101_TEST2, 0x81); //Various Test Settings
  162. cc1101->SpiWriteReg(CC1101_TEST1, 0x35); //Various Test Settings
  163. cc1101->SpiWriteReg(CC1101_TEST0, 0x09); //Various Test Settings
  164. */
  165. }
  166. // f = (f_osc/65536) * (FREQ + CHAN * (256 + CH_SP_M) * 2^(CH_SP_E - 2))
  167. // FREQ = f / (f_osc/65536)
  168. // CHAN = 0
  169. // TODO: CHAN number not implemented!
  170. // TODO: reg values not affetcts
  171. const Band bands[] = {
  172. {300., {0x00, 0x00, 0x00}, 0, 255, 74},
  173. {315., {0x00, 0x00, 0x00}, 0, 255, 74},
  174. {348., {0x00, 0x00, 0x00}, 0, 255, 74},
  175. {386., {0x00, 0x00, 0x00}, 0, 255, 74},
  176. {433.92, {0x00, 0x00, 0x00}, 0, 255, 74},
  177. {438.9, {0x00, 0x00, 0x00}, 0, 255, 74},
  178. {464., {0x00, 0x00, 0x00}, 0, 255, 74},
  179. {779., {0x00, 0x00, 0x00}, 0, 255, 74},
  180. {868., {0x00, 0x00, 0x00}, 0, 255, 74},
  181. {915., {0x00, 0x00, 0x00}, 0, 255, 74},
  182. {928., {0x00, 0x00, 0x00}, 0, 255, 74},
  183. };
  184. const FreqConfig FREQ_LIST[] = {
  185. {&bands[0], 0},
  186. {&bands[1], 0},
  187. {&bands[2], 0},
  188. {&bands[3], 0},
  189. {&bands[4], 0},
  190. {&bands[5], 0},
  191. {&bands[6], 0},
  192. {&bands[7], 0},
  193. {&bands[8], 0},
  194. {&bands[9], 0},
  195. {&bands[10], 0},
  196. };
  197. extern "C" void cc1101_isr() {
  198. gpio_write((GpioPin*)&debug_0, gpio_read(&cc1101_g0_gpio));
  199. }
  200. typedef enum {
  201. EventTypeTick,
  202. EventTypeKey,
  203. } EventType;
  204. typedef struct {
  205. union {
  206. InputEvent input;
  207. } value;
  208. EventType type;
  209. } AppEvent;
  210. typedef enum { ModeRx, ModeTx } Mode;
  211. typedef struct {
  212. int16_t dbm;
  213. uint8_t reg;
  214. } TxLevel;
  215. const TxLevel TX_LEVELS[] = {
  216. {-10, 0},
  217. {-5, 0},
  218. {0, 0},
  219. {5, 0},
  220. };
  221. typedef struct {
  222. Mode mode;
  223. size_t active_freq_idx;
  224. float active_freq;
  225. int16_t last_rssi;
  226. size_t tx_level;
  227. bool need_cc1101_conf;
  228. } State;
  229. static void render_callback(Canvas* canvas, void* ctx) {
  230. State* state = (State*)acquire_mutex((ValueMutex*)ctx, 25);
  231. if(!state) return;
  232. canvas_clear(canvas);
  233. canvas_set_color(canvas, ColorBlack);
  234. canvas_set_font(canvas, FontPrimary);
  235. canvas_draw_str(canvas, 2, 12, "cc1101 workaround");
  236. {
  237. char buf[24];
  238. sprintf(
  239. buf,
  240. "freq: %ld.%02ld MHz",
  241. (uint32_t)state->active_freq,
  242. (uint32_t)(state->active_freq * 100.) % 100);
  243. canvas_set_font(canvas, FontSecondary);
  244. canvas_draw_str(canvas, 2, 25, buf);
  245. }
  246. {
  247. canvas_set_font(canvas, FontSecondary);
  248. if(state->need_cc1101_conf) {
  249. canvas_draw_str(canvas, 2, 36, "mode: configuring...");
  250. } else if(state->mode == ModeRx) {
  251. canvas_draw_str(canvas, 2, 36, "mode: RX");
  252. } else if(state->mode == ModeTx) {
  253. canvas_draw_str(canvas, 2, 36, "mode: TX");
  254. } else {
  255. canvas_draw_str(canvas, 2, 36, "mode: unknown");
  256. }
  257. }
  258. {
  259. if(!state->need_cc1101_conf && state->mode == ModeRx) {
  260. char buf[24];
  261. sprintf(buf, "RSSI: %d dBm", state->last_rssi);
  262. canvas_set_font(canvas, FontSecondary);
  263. canvas_draw_str(canvas, 2, 48, buf);
  264. }
  265. }
  266. {
  267. char buf[24];
  268. sprintf(buf, "tx level: %d dBm", TX_LEVELS[state->tx_level].dbm);
  269. canvas_set_font(canvas, FontSecondary);
  270. canvas_draw_str(canvas, 2, 63, buf);
  271. }
  272. release_mutex((ValueMutex*)ctx, state);
  273. }
  274. static void input_callback(InputEvent* input_event, void* ctx) {
  275. osMessageQueueId_t event_queue = ctx;
  276. AppEvent event;
  277. event.type = EventTypeKey;
  278. event.value.input = *input_event;
  279. osMessageQueuePut(event_queue, &event, 0, 0);
  280. }
  281. extern "C" void cc1101_workaround(void* p) {
  282. osMessageQueueId_t event_queue = osMessageQueueNew(1, sizeof(AppEvent), NULL);
  283. furi_check(event_queue);
  284. State _state;
  285. _state.mode = ModeRx;
  286. _state.active_freq_idx = 4;
  287. FreqConfig conf = FREQ_LIST[_state.active_freq_idx];
  288. _state.active_freq = conf.band->base_freq + CHAN_SPA * conf.channel;
  289. _state.need_cc1101_conf = true;
  290. _state.last_rssi = 0;
  291. _state.tx_level = 0;
  292. ValueMutex state_mutex;
  293. if(!init_mutex(&state_mutex, &_state, sizeof(State))) {
  294. printf("[cc1101] cannot create mutex\n");
  295. furiac_exit(NULL);
  296. }
  297. Widget* widget = widget_alloc();
  298. widget_draw_callback_set(widget, render_callback, &state_mutex);
  299. widget_input_callback_set(widget, input_callback, event_queue);
  300. // Open GUI and register widget
  301. Gui* gui = (Gui*)furi_record_open("gui");
  302. if(gui == NULL) {
  303. printf("[cc1101] gui is not available\n");
  304. furiac_exit(NULL);
  305. }
  306. gui_add_widget(gui, widget, GuiLayerFullscreen);
  307. gpio_init(&debug_0, GpioModeOutputPushPull);
  308. gpio_write((GpioPin*)&debug_0, false);
  309. printf("[cc1101] creating device\n");
  310. GpioPin cs_pin = {CC1101_CS_GPIO_Port, CC1101_CS_Pin};
  311. gpio_init(&cc1101_g0_gpio, GpioModeInput);
  312. // TODO open record
  313. GpioPin* cs_pin_record = &cs_pin;
  314. CC1101 cc1101(cs_pin_record);
  315. printf("[cc1101] init device\n");
  316. uint8_t address = cc1101.Init();
  317. if(address > 0) {
  318. printf("[cc1101] init done: %d\n", address);
  319. } else {
  320. printf("[cc1101] init fail\n");
  321. furiac_exit(NULL);
  322. }
  323. cc1101.SpiStrobe(CC1101_SIDLE);
  324. // flp_config(&cc1101);
  325. tx_config(&cc1101);
  326. // setup_freq(&cc1101, &FREQ_LIST[4]);
  327. // enable_cc1101_irq();
  328. printf("init ok\n");
  329. // TODO open record
  330. GpioPin* led_record = (GpioPin*)&led_gpio[1];
  331. // configure pin
  332. gpio_init(led_record, GpioModeOutputOpenDrain);
  333. const int16_t RSSI_THRESHOLD = -60;
  334. // setup_freq(&cc1101, &FREQ_LIST[1]);
  335. cc1101.SetReceive();
  336. AppEvent event;
  337. while(1) {
  338. osStatus_t event_status = osMessageQueueGet(event_queue, &event, NULL, 100);
  339. State* state = (State*)acquire_mutex_block(&state_mutex);
  340. if(event_status == osOK) {
  341. if(event.type == EventTypeKey) {
  342. if(event.value.input.state && event.value.input.input == InputBack) {
  343. printf("[cc1101] bye!\n");
  344. cli_print("[cc1101] bye!\n");
  345. cc1101.SpiStrobe(CC1101_SIDLE);
  346. cc1101.SpiStrobe(CC1101_SPWD);
  347. cli_print("[cc1101] go to power down\n");
  348. // TODO remove all widgets create by app
  349. widget_enabled_set(widget, false);
  350. furiac_exit(NULL);
  351. }
  352. if(event.value.input.state && event.value.input.input == InputDown) {
  353. if(state->active_freq_idx > 0) {
  354. state->active_freq_idx--;
  355. }
  356. FreqConfig conf = FREQ_LIST[state->active_freq_idx];
  357. state->active_freq = conf.band->base_freq + CHAN_SPA * conf.channel;
  358. state->need_cc1101_conf = true;
  359. }
  360. if(event.value.input.state && event.value.input.input == InputUp) {
  361. if(state->active_freq_idx < (sizeof(FREQ_LIST) / sizeof(FREQ_LIST[0]) - 1)) {
  362. state->active_freq_idx++;
  363. }
  364. FreqConfig conf = FREQ_LIST[state->active_freq_idx];
  365. state->active_freq = conf.band->base_freq + CHAN_SPA * conf.channel;
  366. state->need_cc1101_conf = true;
  367. }
  368. if(event.value.input.state && event.value.input.input == InputRight) {
  369. /*
  370. if(state->tx_level < (sizeof(TX_LEVELS) / sizeof(TX_LEVELS[0]) - 1)) {
  371. state->tx_level++;
  372. } else {
  373. state->tx_level = 0;
  374. }
  375. */
  376. state->active_freq += 0.25;
  377. state->need_cc1101_conf = true;
  378. }
  379. if(event.value.input.state && event.value.input.input == InputLeft) {
  380. /*
  381. if(state->tx_level < (sizeof(TX_LEVELS) / sizeof(TX_LEVELS[0]) - 1)) {
  382. state->tx_level++;
  383. } else {
  384. state->tx_level = 0;
  385. }
  386. */
  387. state->active_freq -= 0.25;
  388. state->need_cc1101_conf = true;
  389. }
  390. if(event.value.input.input == InputOk) {
  391. state->mode = event.value.input.state ? ModeTx : ModeRx;
  392. state->need_cc1101_conf = true;
  393. }
  394. }
  395. } else {
  396. }
  397. if(state->need_cc1101_conf) {
  398. if(state->mode == ModeRx) {
  399. cc1101.SpiStrobe(CC1101_SIDLE);
  400. gpio_init(&cc1101_g0_gpio, GpioModeInput);
  401. setup_freq(&cc1101, state->active_freq);
  402. cc1101.SetReceive();
  403. state->last_rssi = rx_rssi(&cc1101, &FREQ_LIST[state->active_freq_idx]);
  404. } else if(state->mode == ModeTx) {
  405. cc1101.SpiStrobe(CC1101_SIDLE);
  406. setup_freq(&cc1101, state->active_freq);
  407. cc1101.SetTransmit();
  408. gpio_init(&cc1101_g0_gpio, GpioModeOutputPushPull);
  409. gpio_write(&cc1101_g0_gpio, false);
  410. }
  411. state->need_cc1101_conf = false;
  412. }
  413. if(!state->need_cc1101_conf && state->mode == ModeRx) {
  414. // TOOD what about rssi offset
  415. state->last_rssi = rx_rssi(&cc1101, &FREQ_LIST[state->active_freq_idx]);
  416. gpio_write(led_record, state->last_rssi < RSSI_THRESHOLD);
  417. } else if(!state->need_cc1101_conf && state->mode == ModeTx) {
  418. /*
  419. const uint8_t data = 0xA5;
  420. for(uint8_t i = 0; i < 8; i++) {
  421. gpio_write(&cc1101_g0_gpio, (data & (1 << i)) > 0);
  422. osDelay(1);
  423. }
  424. gpio_write(&cc1101_g0_gpio, false);
  425. */
  426. /*
  427. // BELL UDB-Q022-0000
  428. const uint16_t HALF_PERIOD = 500;
  429. for(uint8_t n = 0; n < 4; n++) {
  430. for(uint8_t i = 0; i < 4; i++) {
  431. gpio_write(&cc1101_g0_gpio, true);
  432. delay_us(3 * HALF_PERIOD);
  433. gpio_write(&cc1101_g0_gpio, false);
  434. delay_us(HALF_PERIOD);
  435. }
  436. for(uint8_t i = 0; i < 40; i++) {
  437. gpio_write(&cc1101_g0_gpio, true);
  438. delay_us(HALF_PERIOD);
  439. gpio_write(&cc1101_g0_gpio, false);
  440. delay_us(HALF_PERIOD);
  441. }
  442. }
  443. */
  444. // BELL ERA C61, static code
  445. const uint16_t ONE_ON = 150;
  446. const uint16_t ONE_OFF = 400;
  447. const uint16_t ZERO_ON = 420;
  448. const uint16_t ZERO_OFF = 130;
  449. const bool SEQ[] = {true, true, false, false, true, false, true, false, true,
  450. false, true, true, true, false, true, false, true, true,
  451. true, true, true, false, true, false, true};
  452. for(uint8_t n = 0; n < 10; n++) {
  453. for(uint8_t i = 0; i < sizeof(SEQ) / sizeof(SEQ[0]); i++) {
  454. if(SEQ[i]) {
  455. gpio_write(&cc1101_g0_gpio, false);
  456. delay_us(ONE_ON);
  457. gpio_write(&cc1101_g0_gpio, true);
  458. delay_us(ONE_OFF);
  459. } else {
  460. gpio_write(&cc1101_g0_gpio, false);
  461. delay_us(ZERO_ON);
  462. gpio_write(&cc1101_g0_gpio, true);
  463. delay_us(ZERO_OFF);
  464. }
  465. }
  466. osDelay(4);
  467. }
  468. gpio_write(&cc1101_g0_gpio, false);
  469. }
  470. release_mutex(&state_mutex, state);
  471. widget_update(widget);
  472. }
  473. }