stm32f40g_eval.cfg 835 B

1234567891011121314151617181920212223242526272829
  1. # This is an STM3240G-EVAL board with a single STM32F407IGHx chip
  2. #
  3. # Generated by System Workbench for STM32
  4. # Take care that such file, as generated, may be overridden without any early notice. Please have a look to debug launch configuration setup(s)
  5. source [find interface/stlink.cfg]
  6. set WORKAREASIZE 0x8000
  7. transport select "hla_swd"
  8. set CHIPNAME STM32F407IGHx
  9. set BOARDNAME STM3240G-EVAL
  10. # Enable debug when in low power modes
  11. set ENABLE_LOW_POWER 1
  12. # Stop Watchdog counters when halt
  13. set STOP_WATCHDOG 1
  14. # STlink Debug clock frequency
  15. set CLOCK_FREQ 4000
  16. # use hardware reset, connect under reset
  17. # connect_assert_srst needed if low power mode application running (WFI...)
  18. reset_config srst_only srst_nogate connect_assert_srst
  19. set CONNECT_UNDER_RESET 1
  20. source [find target/stm32f4x.cfg]