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xdmac.h

xdmac.h 92 KB
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  1. /**
    2. 

  2.  * \file
    3. 

  3.  *
    4. 

  4.  * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
    5. 

  5.  *
    6. 

  6.  * \asf_license_start
    7. 

  7.  *
    8. 

  8.  * \page License
    9. 

  9.  *
    10. 

  10.  * Subject to your compliance with these terms, you may use Microchip
    11. 

  11.  * software and any derivatives exclusively with Microchip products.
    12. 

  12.  * It is your responsibility to comply with third party license terms applicable
    13. 

  13.  * to your use of third party software (including open source software) that
    14. 

  14.  * may accompany Microchip software.
    15. 

  15.  *
    16. 

  16.  * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
    17. 

  17.  * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
    18. 

  18.  * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
    19. 

  19.  * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
    20. 

  20.  * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
    21. 

  21.  * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
    22. 

  22.  * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
    23. 

  23.  * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
    24. 

  24.  * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
    25. 

  25.  * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
    26. 

  26.  * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
    27. 

  27.  *
    28. 

  28.  * \asf_license_stop
    29. 

  29.  *
    30. 

  30.  */
    31. 

  31. /*
    32. 

  32.  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
    33. 

  33.  */
    34. 

  34. 

  35. #ifndef _SAME70_XDMAC_INSTANCE_
    36. 

  36. #define _SAME70_XDMAC_INSTANCE_
    37. 

  37. 

  38. /* ========== Register definition for XDMAC peripheral ========== */
    39. 

  39. #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
    40. 

  40.   #define REG_XDMAC_GTYPE                      (0x40078000U) /**< \brief (XDMAC) Global Type Register */
    41. 

  41.   #define REG_XDMAC_GCFG                       (0x40078004U) /**< \brief (XDMAC) Global Configuration Register */
    42. 

  42.   #define REG_XDMAC_GWAC                       (0x40078008U) /**< \brief (XDMAC) Global Weighted Arbiter Configuration Register */
    43. 

  43.   #define REG_XDMAC_GIE                        (0x4007800CU) /**< \brief (XDMAC) Global Interrupt Enable Register */
    44. 

  44.   #define REG_XDMAC_GID                        (0x40078010U) /**< \brief (XDMAC) Global Interrupt Disable Register */
    45. 

  45.   #define REG_XDMAC_GIM                        (0x40078014U) /**< \brief (XDMAC) Global Interrupt Mask Register */
    46. 

  46.   #define REG_XDMAC_GIS                        (0x40078018U) /**< \brief (XDMAC) Global Interrupt Status Register */
    47. 

  47.   #define REG_XDMAC_GE                         (0x4007801CU) /**< \brief (XDMAC) Global Channel Enable Register */
    48. 

  48.   #define REG_XDMAC_GD                         (0x40078020U) /**< \brief (XDMAC) Global Channel Disable Register */
    49. 

  49.   #define REG_XDMAC_GS                         (0x40078024U) /**< \brief (XDMAC) Global Channel Status Register */
    50. 

  50.   #define REG_XDMAC_GRS                        (0x40078028U) /**< \brief (XDMAC) Global Channel Read Suspend Register */
    51. 

  51.   #define REG_XDMAC_GWS                        (0x4007802CU) /**< \brief (XDMAC) Global Channel Write Suspend Register */
    52. 

  52.   #define REG_XDMAC_GRWS                       (0x40078030U) /**< \brief (XDMAC) Global Channel Read Write Suspend Register */
    53. 

  53.   #define REG_XDMAC_GRWR                       (0x40078034U) /**< \brief (XDMAC) Global Channel Read Write Resume Register */
    54. 

  54.   #define REG_XDMAC_GSWR                       (0x40078038U) /**< \brief (XDMAC) Global Channel Software Request Register */
    55. 

  55.   #define REG_XDMAC_GSWS                       (0x4007803CU) /**< \brief (XDMAC) Global Channel Software Request Status Register */
    56. 

  56.   #define REG_XDMAC_GSWF                       (0x40078040U) /**< \brief (XDMAC) Global Channel Software Flush Request Register */
    57. 

  57.   #define REG_XDMAC_CIE0                       (0x40078050U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 0) */
    58. 

  58.   #define REG_XDMAC_CID0                       (0x40078054U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 0) */
    59. 

  59.   #define REG_XDMAC_CIM0                       (0x40078058U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 0) */
    60. 

  60.   #define REG_XDMAC_CIS0                       (0x4007805CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 0) */
    61. 

  61.   #define REG_XDMAC_CSA0                       (0x40078060U) /**< \brief (XDMAC) Channel Source Address Register (chid = 0) */
    62. 

  62.   #define REG_XDMAC_CDA0                       (0x40078064U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 0) */
    63. 

  63.   #define REG_XDMAC_CNDA0                      (0x40078068U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 0) */
    64. 

  64.   #define REG_XDMAC_CNDC0                      (0x4007806CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 0) */
    65. 

  65.   #define REG_XDMAC_CUBC0                      (0x40078070U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 0) */
    66. 

  66.   #define REG_XDMAC_CBC0                       (0x40078074U) /**< \brief (XDMAC) Channel Block Control Register (chid = 0) */
    67. 

  67.   #define REG_XDMAC_CC0                        (0x40078078U) /**< \brief (XDMAC) Channel Configuration Register (chid = 0) */
    68. 

  68.   #define REG_XDMAC_CDS_MSP0                   (0x4007807CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) */
    69. 

  69.   #define REG_XDMAC_CSUS0                      (0x40078080U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 0) */
    70. 

  70.   #define REG_XDMAC_CDUS0                      (0x40078084U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 0) */
    71. 

  71.   #define REG_XDMAC_CIE1                       (0x40078090U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 1) */
    72. 

  72.   #define REG_XDMAC_CID1                       (0x40078094U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 1) */
    73. 

  73.   #define REG_XDMAC_CIM1                       (0x40078098U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 1) */
    74. 

  74.   #define REG_XDMAC_CIS1                       (0x4007809CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 1) */
    75. 

  75.   #define REG_XDMAC_CSA1                       (0x400780A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 1) */
    76. 

  76.   #define REG_XDMAC_CDA1                       (0x400780A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 1) */
    77. 

  77.   #define REG_XDMAC_CNDA1                      (0x400780A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 1) */
    78. 

  78.   #define REG_XDMAC_CNDC1                      (0x400780ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 1) */
    79. 

  79.   #define REG_XDMAC_CUBC1                      (0x400780B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 1) */
    80. 

  80.   #define REG_XDMAC_CBC1                       (0x400780B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 1) */
    81. 

  81.   #define REG_XDMAC_CC1                        (0x400780B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 1) */
    82. 

  82.   #define REG_XDMAC_CDS_MSP1                   (0x400780BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 1) */
    83. 

  83.   #define REG_XDMAC_CSUS1                      (0x400780C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 1) */
    84. 

  84.   #define REG_XDMAC_CDUS1                      (0x400780C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 1) */
    85. 

  85.   #define REG_XDMAC_CIE2                       (0x400780D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 2) */
    86. 

  86.   #define REG_XDMAC_CID2                       (0x400780D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 2) */
    87. 

  87.   #define REG_XDMAC_CIM2                       (0x400780D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 2) */
    88. 

  88.   #define REG_XDMAC_CIS2                       (0x400780DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 2) */
    89. 

  89.   #define REG_XDMAC_CSA2                       (0x400780E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 2) */
    90. 

  90.   #define REG_XDMAC_CDA2                       (0x400780E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 2) */
    91. 

  91.   #define REG_XDMAC_CNDA2                      (0x400780E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 2) */
    92. 

  92.   #define REG_XDMAC_CNDC2                      (0x400780ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 2) */
    93. 

  93.   #define REG_XDMAC_CUBC2                      (0x400780F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 2) */
    94. 

  94.   #define REG_XDMAC_CBC2                       (0x400780F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 2) */
    95. 

  95.   #define REG_XDMAC_CC2                        (0x400780F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 2) */
    96. 

  96.   #define REG_XDMAC_CDS_MSP2                   (0x400780FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 2) */
    97. 

  97.   #define REG_XDMAC_CSUS2                      (0x40078100U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 2) */
    98. 

  98.   #define REG_XDMAC_CDUS2                      (0x40078104U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 2) */
    99. 

  99.   #define REG_XDMAC_CIE3                       (0x40078110U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 3) */
    100. 

  100.   #define REG_XDMAC_CID3                       (0x40078114U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 3) */
    101. 

  101.   #define REG_XDMAC_CIM3                       (0x40078118U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 3) */
    102. 

  102.   #define REG_XDMAC_CIS3                       (0x4007811CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 3) */
    103. 

  103.   #define REG_XDMAC_CSA3                       (0x40078120U) /**< \brief (XDMAC) Channel Source Address Register (chid = 3) */
    104. 

  104.   #define REG_XDMAC_CDA3                       (0x40078124U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 3) */
    105. 

  105.   #define REG_XDMAC_CNDA3                      (0x40078128U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 3) */
    106. 

  106.   #define REG_XDMAC_CNDC3                      (0x4007812CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 3) */
    107. 

  107.   #define REG_XDMAC_CUBC3                      (0x40078130U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 3) */
    108. 

  108.   #define REG_XDMAC_CBC3                       (0x40078134U) /**< \brief (XDMAC) Channel Block Control Register (chid = 3) */
    109. 

  109.   #define REG_XDMAC_CC3                        (0x40078138U) /**< \brief (XDMAC) Channel Configuration Register (chid = 3) */
    110. 

  110.   #define REG_XDMAC_CDS_MSP3                   (0x4007813CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 3) */
    111. 

  111.   #define REG_XDMAC_CSUS3                      (0x40078140U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 3) */
    112. 

  112.   #define REG_XDMAC_CDUS3                      (0x40078144U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 3) */
    113. 

  113.   #define REG_XDMAC_CIE4                       (0x40078150U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 4) */
    114. 

  114.   #define REG_XDMAC_CID4                       (0x40078154U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 4) */
    115. 

  115.   #define REG_XDMAC_CIM4                       (0x40078158U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 4) */
    116. 

  116.   #define REG_XDMAC_CIS4                       (0x4007815CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 4) */
    117. 

  117.   #define REG_XDMAC_CSA4                       (0x40078160U) /**< \brief (XDMAC) Channel Source Address Register (chid = 4) */
    118. 

  118.   #define REG_XDMAC_CDA4                       (0x40078164U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 4) */
    119. 

  119.   #define REG_XDMAC_CNDA4                      (0x40078168U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 4) */
    120. 

  120.   #define REG_XDMAC_CNDC4                      (0x4007816CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 4) */
    121. 

  121.   #define REG_XDMAC_CUBC4                      (0x40078170U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 4) */
    122. 

  122.   #define REG_XDMAC_CBC4                       (0x40078174U) /**< \brief (XDMAC) Channel Block Control Register (chid = 4) */
    123. 

  123.   #define REG_XDMAC_CC4                        (0x40078178U) /**< \brief (XDMAC) Channel Configuration Register (chid = 4) */
    124. 

  124.   #define REG_XDMAC_CDS_MSP4                   (0x4007817CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 4) */
    125. 

  125.   #define REG_XDMAC_CSUS4                      (0x40078180U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 4) */
    126. 

  126.   #define REG_XDMAC_CDUS4                      (0x40078184U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 4) */
    127. 

  127.   #define REG_XDMAC_CIE5                       (0x40078190U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 5) */
    128. 

  128.   #define REG_XDMAC_CID5                       (0x40078194U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 5) */
    129. 

  129.   #define REG_XDMAC_CIM5                       (0x40078198U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 5) */
    130. 

  130.   #define REG_XDMAC_CIS5                       (0x4007819CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 5) */
    131. 

  131.   #define REG_XDMAC_CSA5                       (0x400781A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 5) */
    132. 

  132.   #define REG_XDMAC_CDA5                       (0x400781A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 5) */
    133. 

  133.   #define REG_XDMAC_CNDA5                      (0x400781A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 5) */
    134. 

  134.   #define REG_XDMAC_CNDC5                      (0x400781ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 5) */
    135. 

  135.   #define REG_XDMAC_CUBC5                      (0x400781B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 5) */
    136. 

  136.   #define REG_XDMAC_CBC5                       (0x400781B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 5) */
    137. 

  137.   #define REG_XDMAC_CC5                        (0x400781B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 5) */
    138. 

  138.   #define REG_XDMAC_CDS_MSP5                   (0x400781BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 5) */
    139. 

  139.   #define REG_XDMAC_CSUS5                      (0x400781C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 5) */
    140. 

  140.   #define REG_XDMAC_CDUS5                      (0x400781C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 5) */
    141. 

  141.   #define REG_XDMAC_CIE6                       (0x400781D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 6) */
    142. 

  142.   #define REG_XDMAC_CID6                       (0x400781D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 6) */
    143. 

  143.   #define REG_XDMAC_CIM6                       (0x400781D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 6) */
    144. 

  144.   #define REG_XDMAC_CIS6                       (0x400781DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 6) */
    145. 

  145.   #define REG_XDMAC_CSA6                       (0x400781E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 6) */
    146. 

  146.   #define REG_XDMAC_CDA6                       (0x400781E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 6) */
    147. 

  147.   #define REG_XDMAC_CNDA6                      (0x400781E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 6) */
    148. 

  148.   #define REG_XDMAC_CNDC6                      (0x400781ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 6) */
    149. 

  149.   #define REG_XDMAC_CUBC6                      (0x400781F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 6) */
    150. 

  150.   #define REG_XDMAC_CBC6                       (0x400781F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 6) */
    151. 

  151.   #define REG_XDMAC_CC6                        (0x400781F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 6) */
    152. 

  152.   #define REG_XDMAC_CDS_MSP6                   (0x400781FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 6) */
    153. 

  153.   #define REG_XDMAC_CSUS6                      (0x40078200U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 6) */
    154. 

  154.   #define REG_XDMAC_CDUS6                      (0x40078204U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 6) */
    155. 

  155.   #define REG_XDMAC_CIE7                       (0x40078210U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 7) */
    156. 

  156.   #define REG_XDMAC_CID7                       (0x40078214U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 7) */
    157. 

  157.   #define REG_XDMAC_CIM7                       (0x40078218U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 7) */
    158. 

  158.   #define REG_XDMAC_CIS7                       (0x4007821CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 7) */
    159. 

  159.   #define REG_XDMAC_CSA7                       (0x40078220U) /**< \brief (XDMAC) Channel Source Address Register (chid = 7) */
    160. 

  160.   #define REG_XDMAC_CDA7                       (0x40078224U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 7) */
    161. 

  161.   #define REG_XDMAC_CNDA7                      (0x40078228U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 7) */
    162. 

  162.   #define REG_XDMAC_CNDC7                      (0x4007822CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 7) */
    163. 

  163.   #define REG_XDMAC_CUBC7                      (0x40078230U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 7) */
    164. 

  164.   #define REG_XDMAC_CBC7                       (0x40078234U) /**< \brief (XDMAC) Channel Block Control Register (chid = 7) */
    165. 

  165.   #define REG_XDMAC_CC7                        (0x40078238U) /**< \brief (XDMAC) Channel Configuration Register (chid = 7) */
    166. 

  166.   #define REG_XDMAC_CDS_MSP7                   (0x4007823CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 7) */
    167. 

  167.   #define REG_XDMAC_CSUS7                      (0x40078240U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 7) */
    168. 

  168.   #define REG_XDMAC_CDUS7                      (0x40078244U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 7) */
    169. 

  169.   #define REG_XDMAC_CIE8                       (0x40078250U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 8) */
    170. 

  170.   #define REG_XDMAC_CID8                       (0x40078254U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 8) */
    171. 

  171.   #define REG_XDMAC_CIM8                       (0x40078258U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 8) */
    172. 

  172.   #define REG_XDMAC_CIS8                       (0x4007825CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 8) */
    173. 

  173.   #define REG_XDMAC_CSA8                       (0x40078260U) /**< \brief (XDMAC) Channel Source Address Register (chid = 8) */
    174. 

  174.   #define REG_XDMAC_CDA8                       (0x40078264U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 8) */
    175. 

  175.   #define REG_XDMAC_CNDA8                      (0x40078268U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 8) */
    176. 

  176.   #define REG_XDMAC_CNDC8                      (0x4007826CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 8) */
    177. 

  177.   #define REG_XDMAC_CUBC8                      (0x40078270U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 8) */
    178. 

  178.   #define REG_XDMAC_CBC8                       (0x40078274U) /**< \brief (XDMAC) Channel Block Control Register (chid = 8) */
    179. 

  179.   #define REG_XDMAC_CC8                        (0x40078278U) /**< \brief (XDMAC) Channel Configuration Register (chid = 8) */
    180. 

  180.   #define REG_XDMAC_CDS_MSP8                   (0x4007827CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 8) */
    181. 

  181.   #define REG_XDMAC_CSUS8                      (0x40078280U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 8) */
    182. 

  182.   #define REG_XDMAC_CDUS8                      (0x40078284U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 8) */
    183. 

  183.   #define REG_XDMAC_CIE9                       (0x40078290U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 9) */
    184. 

  184.   #define REG_XDMAC_CID9                       (0x40078294U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 9) */
    185. 

  185.   #define REG_XDMAC_CIM9                       (0x40078298U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 9) */
    186. 

  186.   #define REG_XDMAC_CIS9                       (0x4007829CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 9) */
    187. 

  187.   #define REG_XDMAC_CSA9                       (0x400782A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 9) */
    188. 

  188.   #define REG_XDMAC_CDA9                       (0x400782A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 9) */
    189. 

  189.   #define REG_XDMAC_CNDA9                      (0x400782A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 9) */
    190. 

  190.   #define REG_XDMAC_CNDC9                      (0x400782ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 9) */
    191. 

  191.   #define REG_XDMAC_CUBC9                      (0x400782B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 9) */
    192. 

  192.   #define REG_XDMAC_CBC9                       (0x400782B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 9) */
    193. 

  193.   #define REG_XDMAC_CC9                        (0x400782B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 9) */
    194. 

  194.   #define REG_XDMAC_CDS_MSP9                   (0x400782BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 9) */
    195. 

  195.   #define REG_XDMAC_CSUS9                      (0x400782C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 9) */
    196. 

  196.   #define REG_XDMAC_CDUS9                      (0x400782C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 9) */
    197. 

  197.   #define REG_XDMAC_CIE10                      (0x400782D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 10) */
    198. 

  198.   #define REG_XDMAC_CID10                      (0x400782D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 10) */
    199. 

  199.   #define REG_XDMAC_CIM10                      (0x400782D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 10) */
    200. 

  200.   #define REG_XDMAC_CIS10                      (0x400782DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 10) */
    201. 

  201.   #define REG_XDMAC_CSA10                      (0x400782E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 10) */
    202. 

  202.   #define REG_XDMAC_CDA10                      (0x400782E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 10) */
    203. 

  203.   #define REG_XDMAC_CNDA10                     (0x400782E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 10) */
    204. 

  204.   #define REG_XDMAC_CNDC10                     (0x400782ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 10) */
    205. 

  205.   #define REG_XDMAC_CUBC10                     (0x400782F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 10) */
    206. 

  206.   #define REG_XDMAC_CBC10                      (0x400782F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 10) */
    207. 

  207.   #define REG_XDMAC_CC10                       (0x400782F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 10) */
    208. 

  208.   #define REG_XDMAC_CDS_MSP10                  (0x400782FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 10) */
    209. 

  209.   #define REG_XDMAC_CSUS10                     (0x40078300U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 10) */
    210. 

  210.   #define REG_XDMAC_CDUS10                     (0x40078304U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 10) */
    211. 

  211.   #define REG_XDMAC_CIE11                      (0x40078310U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 11) */
    212. 

  212.   #define REG_XDMAC_CID11                      (0x40078314U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 11) */
    213. 

  213.   #define REG_XDMAC_CIM11                      (0x40078318U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 11) */
    214. 

  214.   #define REG_XDMAC_CIS11                      (0x4007831CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 11) */
    215. 

  215.   #define REG_XDMAC_CSA11                      (0x40078320U) /**< \brief (XDMAC) Channel Source Address Register (chid = 11) */
    216. 

  216.   #define REG_XDMAC_CDA11                      (0x40078324U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 11) */
    217. 

  217.   #define REG_XDMAC_CNDA11                     (0x40078328U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 11) */
    218. 

  218.   #define REG_XDMAC_CNDC11                     (0x4007832CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 11) */
    219. 

  219.   #define REG_XDMAC_CUBC11                     (0x40078330U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 11) */
    220. 

  220.   #define REG_XDMAC_CBC11                      (0x40078334U) /**< \brief (XDMAC) Channel Block Control Register (chid = 11) */
    221. 

  221.   #define REG_XDMAC_CC11                       (0x40078338U) /**< \brief (XDMAC) Channel Configuration Register (chid = 11) */
    222. 

  222.   #define REG_XDMAC_CDS_MSP11                  (0x4007833CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 11) */
    223. 

  223.   #define REG_XDMAC_CSUS11                     (0x40078340U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 11) */
    224. 

  224.   #define REG_XDMAC_CDUS11                     (0x40078344U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 11) */
    225. 

  225.   #define REG_XDMAC_CIE12                      (0x40078350U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 12) */
    226. 

  226.   #define REG_XDMAC_CID12                      (0x40078354U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 12) */
    227. 

  227.   #define REG_XDMAC_CIM12                      (0x40078358U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 12) */
    228. 

  228.   #define REG_XDMAC_CIS12                      (0x4007835CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 12) */
    229. 

  229.   #define REG_XDMAC_CSA12                      (0x40078360U) /**< \brief (XDMAC) Channel Source Address Register (chid = 12) */
    230. 

  230.   #define REG_XDMAC_CDA12                      (0x40078364U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 12) */
    231. 

  231.   #define REG_XDMAC_CNDA12                     (0x40078368U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 12) */
    232. 

  232.   #define REG_XDMAC_CNDC12                     (0x4007836CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 12) */
    233. 

  233.   #define REG_XDMAC_CUBC12                     (0x40078370U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 12) */
    234. 

  234.   #define REG_XDMAC_CBC12                      (0x40078374U) /**< \brief (XDMAC) Channel Block Control Register (chid = 12) */
    235. 

  235.   #define REG_XDMAC_CC12                       (0x40078378U) /**< \brief (XDMAC) Channel Configuration Register (chid = 12) */
    236. 

  236.   #define REG_XDMAC_CDS_MSP12                  (0x4007837CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 12) */
    237. 

  237.   #define REG_XDMAC_CSUS12                     (0x40078380U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 12) */
    238. 

  238.   #define REG_XDMAC_CDUS12                     (0x40078384U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 12) */
    239. 

  239.   #define REG_XDMAC_CIE13                      (0x40078390U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 13) */
    240. 

  240.   #define REG_XDMAC_CID13                      (0x40078394U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 13) */
    241. 

  241.   #define REG_XDMAC_CIM13                      (0x40078398U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 13) */
    242. 

  242.   #define REG_XDMAC_CIS13                      (0x4007839CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 13) */
    243. 

  243.   #define REG_XDMAC_CSA13                      (0x400783A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 13) */
    244. 

  244.   #define REG_XDMAC_CDA13                      (0x400783A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 13) */
    245. 

  245.   #define REG_XDMAC_CNDA13                     (0x400783A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 13) */
    246. 

  246.   #define REG_XDMAC_CNDC13                     (0x400783ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 13) */
    247. 

  247.   #define REG_XDMAC_CUBC13                     (0x400783B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 13) */
    248. 

  248.   #define REG_XDMAC_CBC13                      (0x400783B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 13) */
    249. 

  249.   #define REG_XDMAC_CC13                       (0x400783B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 13) */
    250. 

  250.   #define REG_XDMAC_CDS_MSP13                  (0x400783BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 13) */
    251. 

  251.   #define REG_XDMAC_CSUS13                     (0x400783C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 13) */
    252. 

  252.   #define REG_XDMAC_CDUS13                     (0x400783C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 13) */
    253. 

  253.   #define REG_XDMAC_CIE14                      (0x400783D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 14) */
    254. 

  254.   #define REG_XDMAC_CID14                      (0x400783D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 14) */
    255. 

  255.   #define REG_XDMAC_CIM14                      (0x400783D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 14) */
    256. 

  256.   #define REG_XDMAC_CIS14                      (0x400783DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 14) */
    257. 

  257.   #define REG_XDMAC_CSA14                      (0x400783E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 14) */
    258. 

  258.   #define REG_XDMAC_CDA14                      (0x400783E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 14) */
    259. 

  259.   #define REG_XDMAC_CNDA14                     (0x400783E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 14) */
    260. 

  260.   #define REG_XDMAC_CNDC14                     (0x400783ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 14) */
    261. 

  261.   #define REG_XDMAC_CUBC14                     (0x400783F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 14) */
    262. 

  262.   #define REG_XDMAC_CBC14                      (0x400783F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 14) */
    263. 

  263.   #define REG_XDMAC_CC14                       (0x400783F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 14) */
    264. 

  264.   #define REG_XDMAC_CDS_MSP14                  (0x400783FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 14) */
    265. 

  265.   #define REG_XDMAC_CSUS14                     (0x40078400U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 14) */
    266. 

  266.   #define REG_XDMAC_CDUS14                     (0x40078404U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 14) */
    267. 

  267.   #define REG_XDMAC_CIE15                      (0x40078410U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 15) */
    268. 

  268.   #define REG_XDMAC_CID15                      (0x40078414U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 15) */
    269. 

  269.   #define REG_XDMAC_CIM15                      (0x40078418U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 15) */
    270. 

  270.   #define REG_XDMAC_CIS15                      (0x4007841CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 15) */
    271. 

  271.   #define REG_XDMAC_CSA15                      (0x40078420U) /**< \brief (XDMAC) Channel Source Address Register (chid = 15) */
    272. 

  272.   #define REG_XDMAC_CDA15                      (0x40078424U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 15) */
    273. 

  273.   #define REG_XDMAC_CNDA15                     (0x40078428U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 15) */
    274. 

  274.   #define REG_XDMAC_CNDC15                     (0x4007842CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 15) */
    275. 

  275.   #define REG_XDMAC_CUBC15                     (0x40078430U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 15) */
    276. 

  276.   #define REG_XDMAC_CBC15                      (0x40078434U) /**< \brief (XDMAC) Channel Block Control Register (chid = 15) */
    277. 

  277.   #define REG_XDMAC_CC15                       (0x40078438U) /**< \brief (XDMAC) Channel Configuration Register (chid = 15) */
    278. 

  278.   #define REG_XDMAC_CDS_MSP15                  (0x4007843CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 15) */
    279. 

  279.   #define REG_XDMAC_CSUS15                     (0x40078440U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 15) */
    280. 

  280.   #define REG_XDMAC_CDUS15                     (0x40078444U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 15) */
    281. 

  281.   #define REG_XDMAC_CIE16                      (0x40078450U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 16) */
    282. 

  282.   #define REG_XDMAC_CID16                      (0x40078454U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 16) */
    283. 

  283.   #define REG_XDMAC_CIM16                      (0x40078458U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 16) */
    284. 

  284.   #define REG_XDMAC_CIS16                      (0x4007845CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 16) */
    285. 

  285.   #define REG_XDMAC_CSA16                      (0x40078460U) /**< \brief (XDMAC) Channel Source Address Register (chid = 16) */
    286. 

  286.   #define REG_XDMAC_CDA16                      (0x40078464U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 16) */
    287. 

  287.   #define REG_XDMAC_CNDA16                     (0x40078468U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 16) */
    288. 

  288.   #define REG_XDMAC_CNDC16                     (0x4007846CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 16) */
    289. 

  289.   #define REG_XDMAC_CUBC16                     (0x40078470U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 16) */
    290. 

  290.   #define REG_XDMAC_CBC16                      (0x40078474U) /**< \brief (XDMAC) Channel Block Control Register (chid = 16) */
    291. 

  291.   #define REG_XDMAC_CC16                       (0x40078478U) /**< \brief (XDMAC) Channel Configuration Register (chid = 16) */
    292. 

  292.   #define REG_XDMAC_CDS_MSP16                  (0x4007847CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 16) */
    293. 

  293.   #define REG_XDMAC_CSUS16                     (0x40078480U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 16) */
    294. 

  294.   #define REG_XDMAC_CDUS16                     (0x40078484U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 16) */
    295. 

  295.   #define REG_XDMAC_CIE17                      (0x40078490U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 17) */
    296. 

  296.   #define REG_XDMAC_CID17                      (0x40078494U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 17) */
    297. 

  297.   #define REG_XDMAC_CIM17                      (0x40078498U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 17) */
    298. 

  298.   #define REG_XDMAC_CIS17                      (0x4007849CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 17) */
    299. 

  299.   #define REG_XDMAC_CSA17                      (0x400784A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 17) */
    300. 

  300.   #define REG_XDMAC_CDA17                      (0x400784A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 17) */
    301. 

  301.   #define REG_XDMAC_CNDA17                     (0x400784A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 17) */
    302. 

  302.   #define REG_XDMAC_CNDC17                     (0x400784ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 17) */
    303. 

  303.   #define REG_XDMAC_CUBC17                     (0x400784B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 17) */
    304. 

  304.   #define REG_XDMAC_CBC17                      (0x400784B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 17) */
    305. 

  305.   #define REG_XDMAC_CC17                       (0x400784B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 17) */
    306. 

  306.   #define REG_XDMAC_CDS_MSP17                  (0x400784BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 17) */
    307. 

  307.   #define REG_XDMAC_CSUS17                     (0x400784C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 17) */
    308. 

  308.   #define REG_XDMAC_CDUS17                     (0x400784C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 17) */
    309. 

  309.   #define REG_XDMAC_CIE18                      (0x400784D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 18) */
    310. 

  310.   #define REG_XDMAC_CID18                      (0x400784D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 18) */
    311. 

  311.   #define REG_XDMAC_CIM18                      (0x400784D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 18) */
    312. 

  312.   #define REG_XDMAC_CIS18                      (0x400784DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 18) */
    313. 

  313.   #define REG_XDMAC_CSA18                      (0x400784E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 18) */
    314. 

  314.   #define REG_XDMAC_CDA18                      (0x400784E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 18) */
    315. 

  315.   #define REG_XDMAC_CNDA18                     (0x400784E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 18) */
    316. 

  316.   #define REG_XDMAC_CNDC18                     (0x400784ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 18) */
    317. 

  317.   #define REG_XDMAC_CUBC18                     (0x400784F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 18) */
    318. 

  318.   #define REG_XDMAC_CBC18                      (0x400784F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 18) */
    319. 

  319.   #define REG_XDMAC_CC18                       (0x400784F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 18) */
    320. 

  320.   #define REG_XDMAC_CDS_MSP18                  (0x400784FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 18) */
    321. 

  321.   #define REG_XDMAC_CSUS18                     (0x40078500U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 18) */
    322. 

  322.   #define REG_XDMAC_CDUS18                     (0x40078504U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 18) */
    323. 

  323.   #define REG_XDMAC_CIE19                      (0x40078510U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 19) */
    324. 

  324.   #define REG_XDMAC_CID19                      (0x40078514U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 19) */
    325. 

  325.   #define REG_XDMAC_CIM19                      (0x40078518U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 19) */
    326. 

  326.   #define REG_XDMAC_CIS19                      (0x4007851CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 19) */
    327. 

  327.   #define REG_XDMAC_CSA19                      (0x40078520U) /**< \brief (XDMAC) Channel Source Address Register (chid = 19) */
    328. 

  328.   #define REG_XDMAC_CDA19                      (0x40078524U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 19) */
    329. 

  329.   #define REG_XDMAC_CNDA19                     (0x40078528U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 19) */
    330. 

  330.   #define REG_XDMAC_CNDC19                     (0x4007852CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 19) */
    331. 

  331.   #define REG_XDMAC_CUBC19                     (0x40078530U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 19) */
    332. 

  332.   #define REG_XDMAC_CBC19                      (0x40078534U) /**< \brief (XDMAC) Channel Block Control Register (chid = 19) */
    333. 

  333.   #define REG_XDMAC_CC19                       (0x40078538U) /**< \brief (XDMAC) Channel Configuration Register (chid = 19) */
    334. 

  334.   #define REG_XDMAC_CDS_MSP19                  (0x4007853CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 19) */
    335. 

  335.   #define REG_XDMAC_CSUS19                     (0x40078540U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 19) */
    336. 

  336.   #define REG_XDMAC_CDUS19                     (0x40078544U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 19) */
    337. 

  337.   #define REG_XDMAC_CIE20                      (0x40078550U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 20) */
    338. 

  338.   #define REG_XDMAC_CID20                      (0x40078554U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 20) */
    339. 

  339.   #define REG_XDMAC_CIM20                      (0x40078558U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 20) */
    340. 

  340.   #define REG_XDMAC_CIS20                      (0x4007855CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 20) */
    341. 

  341.   #define REG_XDMAC_CSA20                      (0x40078560U) /**< \brief (XDMAC) Channel Source Address Register (chid = 20) */
    342. 

  342.   #define REG_XDMAC_CDA20                      (0x40078564U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 20) */
    343. 

  343.   #define REG_XDMAC_CNDA20                     (0x40078568U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 20) */
    344. 

  344.   #define REG_XDMAC_CNDC20                     (0x4007856CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 20) */
    345. 

  345.   #define REG_XDMAC_CUBC20                     (0x40078570U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 20) */
    346. 

  346.   #define REG_XDMAC_CBC20                      (0x40078574U) /**< \brief (XDMAC) Channel Block Control Register (chid = 20) */
    347. 

  347.   #define REG_XDMAC_CC20                       (0x40078578U) /**< \brief (XDMAC) Channel Configuration Register (chid = 20) */
    348. 

  348.   #define REG_XDMAC_CDS_MSP20                  (0x4007857CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 20) */
    349. 

  349.   #define REG_XDMAC_CSUS20                     (0x40078580U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 20) */
    350. 

  350.   #define REG_XDMAC_CDUS20                     (0x40078584U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 20) */
    351. 

  351.   #define REG_XDMAC_CIE21                      (0x40078590U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 21) */
    352. 

  352.   #define REG_XDMAC_CID21                      (0x40078594U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 21) */
    353. 

  353.   #define REG_XDMAC_CIM21                      (0x40078598U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 21) */
    354. 

  354.   #define REG_XDMAC_CIS21                      (0x4007859CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 21) */
    355. 

  355.   #define REG_XDMAC_CSA21                      (0x400785A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 21) */
    356. 

  356.   #define REG_XDMAC_CDA21                      (0x400785A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 21) */
    357. 

  357.   #define REG_XDMAC_CNDA21                     (0x400785A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 21) */
    358. 

  358.   #define REG_XDMAC_CNDC21                     (0x400785ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 21) */
    359. 

  359.   #define REG_XDMAC_CUBC21                     (0x400785B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 21) */
    360. 

  360.   #define REG_XDMAC_CBC21                      (0x400785B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 21) */
    361. 

  361.   #define REG_XDMAC_CC21                       (0x400785B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 21) */
    362. 

  362.   #define REG_XDMAC_CDS_MSP21                  (0x400785BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 21) */
    363. 

  363.   #define REG_XDMAC_CSUS21                     (0x400785C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 21) */
    364. 

  364.   #define REG_XDMAC_CDUS21                     (0x400785C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 21) */
    365. 

  365.   #define REG_XDMAC_CIE22                      (0x400785D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 22) */
    366. 

  366.   #define REG_XDMAC_CID22                      (0x400785D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 22) */
    367. 

  367.   #define REG_XDMAC_CIM22                      (0x400785D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 22) */
    368. 

  368.   #define REG_XDMAC_CIS22                      (0x400785DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 22) */
    369. 

  369.   #define REG_XDMAC_CSA22                      (0x400785E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 22) */
    370. 

  370.   #define REG_XDMAC_CDA22                      (0x400785E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 22) */
    371. 

  371.   #define REG_XDMAC_CNDA22                     (0x400785E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 22) */
    372. 

  372.   #define REG_XDMAC_CNDC22                     (0x400785ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 22) */
    373. 

  373.   #define REG_XDMAC_CUBC22                     (0x400785F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 22) */
    374. 

  374.   #define REG_XDMAC_CBC22                      (0x400785F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 22) */
    375. 

  375.   #define REG_XDMAC_CC22                       (0x400785F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 22) */
    376. 

  376.   #define REG_XDMAC_CDS_MSP22                  (0x400785FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 22) */
    377. 

  377.   #define REG_XDMAC_CSUS22                     (0x40078600U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 22) */
    378. 

  378.   #define REG_XDMAC_CDUS22                     (0x40078604U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 22) */
    379. 

  379.   #define REG_XDMAC_CIE23                      (0x40078610U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 23) */
    380. 

  380.   #define REG_XDMAC_CID23                      (0x40078614U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 23) */
    381. 

  381.   #define REG_XDMAC_CIM23                      (0x40078618U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 23) */
    382. 

  382.   #define REG_XDMAC_CIS23                      (0x4007861CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 23) */
    383. 

  383.   #define REG_XDMAC_CSA23                      (0x40078620U) /**< \brief (XDMAC) Channel Source Address Register (chid = 23) */
    384. 

  384.   #define REG_XDMAC_CDA23                      (0x40078624U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 23) */
    385. 

  385.   #define REG_XDMAC_CNDA23                     (0x40078628U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 23) */
    386. 

  386.   #define REG_XDMAC_CNDC23                     (0x4007862CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 23) */
    387. 

  387.   #define REG_XDMAC_CUBC23                     (0x40078630U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 23) */
    388. 

  388.   #define REG_XDMAC_CBC23                      (0x40078634U) /**< \brief (XDMAC) Channel Block Control Register (chid = 23) */
    389. 

  389.   #define REG_XDMAC_CC23                       (0x40078638U) /**< \brief (XDMAC) Channel Configuration Register (chid = 23) */
    390. 

  390.   #define REG_XDMAC_CDS_MSP23                  (0x4007863CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 23) */
    391. 

  391.   #define REG_XDMAC_CSUS23                     (0x40078640U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 23) */
    392. 

  392.   #define REG_XDMAC_CDUS23                     (0x40078644U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 23) */
    393. 

  393.   #define REG_XDMAC_VERSION                    (0x40078FFCU) /**< \brief (XDMAC) XDMAC Version Register */
    394. 

  394. #else
    395. 

  395.   #define REG_XDMAC_GTYPE     (*(__I  uint32_t*)0x40078000U) /**< \brief (XDMAC) Global Type Register */
    396. 

  396.   #define REG_XDMAC_GCFG      (*(__IO uint32_t*)0x40078004U) /**< \brief (XDMAC) Global Configuration Register */
    397. 

  397.   #define REG_XDMAC_GWAC      (*(__I  uint32_t*)0x40078008U) /**< \brief (XDMAC) Global Weighted Arbiter Configuration Register */
    398. 

  398.   #define REG_XDMAC_GIE       (*(__O  uint32_t*)0x4007800CU) /**< \brief (XDMAC) Global Interrupt Enable Register */
    399. 

  399.   #define REG_XDMAC_GID       (*(__O  uint32_t*)0x40078010U) /**< \brief (XDMAC) Global Interrupt Disable Register */
    400. 

  400.   #define REG_XDMAC_GIM       (*(__I  uint32_t*)0x40078014U) /**< \brief (XDMAC) Global Interrupt Mask Register */
    401. 

  401.   #define REG_XDMAC_GIS       (*(__I  uint32_t*)0x40078018U) /**< \brief (XDMAC) Global Interrupt Status Register */
    402. 

  402.   #define REG_XDMAC_GE        (*(__O  uint32_t*)0x4007801CU) /**< \brief (XDMAC) Global Channel Enable Register */
    403. 

  403.   #define REG_XDMAC_GD        (*(__O  uint32_t*)0x40078020U) /**< \brief (XDMAC) Global Channel Disable Register */
    404. 

  404.   #define REG_XDMAC_GS        (*(__I  uint32_t*)0x40078024U) /**< \brief (XDMAC) Global Channel Status Register */
    405. 

  405.   #define REG_XDMAC_GRS       (*(__IO uint32_t*)0x40078028U) /**< \brief (XDMAC) Global Channel Read Suspend Register */
    406. 

  406.   #define REG_XDMAC_GWS       (*(__IO uint32_t*)0x4007802CU) /**< \brief (XDMAC) Global Channel Write Suspend Register */
    407. 

  407.   #define REG_XDMAC_GRWS      (*(__O  uint32_t*)0x40078030U) /**< \brief (XDMAC) Global Channel Read Write Suspend Register */
    408. 

  408.   #define REG_XDMAC_GRWR      (*(__O  uint32_t*)0x40078034U) /**< \brief (XDMAC) Global Channel Read Write Resume Register */
    409. 

  409.   #define REG_XDMAC_GSWR      (*(__O  uint32_t*)0x40078038U) /**< \brief (XDMAC) Global Channel Software Request Register */
    410. 

  410.   #define REG_XDMAC_GSWS      (*(__I  uint32_t*)0x4007803CU) /**< \brief (XDMAC) Global Channel Software Request Status Register */
    411. 

  411.   #define REG_XDMAC_GSWF      (*(__O  uint32_t*)0x40078040U) /**< \brief (XDMAC) Global Channel Software Flush Request Register */
    412. 

  412.   #define REG_XDMAC_CIE0      (*(__O  uint32_t*)0x40078050U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 0) */
    413. 

  413.   #define REG_XDMAC_CID0      (*(__O  uint32_t*)0x40078054U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 0) */
    414. 

  414.   #define REG_XDMAC_CIM0      (*(__I  uint32_t*)0x40078058U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 0) */
    415. 

  415.   #define REG_XDMAC_CIS0      (*(__I  uint32_t*)0x4007805CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 0) */
    416. 

  416.   #define REG_XDMAC_CSA0      (*(__IO uint32_t*)0x40078060U) /**< \brief (XDMAC) Channel Source Address Register (chid = 0) */
    417. 

  417.   #define REG_XDMAC_CDA0      (*(__IO uint32_t*)0x40078064U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 0) */
    418. 

  418.   #define REG_XDMAC_CNDA0     (*(__IO uint32_t*)0x40078068U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 0) */
    419. 

  419.   #define REG_XDMAC_CNDC0     (*(__IO uint32_t*)0x4007806CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 0) */
    420. 

  420.   #define REG_XDMAC_CUBC0     (*(__IO uint32_t*)0x40078070U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 0) */
    421. 

  421.   #define REG_XDMAC_CBC0      (*(__IO uint32_t*)0x40078074U) /**< \brief (XDMAC) Channel Block Control Register (chid = 0) */
    422. 

  422.   #define REG_XDMAC_CC0       (*(__IO uint32_t*)0x40078078U) /**< \brief (XDMAC) Channel Configuration Register (chid = 0) */
    423. 

  423.   #define REG_XDMAC_CDS_MSP0  (*(__IO uint32_t*)0x4007807CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) */
    424. 

  424.   #define REG_XDMAC_CSUS0     (*(__IO uint32_t*)0x40078080U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 0) */
    425. 

  425.   #define REG_XDMAC_CDUS0     (*(__IO uint32_t*)0x40078084U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 0) */
    426. 

  426.   #define REG_XDMAC_CIE1      (*(__O  uint32_t*)0x40078090U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 1) */
    427. 

  427.   #define REG_XDMAC_CID1      (*(__O  uint32_t*)0x40078094U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 1) */
    428. 

  428.   #define REG_XDMAC_CIM1      (*(__I  uint32_t*)0x40078098U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 1) */
    429. 

  429.   #define REG_XDMAC_CIS1      (*(__I  uint32_t*)0x4007809CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 1) */
    430. 

  430.   #define REG_XDMAC_CSA1      (*(__IO uint32_t*)0x400780A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 1) */
    431. 

  431.   #define REG_XDMAC_CDA1      (*(__IO uint32_t*)0x400780A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 1) */
    432. 

  432.   #define REG_XDMAC_CNDA1     (*(__IO uint32_t*)0x400780A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 1) */
    433. 

  433.   #define REG_XDMAC_CNDC1     (*(__IO uint32_t*)0x400780ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 1) */
    434. 

  434.   #define REG_XDMAC_CUBC1     (*(__IO uint32_t*)0x400780B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 1) */
    435. 

  435.   #define REG_XDMAC_CBC1      (*(__IO uint32_t*)0x400780B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 1) */
    436. 

  436.   #define REG_XDMAC_CC1       (*(__IO uint32_t*)0x400780B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 1) */
    437. 

  437.   #define REG_XDMAC_CDS_MSP1  (*(__IO uint32_t*)0x400780BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 1) */
    438. 

  438.   #define REG_XDMAC_CSUS1     (*(__IO uint32_t*)0x400780C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 1) */
    439. 

  439.   #define REG_XDMAC_CDUS1     (*(__IO uint32_t*)0x400780C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 1) */
    440. 

  440.   #define REG_XDMAC_CIE2      (*(__O  uint32_t*)0x400780D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 2) */
    441. 

  441.   #define REG_XDMAC_CID2      (*(__O  uint32_t*)0x400780D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 2) */
    442. 

  442.   #define REG_XDMAC_CIM2      (*(__I  uint32_t*)0x400780D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 2) */
    443. 

  443.   #define REG_XDMAC_CIS2      (*(__I  uint32_t*)0x400780DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 2) */
    444. 

  444.   #define REG_XDMAC_CSA2      (*(__IO uint32_t*)0x400780E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 2) */
    445. 

  445.   #define REG_XDMAC_CDA2      (*(__IO uint32_t*)0x400780E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 2) */
    446. 

  446.   #define REG_XDMAC_CNDA2     (*(__IO uint32_t*)0x400780E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 2) */
    447. 

  447.   #define REG_XDMAC_CNDC2     (*(__IO uint32_t*)0x400780ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 2) */
    448. 

  448.   #define REG_XDMAC_CUBC2     (*(__IO uint32_t*)0x400780F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 2) */
    449. 

  449.   #define REG_XDMAC_CBC2      (*(__IO uint32_t*)0x400780F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 2) */
    450. 

  450.   #define REG_XDMAC_CC2       (*(__IO uint32_t*)0x400780F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 2) */
    451. 

  451.   #define REG_XDMAC_CDS_MSP2  (*(__IO uint32_t*)0x400780FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 2) */
    452. 

  452.   #define REG_XDMAC_CSUS2     (*(__IO uint32_t*)0x40078100U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 2) */
    453. 

  453.   #define REG_XDMAC_CDUS2     (*(__IO uint32_t*)0x40078104U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 2) */
    454. 

  454.   #define REG_XDMAC_CIE3      (*(__O  uint32_t*)0x40078110U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 3) */
    455. 

  455.   #define REG_XDMAC_CID3      (*(__O  uint32_t*)0x40078114U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 3) */
    456. 

  456.   #define REG_XDMAC_CIM3      (*(__I  uint32_t*)0x40078118U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 3) */
    457. 

  457.   #define REG_XDMAC_CIS3      (*(__I  uint32_t*)0x4007811CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 3) */
    458. 

  458.   #define REG_XDMAC_CSA3      (*(__IO uint32_t*)0x40078120U) /**< \brief (XDMAC) Channel Source Address Register (chid = 3) */
    459. 

  459.   #define REG_XDMAC_CDA3      (*(__IO uint32_t*)0x40078124U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 3) */
    460. 

  460.   #define REG_XDMAC_CNDA3     (*(__IO uint32_t*)0x40078128U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 3) */
    461. 

  461.   #define REG_XDMAC_CNDC3     (*(__IO uint32_t*)0x4007812CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 3) */
    462. 

  462.   #define REG_XDMAC_CUBC3     (*(__IO uint32_t*)0x40078130U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 3) */
    463. 

  463.   #define REG_XDMAC_CBC3      (*(__IO uint32_t*)0x40078134U) /**< \brief (XDMAC) Channel Block Control Register (chid = 3) */
    464. 

  464.   #define REG_XDMAC_CC3       (*(__IO uint32_t*)0x40078138U) /**< \brief (XDMAC) Channel Configuration Register (chid = 3) */
    465. 

  465.   #define REG_XDMAC_CDS_MSP3  (*(__IO uint32_t*)0x4007813CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 3) */
    466. 

  466.   #define REG_XDMAC_CSUS3     (*(__IO uint32_t*)0x40078140U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 3) */
    467. 

  467.   #define REG_XDMAC_CDUS3     (*(__IO uint32_t*)0x40078144U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 3) */
    468. 

  468.   #define REG_XDMAC_CIE4      (*(__O  uint32_t*)0x40078150U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 4) */
    469. 

  469.   #define REG_XDMAC_CID4      (*(__O  uint32_t*)0x40078154U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 4) */
    470. 

  470.   #define REG_XDMAC_CIM4      (*(__I  uint32_t*)0x40078158U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 4) */
    471. 

  471.   #define REG_XDMAC_CIS4      (*(__I  uint32_t*)0x4007815CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 4) */
    472. 

  472.   #define REG_XDMAC_CSA4      (*(__IO uint32_t*)0x40078160U) /**< \brief (XDMAC) Channel Source Address Register (chid = 4) */
    473. 

  473.   #define REG_XDMAC_CDA4      (*(__IO uint32_t*)0x40078164U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 4) */
    474. 

  474.   #define REG_XDMAC_CNDA4     (*(__IO uint32_t*)0x40078168U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 4) */
    475. 

  475.   #define REG_XDMAC_CNDC4     (*(__IO uint32_t*)0x4007816CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 4) */
    476. 

  476.   #define REG_XDMAC_CUBC4     (*(__IO uint32_t*)0x40078170U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 4) */
    477. 

  477.   #define REG_XDMAC_CBC4      (*(__IO uint32_t*)0x40078174U) /**< \brief (XDMAC) Channel Block Control Register (chid = 4) */
    478. 

  478.   #define REG_XDMAC_CC4       (*(__IO uint32_t*)0x40078178U) /**< \brief (XDMAC) Channel Configuration Register (chid = 4) */
    479. 

  479.   #define REG_XDMAC_CDS_MSP4  (*(__IO uint32_t*)0x4007817CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 4) */
    480. 

  480.   #define REG_XDMAC_CSUS4     (*(__IO uint32_t*)0x40078180U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 4) */
    481. 

  481.   #define REG_XDMAC_CDUS4     (*(__IO uint32_t*)0x40078184U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 4) */
    482. 

  482.   #define REG_XDMAC_CIE5      (*(__O  uint32_t*)0x40078190U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 5) */
    483. 

  483.   #define REG_XDMAC_CID5      (*(__O  uint32_t*)0x40078194U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 5) */
    484. 

  484.   #define REG_XDMAC_CIM5      (*(__I  uint32_t*)0x40078198U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 5) */
    485. 

  485.   #define REG_XDMAC_CIS5      (*(__I  uint32_t*)0x4007819CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 5) */
    486. 

  486.   #define REG_XDMAC_CSA5      (*(__IO uint32_t*)0x400781A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 5) */
    487. 

  487.   #define REG_XDMAC_CDA5      (*(__IO uint32_t*)0x400781A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 5) */
    488. 

  488.   #define REG_XDMAC_CNDA5     (*(__IO uint32_t*)0x400781A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 5) */
    489. 

  489.   #define REG_XDMAC_CNDC5     (*(__IO uint32_t*)0x400781ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 5) */
    490. 

  490.   #define REG_XDMAC_CUBC5     (*(__IO uint32_t*)0x400781B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 5) */
    491. 

  491.   #define REG_XDMAC_CBC5      (*(__IO uint32_t*)0x400781B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 5) */
    492. 

  492.   #define REG_XDMAC_CC5       (*(__IO uint32_t*)0x400781B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 5) */
    493. 

  493.   #define REG_XDMAC_CDS_MSP5  (*(__IO uint32_t*)0x400781BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 5) */
    494. 

  494.   #define REG_XDMAC_CSUS5     (*(__IO uint32_t*)0x400781C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 5) */
    495. 

  495.   #define REG_XDMAC_CDUS5     (*(__IO uint32_t*)0x400781C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 5) */
    496. 

  496.   #define REG_XDMAC_CIE6      (*(__O  uint32_t*)0x400781D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 6) */
    497. 

  497.   #define REG_XDMAC_CID6      (*(__O  uint32_t*)0x400781D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 6) */
    498. 

  498.   #define REG_XDMAC_CIM6      (*(__I  uint32_t*)0x400781D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 6) */
    499. 

  499.   #define REG_XDMAC_CIS6      (*(__I  uint32_t*)0x400781DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 6) */
    500. 

  500.   #define REG_XDMAC_CSA6      (*(__IO uint32_t*)0x400781E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 6) */
    501. 

  501.   #define REG_XDMAC_CDA6      (*(__IO uint32_t*)0x400781E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 6) */
    502. 

  502.   #define REG_XDMAC_CNDA6     (*(__IO uint32_t*)0x400781E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 6) */
    503. 

  503.   #define REG_XDMAC_CNDC6     (*(__IO uint32_t*)0x400781ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 6) */
    504. 

  504.   #define REG_XDMAC_CUBC6     (*(__IO uint32_t*)0x400781F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 6) */
    505. 

  505.   #define REG_XDMAC_CBC6      (*(__IO uint32_t*)0x400781F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 6) */
    506. 

  506.   #define REG_XDMAC_CC6       (*(__IO uint32_t*)0x400781F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 6) */
    507. 

  507.   #define REG_XDMAC_CDS_MSP6  (*(__IO uint32_t*)0x400781FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 6) */
    508. 

  508.   #define REG_XDMAC_CSUS6     (*(__IO uint32_t*)0x40078200U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 6) */
    509. 

  509.   #define REG_XDMAC_CDUS6     (*(__IO uint32_t*)0x40078204U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 6) */
    510. 

  510.   #define REG_XDMAC_CIE7      (*(__O  uint32_t*)0x40078210U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 7) */
    511. 

  511.   #define REG_XDMAC_CID7      (*(__O  uint32_t*)0x40078214U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 7) */
    512. 

  512.   #define REG_XDMAC_CIM7      (*(__I  uint32_t*)0x40078218U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 7) */
    513. 

  513.   #define REG_XDMAC_CIS7      (*(__I  uint32_t*)0x4007821CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 7) */
    514. 

  514.   #define REG_XDMAC_CSA7      (*(__IO uint32_t*)0x40078220U) /**< \brief (XDMAC) Channel Source Address Register (chid = 7) */
    515. 

  515.   #define REG_XDMAC_CDA7      (*(__IO uint32_t*)0x40078224U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 7) */
    516. 

  516.   #define REG_XDMAC_CNDA7     (*(__IO uint32_t*)0x40078228U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 7) */
    517. 

  517.   #define REG_XDMAC_CNDC7     (*(__IO uint32_t*)0x4007822CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 7) */
    518. 

  518.   #define REG_XDMAC_CUBC7     (*(__IO uint32_t*)0x40078230U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 7) */
    519. 

  519.   #define REG_XDMAC_CBC7      (*(__IO uint32_t*)0x40078234U) /**< \brief (XDMAC) Channel Block Control Register (chid = 7) */
    520. 

  520.   #define REG_XDMAC_CC7       (*(__IO uint32_t*)0x40078238U) /**< \brief (XDMAC) Channel Configuration Register (chid = 7) */
    521. 

  521.   #define REG_XDMAC_CDS_MSP7  (*(__IO uint32_t*)0x4007823CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 7) */
    522. 

  522.   #define REG_XDMAC_CSUS7     (*(__IO uint32_t*)0x40078240U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 7) */
    523. 

  523.   #define REG_XDMAC_CDUS7     (*(__IO uint32_t*)0x40078244U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 7) */
    524. 

  524.   #define REG_XDMAC_CIE8      (*(__O  uint32_t*)0x40078250U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 8) */
    525. 

  525.   #define REG_XDMAC_CID8      (*(__O  uint32_t*)0x40078254U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 8) */
    526. 

  526.   #define REG_XDMAC_CIM8      (*(__I  uint32_t*)0x40078258U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 8) */
    527. 

  527.   #define REG_XDMAC_CIS8      (*(__I  uint32_t*)0x4007825CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 8) */
    528. 

  528.   #define REG_XDMAC_CSA8      (*(__IO uint32_t*)0x40078260U) /**< \brief (XDMAC) Channel Source Address Register (chid = 8) */
    529. 

  529.   #define REG_XDMAC_CDA8      (*(__IO uint32_t*)0x40078264U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 8) */
    530. 

  530.   #define REG_XDMAC_CNDA8     (*(__IO uint32_t*)0x40078268U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 8) */
    531. 

  531.   #define REG_XDMAC_CNDC8     (*(__IO uint32_t*)0x4007826CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 8) */
    532. 

  532.   #define REG_XDMAC_CUBC8     (*(__IO uint32_t*)0x40078270U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 8) */
    533. 

  533.   #define REG_XDMAC_CBC8      (*(__IO uint32_t*)0x40078274U) /**< \brief (XDMAC) Channel Block Control Register (chid = 8) */
    534. 

  534.   #define REG_XDMAC_CC8       (*(__IO uint32_t*)0x40078278U) /**< \brief (XDMAC) Channel Configuration Register (chid = 8) */
    535. 

  535.   #define REG_XDMAC_CDS_MSP8  (*(__IO uint32_t*)0x4007827CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 8) */
    536. 

  536.   #define REG_XDMAC_CSUS8     (*(__IO uint32_t*)0x40078280U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 8) */
    537. 

  537.   #define REG_XDMAC_CDUS8     (*(__IO uint32_t*)0x40078284U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 8) */
    538. 

  538.   #define REG_XDMAC_CIE9      (*(__O  uint32_t*)0x40078290U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 9) */
    539. 

  539.   #define REG_XDMAC_CID9      (*(__O  uint32_t*)0x40078294U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 9) */
    540. 

  540.   #define REG_XDMAC_CIM9      (*(__I  uint32_t*)0x40078298U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 9) */
    541. 

  541.   #define REG_XDMAC_CIS9      (*(__I  uint32_t*)0x4007829CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 9) */
    542. 

  542.   #define REG_XDMAC_CSA9      (*(__IO uint32_t*)0x400782A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 9) */
    543. 

  543.   #define REG_XDMAC_CDA9      (*(__IO uint32_t*)0x400782A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 9) */
    544. 

  544.   #define REG_XDMAC_CNDA9     (*(__IO uint32_t*)0x400782A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 9) */
    545. 

  545.   #define REG_XDMAC_CNDC9     (*(__IO uint32_t*)0x400782ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 9) */
    546. 

  546.   #define REG_XDMAC_CUBC9     (*(__IO uint32_t*)0x400782B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 9) */
    547. 

  547.   #define REG_XDMAC_CBC9      (*(__IO uint32_t*)0x400782B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 9) */
    548. 

  548.   #define REG_XDMAC_CC9       (*(__IO uint32_t*)0x400782B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 9) */
    549. 

  549.   #define REG_XDMAC_CDS_MSP9  (*(__IO uint32_t*)0x400782BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 9) */
    550. 

  550.   #define REG_XDMAC_CSUS9     (*(__IO uint32_t*)0x400782C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 9) */
    551. 

  551.   #define REG_XDMAC_CDUS9     (*(__IO uint32_t*)0x400782C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 9) */
    552. 

  552.   #define REG_XDMAC_CIE10     (*(__O  uint32_t*)0x400782D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 10) */
    553. 

  553.   #define REG_XDMAC_CID10     (*(__O  uint32_t*)0x400782D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 10) */
    554. 

  554.   #define REG_XDMAC_CIM10     (*(__I  uint32_t*)0x400782D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 10) */
    555. 

  555.   #define REG_XDMAC_CIS10     (*(__I  uint32_t*)0x400782DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 10) */
    556. 

  556.   #define REG_XDMAC_CSA10     (*(__IO uint32_t*)0x400782E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 10) */
    557. 

  557.   #define REG_XDMAC_CDA10     (*(__IO uint32_t*)0x400782E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 10) */
    558. 

  558.   #define REG_XDMAC_CNDA10    (*(__IO uint32_t*)0x400782E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 10) */
    559. 

  559.   #define REG_XDMAC_CNDC10    (*(__IO uint32_t*)0x400782ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 10) */
    560. 

  560.   #define REG_XDMAC_CUBC10    (*(__IO uint32_t*)0x400782F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 10) */
    561. 

  561.   #define REG_XDMAC_CBC10     (*(__IO uint32_t*)0x400782F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 10) */
    562. 

  562.   #define REG_XDMAC_CC10      (*(__IO uint32_t*)0x400782F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 10) */
    563. 

  563.   #define REG_XDMAC_CDS_MSP10 (*(__IO uint32_t*)0x400782FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 10) */
    564. 

  564.   #define REG_XDMAC_CSUS10    (*(__IO uint32_t*)0x40078300U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 10) */
    565. 

  565.   #define REG_XDMAC_CDUS10    (*(__IO uint32_t*)0x40078304U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 10) */
    566. 

  566.   #define REG_XDMAC_CIE11     (*(__O  uint32_t*)0x40078310U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 11) */
    567. 

  567.   #define REG_XDMAC_CID11     (*(__O  uint32_t*)0x40078314U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 11) */
    568. 

  568.   #define REG_XDMAC_CIM11     (*(__I  uint32_t*)0x40078318U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 11) */
    569. 

  569.   #define REG_XDMAC_CIS11     (*(__I  uint32_t*)0x4007831CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 11) */
    570. 

  570.   #define REG_XDMAC_CSA11     (*(__IO uint32_t*)0x40078320U) /**< \brief (XDMAC) Channel Source Address Register (chid = 11) */
    571. 

  571.   #define REG_XDMAC_CDA11     (*(__IO uint32_t*)0x40078324U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 11) */
    572. 

  572.   #define REG_XDMAC_CNDA11    (*(__IO uint32_t*)0x40078328U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 11) */
    573. 

  573.   #define REG_XDMAC_CNDC11    (*(__IO uint32_t*)0x4007832CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 11) */
    574. 

  574.   #define REG_XDMAC_CUBC11    (*(__IO uint32_t*)0x40078330U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 11) */
    575. 

  575.   #define REG_XDMAC_CBC11     (*(__IO uint32_t*)0x40078334U) /**< \brief (XDMAC) Channel Block Control Register (chid = 11) */
    576. 

  576.   #define REG_XDMAC_CC11      (*(__IO uint32_t*)0x40078338U) /**< \brief (XDMAC) Channel Configuration Register (chid = 11) */
    577. 

  577.   #define REG_XDMAC_CDS_MSP11 (*(__IO uint32_t*)0x4007833CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 11) */
    578. 

  578.   #define REG_XDMAC_CSUS11    (*(__IO uint32_t*)0x40078340U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 11) */
    579. 

  579.   #define REG_XDMAC_CDUS11    (*(__IO uint32_t*)0x40078344U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 11) */
    580. 

  580.   #define REG_XDMAC_CIE12     (*(__O  uint32_t*)0x40078350U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 12) */
    581. 

  581.   #define REG_XDMAC_CID12     (*(__O  uint32_t*)0x40078354U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 12) */
    582. 

  582.   #define REG_XDMAC_CIM12     (*(__I  uint32_t*)0x40078358U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 12) */
    583. 

  583.   #define REG_XDMAC_CIS12     (*(__I  uint32_t*)0x4007835CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 12) */
    584. 

  584.   #define REG_XDMAC_CSA12     (*(__IO uint32_t*)0x40078360U) /**< \brief (XDMAC) Channel Source Address Register (chid = 12) */
    585. 

  585.   #define REG_XDMAC_CDA12     (*(__IO uint32_t*)0x40078364U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 12) */
    586. 

  586.   #define REG_XDMAC_CNDA12    (*(__IO uint32_t*)0x40078368U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 12) */
    587. 

  587.   #define REG_XDMAC_CNDC12    (*(__IO uint32_t*)0x4007836CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 12) */
    588. 

  588.   #define REG_XDMAC_CUBC12    (*(__IO uint32_t*)0x40078370U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 12) */
    589. 

  589.   #define REG_XDMAC_CBC12     (*(__IO uint32_t*)0x40078374U) /**< \brief (XDMAC) Channel Block Control Register (chid = 12) */
    590. 

  590.   #define REG_XDMAC_CC12      (*(__IO uint32_t*)0x40078378U) /**< \brief (XDMAC) Channel Configuration Register (chid = 12) */
    591. 

  591.   #define REG_XDMAC_CDS_MSP12 (*(__IO uint32_t*)0x4007837CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 12) */
    592. 

  592.   #define REG_XDMAC_CSUS12    (*(__IO uint32_t*)0x40078380U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 12) */
    593. 

  593.   #define REG_XDMAC_CDUS12    (*(__IO uint32_t*)0x40078384U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 12) */
    594. 

  594.   #define REG_XDMAC_CIE13     (*(__O  uint32_t*)0x40078390U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 13) */
    595. 

  595.   #define REG_XDMAC_CID13     (*(__O  uint32_t*)0x40078394U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 13) */
    596. 

  596.   #define REG_XDMAC_CIM13     (*(__I  uint32_t*)0x40078398U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 13) */
    597. 

  597.   #define REG_XDMAC_CIS13     (*(__I  uint32_t*)0x4007839CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 13) */
    598. 

  598.   #define REG_XDMAC_CSA13     (*(__IO uint32_t*)0x400783A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 13) */
    599. 

  599.   #define REG_XDMAC_CDA13     (*(__IO uint32_t*)0x400783A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 13) */
    600. 

  600.   #define REG_XDMAC_CNDA13    (*(__IO uint32_t*)0x400783A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 13) */
    601. 

  601.   #define REG_XDMAC_CNDC13    (*(__IO uint32_t*)0x400783ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 13) */
    602. 

  602.   #define REG_XDMAC_CUBC13    (*(__IO uint32_t*)0x400783B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 13) */
    603. 

  603.   #define REG_XDMAC_CBC13     (*(__IO uint32_t*)0x400783B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 13) */
    604. 

  604.   #define REG_XDMAC_CC13      (*(__IO uint32_t*)0x400783B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 13) */
    605. 

  605.   #define REG_XDMAC_CDS_MSP13 (*(__IO uint32_t*)0x400783BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 13) */
    606. 

  606.   #define REG_XDMAC_CSUS13    (*(__IO uint32_t*)0x400783C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 13) */
    607. 

  607.   #define REG_XDMAC_CDUS13    (*(__IO uint32_t*)0x400783C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 13) */
    608. 

  608.   #define REG_XDMAC_CIE14     (*(__O  uint32_t*)0x400783D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 14) */
    609. 

  609.   #define REG_XDMAC_CID14     (*(__O  uint32_t*)0x400783D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 14) */
    610. 

  610.   #define REG_XDMAC_CIM14     (*(__I  uint32_t*)0x400783D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 14) */
    611. 

  611.   #define REG_XDMAC_CIS14     (*(__I  uint32_t*)0x400783DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 14) */
    612. 

  612.   #define REG_XDMAC_CSA14     (*(__IO uint32_t*)0x400783E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 14) */
    613. 

  613.   #define REG_XDMAC_CDA14     (*(__IO uint32_t*)0x400783E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 14) */
    614. 

  614.   #define REG_XDMAC_CNDA14    (*(__IO uint32_t*)0x400783E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 14) */
    615. 

  615.   #define REG_XDMAC_CNDC14    (*(__IO uint32_t*)0x400783ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 14) */
    616. 

  616.   #define REG_XDMAC_CUBC14    (*(__IO uint32_t*)0x400783F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 14) */
    617. 

  617.   #define REG_XDMAC_CBC14     (*(__IO uint32_t*)0x400783F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 14) */
    618. 

  618.   #define REG_XDMAC_CC14      (*(__IO uint32_t*)0x400783F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 14) */
    619. 

  619.   #define REG_XDMAC_CDS_MSP14 (*(__IO uint32_t*)0x400783FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 14) */
    620. 

  620.   #define REG_XDMAC_CSUS14    (*(__IO uint32_t*)0x40078400U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 14) */
    621. 

  621.   #define REG_XDMAC_CDUS14    (*(__IO uint32_t*)0x40078404U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 14) */
    622. 

  622.   #define REG_XDMAC_CIE15     (*(__O  uint32_t*)0x40078410U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 15) */
    623. 

  623.   #define REG_XDMAC_CID15     (*(__O  uint32_t*)0x40078414U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 15) */
    624. 

  624.   #define REG_XDMAC_CIM15     (*(__I  uint32_t*)0x40078418U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 15) */
    625. 

  625.   #define REG_XDMAC_CIS15     (*(__I  uint32_t*)0x4007841CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 15) */
    626. 

  626.   #define REG_XDMAC_CSA15     (*(__IO uint32_t*)0x40078420U) /**< \brief (XDMAC) Channel Source Address Register (chid = 15) */
    627. 

  627.   #define REG_XDMAC_CDA15     (*(__IO uint32_t*)0x40078424U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 15) */
    628. 

  628.   #define REG_XDMAC_CNDA15    (*(__IO uint32_t*)0x40078428U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 15) */
    629. 

  629.   #define REG_XDMAC_CNDC15    (*(__IO uint32_t*)0x4007842CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 15) */
    630. 

  630.   #define REG_XDMAC_CUBC15    (*(__IO uint32_t*)0x40078430U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 15) */
    631. 

  631.   #define REG_XDMAC_CBC15     (*(__IO uint32_t*)0x40078434U) /**< \brief (XDMAC) Channel Block Control Register (chid = 15) */
    632. 

  632.   #define REG_XDMAC_CC15      (*(__IO uint32_t*)0x40078438U) /**< \brief (XDMAC) Channel Configuration Register (chid = 15) */
    633. 

  633.   #define REG_XDMAC_CDS_MSP15 (*(__IO uint32_t*)0x4007843CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 15) */
    634. 

  634.   #define REG_XDMAC_CSUS15    (*(__IO uint32_t*)0x40078440U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 15) */
    635. 

  635.   #define REG_XDMAC_CDUS15    (*(__IO uint32_t*)0x40078444U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 15) */
    636. 

  636.   #define REG_XDMAC_CIE16     (*(__O  uint32_t*)0x40078450U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 16) */
    637. 

  637.   #define REG_XDMAC_CID16     (*(__O  uint32_t*)0x40078454U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 16) */
    638. 

  638.   #define REG_XDMAC_CIM16     (*(__I  uint32_t*)0x40078458U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 16) */
    639. 

  639.   #define REG_XDMAC_CIS16     (*(__I  uint32_t*)0x4007845CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 16) */
    640. 

  640.   #define REG_XDMAC_CSA16     (*(__IO uint32_t*)0x40078460U) /**< \brief (XDMAC) Channel Source Address Register (chid = 16) */
    641. 

  641.   #define REG_XDMAC_CDA16     (*(__IO uint32_t*)0x40078464U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 16) */
    642. 

  642.   #define REG_XDMAC_CNDA16    (*(__IO uint32_t*)0x40078468U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 16) */
    643. 

  643.   #define REG_XDMAC_CNDC16    (*(__IO uint32_t*)0x4007846CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 16) */
    644. 

  644.   #define REG_XDMAC_CUBC16    (*(__IO uint32_t*)0x40078470U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 16) */
    645. 

  645.   #define REG_XDMAC_CBC16     (*(__IO uint32_t*)0x40078474U) /**< \brief (XDMAC) Channel Block Control Register (chid = 16) */
    646. 

  646.   #define REG_XDMAC_CC16      (*(__IO uint32_t*)0x40078478U) /**< \brief (XDMAC) Channel Configuration Register (chid = 16) */
    647. 

  647.   #define REG_XDMAC_CDS_MSP16 (*(__IO uint32_t*)0x4007847CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 16) */
    648. 

  648.   #define REG_XDMAC_CSUS16    (*(__IO uint32_t*)0x40078480U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 16) */
    649. 

  649.   #define REG_XDMAC_CDUS16    (*(__IO uint32_t*)0x40078484U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 16) */
    650. 

  650.   #define REG_XDMAC_CIE17     (*(__O  uint32_t*)0x40078490U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 17) */
    651. 

  651.   #define REG_XDMAC_CID17     (*(__O  uint32_t*)0x40078494U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 17) */
    652. 

  652.   #define REG_XDMAC_CIM17     (*(__I  uint32_t*)0x40078498U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 17) */
    653. 

  653.   #define REG_XDMAC_CIS17     (*(__I  uint32_t*)0x4007849CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 17) */
    654. 

  654.   #define REG_XDMAC_CSA17     (*(__IO uint32_t*)0x400784A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 17) */
    655. 

  655.   #define REG_XDMAC_CDA17     (*(__IO uint32_t*)0x400784A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 17) */
    656. 

  656.   #define REG_XDMAC_CNDA17    (*(__IO uint32_t*)0x400784A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 17) */
    657. 

  657.   #define REG_XDMAC_CNDC17    (*(__IO uint32_t*)0x400784ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 17) */
    658. 

  658.   #define REG_XDMAC_CUBC17    (*(__IO uint32_t*)0x400784B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 17) */
    659. 

  659.   #define REG_XDMAC_CBC17     (*(__IO uint32_t*)0x400784B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 17) */
    660. 

  660.   #define REG_XDMAC_CC17      (*(__IO uint32_t*)0x400784B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 17) */
    661. 

  661.   #define REG_XDMAC_CDS_MSP17 (*(__IO uint32_t*)0x400784BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 17) */
    662. 

  662.   #define REG_XDMAC_CSUS17    (*(__IO uint32_t*)0x400784C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 17) */
    663. 

  663.   #define REG_XDMAC_CDUS17    (*(__IO uint32_t*)0x400784C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 17) */
    664. 

  664.   #define REG_XDMAC_CIE18     (*(__O  uint32_t*)0x400784D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 18) */
    665. 

  665.   #define REG_XDMAC_CID18     (*(__O  uint32_t*)0x400784D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 18) */
    666. 

  666.   #define REG_XDMAC_CIM18     (*(__I  uint32_t*)0x400784D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 18) */
    667. 

  667.   #define REG_XDMAC_CIS18     (*(__I  uint32_t*)0x400784DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 18) */
    668. 

  668.   #define REG_XDMAC_CSA18     (*(__IO uint32_t*)0x400784E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 18) */
    669. 

  669.   #define REG_XDMAC_CDA18     (*(__IO uint32_t*)0x400784E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 18) */
    670. 

  670.   #define REG_XDMAC_CNDA18    (*(__IO uint32_t*)0x400784E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 18) */
    671. 

  671.   #define REG_XDMAC_CNDC18    (*(__IO uint32_t*)0x400784ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 18) */
    672. 

  672.   #define REG_XDMAC_CUBC18    (*(__IO uint32_t*)0x400784F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 18) */
    673. 

  673.   #define REG_XDMAC_CBC18     (*(__IO uint32_t*)0x400784F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 18) */
    674. 

  674.   #define REG_XDMAC_CC18      (*(__IO uint32_t*)0x400784F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 18) */
    675. 

  675.   #define REG_XDMAC_CDS_MSP18 (*(__IO uint32_t*)0x400784FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 18) */
    676. 

  676.   #define REG_XDMAC_CSUS18    (*(__IO uint32_t*)0x40078500U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 18) */
    677. 

  677.   #define REG_XDMAC_CDUS18    (*(__IO uint32_t*)0x40078504U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 18) */
    678. 

  678.   #define REG_XDMAC_CIE19     (*(__O  uint32_t*)0x40078510U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 19) */
    679. 

  679.   #define REG_XDMAC_CID19     (*(__O  uint32_t*)0x40078514U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 19) */
    680. 

  680.   #define REG_XDMAC_CIM19     (*(__I  uint32_t*)0x40078518U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 19) */
    681. 

  681.   #define REG_XDMAC_CIS19     (*(__I  uint32_t*)0x4007851CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 19) */
    682. 

  682.   #define REG_XDMAC_CSA19     (*(__IO uint32_t*)0x40078520U) /**< \brief (XDMAC) Channel Source Address Register (chid = 19) */
    683. 

  683.   #define REG_XDMAC_CDA19     (*(__IO uint32_t*)0x40078524U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 19) */
    684. 

  684.   #define REG_XDMAC_CNDA19    (*(__IO uint32_t*)0x40078528U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 19) */
    685. 

  685.   #define REG_XDMAC_CNDC19    (*(__IO uint32_t*)0x4007852CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 19) */
    686. 

  686.   #define REG_XDMAC_CUBC19    (*(__IO uint32_t*)0x40078530U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 19) */
    687. 

  687.   #define REG_XDMAC_CBC19     (*(__IO uint32_t*)0x40078534U) /**< \brief (XDMAC) Channel Block Control Register (chid = 19) */
    688. 

  688.   #define REG_XDMAC_CC19      (*(__IO uint32_t*)0x40078538U) /**< \brief (XDMAC) Channel Configuration Register (chid = 19) */
    689. 

  689.   #define REG_XDMAC_CDS_MSP19 (*(__IO uint32_t*)0x4007853CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 19) */
    690. 

  690.   #define REG_XDMAC_CSUS19    (*(__IO uint32_t*)0x40078540U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 19) */
    691. 

  691.   #define REG_XDMAC_CDUS19    (*(__IO uint32_t*)0x40078544U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 19) */
    692. 

  692.   #define REG_XDMAC_CIE20     (*(__O  uint32_t*)0x40078550U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 20) */
    693. 

  693.   #define REG_XDMAC_CID20     (*(__O  uint32_t*)0x40078554U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 20) */
    694. 

  694.   #define REG_XDMAC_CIM20     (*(__I  uint32_t*)0x40078558U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 20) */
    695. 

  695.   #define REG_XDMAC_CIS20     (*(__I  uint32_t*)0x4007855CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 20) */
    696. 

  696.   #define REG_XDMAC_CSA20     (*(__IO uint32_t*)0x40078560U) /**< \brief (XDMAC) Channel Source Address Register (chid = 20) */
    697. 

  697.   #define REG_XDMAC_CDA20     (*(__IO uint32_t*)0x40078564U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 20) */
    698. 

  698.   #define REG_XDMAC_CNDA20    (*(__IO uint32_t*)0x40078568U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 20) */
    699. 

  699.   #define REG_XDMAC_CNDC20    (*(__IO uint32_t*)0x4007856CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 20) */
    700. 

  700.   #define REG_XDMAC_CUBC20    (*(__IO uint32_t*)0x40078570U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 20) */
    701. 

  701.   #define REG_XDMAC_CBC20     (*(__IO uint32_t*)0x40078574U) /**< \brief (XDMAC) Channel Block Control Register (chid = 20) */
    702. 

  702.   #define REG_XDMAC_CC20      (*(__IO uint32_t*)0x40078578U) /**< \brief (XDMAC) Channel Configuration Register (chid = 20) */
    703. 

  703.   #define REG_XDMAC_CDS_MSP20 (*(__IO uint32_t*)0x4007857CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 20) */
    704. 

  704.   #define REG_XDMAC_CSUS20    (*(__IO uint32_t*)0x40078580U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 20) */
    705. 

  705.   #define REG_XDMAC_CDUS20    (*(__IO uint32_t*)0x40078584U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 20) */
    706. 

  706.   #define REG_XDMAC_CIE21     (*(__O  uint32_t*)0x40078590U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 21) */
    707. 

  707.   #define REG_XDMAC_CID21     (*(__O  uint32_t*)0x40078594U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 21) */
    708. 

  708.   #define REG_XDMAC_CIM21     (*(__I  uint32_t*)0x40078598U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 21) */
    709. 

  709.   #define REG_XDMAC_CIS21     (*(__I  uint32_t*)0x4007859CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 21) */
    710. 

  710.   #define REG_XDMAC_CSA21     (*(__IO uint32_t*)0x400785A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 21) */
    711. 

  711.   #define REG_XDMAC_CDA21     (*(__IO uint32_t*)0x400785A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 21) */
    712. 

  712.   #define REG_XDMAC_CNDA21    (*(__IO uint32_t*)0x400785A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 21) */
    713. 

  713.   #define REG_XDMAC_CNDC21    (*(__IO uint32_t*)0x400785ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 21) */
    714. 

  714.   #define REG_XDMAC_CUBC21    (*(__IO uint32_t*)0x400785B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 21) */
    715. 

  715.   #define REG_XDMAC_CBC21     (*(__IO uint32_t*)0x400785B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 21) */
    716. 

  716.   #define REG_XDMAC_CC21      (*(__IO uint32_t*)0x400785B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 21) */
    717. 

  717.   #define REG_XDMAC_CDS_MSP21 (*(__IO uint32_t*)0x400785BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 21) */
    718. 

  718.   #define REG_XDMAC_CSUS21    (*(__IO uint32_t*)0x400785C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 21) */
    719. 

  719.   #define REG_XDMAC_CDUS21    (*(__IO uint32_t*)0x400785C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 21) */
    720. 

  720.   #define REG_XDMAC_CIE22     (*(__O  uint32_t*)0x400785D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 22) */
    721. 

  721.   #define REG_XDMAC_CID22     (*(__O  uint32_t*)0x400785D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 22) */
    722. 

  722.   #define REG_XDMAC_CIM22     (*(__I  uint32_t*)0x400785D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 22) */
    723. 

  723.   #define REG_XDMAC_CIS22     (*(__I  uint32_t*)0x400785DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 22) */
    724. 

  724.   #define REG_XDMAC_CSA22     (*(__IO uint32_t*)0x400785E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 22) */
    725. 

  725.   #define REG_XDMAC_CDA22     (*(__IO uint32_t*)0x400785E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 22) */
    726. 

  726.   #define REG_XDMAC_CNDA22    (*(__IO uint32_t*)0x400785E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 22) */
    727. 

  727.   #define REG_XDMAC_CNDC22    (*(__IO uint32_t*)0x400785ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 22) */
    728. 

  728.   #define REG_XDMAC_CUBC22    (*(__IO uint32_t*)0x400785F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 22) */
    729. 

  729.   #define REG_XDMAC_CBC22     (*(__IO uint32_t*)0x400785F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 22) */
    730. 

  730.   #define REG_XDMAC_CC22      (*(__IO uint32_t*)0x400785F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 22) */
    731. 

  731.   #define REG_XDMAC_CDS_MSP22 (*(__IO uint32_t*)0x400785FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 22) */
    732. 

  732.   #define REG_XDMAC_CSUS22    (*(__IO uint32_t*)0x40078600U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 22) */
    733. 

  733.   #define REG_XDMAC_CDUS22    (*(__IO uint32_t*)0x40078604U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 22) */
    734. 

  734.   #define REG_XDMAC_CIE23     (*(__O  uint32_t*)0x40078610U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 23) */
    735. 

  735.   #define REG_XDMAC_CID23     (*(__O  uint32_t*)0x40078614U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 23) */
    736. 

  736.   #define REG_XDMAC_CIM23     (*(__I  uint32_t*)0x40078618U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 23) */
    737. 

  737.   #define REG_XDMAC_CIS23     (*(__I  uint32_t*)0x4007861CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 23) */
    738. 

  738.   #define REG_XDMAC_CSA23     (*(__IO uint32_t*)0x40078620U) /**< \brief (XDMAC) Channel Source Address Register (chid = 23) */
    739. 

  739.   #define REG_XDMAC_CDA23     (*(__IO uint32_t*)0x40078624U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 23) */
    740. 

  740.   #define REG_XDMAC_CNDA23    (*(__IO uint32_t*)0x40078628U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 23) */
    741. 

  741.   #define REG_XDMAC_CNDC23    (*(__IO uint32_t*)0x4007862CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 23) */
    742. 

  742.   #define REG_XDMAC_CUBC23    (*(__IO uint32_t*)0x40078630U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 23) */
    743. 

  743.   #define REG_XDMAC_CBC23     (*(__IO uint32_t*)0x40078634U) /**< \brief (XDMAC) Channel Block Control Register (chid = 23) */
    744. 

  744.   #define REG_XDMAC_CC23      (*(__IO uint32_t*)0x40078638U) /**< \brief (XDMAC) Channel Configuration Register (chid = 23) */
    745. 

  745.   #define REG_XDMAC_CDS_MSP23 (*(__IO uint32_t*)0x4007863CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 23) */
    746. 

  746.   #define REG_XDMAC_CSUS23    (*(__IO uint32_t*)0x40078640U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 23) */
    747. 

  747.   #define REG_XDMAC_CDUS23    (*(__IO uint32_t*)0x40078644U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 23) */
    748. 

  748.   #define REG_XDMAC_VERSION   (*(__IO uint32_t*)0x40078FFCU) /**< \brief (XDMAC) XDMAC Version Register */
    749. 

  749. #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
    750. 

  750. 

  751. #endif /* _SAME70_XDMAC_INSTANCE_ */
    752.