imu_lsm6ds3trc.c 3.2 KB

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  1. #include "lsm6ds3tr_c_reg.h"
  2. #include <furi_hal.h>
  3. #include "imu.h"
  4. #define TAG "LSM6DS3TR-C"
  5. #define LSM6DS3_ADDRESS (0x6A << 1)
  6. static const double DEG_TO_RAD = 0.017453292519943295769236907684886;
  7. stmdev_ctx_t lsm6ds3trc_ctx;
  8. int32_t lsm6ds3trc_write_i2c(void* handle, uint8_t reg_addr, const uint8_t* data, uint16_t len) {
  9. if(furi_hal_i2c_write_mem(handle, LSM6DS3_ADDRESS, reg_addr, (uint8_t*)data, len, 50))
  10. return 0;
  11. return -1;
  12. }
  13. int32_t lsm6ds3trc_read_i2c(void* handle, uint8_t reg_addr, uint8_t* read_data, uint16_t len) {
  14. if(furi_hal_i2c_read_mem(handle, LSM6DS3_ADDRESS, reg_addr, read_data, len, 50)) return 0;
  15. return -1;
  16. }
  17. bool lsm6ds3trc_begin() {
  18. FURI_LOG_I(TAG, "Init LSM6DS3TR-C");
  19. if(!furi_hal_i2c_is_device_ready(&furi_hal_i2c_handle_external, LSM6DS3_ADDRESS, 50)) {
  20. FURI_LOG_E(TAG, "Not ready");
  21. return false;
  22. }
  23. lsm6ds3trc_ctx.write_reg = lsm6ds3trc_write_i2c;
  24. lsm6ds3trc_ctx.read_reg = lsm6ds3trc_read_i2c;
  25. lsm6ds3trc_ctx.mdelay = furi_delay_ms;
  26. lsm6ds3trc_ctx.handle = &furi_hal_i2c_handle_external;
  27. uint8_t whoami;
  28. lsm6ds3tr_c_device_id_get(&lsm6ds3trc_ctx, &whoami);
  29. if(whoami != LSM6DS3TR_C_ID) {
  30. FURI_LOG_I(TAG, "Unknown model: %x", (int)whoami);
  31. return false;
  32. }
  33. lsm6ds3tr_c_reset_set(&lsm6ds3trc_ctx, PROPERTY_ENABLE);
  34. uint8_t rst = PROPERTY_ENABLE;
  35. while(rst) lsm6ds3tr_c_reset_get(&lsm6ds3trc_ctx, &rst);
  36. lsm6ds3tr_c_block_data_update_set(&lsm6ds3trc_ctx, PROPERTY_ENABLE);
  37. lsm6ds3tr_c_fifo_mode_set(&lsm6ds3trc_ctx, LSM6DS3TR_C_BYPASS_MODE);
  38. lsm6ds3tr_c_xl_data_rate_set(&lsm6ds3trc_ctx, LSM6DS3TR_C_XL_ODR_104Hz);
  39. lsm6ds3tr_c_xl_full_scale_set(&lsm6ds3trc_ctx, LSM6DS3TR_C_4g);
  40. lsm6ds3tr_c_xl_lp1_bandwidth_set(&lsm6ds3trc_ctx, LSM6DS3TR_C_XL_LP1_ODR_DIV_4);
  41. lsm6ds3tr_c_gy_data_rate_set(&lsm6ds3trc_ctx, LSM6DS3TR_C_GY_ODR_104Hz);
  42. lsm6ds3tr_c_gy_full_scale_set(&lsm6ds3trc_ctx, LSM6DS3TR_C_2000dps);
  43. lsm6ds3tr_c_gy_power_mode_set(&lsm6ds3trc_ctx, LSM6DS3TR_C_GY_HIGH_PERFORMANCE);
  44. lsm6ds3tr_c_gy_band_pass_set(&lsm6ds3trc_ctx, LSM6DS3TR_C_LP2_ONLY);
  45. FURI_LOG_I(TAG, "Init OK");
  46. return true;
  47. }
  48. void lsm6ds3trc_end() {
  49. lsm6ds3tr_c_xl_data_rate_set(&lsm6ds3trc_ctx, LSM6DS3TR_C_XL_ODR_OFF);
  50. lsm6ds3tr_c_gy_data_rate_set(&lsm6ds3trc_ctx, LSM6DS3TR_C_GY_ODR_OFF);
  51. }
  52. int lsm6ds3trc_read(double* vec) {
  53. int ret = 0;
  54. int16_t data[3];
  55. lsm6ds3tr_c_reg_t reg;
  56. lsm6ds3tr_c_status_reg_get(&lsm6ds3trc_ctx, &reg.status_reg);
  57. if(reg.status_reg.xlda) {
  58. lsm6ds3tr_c_acceleration_raw_get(&lsm6ds3trc_ctx, data);
  59. vec[2] = (double)lsm6ds3tr_c_from_fs2g_to_mg(data[0]) / 1000;
  60. vec[0] = (double)lsm6ds3tr_c_from_fs2g_to_mg(data[1]) / 1000;
  61. vec[1] = (double)lsm6ds3tr_c_from_fs2g_to_mg(data[2]) / 1000;
  62. ret |= ACC_DATA_READY;
  63. }
  64. if(reg.status_reg.gda) {
  65. lsm6ds3tr_c_angular_rate_raw_get(&lsm6ds3trc_ctx, data);
  66. vec[5] = (double)lsm6ds3tr_c_from_fs2000dps_to_mdps(data[0]) * DEG_TO_RAD / 1000;
  67. vec[3] = (double)lsm6ds3tr_c_from_fs2000dps_to_mdps(data[1]) * DEG_TO_RAD / 1000;
  68. vec[4] = (double)lsm6ds3tr_c_from_fs2000dps_to_mdps(data[2]) * DEG_TO_RAD / 1000;
  69. ret |= GYR_DATA_READY;
  70. }
  71. return ret;
  72. }