cc1101-workaround.cpp 20 KB

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  1. #include "cc1101.h"
  2. #include <furi.h>
  3. #include <api-hal.h>
  4. #include <gui/gui.h>
  5. #include <input/input.h>
  6. #define RSSI_DELAY 5000 //rssi delay in micro second
  7. #define CHAN_SPA 0.05 // channel spacing
  8. int16_t rssi_to_dbm(uint8_t rssi_dec, uint8_t rssiOffset) {
  9. int16_t rssi;
  10. if(rssi_dec >= 128) {
  11. rssi = (int16_t)((int16_t)(rssi_dec - 256) / 2) - rssiOffset;
  12. } else {
  13. rssi = (rssi_dec / 2) - rssiOffset;
  14. }
  15. return rssi;
  16. }
  17. typedef struct {
  18. float base_freq;
  19. uint8_t reg[3]; // FREQ2, FREQ1, FREQ0
  20. uint8_t first_channel;
  21. uint8_t last_channel;
  22. uint8_t rssi_offset;
  23. } Band;
  24. typedef struct {
  25. const Band* band;
  26. uint16_t channel;
  27. } FreqConfig;
  28. void setup_freq(CC1101* cc1101, float freq) {
  29. // cc1101->SpiWriteReg(CC1101_MCSM0, 0x08); // disalbe FS_AUTOCAL
  30. // cc1101->SpiWriteReg(CC1101_AGCCTRL2, 0x43 | 0x0C); // MAX_DVGA_GAIN to 11 for fast rssi
  31. // cc1101->SpiWriteReg(CC1101_AGCCTRL0, 0xB0); // max AGC WAIT_TIME; 0 filter_length
  32. // cc1101->SetMod(GFSK); // set to GFSK for fast rssi measurement | +8 is dcfilter off
  33. uint32_t freq_reg = freq * 1e6 / (F_OSC / 65536);
  34. cc1101->SetFreq((freq_reg >> 16) & 0xFF, (freq_reg >> 8) & 0xFF, (freq_reg)&0xFF);
  35. cc1101->SetChannel(0);
  36. /*
  37. //set test0 to 0x09
  38. cc1101->SpiWriteReg(CC1101_TEST0, 0x09);
  39. //set FSCAL2 to 0x2A to force VCO HIGH
  40. cc1101->SpiWriteReg(CC1101_FSCAL2, 0x2A);
  41. // perform a manual calibration by issuing SCAL command
  42. cc1101->SpiStrobe(CC1101_SCAL);
  43. */
  44. }
  45. static GpioPin debug_0 = {GPIOB, GPIO_PIN_2};
  46. int16_t rx_rssi(CC1101* cc1101, const FreqConfig* config) {
  47. // cc1101->SpiStrobe(CC1101_SFRX);
  48. // cc1101->SetReceive();
  49. // uint8_t begin_size = cc1101->SpiReadStatus(CC1101_RXBYTES);
  50. // uint8_t rx_status = cc1101->SpiReadStatus(CC1101_MARCSTATE);
  51. // delay_us(RSSI_DELAY);
  52. // osDelay(15);
  53. // uint8_t end_size = cc1101->SpiReadStatus(CC1101_RXBYTES);
  54. // 1.4.8) read PKTSTATUS register while the radio is in RX state
  55. /*uint8_t _pkt_status = */ // cc1101->SpiReadStatus(CC1101_PKTSTATUS);
  56. // 1.4.9) enter IDLE state by issuing a SIDLE command
  57. // cc1101->SpiStrobe(CC1101_SIDLE);
  58. // //read rssi value and converto to dBm form
  59. uint8_t rssi_dec = (uint8_t)cc1101->SpiReadStatus(CC1101_RSSI);
  60. int16_t rssi_dBm = rssi_to_dbm(rssi_dec, config->band->rssi_offset);
  61. /*
  62. char buf[256];
  63. sprintf(buf, "status: %d -> %d, rssi: %d\n", rx_status, cc1101->SpiReadStatus(CC1101_MARCSTATE), rssi_dBm);
  64. printf(buf);
  65. sprintf(buf, "begin: %d, end: %d\n", begin_size, end_size);
  66. printf(buf);
  67. */
  68. // uint8_t rx_data[64];
  69. // uint8_t fifo_length = end_size - begin_size;
  70. /*
  71. if(fifo_length < 64) {
  72. // cc1101->SpiReadBurstReg(CC1101_RXFIFO, rx_data, fifo_length);
  73. *
  74. printf("FIFO:");
  75. for(uint8_t i = 0; i < fifo_length; i++) {
  76. for(uint8_t bit = 0; bit < 8; bit++) {
  77. printf("%s", (rx_data[i] & (1 << bit)) > 0 ? "1" : "0");
  78. }
  79. printf(" ");
  80. }
  81. printf("\r\n");
  82. *
  83. for(uint8_t i = 0; i < fifo_length; i++) {
  84. for(uint8_t bit = 0; bit < 8; bit++) {
  85. gpio_write((GpioPin*)&debug_0, (rx_data[i] & (1 << bit)) > 0);
  86. delay_us(5);
  87. }
  88. }
  89. } else {
  90. printf("fifo size over\r\n");
  91. }
  92. */
  93. return rssi_dBm;
  94. }
  95. /*
  96. void flp_config(CC1101* cc1101) {
  97. cc1101->SpiWriteReg(
  98. CC1101_MCSM0, 0x18); // calibrate when going from IDLE to RX or TX ; 149 - 155 μs timeout
  99. // MCSM0.FS_AUTOCAL[1:0] = 1
  100. cc1101->SpiWriteReg(CC1101_AGCCTRL2, 0x43);
  101. cc1101->SpiWriteReg(CC1101_AGCCTRL1, 0x49);
  102. cc1101->SpiWriteReg(CC1101_AGCCTRL0, 0x91);
  103. //freq synthesizer calibration
  104. cc1101->SpiWriteReg(CC1101_FSCAL3, 0xEA);
  105. cc1101->SpiWriteReg(CC1101_FSCAL2, 0x2A);
  106. cc1101->SpiWriteReg(CC1101_FSCAL1, 0x00);
  107. cc1101->SpiWriteReg(CC1101_FSCAL0, 0x1F);
  108. // async data out
  109. cc1101->SpiSetRegValue(CC1101_IOCFG0, 13, 5, 0); // GDO0 Output Pin Configuration
  110. cc1101->SpiSetRegValue(CC1101_IOCFG0, 13, 5, 0); // WAT
  111. // FIFOTHR.ADC_RETENTION = 1
  112. cc1101->SpiSetRegValue(CC1101_FIFOTHR, 1, 6, 6);
  113. // PKTCTRL1.APPEND_STATUS = 0
  114. cc1101->SpiSetRegValue(CC1101_PKTCTRL1, 0, 2, 2);
  115. // PKTCTRL0.WHITE_DATA = 0
  116. cc1101->SpiSetRegValue(CC1101_PKTCTRL0, 0, 6, 6);
  117. // PKTCTRL0.LENGTH_CONFIG = 2 // Infinite packet length mode
  118. cc1101->SpiSetRegValue(CC1101_PKTCTRL0, 2, 1, 0);
  119. // PKTCTRL0.CRC_EN = 0
  120. cc1101->SpiSetRegValue(CC1101_PKTCTRL0, 0, 2, 2);
  121. // PKTCTRL0.PKT_FORMAT = 3
  122. cc1101->SpiSetRegValue(CC1101_PKTCTRL0, 3, 5, 4);
  123. // bandwidth 50-100 kHz
  124. if(!cc1101->setRxBandwidth(75.0)) {
  125. printf("wrong rx bw\r\n");
  126. }
  127. // datarate ~30 kbps
  128. if(!cc1101->setBitRate(100.)) {
  129. printf("wrong bitrate\r\n");
  130. }
  131. // mod
  132. // MDMCFG2.MOD_FORMAT = 3 (3: OOK, 0: 2-FSK)
  133. cc1101->SpiSetRegValue(CC1101_MDMCFG2, 3, 6, 4);
  134. // MDMCFG2.SYNC_MODE = 0
  135. cc1101->SpiSetRegValue(CC1101_MDMCFG2, 0, 2, 0);
  136. }
  137. */
  138. void tx_config(CC1101* cc1101) {
  139. // cc1101->SpiWriteReg(CC1101_IOCFG2,0x0B); //GDO2 Output Pin Configuration
  140. // cc1101->SpiWriteReg(CC1101_IOCFG0,0x0C); //GDO0 Output Pin Configuration
  141. cc1101->SpiSetRegValue(CC1101_IOCFG0, 13, 5, 0); // GDO0 Output Pin Configuration
  142. cc1101->SpiWriteReg(CC1101_FIFOTHR, 0x47); //RX FIFO and TX FIFO Thresholds
  143. cc1101->SpiWriteReg(CC1101_PKTCTRL0, 0x32); //Packet Automation Control
  144. cc1101->SpiWriteReg(CC1101_FSCTRL1, 0x06); //Frequency Synthesizer Control
  145. cc1101->SpiWriteReg(CC1101_FREQ2, 0x10); //Frequency Control Word, High Byte
  146. cc1101->SpiWriteReg(CC1101_FREQ1, 0xB0); //Frequency Control Word, Middle Byte
  147. cc1101->SpiWriteReg(CC1101_FREQ0, 0x71); //Frequency Control Word, Low Byte
  148. cc1101->SpiWriteReg(CC1101_MDMCFG4, 0x6A); //Modem Configuration
  149. cc1101->SpiWriteReg(CC1101_MDMCFG3, 0x2E); //Modem Configuration
  150. cc1101->SpiWriteReg(CC1101_MDMCFG2, 0x30); //Modem Configuration
  151. cc1101->SpiWriteReg(CC1101_DEVIATN, 0x15); //Modem Deviation Setting
  152. cc1101->SpiWriteReg(CC1101_MCSM0, 0x18); //Main Radio Control State Machine Configuration
  153. cc1101->SpiWriteReg(CC1101_FOCCFG, 0x16); //Frequency Offset Compensation Configuration
  154. cc1101->SpiWriteReg(CC1101_WORCTRL, 0xFB); //Wake On Radio Control
  155. cc1101->SpiWriteReg(CC1101_FREND0, 0x11); //Front End TX Configuration
  156. cc1101->SpiWriteReg(CC1101_FSCAL3, 0xE9); //Frequency Synthesizer Calibration
  157. cc1101->SpiWriteReg(CC1101_FSCAL2, 0x2A); //Frequency Synthesizer Calibration
  158. cc1101->SpiWriteReg(CC1101_FSCAL1, 0x00); //Frequency Synthesizer Calibration
  159. cc1101->SpiWriteReg(CC1101_FSCAL0, 0x1F); //Frequency Synthesizer Calibration
  160. /*
  161. cc1101->SpiWriteReg(CC1101_TEST2, 0x81); //Various Test Settings
  162. cc1101->SpiWriteReg(CC1101_TEST1, 0x35); //Various Test Settings
  163. cc1101->SpiWriteReg(CC1101_TEST0, 0x09); //Various Test Settings
  164. */
  165. }
  166. // f = (f_osc/65536) * (FREQ + CHAN * (256 + CH_SP_M) * 2^(CH_SP_E - 2))
  167. // FREQ = f / (f_osc/65536)
  168. // CHAN = 0
  169. // TODO: CHAN number not implemented!
  170. // TODO: reg values not affetcts
  171. const Band bands[] = {
  172. {301., {0x00, 0x00, 0x00}, 0, 255, 74},
  173. {315., {0x00, 0x00, 0x00}, 0, 255, 74},
  174. {346., {0x00, 0x00, 0x00}, 0, 255, 74},
  175. {385., {0x00, 0x00, 0x00}, 0, 255, 74},
  176. {433.92, {0x00, 0x00, 0x00}, 0, 255, 74},
  177. {438.9, {0x00, 0x00, 0x00}, 0, 255, 74},
  178. {463., {0x00, 0x00, 0x00}, 0, 255, 74},
  179. {781., {0x00, 0x00, 0x00}, 0, 255, 74},
  180. {868., {0x00, 0x00, 0x00}, 0, 255, 74},
  181. {915., {0x00, 0x00, 0x00}, 0, 255, 74},
  182. {925., {0x00, 0x00, 0x00}, 0, 255, 74},
  183. };
  184. const FreqConfig FREQ_LIST[] = {
  185. {&bands[0], 0},
  186. {&bands[1], 0},
  187. {&bands[2], 0},
  188. {&bands[3], 0},
  189. {&bands[4], 0},
  190. {&bands[5], 0},
  191. {&bands[6], 0},
  192. {&bands[7], 0},
  193. {&bands[8], 0},
  194. {&bands[9], 0},
  195. {&bands[10], 0},
  196. };
  197. extern "C" void cc1101_isr(void* _pin, void* _ctx) {
  198. uint32_t pin = (uint32_t)_pin;
  199. if(pin == CC1101_G0_Pin) {
  200. gpio_write((GpioPin*)&debug_0, gpio_read(&cc1101_g0_gpio));
  201. }
  202. }
  203. typedef enum {
  204. EventTypeTick,
  205. EventTypeKey,
  206. } EventType;
  207. typedef struct {
  208. union {
  209. InputEvent input;
  210. } value;
  211. EventType type;
  212. } AppEvent;
  213. typedef enum { ModeRx, ModeTx } Mode;
  214. typedef struct {
  215. int16_t dbm;
  216. uint8_t reg;
  217. } TxLevel;
  218. const TxLevel TX_LEVELS[] = {
  219. {-10, 0},
  220. {-5, 0},
  221. {0, 0},
  222. {5, 0},
  223. };
  224. typedef struct {
  225. Mode mode;
  226. size_t active_freq_idx;
  227. float active_freq;
  228. int16_t last_rssi;
  229. size_t tx_level;
  230. bool need_cc1101_conf;
  231. RfBand rf_band;
  232. } State;
  233. static void render_callback(Canvas* canvas, void* ctx) {
  234. State* state = (State*)acquire_mutex((ValueMutex*)ctx, 25);
  235. if(!state) return;
  236. canvas_clear(canvas);
  237. canvas_set_color(canvas, ColorBlack);
  238. canvas_set_font(canvas, FontPrimary);
  239. canvas_draw_str(canvas, 2, 12, "cc1101 workaround");
  240. {
  241. char buf[24];
  242. sprintf(
  243. buf,
  244. "freq: %ld.%02ld MHz",
  245. (uint32_t)state->active_freq,
  246. (uint32_t)(state->active_freq * 100.) % 100);
  247. canvas_set_font(canvas, FontSecondary);
  248. canvas_draw_str(canvas, 2, 25, buf);
  249. }
  250. {
  251. canvas_set_font(canvas, FontSecondary);
  252. if(state->need_cc1101_conf) {
  253. canvas_draw_str(canvas, 2, 36, "mode: configuring...");
  254. } else if(state->mode == ModeRx) {
  255. canvas_draw_str(canvas, 2, 36, "mode: RX");
  256. } else if(state->mode == ModeTx) {
  257. canvas_draw_str(canvas, 2, 36, "mode: TX");
  258. } else {
  259. canvas_draw_str(canvas, 2, 36, "mode: unknown");
  260. }
  261. }
  262. {
  263. if(!state->need_cc1101_conf && state->mode == ModeRx) {
  264. char buf[24];
  265. sprintf(buf, "RSSI: %d dBm", state->last_rssi);
  266. canvas_set_font(canvas, FontSecondary);
  267. canvas_draw_str(canvas, 2, 48, buf);
  268. }
  269. }
  270. {
  271. char buf[24];
  272. // sprintf(buf, "tx level: %d dBm", TX_LEVELS[state->tx_level].dbm);
  273. sprintf(buf, "RF band: %d", (uint8_t)state->rf_band);
  274. canvas_set_font(canvas, FontSecondary);
  275. if(state->rf_band == RfBandIsolation) {
  276. canvas_draw_str(canvas, 2, 63, "RF band: isolation");
  277. } else {
  278. canvas_draw_str(canvas, 2, 63, buf);
  279. }
  280. }
  281. release_mutex((ValueMutex*)ctx, state);
  282. }
  283. static void input_callback(InputEvent* input_event, void* ctx) {
  284. osMessageQueueId_t event_queue = ctx;
  285. AppEvent event;
  286. event.type = EventTypeKey;
  287. event.value.input = *input_event;
  288. osMessageQueuePut(event_queue, &event, 0, 0);
  289. }
  290. extern "C" int32_t cc1101_workaround(void* p) {
  291. osMessageQueueId_t event_queue = osMessageQueueNew(8, sizeof(AppEvent), NULL);
  292. furi_check(event_queue);
  293. State _state;
  294. _state.mode = ModeRx;
  295. _state.active_freq_idx = 4;
  296. FreqConfig conf = FREQ_LIST[_state.active_freq_idx];
  297. _state.active_freq = conf.band->base_freq + CHAN_SPA * conf.channel;
  298. _state.need_cc1101_conf = true;
  299. _state.last_rssi = 0;
  300. _state.tx_level = 0;
  301. _state.rf_band = RfBand1;
  302. ValueMutex state_mutex;
  303. if(!init_mutex(&state_mutex, &_state, sizeof(State))) {
  304. printf("[cc1101] cannot create mutex\r\n");
  305. return 255;
  306. }
  307. ViewPort* view_port = view_port_alloc();
  308. view_port_draw_callback_set(view_port, render_callback, &state_mutex);
  309. view_port_input_callback_set(view_port, input_callback, event_queue);
  310. // Open GUI and register view_port
  311. Gui* gui = (Gui*)furi_record_open("gui");
  312. if(gui == NULL) {
  313. printf("[cc1101] gui is not available\r\n");
  314. return 255;
  315. }
  316. gui_add_view_port(gui, view_port, GuiLayerFullscreen);
  317. gpio_init(&debug_0, GpioModeOutputPushPull);
  318. gpio_write((GpioPin*)&debug_0, false);
  319. printf("[cc1101] creating device\r\n");
  320. GpioPin cs_pin = {CC1101_CS_GPIO_Port, CC1101_CS_Pin};
  321. gpio_init(&cc1101_g0_gpio, GpioModeInput);
  322. api_interrupt_add(cc1101_isr, InterruptTypeExternalInterrupt, NULL);
  323. // TODO open record
  324. GpioPin* cs_pin_record = &cs_pin;
  325. CC1101 cc1101(cs_pin_record);
  326. printf("[cc1101] init device\r\n");
  327. uint8_t address = cc1101.Init();
  328. if(address > 0) {
  329. printf("[cc1101] init done: %d\r\n", address);
  330. } else {
  331. printf("[cc1101] init fail\r\n");
  332. return 255;
  333. }
  334. cc1101.SpiStrobe(CC1101_SIDLE);
  335. // flp_config(&cc1101);
  336. tx_config(&cc1101);
  337. // setup_freq(&cc1101, &FREQ_LIST[4]);
  338. // enable_cc1101_irq();
  339. printf("init ok\r\n");
  340. const int16_t RSSI_THRESHOLD = -60;
  341. // setup_freq(&cc1101, &FREQ_LIST[1]);
  342. cc1101.SetReceive();
  343. AppEvent event;
  344. while(1) {
  345. osStatus_t event_status = osMessageQueueGet(event_queue, &event, NULL, 100);
  346. State* state = (State*)acquire_mutex_block(&state_mutex);
  347. if(event_status == osOK) {
  348. if(event.type == EventTypeKey) {
  349. if(event.value.input.type == InputTypeShort &&
  350. event.value.input.key == InputKeyBack) {
  351. printf("[cc1101] bye!\r\n");
  352. cc1101.SpiStrobe(CC1101_SIDLE);
  353. cc1101.SpiStrobe(CC1101_SPWD);
  354. printf("[cc1101] go to power down\r\n");
  355. // TODO remove all view_ports create by app
  356. view_port_enabled_set(view_port, false);
  357. return 255;
  358. }
  359. if(event.value.input.type == InputTypeShort &&
  360. event.value.input.key == InputKeyDown) {
  361. if(state->active_freq_idx > 0) {
  362. state->active_freq_idx--;
  363. }
  364. FreqConfig conf = FREQ_LIST[state->active_freq_idx];
  365. state->active_freq = conf.band->base_freq + CHAN_SPA * conf.channel;
  366. state->need_cc1101_conf = true;
  367. }
  368. if(event.value.input.type == InputTypeShort &&
  369. event.value.input.key == InputKeyUp) {
  370. if(state->active_freq_idx < (sizeof(FREQ_LIST) / sizeof(FREQ_LIST[0]) - 1)) {
  371. state->active_freq_idx++;
  372. }
  373. FreqConfig conf = FREQ_LIST[state->active_freq_idx];
  374. state->active_freq = conf.band->base_freq + CHAN_SPA * conf.channel;
  375. state->need_cc1101_conf = true;
  376. }
  377. if(event.value.input.type == InputTypeShort &&
  378. event.value.input.key == InputKeyRight) {
  379. /*
  380. if(state->tx_level < (sizeof(TX_LEVELS) / sizeof(TX_LEVELS[0]) - 1)) {
  381. state->tx_level++;
  382. } else {
  383. state->tx_level = 0;
  384. }
  385. */
  386. if(state->rf_band < RfBand3) {
  387. state->rf_band = (RfBand)((uint8_t)state->rf_band + 1);
  388. } else {
  389. state->active_freq += 0.25;
  390. }
  391. state->need_cc1101_conf = true;
  392. }
  393. if(event.value.input.type == InputTypeShort &&
  394. event.value.input.key == InputKeyLeft) {
  395. /*
  396. if(state->tx_level < (sizeof(TX_LEVELS) / sizeof(TX_LEVELS[0]) - 1)) {
  397. state->tx_level++;
  398. } else {
  399. state->tx_level = 0;
  400. }
  401. */
  402. if(state->rf_band > RfBandIsolation) {
  403. state->rf_band = (RfBand)((uint8_t)state->rf_band - 1);
  404. } else {
  405. state->active_freq -= 0.25;
  406. }
  407. state->need_cc1101_conf = true;
  408. }
  409. if(event.value.input.key == InputKeyOk) {
  410. if(event.value.input.type == InputTypePress) {
  411. state->mode = ModeTx;
  412. state->need_cc1101_conf = true;
  413. } else if(event.value.input.type == InputTypeRelease) {
  414. state->mode = ModeRx;
  415. state->need_cc1101_conf = true;
  416. }
  417. }
  418. }
  419. } else {
  420. }
  421. if(state->need_cc1101_conf) {
  422. if(state->mode == ModeRx) {
  423. cc1101.SpiStrobe(CC1101_SIDLE);
  424. gpio_init(&cc1101_g0_gpio, GpioModeInput);
  425. setup_freq(&cc1101, state->active_freq);
  426. cc1101.SetReceive();
  427. state->last_rssi = rx_rssi(&cc1101, &FREQ_LIST[state->active_freq_idx]);
  428. } else if(state->mode == ModeTx) {
  429. cc1101.SpiStrobe(CC1101_SIDLE);
  430. setup_freq(&cc1101, state->active_freq);
  431. cc1101.SetTransmit();
  432. gpio_init(&cc1101_g0_gpio, GpioModeOutputPushPull);
  433. gpio_write(&cc1101_g0_gpio, false);
  434. }
  435. api_hal_rf_band_set(state->rf_band);
  436. state->need_cc1101_conf = false;
  437. }
  438. if(!state->need_cc1101_conf && state->mode == ModeRx) {
  439. // TOOD what about rssi offset
  440. state->last_rssi = rx_rssi(&cc1101, &FREQ_LIST[state->active_freq_idx]);
  441. api_hal_light_set(LightGreen, state->last_rssi > RSSI_THRESHOLD ? 0xFF : 0x00);
  442. } else if(!state->need_cc1101_conf && state->mode == ModeTx) {
  443. /*
  444. const uint8_t data = 0xA5;
  445. for(uint8_t i = 0; i < 8; i++) {
  446. gpio_write(&cc1101_g0_gpio, (data & (1 << i)) > 0);
  447. osDelay(1);
  448. }
  449. gpio_write(&cc1101_g0_gpio, false);
  450. */
  451. /*
  452. // BELL UDB-Q022-0000
  453. const uint16_t HALF_PERIOD = 500;
  454. for(uint8_t n = 0; n < 4; n++) {
  455. for(uint8_t i = 0; i < 4; i++) {
  456. gpio_write(&cc1101_g0_gpio, true);
  457. delay_us(3 * HALF_PERIOD);
  458. gpio_write(&cc1101_g0_gpio, false);
  459. delay_us(HALF_PERIOD);
  460. }
  461. for(uint8_t i = 0; i < 40; i++) {
  462. gpio_write(&cc1101_g0_gpio, true);
  463. delay_us(HALF_PERIOD);
  464. gpio_write(&cc1101_g0_gpio, false);
  465. delay_us(HALF_PERIOD);
  466. }
  467. }
  468. */
  469. // BELL ERA C61, static code
  470. const uint16_t ONE_ON = 150;
  471. const uint16_t ONE_OFF = 400;
  472. const uint16_t ZERO_ON = 420;
  473. const uint16_t ZERO_OFF = 130;
  474. const bool SEQ[] = {true, true, false, false, true, false, true, false, true,
  475. false, true, true, true, false, true, false, true, true,
  476. true, true, true, false, true, false, true};
  477. for(uint8_t n = 0; n < 10; n++) {
  478. for(uint8_t i = 0; i < sizeof(SEQ) / sizeof(SEQ[0]); i++) {
  479. if(SEQ[i]) {
  480. gpio_write(&cc1101_g0_gpio, false);
  481. delay_us(ONE_ON);
  482. gpio_write(&cc1101_g0_gpio, true);
  483. delay_us(ONE_OFF);
  484. } else {
  485. gpio_write(&cc1101_g0_gpio, false);
  486. delay_us(ZERO_ON);
  487. gpio_write(&cc1101_g0_gpio, true);
  488. delay_us(ZERO_OFF);
  489. }
  490. }
  491. osDelay(4);
  492. }
  493. gpio_write(&cc1101_g0_gpio, false);
  494. }
  495. release_mutex(&state_mutex, state);
  496. view_port_update(view_port);
  497. }
  498. return 0;
  499. }