lsm6ds3trc.c 3.4 KB

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  1. #include "imu.h"
  2. #include "../../lib/lsm6ds3tr-api/lsm6ds3tr-c_reg.h"
  3. #define LSM6DS3_TAG "LSM6DS3"
  4. #define LSM6DS3_DEV_ADDRESS (0x6A << 1)
  5. stmdev_ctx_t lsm6ds3trc_ctx;
  6. int32_t lsm6ds3trc_write_i2c(void* handle, uint8_t reg_addr, const uint8_t* data, uint16_t len) {
  7. if(furi_hal_i2c_write_mem(handle, LSM6DS3_DEV_ADDRESS, reg_addr, (uint8_t*)data, len, 50))
  8. return 0;
  9. return -1;
  10. }
  11. int32_t lsm6ds3trc_read_i2c(void* handle, uint8_t reg_addr, uint8_t* read_data, uint16_t len) {
  12. if(furi_hal_i2c_read_mem(handle, LSM6DS3_DEV_ADDRESS, reg_addr, read_data, len, 50)) return 0;
  13. return -1;
  14. }
  15. bool lsm6ds3trc_begin() {
  16. FURI_LOG_I(LSM6DS3_TAG, "Init LSM6DS3TR-C");
  17. if(!furi_hal_i2c_is_device_ready(&furi_hal_i2c_handle_external, LSM6DS3_DEV_ADDRESS, 50)) {
  18. FURI_LOG_E(LSM6DS3_TAG, "Not ready");
  19. return false;
  20. }
  21. lsm6ds3trc_ctx.write_reg = lsm6ds3trc_write_i2c;
  22. lsm6ds3trc_ctx.read_reg = lsm6ds3trc_read_i2c;
  23. lsm6ds3trc_ctx.mdelay = furi_delay_ms;
  24. lsm6ds3trc_ctx.handle = (void*)&furi_hal_i2c_handle_external;
  25. uint8_t whoami;
  26. lsm6ds3tr_c_device_id_get(&lsm6ds3trc_ctx, &whoami);
  27. if(whoami != LSM6DS3TR_C_ID) {
  28. FURI_LOG_I(LSM6DS3_TAG, "Unknown model: %x", (int)whoami);
  29. return false;
  30. }
  31. lsm6ds3tr_c_reset_set(&lsm6ds3trc_ctx, PROPERTY_ENABLE);
  32. uint8_t rst = PROPERTY_ENABLE;
  33. while(rst)
  34. lsm6ds3tr_c_reset_get(&lsm6ds3trc_ctx, &rst);
  35. lsm6ds3tr_c_block_data_update_set(&lsm6ds3trc_ctx, PROPERTY_ENABLE);
  36. lsm6ds3tr_c_fifo_mode_set(&lsm6ds3trc_ctx, LSM6DS3TR_C_BYPASS_MODE);
  37. lsm6ds3tr_c_xl_data_rate_set(&lsm6ds3trc_ctx, LSM6DS3TR_C_XL_ODR_104Hz);
  38. lsm6ds3tr_c_xl_full_scale_set(&lsm6ds3trc_ctx, LSM6DS3TR_C_4g);
  39. lsm6ds3tr_c_xl_lp1_bandwidth_set(&lsm6ds3trc_ctx, LSM6DS3TR_C_XL_LP1_ODR_DIV_4);
  40. lsm6ds3tr_c_gy_data_rate_set(&lsm6ds3trc_ctx, LSM6DS3TR_C_GY_ODR_104Hz);
  41. lsm6ds3tr_c_gy_full_scale_set(&lsm6ds3trc_ctx, LSM6DS3TR_C_2000dps);
  42. lsm6ds3tr_c_gy_power_mode_set(&lsm6ds3trc_ctx, LSM6DS3TR_C_GY_HIGH_PERFORMANCE);
  43. lsm6ds3tr_c_gy_band_pass_set(&lsm6ds3trc_ctx, LSM6DS3TR_C_LP2_ONLY);
  44. FURI_LOG_I(LSM6DS3_TAG, "Init OK");
  45. return true;
  46. }
  47. void lsm6ds3trc_end() {
  48. lsm6ds3tr_c_xl_data_rate_set(&lsm6ds3trc_ctx, LSM6DS3TR_C_XL_ODR_OFF);
  49. lsm6ds3tr_c_gy_data_rate_set(&lsm6ds3trc_ctx, LSM6DS3TR_C_GY_ODR_OFF);
  50. }
  51. int lsm6ds3trc_read(double* vec) {
  52. int ret = 0;
  53. int16_t data[3];
  54. lsm6ds3tr_c_reg_t reg;
  55. lsm6ds3tr_c_status_reg_get(&lsm6ds3trc_ctx, &reg.status_reg);
  56. if(reg.status_reg.xlda) {
  57. lsm6ds3tr_c_acceleration_raw_get(&lsm6ds3trc_ctx, data);
  58. vec[1] = (double)lsm6ds3tr_c_from_fs2g_to_mg(data[0]) / 1000;
  59. vec[0] = (double)lsm6ds3tr_c_from_fs2g_to_mg(data[1]) / 1000;
  60. vec[2] = -(double)lsm6ds3tr_c_from_fs2g_to_mg(data[2]) / 1000;
  61. ret |= ACC_DATA_READY;
  62. }
  63. if(reg.status_reg.gda) {
  64. lsm6ds3tr_c_angular_rate_raw_get(&lsm6ds3trc_ctx, data);
  65. vec[4] = (double)lsm6ds3tr_c_from_fs2000dps_to_mdps(data[0]) * DEG_TO_RAD / 1000;
  66. vec[3] = (double)lsm6ds3tr_c_from_fs2000dps_to_mdps(data[1]) * DEG_TO_RAD / 1000;
  67. vec[5] = -(double)lsm6ds3tr_c_from_fs2000dps_to_mdps(data[2]) * DEG_TO_RAD / 1000;
  68. ret |= GYR_DATA_READY;
  69. }
  70. return ret;
  71. }
  72. struct imu_t imu_lsm6ds3trc =
  73. {LSM6DS3_DEV_ADDRESS, lsm6ds3trc_begin, lsm6ds3trc_end, lsm6ds3trc_read, LSM6DS3_TAG};