Add dap_link from https://github.com/xMasterX/all-the-plugins

git-subtree-dir: dap_link
git-subtree-mainline: 5444090a68f42fe5d8a70ecdb69d7f289e89cba7
git-subtree-split: dcd256bc647a954c9a41119d6d17116ceb87c524

dap_link/.gitsubtree

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+https://github.com/xMasterX/all-the-plugins dev base_pack/dap_link

dap_link/README.md

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+# Flipper Zero as CMSIS DAP/DAP Link
+
+Flipper Zero as a [Free-DAP](https://github.com/ataradov/free-dap) based SWD\JTAG debugger. Free-DAP is a free and open source firmware implementation of the [CMSIS-DAP](https://www.keil.com/pack/doc/CMSIS_Dev/DAP/html/index.html) debugger.
+
+## Protocols
+
+SWD, JTAG , CMSIS-DAP v1 (18 KiB/s), CMSIS-DAP v2 (46 KiB/s), VCP (USB-UART).
+
+WinUSB for driverless installation for Windows 8 and above.
+
+## Usage
+
+### VSCode + Cortex-Debug
+
+  Set `"device": "cmsis-dap"`
+  
+<details>
+  <summary>BluePill configuration example</summary>
+  
+  ```json
+{
+    "name": "Attach (DAP)",
+    "cwd": "${workspaceFolder}",
+    "executable": "./build/firmware.elf",
+    "request": "attach",
+    "type": "cortex-debug",
+    "servertype": "openocd",
+    "device": "cmsis-dap",
+    "configFiles": [
+        "interface/cmsis-dap.cfg",
+        "target/stm32f1x.cfg",
+    ],
+},
+  ```
+</details>
+
+<details>
+  <summary>Flipper Zero configuration example</summary>
+  
+  ```json
+{
+    "name": "Attach (DAP)",
+    "cwd": "${workspaceFolder}",
+    "executable": "./build/latest/firmware.elf",
+    "request": "attach",
+    "type": "cortex-debug",
+    "servertype": "openocd",
+    "device": "cmsis-dap",
+    "svdFile": "./debug/STM32WB55_CM4.svd",
+    "rtos": "FreeRTOS",
+    "configFiles": [
+        "interface/cmsis-dap.cfg",
+        "./debug/stm32wbx.cfg",
+    ],
+    "postAttachCommands": [
+        "source debug/flipperapps.py",
+    ],
+},
+  ```
+</details>
+
+### OpenOCD
+Use `interface/cmsis-dap.cfg`. You will need OpenOCD v0.11.0.
+
+Additional commands: 
+* `cmsis_dap_backend hid` for CMSIS-DAP v1 protocol.
+* `cmsis_dap_backend usb_bulk` for CMSIS-DAP v2 protocol.
+* `cmsis_dap_serial DAP_Oyevoxo` use DAP-Link running on Flipper named `Oyevoxo`.
+* `cmsis-dap cmd 81` - reboot connected DAP-Link.
+
+<details>
+  <summary>Flash BluePill</summary>
+  
+  ```
+openocd -f interface/cmsis-dap.cfg -f target/stm32f1x.cfg -c init -c "program build/firmware.bin reset exit 0x8000000"
+  ```
+</details>
+
+<details>
+  <summary>Flash Flipper Zero using DAP v2 protocol</summary>
+  
+  ```
+openocd -f interface/cmsis-dap.cfg -c "cmsis_dap_backend usb_bulk" -f debug/stm32wbx.cfg -c init -c "program build/latest/firmware.bin reset exit 0x8000000"
+  ```
+</details>
+
+<details>
+  <summary>Reboot connected DAP-Link on Flipper named Oyevoxo</summary>
+  
+  ```
+openocd -f interface/cmsis-dap.cfg -c "cmsis_dap_serial DAP_Oyevoxo" -c "transport select swd" -c "adapter speed 4000000" -c init -c "cmsis-dap cmd 81" -c "exit"
+  ```
+</details>
+
+### PlatformIO
+Use `debug_tool = cmsis-dap` and `upload_protocol = cmsis-dap`. [Documentation](https://docs.platformio.org/en/latest/plus/debug-tools/cmsis-dap.html#debugging-tool-cmsis-dap). Remember that Windows 8 and above do not require drivers.
+
+<details>
+  <summary>BluePill platformio.ini example</summary>
+  
+  ```
+[env:bluepill_f103c8]
+platform = ststm32
+board = bluepill_f103c8
+debug_tool = cmsis-dap
+upload_protocol = cmsis-dap
+  ```
+</details>

dap_link/application.fam

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+App(
+    appid="dap_link",
+    name="DAP Link",
+    apptype=FlipperAppType.EXTERNAL,
+    entry_point="dap_link_app",
+    requires=[
+        "gui",
+        "dialogs",
+    ],
+    stack_size=4 * 1024,
+    fap_description="Enables use of Flipper as a debug probe for ARM devices, implements the CMSIS-DAP protocol",
+    fap_version="1.1",
+    fap_icon="dap_link.png",
+    fap_category="GPIO",
+    fap_private_libs=[
+        Lib(
+            name="free-dap",
+            cincludes=["."],
+            sources=[
+                "dap.c",
+            ],
+        ),
+    ],
+    fap_icon_assets="icons",
+)

dap_link/dap_config.h

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+// SPDX-License-Identifier: BSD-3-Clause
+// Copyright (c) 2022, Alex Taradov <alex@taradov.com>. All rights reserved.
+
+#ifndef _DAP_CONFIG_H_
+#define _DAP_CONFIG_H_
+
+/*- Includes ----------------------------------------------------------------*/
+#include <furi_hal_gpio.h>
+
+/*- Definitions -------------------------------------------------------------*/
+#define DAP_CONFIG_ENABLE_JTAG
+
+#define DAP_CONFIG_DEFAULT_PORT DAP_PORT_SWD
+#define DAP_CONFIG_DEFAULT_CLOCK 4200000 // Hz
+
+#define DAP_CONFIG_PACKET_SIZE 64
+#define DAP_CONFIG_PACKET_COUNT 1
+
+#define DAP_CONFIG_JTAG_DEV_COUNT 8
+
+// DAP_CONFIG_PRODUCT_STR must contain "CMSIS-DAP" to be compatible with the standard
+#define DAP_CONFIG_VENDOR_STR "Flipper Zero"
+#define DAP_CONFIG_PRODUCT_STR "Generic CMSIS-DAP Adapter"
+#define DAP_CONFIG_SER_NUM_STR usb_serial_number
+#define DAP_CONFIG_CMSIS_DAP_VER_STR "2.0.0"
+
+#define DAP_CONFIG_RESET_TARGET_FN dap_app_target_reset
+#define DAP_CONFIG_VENDOR_FN dap_app_vendor_cmd
+
+// Attribute to use for performance-critical functions
+#define DAP_CONFIG_PERFORMANCE_ATTR
+
+// A value at which dap_clock_test() produces 1 kHz output on the SWCLK pin
+// #define DAP_CONFIG_DELAY_CONSTANT 19000
+#define DAP_CONFIG_DELAY_CONSTANT 6290
+
+// A threshold for switching to fast clock (no added delays)
+// This is the frequency produced by dap_clock_test(1) on the SWCLK pin
+#define DAP_CONFIG_FAST_CLOCK 2400000 // Hz
+
+/*- Prototypes --------------------------------------------------------------*/
+extern char usb_serial_number[16];
+
+/*- Implementations ---------------------------------------------------------*/
+extern GpioPin flipper_dap_swclk_pin;
+extern GpioPin flipper_dap_swdio_pin;
+extern GpioPin flipper_dap_reset_pin;
+extern GpioPin flipper_dap_tdo_pin;
+extern GpioPin flipper_dap_tdi_pin;
+
+extern void dap_app_vendor_cmd(uint8_t cmd);
+extern void dap_app_target_reset();
+extern void dap_app_disconnect();
+extern void dap_app_connect_swd();
+extern void dap_app_connect_jtag();
+
+//-----------------------------------------------------------------------------
+static inline void DAP_CONFIG_SWCLK_TCK_write(int value) {
+    furi_hal_gpio_write(&flipper_dap_swclk_pin, value);
+}
+
+//-----------------------------------------------------------------------------
+static inline void DAP_CONFIG_SWDIO_TMS_write(int value) {
+    furi_hal_gpio_write(&flipper_dap_swdio_pin, value);
+}
+
+//-----------------------------------------------------------------------------
+static inline void DAP_CONFIG_TDI_write(int value) {
+#ifdef DAP_CONFIG_ENABLE_JTAG
+    furi_hal_gpio_write(&flipper_dap_tdi_pin, value);
+#else
+    (void)value;
+#endif
+}
+
+//-----------------------------------------------------------------------------
+static inline void DAP_CONFIG_TDO_write(int value) {
+#ifdef DAP_CONFIG_ENABLE_JTAG
+    furi_hal_gpio_write(&flipper_dap_tdo_pin, value);
+#else
+    (void)value;
+#endif
+}
+
+//-----------------------------------------------------------------------------
+static inline void DAP_CONFIG_nTRST_write(int value) {
+    (void)value;
+}
+
+//-----------------------------------------------------------------------------
+static inline void DAP_CONFIG_nRESET_write(int value) {
+    furi_hal_gpio_write(&flipper_dap_reset_pin, value);
+}
+
+//-----------------------------------------------------------------------------
+static inline int DAP_CONFIG_SWCLK_TCK_read(void) {
+    return furi_hal_gpio_read(&flipper_dap_swclk_pin);
+}
+
+//-----------------------------------------------------------------------------
+static inline int DAP_CONFIG_SWDIO_TMS_read(void) {
+    return furi_hal_gpio_read(&flipper_dap_swdio_pin);
+}
+
+//-----------------------------------------------------------------------------
+static inline int DAP_CONFIG_TDO_read(void) {
+#ifdef DAP_CONFIG_ENABLE_JTAG
+    return furi_hal_gpio_read(&flipper_dap_tdo_pin);
+#else
+    return 0;
+#endif
+}
+
+//-----------------------------------------------------------------------------
+static inline int DAP_CONFIG_TDI_read(void) {
+#ifdef DAP_CONFIG_ENABLE_JTAG
+    return furi_hal_gpio_read(&flipper_dap_tdi_pin);
+#else
+    return 0;
+#endif
+}
+
+//-----------------------------------------------------------------------------
+static inline int DAP_CONFIG_nTRST_read(void) {
+    return 0;
+}
+
+//-----------------------------------------------------------------------------
+static inline int DAP_CONFIG_nRESET_read(void) {
+    return furi_hal_gpio_read(&flipper_dap_reset_pin);
+}
+
+//-----------------------------------------------------------------------------
+static inline void DAP_CONFIG_SWCLK_TCK_set(void) {
+    LL_GPIO_SetOutputPin(flipper_dap_swclk_pin.port, flipper_dap_swclk_pin.pin);
+}
+
+//-----------------------------------------------------------------------------
+static inline void DAP_CONFIG_SWCLK_TCK_clr(void) {
+    LL_GPIO_ResetOutputPin(flipper_dap_swclk_pin.port, flipper_dap_swclk_pin.pin);
+}
+
+//-----------------------------------------------------------------------------
+static inline void DAP_CONFIG_SWDIO_TMS_in(void) {
+    LL_GPIO_SetPinMode(flipper_dap_swdio_pin.port, flipper_dap_swdio_pin.pin, LL_GPIO_MODE_INPUT);
+}
+
+//-----------------------------------------------------------------------------
+static inline void DAP_CONFIG_SWDIO_TMS_out(void) {
+    LL_GPIO_SetPinMode(flipper_dap_swdio_pin.port, flipper_dap_swdio_pin.pin, LL_GPIO_MODE_OUTPUT);
+}
+
+//-----------------------------------------------------------------------------
+static inline void DAP_CONFIG_SETUP(void) {
+    furi_hal_gpio_init(&flipper_dap_swdio_pin, GpioModeInput, GpioPullNo, GpioSpeedVeryHigh);
+    furi_hal_gpio_init(&flipper_dap_swclk_pin, GpioModeInput, GpioPullNo, GpioSpeedVeryHigh);
+    furi_hal_gpio_init(&flipper_dap_reset_pin, GpioModeInput, GpioPullNo, GpioSpeedVeryHigh);
+#ifdef DAP_CONFIG_ENABLE_JTAG
+    furi_hal_gpio_init(&flipper_dap_tdo_pin, GpioModeInput, GpioPullNo, GpioSpeedVeryHigh);
+    furi_hal_gpio_init(&flipper_dap_tdi_pin, GpioModeInput, GpioPullNo, GpioSpeedVeryHigh);
+#endif
+}
+
+//-----------------------------------------------------------------------------
+static inline void DAP_CONFIG_DISCONNECT(void) {
+    furi_hal_gpio_init(&flipper_dap_swdio_pin, GpioModeInput, GpioPullNo, GpioSpeedVeryHigh);
+    furi_hal_gpio_init(&flipper_dap_swclk_pin, GpioModeInput, GpioPullNo, GpioSpeedVeryHigh);
+    furi_hal_gpio_init(&flipper_dap_reset_pin, GpioModeInput, GpioPullNo, GpioSpeedVeryHigh);
+#ifdef DAP_CONFIG_ENABLE_JTAG
+    furi_hal_gpio_init(&flipper_dap_tdo_pin, GpioModeInput, GpioPullNo, GpioSpeedVeryHigh);
+    furi_hal_gpio_init(&flipper_dap_tdi_pin, GpioModeInput, GpioPullNo, GpioSpeedVeryHigh);
+#endif
+    dap_app_disconnect();
+}
+
+//-----------------------------------------------------------------------------
+static inline void DAP_CONFIG_CONNECT_SWD(void) {
+    furi_hal_gpio_init(
+        &flipper_dap_swdio_pin, GpioModeOutputPushPull, GpioPullNo, GpioSpeedVeryHigh);
+    furi_hal_gpio_write(&flipper_dap_swdio_pin, true);
+
+    furi_hal_gpio_init(
+        &flipper_dap_swclk_pin, GpioModeOutputPushPull, GpioPullNo, GpioSpeedVeryHigh);
+    furi_hal_gpio_write(&flipper_dap_swclk_pin, true);
+
+    furi_hal_gpio_init(
+        &flipper_dap_reset_pin, GpioModeOutputPushPull, GpioPullNo, GpioSpeedVeryHigh);
+    furi_hal_gpio_write(&flipper_dap_reset_pin, true);
+
+#ifdef DAP_CONFIG_ENABLE_JTAG
+    furi_hal_gpio_init(&flipper_dap_tdo_pin, GpioModeInput, GpioPullNo, GpioSpeedVeryHigh);
+    furi_hal_gpio_init(&flipper_dap_tdi_pin, GpioModeInput, GpioPullNo, GpioSpeedVeryHigh);
+#endif
+    dap_app_connect_swd();
+}
+
+//-----------------------------------------------------------------------------
+static inline void DAP_CONFIG_CONNECT_JTAG(void) {
+    furi_hal_gpio_init(
+        &flipper_dap_swdio_pin, GpioModeOutputPushPull, GpioPullNo, GpioSpeedVeryHigh);
+    furi_hal_gpio_write(&flipper_dap_swdio_pin, true);
+
+    furi_hal_gpio_init(
+        &flipper_dap_swclk_pin, GpioModeOutputPushPull, GpioPullNo, GpioSpeedVeryHigh);
+    furi_hal_gpio_write(&flipper_dap_swclk_pin, true);
+
+    furi_hal_gpio_init(
+        &flipper_dap_reset_pin, GpioModeOutputPushPull, GpioPullNo, GpioSpeedVeryHigh);
+    furi_hal_gpio_write(&flipper_dap_reset_pin, true);
+
+#ifdef DAP_CONFIG_ENABLE_JTAG
+    furi_hal_gpio_init(&flipper_dap_tdo_pin, GpioModeInput, GpioPullNo, GpioSpeedVeryHigh);
+
+    furi_hal_gpio_init(
+        &flipper_dap_tdi_pin, GpioModeOutputPushPull, GpioPullNo, GpioSpeedVeryHigh);
+    furi_hal_gpio_write(&flipper_dap_tdi_pin, true);
+#endif
+    dap_app_connect_jtag();
+}
+
+//-----------------------------------------------------------------------------
+static inline void DAP_CONFIG_LED(int index, int state) {
+    (void)index;
+    (void)state;
+}
+
+//-----------------------------------------------------------------------------
+__attribute__((always_inline)) static inline void DAP_CONFIG_DELAY(uint32_t cycles) {
+    asm volatile("1: subs %[cycles], %[cycles], #1 \n"
+                 "   bne 1b \n"
+                 : [cycles] "+l"(cycles));
+}
+
+#endif // _DAP_CONFIG_H_

dap_link/dap_link.c

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+#include <dap.h>
+#include <furi.h>
+#include <furi_hal_version.h>
+#include <furi_hal_gpio.h>
+#include <furi_hal_uart.h>
+#include <furi_hal_console.h>
+#include <furi_hal_resources.h>
+#include <furi_hal_power.h>
+#include <stm32wbxx_ll_usart.h>
+#include <stm32wbxx_ll_lpuart.h>
+
+#include "dap_link.h"
+#include "dap_config.h"
+#include "gui/dap_gui.h"
+#include "usb/dap_v2_usb.h"
+#include <dialogs/dialogs.h>
+#include "dap_link_icons.h"
+
+/***************************************************************************/
+/****************************** DAP COMMON *********************************/
+/***************************************************************************/
+
+struct DapApp {
+    FuriThread* dap_thread;
+    FuriThread* cdc_thread;
+    FuriThread* gui_thread;
+
+    DapState state;
+    DapConfig config;
+};
+
+void dap_app_get_state(DapApp* app, DapState* state) {
+    *state = app->state;
+}
+
+#define DAP_PROCESS_THREAD_TICK 500
+
+typedef enum {
+    DapEventStop = (1 << 0),
+} DapEvent;
+
+void dap_thread_send_stop(FuriThread* thread) {
+    furi_thread_flags_set(furi_thread_get_id(thread), DapEventStop);
+}
+
+GpioPin flipper_dap_swclk_pin;
+GpioPin flipper_dap_swdio_pin;
+GpioPin flipper_dap_reset_pin;
+GpioPin flipper_dap_tdo_pin;
+GpioPin flipper_dap_tdi_pin;
+
+/***************************************************************************/
+/****************************** DAP PROCESS ********************************/
+/***************************************************************************/
+
+typedef struct {
+    uint8_t data[DAP_CONFIG_PACKET_SIZE];
+    uint8_t size;
+} DapPacket;
+
+typedef enum {
+    DapThreadEventStop = DapEventStop,
+    DapThreadEventRxV1 = (1 << 1),
+    DapThreadEventRxV2 = (1 << 2),
+    DapThreadEventUsbConnect = (1 << 3),
+    DapThreadEventUsbDisconnect = (1 << 4),
+    DapThreadEventApplyConfig = (1 << 5),
+    DapThreadEventAll = DapThreadEventStop | DapThreadEventRxV1 | DapThreadEventRxV2 |
+                        DapThreadEventUsbConnect | DapThreadEventUsbDisconnect |
+                        DapThreadEventApplyConfig,
+} DapThreadEvent;
+
+#define USB_SERIAL_NUMBER_LEN 16
+char usb_serial_number[USB_SERIAL_NUMBER_LEN] = {0};
+
+const char* dap_app_get_serial(DapApp* app) {
+    UNUSED(app);
+    return usb_serial_number;
+}
+
+static void dap_app_rx1_callback(void* context) {
+    furi_assert(context);
+    FuriThreadId thread_id = (FuriThreadId)context;
+    furi_thread_flags_set(thread_id, DapThreadEventRxV1);
+}
+
+static void dap_app_rx2_callback(void* context) {
+    furi_assert(context);
+    FuriThreadId thread_id = (FuriThreadId)context;
+    furi_thread_flags_set(thread_id, DapThreadEventRxV2);
+}
+
+static void dap_app_usb_state_callback(bool state, void* context) {
+    furi_assert(context);
+    FuriThreadId thread_id = (FuriThreadId)context;
+    if(state) {
+        furi_thread_flags_set(thread_id, DapThreadEventUsbConnect);
+    } else {
+        furi_thread_flags_set(thread_id, DapThreadEventUsbDisconnect);
+    }
+}
+
+static void dap_app_process_v1() {
+    DapPacket tx_packet;
+    DapPacket rx_packet;
+    memset(&tx_packet, 0, sizeof(DapPacket));
+    rx_packet.size = dap_v1_usb_rx(rx_packet.data, DAP_CONFIG_PACKET_SIZE);
+    dap_process_request(rx_packet.data, rx_packet.size, tx_packet.data, DAP_CONFIG_PACKET_SIZE);
+    dap_v1_usb_tx(tx_packet.data, DAP_CONFIG_PACKET_SIZE);
+}
+
+static void dap_app_process_v2() {
+    DapPacket tx_packet;
+    DapPacket rx_packet;
+    memset(&tx_packet, 0, sizeof(DapPacket));
+    rx_packet.size = dap_v2_usb_rx(rx_packet.data, DAP_CONFIG_PACKET_SIZE);
+    size_t len = dap_process_request(
+        rx_packet.data, rx_packet.size, tx_packet.data, DAP_CONFIG_PACKET_SIZE);
+    dap_v2_usb_tx(tx_packet.data, len);
+}
+
+void dap_app_vendor_cmd(uint8_t cmd) {
+    // openocd -c "cmsis-dap cmd 81"
+    if(cmd == 0x01) {
+        furi_hal_power_reset();
+    }
+}
+
+void dap_app_target_reset() {
+    FURI_LOG_I("DAP", "Target reset");
+}
+
+static void dap_init_gpio(DapSwdPins swd_pins) {
+    switch(swd_pins) {
+    case DapSwdPinsPA7PA6:
+        flipper_dap_swclk_pin = gpio_ext_pa7;
+        flipper_dap_swdio_pin = gpio_ext_pa6;
+        break;
+    case DapSwdPinsPA14PA13:
+        flipper_dap_swclk_pin = (GpioPin){.port = GPIOA, .pin = LL_GPIO_PIN_14};
+        flipper_dap_swdio_pin = (GpioPin){.port = GPIOA, .pin = LL_GPIO_PIN_13};
+        break;
+    }
+
+    flipper_dap_reset_pin = gpio_ext_pa4;
+    flipper_dap_tdo_pin = gpio_ext_pb3;
+    flipper_dap_tdi_pin = gpio_ext_pb2;
+}
+
+static void dap_deinit_gpio(DapSwdPins swd_pins) {
+    // setup gpio pins to default state
+    furi_hal_gpio_init(&flipper_dap_reset_pin, GpioModeAnalog, GpioPullNo, GpioSpeedLow);
+    furi_hal_gpio_init(&flipper_dap_tdo_pin, GpioModeAnalog, GpioPullNo, GpioSpeedLow);
+    furi_hal_gpio_init(&flipper_dap_tdi_pin, GpioModeAnalog, GpioPullNo, GpioSpeedLow);
+
+    if(DapSwdPinsPA14PA13 == swd_pins) {
+        // PA14 and PA13 are used by SWD
+        furi_hal_gpio_init_ex(
+            &flipper_dap_swclk_pin,
+            GpioModeAltFunctionPushPull,
+            GpioPullDown,
+            GpioSpeedLow,
+            GpioAltFn0JTCK_SWCLK);
+        furi_hal_gpio_init_ex(
+            &flipper_dap_swdio_pin,
+            GpioModeAltFunctionPushPull,
+            GpioPullUp,
+            GpioSpeedVeryHigh,
+            GpioAltFn0JTMS_SWDIO);
+    } else {
+        furi_hal_gpio_init(&flipper_dap_swclk_pin, GpioModeAnalog, GpioPullNo, GpioSpeedLow);
+        furi_hal_gpio_init(&flipper_dap_swdio_pin, GpioModeAnalog, GpioPullNo, GpioSpeedLow);
+    }
+}
+
+static int32_t dap_process(void* p) {
+    DapApp* app = p;
+    DapState* dap_state = &(app->state);
+
+    // allocate resources
+    FuriHalUsbInterface* usb_config_prev;
+    app->config.swd_pins = DapSwdPinsPA7PA6;
+    DapSwdPins swd_pins_prev = app->config.swd_pins;
+
+    // init pins
+    dap_init_gpio(swd_pins_prev);
+
+    // init dap
+    dap_init();
+
+    // get name
+    const char* name = furi_hal_version_get_name_ptr();
+    if(!name) {
+        name = "Flipper";
+    }
+    snprintf(usb_serial_number, USB_SERIAL_NUMBER_LEN, "DAP_%s", name);
+
+    // init usb
+    usb_config_prev = furi_hal_usb_get_config();
+    dap_common_usb_alloc_name(usb_serial_number);
+    dap_common_usb_set_context(furi_thread_get_id(furi_thread_get_current()));
+    dap_v1_usb_set_rx_callback(dap_app_rx1_callback);
+    dap_v2_usb_set_rx_callback(dap_app_rx2_callback);
+    dap_common_usb_set_state_callback(dap_app_usb_state_callback);
+    furi_hal_usb_set_config(&dap_v2_usb_hid, NULL);
+
+    // work
+    uint32_t events;
+    while(1) {
+        events = furi_thread_flags_wait(DapThreadEventAll, FuriFlagWaitAny, FuriWaitForever);
+
+        if(!(events & FuriFlagError)) {
+            if(events & DapThreadEventRxV1) {
+                dap_app_process_v1();
+                dap_state->dap_counter++;
+                dap_state->dap_version = DapVersionV1;
+            }
+
+            if(events & DapThreadEventRxV2) {
+                dap_app_process_v2();
+                dap_state->dap_counter++;
+                dap_state->dap_version = DapVersionV2;
+            }
+
+            if(events & DapThreadEventUsbConnect) {
+                dap_state->usb_connected = true;
+            }
+
+            if(events & DapThreadEventUsbDisconnect) {
+                dap_state->usb_connected = false;
+                dap_state->dap_version = DapVersionUnknown;
+            }
+
+            if(events & DapThreadEventApplyConfig) {
+                if(swd_pins_prev != app->config.swd_pins) {
+                    dap_deinit_gpio(swd_pins_prev);
+                    swd_pins_prev = app->config.swd_pins;
+                    dap_init_gpio(swd_pins_prev);
+                }
+            }
+
+            if(events & DapThreadEventStop) {
+                break;
+            }
+        }
+    }
+
+    // deinit usb
+    furi_hal_usb_set_config(usb_config_prev, NULL);
+    dap_common_usb_free_name();
+    dap_deinit_gpio(swd_pins_prev);
+    return 0;
+}
+
+/***************************************************************************/
+/****************************** CDC PROCESS ********************************/
+/***************************************************************************/
+
+typedef enum {
+    CdcThreadEventStop = DapEventStop,
+    CdcThreadEventUartRx = (1 << 1),
+    CdcThreadEventCdcRx = (1 << 2),
+    CdcThreadEventCdcConfig = (1 << 3),
+    CdcThreadEventApplyConfig = (1 << 4),
+    CdcThreadEventCdcDtrHigh = (1 << 5),
+    CdcThreadEventCdcDtrLow = (1 << 6),
+    CdcThreadEventCdcTxComplete = (1 << 7),
+
+    CdcThreadEventAll = CdcThreadEventStop | CdcThreadEventUartRx | CdcThreadEventCdcRx |
+                        CdcThreadEventCdcConfig | CdcThreadEventApplyConfig |
+                        CdcThreadEventCdcDtrHigh | CdcThreadEventCdcDtrLow |
+                        CdcThreadEventCdcTxComplete,
+} CdcThreadEvent;
+
+typedef struct {
+    FuriStreamBuffer* rx_stream;
+    FuriThreadId thread_id;
+    FuriHalUartId uart_id;
+    struct usb_cdc_line_coding line_coding;
+} CDCProcess;
+
+static void cdc_uart_irq_cb(UartIrqEvent ev, uint8_t data, void* ctx) {
+    CDCProcess* app = ctx;
+
+    if(ev == UartIrqEventRXNE) {
+        furi_stream_buffer_send(app->rx_stream, &data, 1, 0);
+        furi_thread_flags_set(app->thread_id, CdcThreadEventUartRx);
+    }
+}
+
+static void cdc_usb_rx_callback(void* context) {
+    CDCProcess* app = context;
+    furi_thread_flags_set(app->thread_id, CdcThreadEventCdcRx);
+}
+
+static void cdc_usb_tx_complete_callback(void* context) {
+    CDCProcess* app = context;
+    furi_thread_flags_set(app->thread_id, CdcThreadEventCdcTxComplete);
+}
+
+static void cdc_usb_control_line_callback(uint8_t state, void* context) {
+    CDCProcess* app = context;
+    // bit 0: DTR state, bit 1: RTS state
+    bool dtr = state & (1 << 0);
+
+    if(dtr == true) {
+        furi_thread_flags_set(app->thread_id, CdcThreadEventCdcDtrHigh);
+    } else {
+        furi_thread_flags_set(app->thread_id, CdcThreadEventCdcDtrLow);
+    }
+}
+
+static void cdc_usb_config_callback(struct usb_cdc_line_coding* config, void* context) {
+    CDCProcess* app = context;
+    app->line_coding = *config;
+    furi_thread_flags_set(app->thread_id, CdcThreadEventCdcConfig);
+}
+
+static FuriHalUartId cdc_init_uart(
+    DapUartType type,
+    DapUartTXRX swap,
+    uint32_t baudrate,
+    void (*cb)(UartIrqEvent ev, uint8_t data, void* ctx),
+    void* ctx) {
+    FuriHalUartId uart_id = FuriHalUartIdUSART1;
+    if(baudrate == 0) baudrate = 115200;
+
+    switch(type) {
+    case DapUartTypeUSART1:
+        uart_id = FuriHalUartIdUSART1;
+        furi_hal_console_disable();
+        furi_hal_uart_deinit(uart_id);
+        if(swap == DapUartTXRXSwap) {
+            LL_USART_SetTXRXSwap(USART1, LL_USART_TXRX_SWAPPED);
+        } else {
+            LL_USART_SetTXRXSwap(USART1, LL_USART_TXRX_STANDARD);
+        }
+        furi_hal_uart_init(uart_id, baudrate);
+        furi_hal_uart_set_irq_cb(uart_id, cb, ctx);
+        break;
+    case DapUartTypeLPUART1:
+        uart_id = FuriHalUartIdLPUART1;
+        furi_hal_uart_deinit(uart_id);
+        if(swap == DapUartTXRXSwap) {
+            LL_LPUART_SetTXRXSwap(LPUART1, LL_LPUART_TXRX_SWAPPED);
+        } else {
+            LL_LPUART_SetTXRXSwap(LPUART1, LL_LPUART_TXRX_STANDARD);
+        }
+        furi_hal_uart_init(uart_id, baudrate);
+        furi_hal_uart_set_irq_cb(uart_id, cb, ctx);
+        break;
+    }
+
+    return uart_id;
+}
+
+static void cdc_deinit_uart(DapUartType type) {
+    switch(type) {
+    case DapUartTypeUSART1:
+        furi_hal_uart_deinit(FuriHalUartIdUSART1);
+        LL_USART_SetTXRXSwap(USART1, LL_USART_TXRX_STANDARD);
+        furi_hal_console_init();
+        break;
+    case DapUartTypeLPUART1:
+        furi_hal_uart_deinit(FuriHalUartIdLPUART1);
+        LL_LPUART_SetTXRXSwap(LPUART1, LL_LPUART_TXRX_STANDARD);
+        break;
+    }
+}
+
+static int32_t dap_cdc_process(void* p) {
+    DapApp* dap_app = p;
+    DapState* dap_state = &(dap_app->state);
+
+    dap_app->config.uart_pins = DapUartTypeLPUART1;
+    dap_app->config.uart_swap = DapUartTXRXNormal;
+
+    DapUartType uart_pins_prev = dap_app->config.uart_pins;
+    DapUartTXRX uart_swap_prev = dap_app->config.uart_swap;
+
+    CDCProcess* app = malloc(sizeof(CDCProcess));
+    app->thread_id = furi_thread_get_id(furi_thread_get_current());
+    app->rx_stream = furi_stream_buffer_alloc(512, 1);
+
+    const uint8_t rx_buffer_size = 64;
+    uint8_t* rx_buffer = malloc(rx_buffer_size);
+
+    app->uart_id = cdc_init_uart(
+        uart_pins_prev, uart_swap_prev, dap_state->cdc_baudrate, cdc_uart_irq_cb, app);
+
+    dap_cdc_usb_set_context(app);
+    dap_cdc_usb_set_rx_callback(cdc_usb_rx_callback);
+    dap_cdc_usb_set_tx_complete_callback(cdc_usb_tx_complete_callback);
+    dap_cdc_usb_set_control_line_callback(cdc_usb_control_line_callback);
+    dap_cdc_usb_set_config_callback(cdc_usb_config_callback);
+
+    bool cdc_connect = false;
+
+    uint32_t events;
+    while(1) {
+        events = furi_thread_flags_wait(CdcThreadEventAll, FuriFlagWaitAny, FuriWaitForever);
+
+        if(!(events & FuriFlagError)) {
+            if(events & CdcThreadEventCdcConfig) {
+                if(dap_state->cdc_baudrate != app->line_coding.dwDTERate) {
+                    dap_state->cdc_baudrate = app->line_coding.dwDTERate;
+                    if(dap_state->cdc_baudrate > 0) {
+                        furi_hal_uart_set_br(app->uart_id, dap_state->cdc_baudrate);
+                    }
+                }
+            }
+
+            if(events & (CdcThreadEventUartRx | CdcThreadEventCdcTxComplete)) {
+                size_t len =
+                    furi_stream_buffer_receive(app->rx_stream, rx_buffer, rx_buffer_size, 0);
+                if(cdc_connect) {
+                    if(len > 0) {
+                        dap_cdc_usb_tx(rx_buffer, len);
+                    }
+                    dap_state->cdc_rx_counter += len;
+                }
+            }
+
+            if(events & CdcThreadEventCdcRx) {
+                size_t len = dap_cdc_usb_rx(rx_buffer, rx_buffer_size);
+                if(len > 0) {
+                    furi_hal_uart_tx(app->uart_id, rx_buffer, len);
+                }
+                dap_state->cdc_tx_counter += len;
+            }
+
+            if(events & CdcThreadEventApplyConfig) {
+                if(uart_pins_prev != dap_app->config.uart_pins ||
+                   uart_swap_prev != dap_app->config.uart_swap) {
+                    cdc_deinit_uart(uart_pins_prev);
+                    uart_pins_prev = dap_app->config.uart_pins;
+                    uart_swap_prev = dap_app->config.uart_swap;
+                    app->uart_id = cdc_init_uart(
+                        uart_pins_prev,
+                        uart_swap_prev,
+                        dap_state->cdc_baudrate,
+                        cdc_uart_irq_cb,
+                        app);
+                }
+            }
+
+            if(events & CdcThreadEventStop) {
+                break;
+            }
+            if(events & CdcThreadEventCdcDtrHigh) {
+                cdc_connect = true;
+            }
+            if(events & CdcThreadEventCdcDtrLow) {
+                cdc_connect = false;
+            }
+        }
+    }
+
+    cdc_deinit_uart(uart_pins_prev);
+    free(rx_buffer);
+    furi_stream_buffer_free(app->rx_stream);
+    free(app);
+
+    return 0;
+}
+
+/***************************************************************************/
+/******************************* MAIN APP **********************************/
+/***************************************************************************/
+
+static DapApp* dap_app_alloc() {
+    DapApp* dap_app = malloc(sizeof(DapApp));
+    dap_app->dap_thread = furi_thread_alloc_ex("DapProcess", 1024, dap_process, dap_app);
+    dap_app->cdc_thread = furi_thread_alloc_ex("DapCdcProcess", 1024, dap_cdc_process, dap_app);
+    dap_app->gui_thread = furi_thread_alloc_ex("DapGui", 1024, dap_gui_thread, dap_app);
+    return dap_app;
+}
+
+static void dap_app_free(DapApp* dap_app) {
+    furi_assert(dap_app);
+    furi_thread_free(dap_app->dap_thread);
+    furi_thread_free(dap_app->cdc_thread);
+    furi_thread_free(dap_app->gui_thread);
+    free(dap_app);
+}
+
+static DapApp* app_handle = NULL;
+
+void dap_app_disconnect() {
+    app_handle->state.dap_mode = DapModeDisconnected;
+}
+
+void dap_app_connect_swd() {
+    app_handle->state.dap_mode = DapModeSWD;
+}
+
+void dap_app_connect_jtag() {
+    app_handle->state.dap_mode = DapModeJTAG;
+}
+
+void dap_app_set_config(DapApp* app, DapConfig* config) {
+    app->config = *config;
+    furi_thread_flags_set(furi_thread_get_id(app->dap_thread), DapThreadEventApplyConfig);
+    furi_thread_flags_set(furi_thread_get_id(app->cdc_thread), CdcThreadEventApplyConfig);
+}
+
+DapConfig* dap_app_get_config(DapApp* app) {
+    return &app->config;
+}
+
+int32_t dap_link_app(void* p) {
+    UNUSED(p);
+
+    if(furi_hal_usb_is_locked()) {
+        DialogsApp* dialogs = furi_record_open(RECORD_DIALOGS);
+        DialogMessage* message = dialog_message_alloc();
+        dialog_message_set_header(message, "Connection\nis active!", 3, 2, AlignLeft, AlignTop);
+        dialog_message_set_text(
+            message,
+            "Disconnect from\nPC or phone to\nuse this function.",
+            3,
+            30,
+            AlignLeft,
+            AlignTop);
+        dialog_message_set_icon(message, &I_ActiveConnection_50x64, 78, 0);
+        dialog_message_show(dialogs, message);
+        dialog_message_free(message);
+        furi_record_close(RECORD_DIALOGS);
+        return -1;
+    }
+
+    // alloc app
+    DapApp* app = dap_app_alloc();
+    app_handle = app;
+
+    furi_thread_start(app->dap_thread);
+    furi_thread_start(app->cdc_thread);
+    furi_thread_start(app->gui_thread);
+
+    // wait until gui thread is finished
+    furi_thread_join(app->gui_thread);
+
+    // send stop event to threads
+    dap_thread_send_stop(app->dap_thread);
+    dap_thread_send_stop(app->cdc_thread);
+
+    // wait for threads to stop
+    furi_thread_join(app->dap_thread);
+    furi_thread_join(app->cdc_thread);
+
+    // free app
+    dap_app_free(app);
+
+    return 0;
+}

dap_link/dap_link.h

@@ -0,0 +1,55 @@
+#pragma once
+#include <stdint.h>
+
+typedef enum {
+    DapModeDisconnected,
+    DapModeSWD,
+    DapModeJTAG,
+} DapMode;
+
+typedef enum {
+    DapVersionUnknown,
+    DapVersionV1,
+    DapVersionV2,
+} DapVersion;
+
+typedef struct {
+    bool usb_connected;
+    DapMode dap_mode;
+    DapVersion dap_version;
+    uint32_t dap_counter;
+    uint32_t cdc_baudrate;
+    uint32_t cdc_tx_counter;
+    uint32_t cdc_rx_counter;
+} DapState;
+
+typedef enum {
+    DapSwdPinsPA7PA6, // Pins 2, 3
+    DapSwdPinsPA14PA13, // Pins 10, 12
+} DapSwdPins;
+
+typedef enum {
+    DapUartTypeUSART1, // Pins 13, 14
+    DapUartTypeLPUART1, // Pins 15, 16
+} DapUartType;
+
+typedef enum {
+    DapUartTXRXNormal,
+    DapUartTXRXSwap,
+} DapUartTXRX;
+
+typedef struct {
+    DapSwdPins swd_pins;
+    DapUartType uart_pins;
+    DapUartTXRX uart_swap;
+} DapConfig;
+
+typedef struct DapApp DapApp;
+
+void dap_app_get_state(DapApp* app, DapState* state);
+
+const char* dap_app_get_serial(DapApp* app);
+
+void dap_app_set_config(DapApp* app, DapConfig* config);
+
+DapConfig* dap_app_get_config(DapApp* app);

dap_link/gui/dap_gui.c

@@ -0,0 +1,92 @@
+#include "dap_gui.h"
+#include "dap_gui_i.h"
+
+#define DAP_GUI_TICK 250
+
+static bool dap_gui_custom_event_callback(void* context, uint32_t event) {
+    furi_assert(context);
+    DapGuiApp* app = context;
+    return scene_manager_handle_custom_event(app->scene_manager, event);
+}
+
+static bool dap_gui_back_event_callback(void* context) {
+    furi_assert(context);
+    DapGuiApp* app = context;
+    return scene_manager_handle_back_event(app->scene_manager);
+}
+
+static void dap_gui_tick_event_callback(void* context) {
+    furi_assert(context);
+    DapGuiApp* app = context;
+    scene_manager_handle_tick_event(app->scene_manager);
+}
+
+DapGuiApp* dap_gui_alloc() {
+    DapGuiApp* app = malloc(sizeof(DapGuiApp));
+    app->gui = furi_record_open(RECORD_GUI);
+    app->view_dispatcher = view_dispatcher_alloc();
+    app->scene_manager = scene_manager_alloc(&dap_scene_handlers, app);
+    view_dispatcher_enable_queue(app->view_dispatcher);
+    view_dispatcher_set_event_callback_context(app->view_dispatcher, app);
+
+    view_dispatcher_set_custom_event_callback(app->view_dispatcher, dap_gui_custom_event_callback);
+    view_dispatcher_set_navigation_event_callback(
+        app->view_dispatcher, dap_gui_back_event_callback);
+    view_dispatcher_set_tick_event_callback(
+        app->view_dispatcher, dap_gui_tick_event_callback, DAP_GUI_TICK);
+
+    view_dispatcher_attach_to_gui(app->view_dispatcher, app->gui, ViewDispatcherTypeFullscreen);
+
+    app->notifications = furi_record_open(RECORD_NOTIFICATION);
+
+    app->var_item_list = variable_item_list_alloc();
+    view_dispatcher_add_view(
+        app->view_dispatcher,
+        DapGuiAppViewVarItemList,
+        variable_item_list_get_view(app->var_item_list));
+
+    app->main_view = dap_main_view_alloc();
+    view_dispatcher_add_view(
+        app->view_dispatcher, DapGuiAppViewMainView, dap_main_view_get_view(app->main_view));
+
+    app->widget = widget_alloc();
+    view_dispatcher_add_view(
+        app->view_dispatcher, DapGuiAppViewWidget, widget_get_view(app->widget));
+
+    scene_manager_next_scene(app->scene_manager, DapSceneMain);
+
+    return app;
+}
+
+void dap_gui_free(DapGuiApp* app) {
+    view_dispatcher_remove_view(app->view_dispatcher, DapGuiAppViewVarItemList);
+    variable_item_list_free(app->var_item_list);
+
+    view_dispatcher_remove_view(app->view_dispatcher, DapGuiAppViewMainView);
+    dap_main_view_free(app->main_view);
+
+    view_dispatcher_remove_view(app->view_dispatcher, DapGuiAppViewWidget);
+    widget_free(app->widget);
+
+    // View dispatcher
+    view_dispatcher_free(app->view_dispatcher);
+    scene_manager_free(app->scene_manager);
+
+    // Close records
+    furi_record_close(RECORD_GUI);
+    furi_record_close(RECORD_NOTIFICATION);
+
+    free(app);
+}
+
+int32_t dap_gui_thread(void* arg) {
+    DapGuiApp* app = dap_gui_alloc();
+    app->dap_app = arg;
+
+    notification_message_block(app->notifications, &sequence_display_backlight_enforce_on);
+    view_dispatcher_run(app->view_dispatcher);
+    notification_message_block(app->notifications, &sequence_display_backlight_enforce_auto);
+
+    dap_gui_free(app);
+    return 0;
+}

dap_link/gui/dap_gui.h

@@ -0,0 +1,4 @@
+#pragma once
+#include <stdint.h>
+
+int32_t dap_gui_thread(void* arg);

dap_link/gui/dap_gui_custom_event.h

@@ -0,0 +1,7 @@
+#pragma once
+
+typedef enum {
+    DapAppCustomEventConfig,
+    DapAppCustomEventHelp,
+    DapAppCustomEventAbout,
+} DapAppCustomEvent;

dap_link/gui/dap_gui_i.h

@@ -0,0 +1,34 @@
+#pragma once
+
+#include <gui/gui.h>
+#include <gui/view_dispatcher.h>
+#include <gui/scene_manager.h>
+#include <gui/modules/submenu.h>
+#include <notification/notification_messages.h>
+#include <gui/modules/variable_item_list.h>
+#include <gui/modules/widget.h>
+
+#include "dap_gui.h"
+#include "../dap_link.h"
+#include "scenes/config/dap_scene.h"
+#include "dap_gui_custom_event.h"
+#include "views/dap_main_view.h"
+
+typedef struct {
+    DapApp* dap_app;
+
+    Gui* gui;
+    NotificationApp* notifications;
+    ViewDispatcher* view_dispatcher;
+    SceneManager* scene_manager;
+
+    VariableItemList* var_item_list;
+    DapMainView* main_view;
+    Widget* widget;
+} DapGuiApp;
+
+typedef enum {
+    DapGuiAppViewVarItemList,
+    DapGuiAppViewMainView,
+    DapGuiAppViewWidget,
+} DapGuiAppView;

dap_link/gui/scenes/config/dap_scene.c

@@ -0,0 +1,30 @@
+#include "dap_scene.h"
+
+// Generate scene on_enter handlers array
+#define ADD_SCENE(prefix, name, id) prefix##_scene_##name##_on_enter,
+void (*const dap_scene_on_enter_handlers[])(void*) = {
+#include "dap_scene_config.h"
+};
+#undef ADD_SCENE
+
+// Generate scene on_event handlers array
+#define ADD_SCENE(prefix, name, id) prefix##_scene_##name##_on_event,
+bool (*const dap_scene_on_event_handlers[])(void* context, SceneManagerEvent event) = {
+#include "dap_scene_config.h"
+};
+#undef ADD_SCENE
+
+// Generate scene on_exit handlers array
+#define ADD_SCENE(prefix, name, id) prefix##_scene_##name##_on_exit,
+void (*const dap_scene_on_exit_handlers[])(void* context) = {
+#include "dap_scene_config.h"
+};
+#undef ADD_SCENE
+
+// Initialize scene handlers configuration structure
+const SceneManagerHandlers dap_scene_handlers = {
+    .on_enter_handlers = dap_scene_on_enter_handlers,
+    .on_event_handlers = dap_scene_on_event_handlers,
+    .on_exit_handlers = dap_scene_on_exit_handlers,
+    .scene_num = DapSceneNum,
+};

dap_link/gui/scenes/config/dap_scene.h

@@ -0,0 +1,29 @@
+#pragma once
+
+#include <gui/scene_manager.h>
+
+// Generate scene id and total number
+#define ADD_SCENE(prefix, name, id) DapScene##id,
+typedef enum {
+#include "dap_scene_config.h"
+    DapSceneNum,
+} DapScene;
+#undef ADD_SCENE
+
+extern const SceneManagerHandlers dap_scene_handlers;
+
+// Generate scene on_enter handlers declaration
+#define ADD_SCENE(prefix, name, id) void prefix##_scene_##name##_on_enter(void*);
+#include "dap_scene_config.h"
+#undef ADD_SCENE
+
+// Generate scene on_event handlers declaration
+#define ADD_SCENE(prefix, name, id) \
+    bool prefix##_scene_##name##_on_event(void* context, SceneManagerEvent event);
+#include "dap_scene_config.h"
+#undef ADD_SCENE
+
+// Generate scene on_exit handlers declaration
+#define ADD_SCENE(prefix, name, id) void prefix##_scene_##name##_on_exit(void* context);
+#include "dap_scene_config.h"
+#undef ADD_SCENE

dap_link/gui/scenes/config/dap_scene_config.h

@@ -0,0 +1,4 @@
+ADD_SCENE(dap, main, Main)
+ADD_SCENE(dap, config, Config)
+ADD_SCENE(dap, help, Help)
+ADD_SCENE(dap, about, About)

dap_link/gui/scenes/dap_scene_about.c

@@ -0,0 +1,68 @@
+#include "../dap_gui_i.h"
+
+#define DAP_VERSION_APP "0.1.0"
+#define DAP_DEVELOPED "Dr_Zlo"
+#define DAP_GITHUB "https://github.com/flipperdevices/flipperzero-good-faps"
+
+void dap_scene_about_on_enter(void* context) {
+    DapGuiApp* app = context;
+
+    FuriString* temp_str;
+    temp_str = furi_string_alloc();
+    furi_string_printf(temp_str, "\e#%s\n", "Information");
+
+    furi_string_cat_printf(temp_str, "Version: %s\n", DAP_VERSION_APP);
+    furi_string_cat_printf(temp_str, "Developed by: %s\n", DAP_DEVELOPED);
+    furi_string_cat_printf(temp_str, "Github: %s\n\n", DAP_GITHUB);
+
+    furi_string_cat_printf(temp_str, "\e#%s\n", "Description");
+    furi_string_cat_printf(
+        temp_str, "CMSIS-DAP debugger\nbased on Free-DAP\nThanks to Alex Taradov\n\n");
+
+    furi_string_cat_printf(
+        temp_str,
+        "Supported protocols:\n"
+        "SWD, JTAG, UART\n"
+        "DAP v1 (cmsis_backend hid), DAP v2 (cmsis_backend usb_bulk), VCP\n");
+
+    widget_add_text_box_element(
+        app->widget,
+        0,
+        0,
+        128,
+        14,
+        AlignCenter,
+        AlignBottom,
+        "\e#\e!                                                      \e!\n",
+        false);
+    widget_add_text_box_element(
+        app->widget,
+        0,
+        2,
+        128,
+        14,
+        AlignCenter,
+        AlignBottom,
+        "\e#\e!              DAP Link              \e!\n",
+        false);
+    widget_add_text_scroll_element(app->widget, 0, 16, 128, 50, furi_string_get_cstr(temp_str));
+    furi_string_free(temp_str);
+
+    view_dispatcher_switch_to_view(app->view_dispatcher, DapGuiAppViewWidget);
+}
+
+bool dap_scene_about_on_event(void* context, SceneManagerEvent event) {
+    DapGuiApp* app = context;
+    bool consumed = false;
+    UNUSED(app);
+    UNUSED(event);
+
+    return consumed;
+}
+
+void dap_scene_about_on_exit(void* context) {
+    DapGuiApp* app = context;
+
+    // Clear views
+    widget_reset(app->widget);
+}

dap_link/gui/scenes/dap_scene_config.c

@@ -0,0 +1,107 @@
+#include "../dap_gui_i.h"
+
+static const char* swd_pins[] = {[DapSwdPinsPA7PA6] = "2,3", [DapSwdPinsPA14PA13] = "10,12"};
+static const char* uart_pins[] = {[DapUartTypeUSART1] = "13,14", [DapUartTypeLPUART1] = "15,16"};
+static const char* uart_swap[] = {[DapUartTXRXNormal] = "No", [DapUartTXRXSwap] = "Yes"};
+
+static void swd_pins_cb(VariableItem* item) {
+    DapGuiApp* app = variable_item_get_context(item);
+    uint8_t index = variable_item_get_current_value_index(item);
+
+    variable_item_set_current_value_text(item, swd_pins[index]);
+
+    DapConfig* config = dap_app_get_config(app->dap_app);
+    config->swd_pins = index;
+    dap_app_set_config(app->dap_app, config);
+}
+
+static void uart_pins_cb(VariableItem* item) {
+    DapGuiApp* app = variable_item_get_context(item);
+    uint8_t index = variable_item_get_current_value_index(item);
+
+    variable_item_set_current_value_text(item, uart_pins[index]);
+
+    DapConfig* config = dap_app_get_config(app->dap_app);
+    config->uart_pins = index;
+    dap_app_set_config(app->dap_app, config);
+}
+
+static void uart_swap_cb(VariableItem* item) {
+    DapGuiApp* app = variable_item_get_context(item);
+    uint8_t index = variable_item_get_current_value_index(item);
+
+    variable_item_set_current_value_text(item, uart_swap[index]);
+
+    DapConfig* config = dap_app_get_config(app->dap_app);
+    config->uart_swap = index;
+    dap_app_set_config(app->dap_app, config);
+}
+
+static void ok_cb(void* context, uint32_t index) {
+    DapGuiApp* app = context;
+    switch(index) {
+    case 3:
+        view_dispatcher_send_custom_event(app->view_dispatcher, DapAppCustomEventHelp);
+        break;
+    case 4:
+        view_dispatcher_send_custom_event(app->view_dispatcher, DapAppCustomEventAbout);
+        break;
+    default:
+        break;
+    }
+}
+
+void dap_scene_config_on_enter(void* context) {
+    DapGuiApp* app = context;
+    VariableItemList* var_item_list = app->var_item_list;
+    VariableItem* item;
+    DapConfig* config = dap_app_get_config(app->dap_app);
+
+    item = variable_item_list_add(
+        var_item_list, "SWC SWD Pins", COUNT_OF(swd_pins), swd_pins_cb, app);
+    variable_item_set_current_value_index(item, config->swd_pins);
+    variable_item_set_current_value_text(item, swd_pins[config->swd_pins]);
+
+    item =
+        variable_item_list_add(var_item_list, "UART Pins", COUNT_OF(uart_pins), uart_pins_cb, app);
+    variable_item_set_current_value_index(item, config->uart_pins);
+    variable_item_set_current_value_text(item, uart_pins[config->uart_pins]);
+
+    item = variable_item_list_add(
+        var_item_list, "Swap TX RX", COUNT_OF(uart_swap), uart_swap_cb, app);
+    variable_item_set_current_value_index(item, config->uart_swap);
+    variable_item_set_current_value_text(item, uart_swap[config->uart_swap]);
+
+    variable_item_list_add(var_item_list, "Help and Pinout", 0, NULL, NULL);
+    variable_item_list_add(var_item_list, "About", 0, NULL, NULL);
+
+    variable_item_list_set_selected_item(
+        var_item_list, scene_manager_get_scene_state(app->scene_manager, DapSceneConfig));
+
+    variable_item_list_set_enter_callback(var_item_list, ok_cb, app);
+
+    view_dispatcher_switch_to_view(app->view_dispatcher, DapGuiAppViewVarItemList);
+}
+
+bool dap_scene_config_on_event(void* context, SceneManagerEvent event) {
+    DapGuiApp* app = context;
+    if(event.type == SceneManagerEventTypeCustom) {
+        if(event.event == DapAppCustomEventHelp) {
+            scene_manager_next_scene(app->scene_manager, DapSceneHelp);
+            return true;
+        } else if(event.event == DapAppCustomEventAbout) {
+            scene_manager_next_scene(app->scene_manager, DapSceneAbout);
+            return true;
+        }
+    }
+    return false;
+}
+
+void dap_scene_config_on_exit(void* context) {
+    DapGuiApp* app = context;
+    scene_manager_set_scene_state(
+        app->scene_manager,
+        DapSceneConfig,
+        variable_item_list_get_selected_item_index(app->var_item_list));
+    variable_item_list_reset(app->var_item_list);
+}

dap_link/gui/scenes/dap_scene_help.c

@@ -0,0 +1,102 @@
+#include "../dap_gui_i.h"
+
+void dap_scene_help_on_enter(void* context) {
+    DapGuiApp* app = context;
+    DapConfig* config = dap_app_get_config(app->dap_app);
+    FuriString* string = furi_string_alloc();
+
+    furi_string_cat(string, "CMSIS DAP/DAP Link v2\r\n");
+    furi_string_cat_printf(string, "Serial: %s\r\n", dap_app_get_serial(app->dap_app));
+    furi_string_cat(
+        string,
+        "Pinout:\r\n"
+        "\e#SWD:\r\n");
+
+    switch(config->swd_pins) {
+    case DapSwdPinsPA7PA6:
+        furi_string_cat(
+            string,
+            "    SWC: 2 [A7]\r\n"
+            "    SWD: 3 [A6]\r\n");
+        break;
+    case DapSwdPinsPA14PA13:
+        furi_string_cat(
+            string,
+            "    SWC: 10 [SWC]\r\n"
+            "    SWD: 12 [SIO]\r\n");
+        break;
+    default:
+        break;
+    }
+
+    furi_string_cat(string, "\e#JTAG:\r\n");
+    switch(config->swd_pins) {
+    case DapSwdPinsPA7PA6:
+        furi_string_cat(
+            string,
+            "    TCK: 2 [A7]\r\n"
+            "    TMS: 3 [A6]\r\n"
+            "    RST: 4 [A4]\r\n"
+            "    TDO: 5 [B3]\r\n"
+            "    TDI: 6 [B2]\r\n");
+        break;
+    case DapSwdPinsPA14PA13:
+        furi_string_cat(
+            string,
+            "    RST: 4 [A4]\r\n"
+            "    TDO: 5 [B3]\r\n"
+            "    TDI: 6 [B2]\r\n"
+            "    TCK: 10 [SWC]\r\n"
+            "    TMS: 12 [SIO]\r\n");
+        break;
+    default:
+        break;
+    }
+
+    furi_string_cat(string, "\e#UART:\r\n");
+    switch(config->uart_pins) {
+    case DapUartTypeUSART1:
+        if(config->uart_swap == DapUartTXRXNormal) {
+            furi_string_cat(
+                string,
+                "    TX: 13 [TX]\r\n"
+                "    RX: 14 [RX]\r\n");
+        } else {
+            furi_string_cat(
+                string,
+                "    RX: 13 [TX]\r\n"
+                "    TX: 14 [RX]\r\n");
+        }
+        break;
+    case DapUartTypeLPUART1:
+        if(config->uart_swap == DapUartTXRXNormal) {
+            furi_string_cat(
+                string,
+                "    TX: 15 [C1]\r\n"
+                "    RX: 16 [C0]\r\n");
+        } else {
+            furi_string_cat(
+                string,
+                "    RX: 15 [C1]\r\n"
+                "    TX: 16 [C0]\r\n");
+        }
+        break;
+    default:
+        break;
+    }
+
+    widget_add_text_scroll_element(app->widget, 0, 0, 128, 64, furi_string_get_cstr(string));
+    furi_string_free(string);
+    view_dispatcher_switch_to_view(app->view_dispatcher, DapGuiAppViewWidget);
+}
+
+bool dap_scene_help_on_event(void* context, SceneManagerEvent event) {
+    UNUSED(context);
+    UNUSED(event);
+    return false;
+}
+
+void dap_scene_help_on_exit(void* context) {
+    DapGuiApp* app = context;
+    widget_reset(app->widget);
+}

dap_link/gui/scenes/dap_scene_main.c

@@ -0,0 +1,154 @@
+#include "../dap_gui_i.h"
+#include "../../dap_link.h"
+
+typedef struct {
+    DapState dap_state;
+    bool dap_active;
+    bool tx_active;
+    bool rx_active;
+} DapSceneMainState;
+
+static bool process_dap_state(DapGuiApp* app) {
+    DapSceneMainState* state =
+        (DapSceneMainState*)scene_manager_get_scene_state(app->scene_manager, DapSceneMain);
+    if(state == NULL) return true;
+
+    DapState* prev_state = &state->dap_state;
+    DapState next_state;
+    dap_app_get_state(app->dap_app, &next_state);
+    bool need_to_update = false;
+
+    if(prev_state->dap_mode != next_state.dap_mode) {
+        switch(next_state.dap_mode) {
+        case DapModeDisconnected:
+            dap_main_view_set_mode(app->main_view, DapMainViewModeDisconnected);
+            notification_message(app->notifications, &sequence_blink_stop);
+            break;
+        case DapModeSWD:
+            dap_main_view_set_mode(app->main_view, DapMainViewModeSWD);
+            notification_message(app->notifications, &sequence_blink_start_blue);
+            break;
+        case DapModeJTAG:
+            dap_main_view_set_mode(app->main_view, DapMainViewModeJTAG);
+            notification_message(app->notifications, &sequence_blink_start_magenta);
+            break;
+        }
+        need_to_update = true;
+    }
+
+    if(prev_state->dap_version != next_state.dap_version) {
+        switch(next_state.dap_version) {
+        case DapVersionUnknown:
+            dap_main_view_set_version(app->main_view, DapMainViewVersionUnknown);
+            break;
+        case DapVersionV1:
+            dap_main_view_set_version(app->main_view, DapMainViewVersionV1);
+            break;
+        case DapVersionV2:
+            dap_main_view_set_version(app->main_view, DapMainViewVersionV2);
+            break;
+        }
+        need_to_update = true;
+    }
+
+    if(prev_state->usb_connected != next_state.usb_connected) {
+        dap_main_view_set_usb_connected(app->main_view, next_state.usb_connected);
+        need_to_update = true;
+    }
+
+    if(prev_state->dap_counter != next_state.dap_counter) {
+        if(!state->dap_active) {
+            state->dap_active = true;
+            dap_main_view_set_dap(app->main_view, state->dap_active);
+            need_to_update = true;
+        }
+    } else {
+        if(state->dap_active) {
+            state->dap_active = false;
+            dap_main_view_set_dap(app->main_view, state->dap_active);
+            need_to_update = true;
+        }
+    }
+
+    if(prev_state->cdc_baudrate != next_state.cdc_baudrate) {
+        dap_main_view_set_baudrate(app->main_view, next_state.cdc_baudrate);
+        need_to_update = true;
+    }
+
+    if(prev_state->cdc_tx_counter != next_state.cdc_tx_counter) {
+        if(!state->tx_active) {
+            state->tx_active = true;
+            dap_main_view_set_tx(app->main_view, state->tx_active);
+            need_to_update = true;
+            notification_message(app->notifications, &sequence_blink_start_red);
+        }
+    } else {
+        if(state->tx_active) {
+            state->tx_active = false;
+            dap_main_view_set_tx(app->main_view, state->tx_active);
+            need_to_update = true;
+            notification_message(app->notifications, &sequence_blink_stop);
+        }
+    }
+
+    if(prev_state->cdc_rx_counter != next_state.cdc_rx_counter) {
+        if(!state->rx_active) {
+            state->rx_active = true;
+            dap_main_view_set_rx(app->main_view, state->rx_active);
+            need_to_update = true;
+            notification_message(app->notifications, &sequence_blink_start_green);
+        }
+    } else {
+        if(state->rx_active) {
+            state->rx_active = false;
+            dap_main_view_set_rx(app->main_view, state->rx_active);
+            need_to_update = true;
+            notification_message(app->notifications, &sequence_blink_stop);
+        }
+    }
+
+    if(need_to_update) {
+        dap_main_view_update(app->main_view);
+    }
+
+    *prev_state = next_state;
+    return true;
+}
+
+static void dap_scene_main_on_left(void* context) {
+    DapGuiApp* app = (DapGuiApp*)context;
+    view_dispatcher_send_custom_event(app->view_dispatcher, DapAppCustomEventConfig);
+}
+
+void dap_scene_main_on_enter(void* context) {
+    DapGuiApp* app = context;
+    DapSceneMainState* state = malloc(sizeof(DapSceneMainState));
+    dap_main_view_set_left_callback(app->main_view, dap_scene_main_on_left, app);
+    view_dispatcher_switch_to_view(app->view_dispatcher, DapGuiAppViewMainView);
+    scene_manager_set_scene_state(app->scene_manager, DapSceneMain, (uint32_t)state);
+}
+
+bool dap_scene_main_on_event(void* context, SceneManagerEvent event) {
+    DapGuiApp* app = context;
+
+    if(event.type == SceneManagerEventTypeCustom) {
+        if(event.event == DapAppCustomEventConfig) {
+            scene_manager_next_scene(app->scene_manager, DapSceneConfig);
+            return true;
+        }
+    } else if(event.type == SceneManagerEventTypeTick) {
+        return process_dap_state(app);
+    }
+
+    return false;
+}
+
+void dap_scene_main_on_exit(void* context) {
+    DapGuiApp* app = context;
+    DapSceneMainState* state =
+        (DapSceneMainState*)scene_manager_get_scene_state(app->scene_manager, DapSceneMain);
+    scene_manager_set_scene_state(app->scene_manager, DapSceneMain, (uint32_t)NULL);
+    FURI_SW_MEMBARRIER();
+    free(state);
+    notification_message(app->notifications, &sequence_blink_stop);
+}

dap_link/gui/views/dap_main_view.c

@@ -0,0 +1,189 @@
+#include "dap_main_view.h"
+#include "dap_link_icons.h"
+#include <gui/elements.h>
+
+// extern const Icon I_ArrowDownEmpty_12x18;
+// extern const Icon I_ArrowDownFilled_12x18;
+// extern const Icon I_ArrowUpEmpty_12x18;
+// extern const Icon I_ArrowUpFilled_12x18;
+
+struct DapMainView {
+    View* view;
+    DapMainViewButtonCallback cb_left;
+    void* cb_context;
+};
+
+typedef struct {
+    DapMainViewMode mode;
+    DapMainViewVersion version;
+    bool usb_connected;
+    uint32_t baudrate;
+    bool dap_active;
+    bool tx_active;
+    bool rx_active;
+} DapMainViewModel;
+
+static void dap_main_view_draw_callback(Canvas* canvas, void* _model) {
+    DapMainViewModel* model = _model;
+    UNUSED(model);
+    canvas_clear(canvas);
+    elements_button_left(canvas, "Config");
+
+    canvas_set_color(canvas, ColorBlack);
+    canvas_draw_box(canvas, 0, 0, 127, 11);
+    canvas_set_color(canvas, ColorWhite);
+
+    const char* header_string;
+    if(model->usb_connected) {
+        if(model->version == DapMainViewVersionV1) {
+            header_string = "DAP Link V1 Connected";
+        } else if(model->version == DapMainViewVersionV2) {
+            header_string = "DAP Link V2 Connected";
+        } else {
+            header_string = "DAP Link Connected";
+        }
+    } else {
+        header_string = "DAP Link";
+    }
+
+    canvas_draw_str_aligned(canvas, 64, 9, AlignCenter, AlignBottom, header_string);
+
+    canvas_set_color(canvas, ColorBlack);
+    if(model->dap_active) {
+        canvas_draw_icon(canvas, 14, 16, &I_ArrowUpFilled_12x18);
+        canvas_draw_icon_ex(canvas, 28, 16, &I_ArrowUpFilled_12x18, IconRotation180);
+    } else {
+        canvas_draw_icon(canvas, 14, 16, &I_ArrowUpEmpty_12x18);
+        canvas_draw_icon_ex(canvas, 28, 16, &I_ArrowUpEmpty_12x18, IconRotation180);
+    }
+
+    switch(model->mode) {
+    case DapMainViewModeDisconnected:
+        canvas_draw_str_aligned(canvas, 26, 38, AlignCenter, AlignTop, "----");
+        break;
+    case DapMainViewModeSWD:
+        canvas_draw_str_aligned(canvas, 26, 38, AlignCenter, AlignTop, "SWD");
+        break;
+    case DapMainViewModeJTAG:
+        canvas_draw_str_aligned(canvas, 26, 38, AlignCenter, AlignTop, "JTAG");
+        break;
+    }
+
+    if(model->tx_active) {
+        canvas_draw_icon(canvas, 87, 16, &I_ArrowUpFilled_12x18);
+    } else {
+        canvas_draw_icon(canvas, 87, 16, &I_ArrowUpEmpty_12x18);
+    }
+
+    if(model->rx_active) {
+        canvas_draw_icon_ex(canvas, 101, 16, &I_ArrowUpFilled_12x18, IconRotation180);
+    } else {
+        canvas_draw_icon_ex(canvas, 101, 16, &I_ArrowUpEmpty_12x18, IconRotation180);
+    }
+
+    canvas_draw_str_aligned(canvas, 100, 38, AlignCenter, AlignTop, "UART");
+
+    canvas_draw_line(canvas, 44, 52, 123, 52);
+    if(model->baudrate == 0) {
+        canvas_draw_str(canvas, 45, 62, "Baud: ????");
+    } else {
+        char baudrate_str[18];
+        snprintf(baudrate_str, 18, "Baud: %lu", model->baudrate);
+        canvas_draw_str(canvas, 45, 62, baudrate_str);
+    }
+}
+
+static bool dap_main_view_input_callback(InputEvent* event, void* context) {
+    furi_assert(context);
+    DapMainView* dap_main_view = context;
+    bool consumed = false;
+
+    if(event->type == InputTypeShort) {
+        if(event->key == InputKeyLeft) {
+            if(dap_main_view->cb_left) {
+                dap_main_view->cb_left(dap_main_view->cb_context);
+            }
+            consumed = true;
+        }
+    }
+
+    return consumed;
+}
+
+DapMainView* dap_main_view_alloc() {
+    DapMainView* dap_main_view = malloc(sizeof(DapMainView));
+
+    dap_main_view->view = view_alloc();
+    view_allocate_model(dap_main_view->view, ViewModelTypeLocking, sizeof(DapMainViewModel));
+    view_set_context(dap_main_view->view, dap_main_view);
+    view_set_draw_callback(dap_main_view->view, dap_main_view_draw_callback);
+    view_set_input_callback(dap_main_view->view, dap_main_view_input_callback);
+    return dap_main_view;
+}
+
+void dap_main_view_free(DapMainView* dap_main_view) {
+    view_free(dap_main_view->view);
+    free(dap_main_view);
+}
+
+View* dap_main_view_get_view(DapMainView* dap_main_view) {
+    return dap_main_view->view;
+}
+
+void dap_main_view_set_left_callback(
+    DapMainView* dap_main_view,
+    DapMainViewButtonCallback callback,
+    void* context) {
+    with_view_model(
+        dap_main_view->view,
+        DapMainViewModel * model,
+        {
+            UNUSED(model);
+            dap_main_view->cb_left = callback;
+            dap_main_view->cb_context = context;
+        },
+        true);
+}
+
+void dap_main_view_set_mode(DapMainView* dap_main_view, DapMainViewMode mode) {
+    with_view_model(
+        dap_main_view->view, DapMainViewModel * model, { model->mode = mode; }, false);
+}
+
+void dap_main_view_set_dap(DapMainView* dap_main_view, bool active) {
+    with_view_model(
+        dap_main_view->view, DapMainViewModel * model, { model->dap_active = active; }, false);
+}
+
+void dap_main_view_set_tx(DapMainView* dap_main_view, bool active) {
+    with_view_model(
+        dap_main_view->view, DapMainViewModel * model, { model->tx_active = active; }, false);
+}
+
+void dap_main_view_set_rx(DapMainView* dap_main_view, bool active) {
+    with_view_model(
+        dap_main_view->view, DapMainViewModel * model, { model->rx_active = active; }, false);
+}
+
+void dap_main_view_set_baudrate(DapMainView* dap_main_view, uint32_t baudrate) {
+    with_view_model(
+        dap_main_view->view, DapMainViewModel * model, { model->baudrate = baudrate; }, false);
+}
+
+void dap_main_view_update(DapMainView* dap_main_view) {
+    with_view_model(
+        dap_main_view->view, DapMainViewModel * model, { UNUSED(model); }, true);
+}
+
+void dap_main_view_set_version(DapMainView* dap_main_view, DapMainViewVersion version) {
+    with_view_model(
+        dap_main_view->view, DapMainViewModel * model, { model->version = version; }, false);
+}
+
+void dap_main_view_set_usb_connected(DapMainView* dap_main_view, bool connected) {
+    with_view_model(
+        dap_main_view->view,
+        DapMainViewModel * model,
+        { model->usb_connected = connected; },
+        false);
+}

dap_link/gui/views/dap_main_view.h

@@ -0,0 +1,45 @@
+#pragma once
+#include <gui/view.h>
+
+typedef struct DapMainView DapMainView;
+
+typedef void (*DapMainViewButtonCallback)(void* context);
+
+typedef enum {
+    DapMainViewVersionUnknown,
+    DapMainViewVersionV1,
+    DapMainViewVersionV2,
+} DapMainViewVersion;
+
+typedef enum {
+    DapMainViewModeDisconnected,
+    DapMainViewModeSWD,
+    DapMainViewModeJTAG,
+} DapMainViewMode;
+
+DapMainView* dap_main_view_alloc();
+
+void dap_main_view_free(DapMainView* dap_main_view);
+
+View* dap_main_view_get_view(DapMainView* dap_main_view);
+
+void dap_main_view_set_left_callback(
+    DapMainView* dap_main_view,
+    DapMainViewButtonCallback callback,
+    void* context);
+
+void dap_main_view_set_mode(DapMainView* dap_main_view, DapMainViewMode mode);
+
+void dap_main_view_set_version(DapMainView* dap_main_view, DapMainViewVersion version);
+
+void dap_main_view_set_dap(DapMainView* dap_main_view, bool active);
+
+void dap_main_view_set_tx(DapMainView* dap_main_view, bool active);
+
+void dap_main_view_set_rx(DapMainView* dap_main_view, bool active);
+
+void dap_main_view_set_usb_connected(DapMainView* dap_main_view, bool connected);
+
+void dap_main_view_set_baudrate(DapMainView* dap_main_view, uint32_t baudrate);
+
+void dap_main_view_update(DapMainView* dap_main_view);

dap_link/lib/free-dap/LICENSE

@@ -0,0 +1,27 @@
+Copyright (c) 2016, Alex Taradov <alex@taradov.com>
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+  list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright notice,
+  this list of conditions and the following disclaimer in the documentation
+  and/or other materials provided with the distribution.
+
+* Neither the name of free-dap nor the names of its
+  contributors may be used to endorse or promote products derived from
+  this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

dap_link/lib/free-dap/README.md

@@ -0,0 +1,100 @@
+# Free-DAP
+
+This is a free and open implementation of the CMSIS-DAP debugger firmware.
+
+Both SWD and JTAG protocols are supported. However JTAG was not well tested due to lack of
+good targets. If you have any issues with it - let me know and I'll try to help.
+
+## Platform requirements
+
+To create a CMSIS-DAP compliant debugger, your platform must:
+ * Implement USB HID (and raw bulk for CMSIS-DAP v2) device able to receive and send arbitrary payloads
+ * Provide configuration file dap_config.h with definitions for hardware-dependent calls
+ * Call dap_init() at the initialization time
+ * Call dap_process_request() for every received request and send the response back
+
+## CMSIS-DAP version support
+
+Free-DAP library itself is protocol agnostic and implementation of the specific version
+of the CMSIS-DAP protocol (v1 or v2) is up to the individual platforms.
+
+Currently RP2040 and SAM D11 implementaitons were updated to support CMSIS-DAP v2.
+Other platforms would be updated if requested or needed by me.
+
+## Configuration
+
+For complete list of settings see one of the existing configuration file, they are
+pretty obvious.
+
+To configure clock frequency you need to specify two parameters:
+  * DAP_CONFIG_DELAY_CONSTANT - clock timing constant. This constant can be determined
+    by calling dap_clock_test() with varying parameter value and measuring the frequency
+    on the SWCLK pin. Delay constant value is the value of the parameter at which
+    output frequency equals to 1 kHz.
+  * DAP_CONFIG_FAST_CLOCK - threshold for switching to fast clock routines. This value
+    defines the frequency, at which more optimal pin manipulation functions are used.
+    This is the frequency produced by dap_clock_test(1) on the SWCLK pin.
+    You can also measure maximum achievable frequency on your platform by calling dap_clock_test(0).
+
+Your configuration file will need to define the following pin manipulation functions:
+
+ * DAP_CONFIG_SWCLK_TCK_write()
+ * DAP_CONFIG_SWDIO_TMS_write()
+ * DAP_CONFIG_TDO_write()
+ * DAP_CONFIG_nTRST_write()
+ * DAP_CONFIG_nRESET_write()
+ * DAP_CONFIG_SWCLK_TCK_read()
+ * DAP_CONFIG_SWDIO_TMS_read()
+ * DAP_CONFIG_TDI_read()
+ * DAP_CONFIG_TDO_read()
+ * DAP_CONFIG_nTRST_read()
+ * DAP_CONFIG_nRESET_read()
+ * DAP_CONFIG_SWCLK_TCK_set()
+ * DAP_CONFIG_SWCLK_TCK_clr()
+ * DAP_CONFIG_SWDIO_TMS_in()
+ * DAP_CONFIG_SWDIO_TMS_out()
+
+Note that all pin manipulation functions are required even if one of the interfaces (JTAG or SWD) is not enabled.
+
+Additionally configuration file must provide basic initialization and control functions:
+
+ * DAP_CONFIG_SETUP()
+ * DAP_CONFIG_DISCONNECT()
+ * DAP_CONFIG_CONNECT_SWD()
+ * DAP_CONFIG_CONNECT_JTAG()
+ * DAP_CONFIG_LED()
+ * DAP_CONFIG_DELAY()
+
+## Tools
+
+A complete RP2040 build requres bin2uf2 utility to generate UF2 file suitable for the RP2040 MSC bootloader.
+This utility can be downloded [here](https://github.com/ataradov/tools/tree/master/bin2uf2).
+
+## Binaries
+
+Generally there are no pre-built binaries due to effort required to maintain
+them and low potential benefit because of custom hardware requirement.
+
+For RP2040 and Raspberry Pi Pico board specifically there is a binary, since
+it is a standard and a widely available board that has a nonvolatile bootloader.
+
+The UF2 file is located [here](bin/free_dap_rp2040.uf2). Simply boot into
+a BootROM MSC mode and copy that file to the drive.
+
+I will try to do my best to keep this binary in sync with the code updates, but
+it is a manual process, so I may forget. Let me know if you have any issues.
+
+The pins used are as follows:
+
+| GPIO | Function |
+|:---:|:---|
+| 11 | SWCLK/TCK |
+| 12 | SWDIO/TMS |
+| 13 | TDI |
+| 14 | TDO |
+| 15 | nRESET |
+| 0 | VCP TX |
+| 1 | VCP RX |
+| 2 | VCP Status |
+| 25 (LED) | DAP Status |
+

dap_link/lib/free-dap/dap.c

@@ -0,0 +1,1509 @@
+/*
+ * Copyright (c) 2016-2021, Alex Taradov <alex@taradov.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*- Includes ----------------------------------------------------------------*/
+#include <string.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include "dap_config.h"
+#include "dap.h"
+
+/*- Definitions -------------------------------------------------------------*/
+#define ARRAY_SIZE(x)  ((int)(sizeof(x) / sizeof(0[x])))
+
+enum
+{
+  ID_DAP_INFO               = 0x00,
+  ID_DAP_HOST_STATUS        = 0x01,
+  ID_DAP_CONNECT            = 0x02,
+  ID_DAP_DISCONNECT         = 0x03,
+  ID_DAP_TRANSFER_CONFIGURE = 0x04,
+  ID_DAP_TRANSFER           = 0x05,
+  ID_DAP_TRANSFER_BLOCK     = 0x06,
+  ID_DAP_TRANSFER_ABORT     = 0x07,
+  ID_DAP_WRITE_ABORT        = 0x08,
+  ID_DAP_DELAY              = 0x09,
+  ID_DAP_RESET_TARGET       = 0x0a,
+
+  ID_DAP_SWJ_PINS           = 0x10,
+  ID_DAP_SWJ_CLOCK          = 0x11,
+  ID_DAP_SWJ_SEQUENCE       = 0x12,
+
+  ID_DAP_SWD_CONFIGURE      = 0x13,
+  ID_DAP_SWD_SEQUENCE       = 0x1d,
+
+  ID_DAP_JTAG_SEQUENCE      = 0x14,
+  ID_DAP_JTAG_CONFIGURE     = 0x15,
+  ID_DAP_JTAG_IDCODE        = 0x16,
+
+  ID_DAP_SWO_TRANSPORT      = 0x17,
+  ID_DAP_SWO_MODE           = 0x18,
+  ID_DAP_SWO_BAUDRATE       = 0x19,
+  ID_DAP_SWO_CONTROL        = 0x1a,
+  ID_DAP_SWO_STATUS         = 0x1b,
+  ID_DAP_SWO_EXT_STATUS     = 0x1e,
+  ID_DAP_SWO_DATA           = 0x1c,
+
+  ID_DAP_QUEUE_COMMANDS     = 0x7e,
+  ID_DAP_EXECUTE_COMMANDS   = 0x7f,
+
+  ID_DAP_VENDOR_0           = 0x80,
+  ID_DAP_VENDOR_31          = 0x9f,
+  ID_DAP_VENDOR_EX_FIRS     = 0xa0,
+  ID_DAP_VENDOR_EX_LAST     = 0xfe,
+
+  ID_DAP_INVALID            = 0xff,
+};
+
+enum
+{
+  DAP_INFO_VENDOR           = 0x01,
+  DAP_INFO_PRODUCT          = 0x02,
+  DAP_INFO_SER_NUM          = 0x03,
+  DAP_INFO_CMSIS_DAP_VER    = 0x04,
+  DAP_INFO_DEVICE_VENDOR    = 0x05,
+  DAP_INFO_DEVICE_NAME      = 0x06,
+  DAP_INFO_BOARD_VENDOR     = 0x07,
+  DAP_INFO_BOARD_NAME       = 0x08,
+  DAP_INFO_FW_VER           = 0x09,
+  DAP_INFO_CAPABILITIES     = 0xf0,
+  DAP_INFO_TDT              = 0xf1,
+  DAP_INFO_UART_RX_SIZE     = 0xfb,
+  DAP_INFO_UART_TX_SIZE     = 0xfc,
+  DAP_INFO_SWO_BUF_SIZE     = 0xfd,
+  DAP_INFO_PACKET_COUNT     = 0xfe,
+  DAP_INFO_PACKET_SIZE      = 0xff,
+};
+
+enum
+{
+  DAP_CAP_SWD               = (1 << 0),
+  DAP_CAP_JTAG              = (1 << 1),
+  DAP_CAP_SWO_UART          = (1 << 2),
+  DAP_CAP_SWO_MANCHESTER    = (1 << 3),
+  DAP_CAP_ATOMIC_CMD        = (1 << 4),
+  DAP_CAP_TDT               = (1 << 5),
+  DAP_CAP_SWO_STREAMING     = (1 << 6),
+  DAP_CAP_UART_COM_PORT     = (1 << 7),
+};
+
+enum
+{
+  DAP_TRANSFER_APnDP        = 1 << 0,
+  DAP_TRANSFER_RnW          = 1 << 1,
+  DAP_TRANSFER_A2           = 1 << 2,
+  DAP_TRANSFER_A3           = 1 << 3,
+  DAP_TRANSFER_MATCH_VALUE  = 1 << 4,
+  DAP_TRANSFER_MATCH_MASK   = 1 << 5,
+  DAP_TRANSFER_JTAG_ABORT   = 1 << 16,
+};
+
+enum
+{
+  DAP_TRANSFER_INVALID      = 0,
+  DAP_TRANSFER_OK           = 1 << 0,
+  DAP_TRANSFER_WAIT         = 1 << 1,
+  DAP_TRANSFER_FAULT        = 1 << 2,
+  DAP_TRANSFER_ERROR        = 1 << 3,
+  DAP_TRANSFER_MISMATCH     = 1 << 4,
+};
+
+enum
+{
+  DAP_PORT_DISABLED         = 0,
+  DAP_PORT_AUTODETECT       = 0,
+  DAP_PORT_SWD              = 1,
+  DAP_PORT_JTAG             = 2,
+};
+
+enum
+{
+  DAP_SWJ_SWCLK_TCK         = 1 << 0,
+  DAP_SWJ_SWDIO_TMS         = 1 << 1,
+  DAP_SWJ_TDI               = 1 << 2,
+  DAP_SWJ_TDO               = 1 << 3,
+  DAP_SWJ_nTRST             = 1 << 5,
+  DAP_SWJ_nRESET            = 1 << 7,
+};
+
+enum
+{
+  DAP_OK                    = 0x00,
+  DAP_ERROR                 = 0xff,
+};
+
+enum
+{
+  SWD_DP_R_IDCODE           = 0x00,
+  SWD_DP_W_ABORT            = 0x00,
+  SWD_DP_R_RDBUFF           = 0x0c,
+};
+
+enum
+{
+  JTAG_ABORT                = 0x08,
+  JTAG_DPACC                = 0x0a,
+  JTAG_APACC                = 0x0b,
+  JTAG_IDCODE               = 0x0e,
+  JTAG_BYPASS               = 0x0f,
+  JTAG_INVALID              = 0xff,
+};
+
+enum
+{
+  JTAG_SEQUENCE_COUNT       = 0x3f,
+  JTAG_SEQUENCE_TMS         = 0x40,
+  JTAG_SEQUENCE_TDO         = 0x80,
+};
+
+enum
+{
+  SWD_SEQUENCE_COUNT        = 0x3f,
+  SWD_SEQUENCE_DIN          = 0x80,
+};
+
+#define ARM_JTAG_IR_LENGTH  4
+
+/*- Constants ---------------------------------------------------------------*/
+static const struct
+{
+  int    id;
+  char   * const str;
+} dap_info_strings[] =
+{
+#ifdef DAP_CONFIG_VENDOR_STR
+  { DAP_INFO_VENDOR,        DAP_CONFIG_VENDOR_STR },
+#endif
+#ifdef DAP_CONFIG_PRODUCT_STR
+  { DAP_INFO_PRODUCT,       DAP_CONFIG_PRODUCT_STR },
+#endif
+#ifdef DAP_CONFIG_SER_NUM_STR
+  { DAP_INFO_SER_NUM,       DAP_CONFIG_SER_NUM_STR },
+#endif
+#ifdef DAP_CONFIG_CMSIS_DAP_VER_STR
+  { DAP_INFO_CMSIS_DAP_VER, DAP_CONFIG_CMSIS_DAP_VER_STR },
+#endif
+#ifdef DAP_CONFIG_DEVICE_VENDOR_STR
+  { DAP_INFO_DEVICE_VENDOR, DAP_CONFIG_DEVICE_VENDOR_STR },
+#endif
+#ifdef DAP_CONFIG_DEVICE_NAME_STR
+  { DAP_INFO_DEVICE_NAME,   DAP_CONFIG_DEVICE_NAME_STR },
+#endif
+#ifdef DAP_CONFIG_BOARD_VENDOR_STR
+  { DAP_INFO_BOARD_VENDOR,  DAP_CONFIG_BOARD_VENDOR_STR },
+#endif
+#ifdef DAP_CONFIG_BOARD_NAME_STR
+  { DAP_INFO_BOARD_NAME,    DAP_CONFIG_BOARD_NAME_STR },
+#endif
+#ifdef DAP_CONFIG_FW_VER_STR
+  { DAP_INFO_FW_VER,        DAP_CONFIG_FW_VER_STR },
+#endif
+};
+
+/*- Variables ---------------------------------------------------------------*/
+static int dap_port;
+static volatile bool dap_abort;
+static uint32_t dap_match_mask;
+static int dap_idle_cycles;
+static int dap_retry_count;
+static int dap_match_retry_count;
+static int dap_clock_delay;
+
+static void (*dap_swj_run)(int);
+static void (*dap_swd_write)(uint32_t, int);
+static uint32_t (*dap_swd_read)(int);
+
+#ifdef DAP_CONFIG_ENABLE_JTAG
+static uint32_t (*dap_jtag_write)(uint32_t, int);
+static uint32_t (*dap_jtag_read)(int);
+static uint32_t (*dap_jtag_rdwr)(uint32_t, int);
+#endif
+
+static uint8_t *dap_req_buf;
+static int dap_req_size;
+static int dap_req_ptr;
+
+static uint8_t *dap_resp_buf;
+static int dap_resp_size;
+static int dap_resp_ptr;
+
+static bool dap_buf_error;
+
+static int dap_swd_turnaround;
+static bool dap_swd_data_phase;
+
+#ifdef DAP_CONFIG_ENABLE_JTAG
+static int dap_jtag_dev_count;
+static int dap_jtag_dev_index;
+static int dap_jtag_ir_length[DAP_CONFIG_JTAG_DEV_COUNT];
+static int dap_jtag_ir_before[DAP_CONFIG_JTAG_DEV_COUNT];
+static int dap_jtag_ir_after[DAP_CONFIG_JTAG_DEV_COUNT];
+static int dap_jtag_ir;
+#endif
+
+/*- Implementations ---------------------------------------------------------*/
+
+//-----------------------------------------------------------------------------
+static void dap_delay_us(int delay)
+{
+  while (delay)
+  {
+    int del = (delay > 100000) ? 100000 : delay;
+    DAP_CONFIG_DELAY((DAP_CONFIG_DELAY_CONSTANT * 2 * del) / 1000);
+    delay -= del;
+  }
+}
+
+//-----------------------------------------------------------------------------
+#define DAP_SWJ_FN(ver, delay) \
+  DAP_CONFIG_PERFORMANCE_ATTR						\
+  static void dap_swj_run_##ver(int cycles)				\
+  {									\
+    while (cycles--)							\
+    {									\
+      DAP_CONFIG_SWCLK_TCK_clr();					\
+      delay(dap_clock_delay);						\
+      DAP_CONFIG_SWCLK_TCK_set();					\
+      delay(dap_clock_delay);						\
+    }									\
+  }
+DAP_SWJ_FN(slow, DAP_CONFIG_DELAY)
+DAP_SWJ_FN(fast, (void))
+
+//-----------------------------------------------------------------------------
+#define DAP_SWD_FN(ver, delay) \
+  DAP_CONFIG_PERFORMANCE_ATTR						\
+  static void dap_swd_write_##ver(uint32_t value, int size)		\
+  {									\
+    for (int i = 0; i < size; i++)					\
+    {									\
+      DAP_CONFIG_SWDIO_TMS_write(value & 1);				\
+      DAP_CONFIG_SWCLK_TCK_clr();					\
+      delay(dap_clock_delay);						\
+      DAP_CONFIG_SWCLK_TCK_set();					\
+      delay(dap_clock_delay);						\
+      value >>= 1;							\
+    }									\
+  }									\
+									\
+  DAP_CONFIG_PERFORMANCE_ATTR						\
+  static uint32_t dap_swd_read_##ver(int size)				\
+  {									\
+    uint32_t value = 0;							\
+    uint32_t bit;							\
+    for (int i = 0; i < size; i++)					\
+    {									\
+      DAP_CONFIG_SWCLK_TCK_clr();					\
+      delay(dap_clock_delay);						\
+      bit = DAP_CONFIG_SWDIO_TMS_read();				\
+      DAP_CONFIG_SWCLK_TCK_set();					\
+      delay(dap_clock_delay);						\
+      value |= (bit << i);						\
+    }									\
+    return value;							\
+  }
+
+DAP_SWD_FN(slow, DAP_CONFIG_DELAY)
+DAP_SWD_FN(fast, (void))
+
+//-----------------------------------------------------------------------------
+static inline uint32_t dap_parity(uint32_t value)
+{
+  value ^= value >> 16;
+  value ^= value >> 8;
+  value ^= value >> 4;
+  value &= 0x0f;
+
+  return (0x6996 >> value) & 1;
+}
+
+//-----------------------------------------------------------------------------
+static int dap_swd_operation(int req, uint32_t *data)
+{
+  uint32_t value;
+  int ack = 0;
+
+  req &= (DAP_TRANSFER_APnDP | DAP_TRANSFER_RnW | DAP_TRANSFER_A2 | DAP_TRANSFER_A3);
+
+  dap_swd_write(0x81 | (dap_parity(req) << 5) | (req << 1), 8);
+
+  DAP_CONFIG_SWDIO_TMS_in();
+
+  dap_swj_run(dap_swd_turnaround);
+
+  ack = dap_swd_read(3);
+
+  if (DAP_TRANSFER_OK == ack)
+  {
+    if (req & DAP_TRANSFER_RnW)
+    {
+      value = dap_swd_read(32);
+
+      if (dap_parity(value) != dap_swd_read(1))
+        ack = DAP_TRANSFER_ERROR;
+
+      if (data)
+        *data = value;
+
+      dap_swj_run(dap_swd_turnaround);
+
+      DAP_CONFIG_SWDIO_TMS_out();
+    }
+    else
+    {
+      dap_swj_run(dap_swd_turnaround);
+
+      DAP_CONFIG_SWDIO_TMS_out();
+
+      dap_swd_write(*data, 32);
+      dap_swd_write(dap_parity(*data), 1);
+    }
+
+    DAP_CONFIG_SWDIO_TMS_write(0);
+    dap_swj_run(dap_idle_cycles);
+  }
+
+  else if (DAP_TRANSFER_WAIT == ack || DAP_TRANSFER_FAULT == ack)
+  {
+    if (dap_swd_data_phase && (req & DAP_TRANSFER_RnW))
+      dap_swj_run(32 + 1);
+
+    dap_swj_run(dap_swd_turnaround);
+
+    DAP_CONFIG_SWDIO_TMS_out();
+
+    if (dap_swd_data_phase && (0 == (req & DAP_TRANSFER_RnW)))
+    {
+      DAP_CONFIG_SWDIO_TMS_write(0);
+      dap_swj_run(32 + 1);
+    }
+  }
+
+  else
+  {
+    dap_swj_run(dap_swd_turnaround + 32 + 1);
+  }
+
+  DAP_CONFIG_SWDIO_TMS_write(1);
+
+  return ack;
+}
+
+#ifdef DAP_CONFIG_ENABLE_JTAG
+//-----------------------------------------------------------------------------
+#define DAP_JTAG_FN(ver, delay) \
+  DAP_CONFIG_PERFORMANCE_ATTR						\
+  static uint32_t dap_jtag_write_##ver(uint32_t value, int size)	\
+  {									\
+    for (int i = 0; i < size; i++)					\
+    {									\
+      DAP_CONFIG_TDI_write(value & 1);					\
+      DAP_CONFIG_SWCLK_TCK_clr();					\
+      delay(dap_clock_delay);						\
+      DAP_CONFIG_SWCLK_TCK_set();					\
+      delay(dap_clock_delay);						\
+      value >>= 1;							\
+    }									\
+    return value;							\
+  }									\
+									\
+  DAP_CONFIG_PERFORMANCE_ATTR						\
+  static uint32_t dap_jtag_read_##ver(int size)				\
+  {									\
+    uint32_t value = 0;							\
+    uint32_t bit;							\
+    for (int i = 0; i < size; i++)					\
+    {									\
+      DAP_CONFIG_SWCLK_TCK_clr();					\
+      delay(dap_clock_delay);						\
+      bit = DAP_CONFIG_TDO_read();					\
+      DAP_CONFIG_SWCLK_TCK_set();					\
+      delay(dap_clock_delay);						\
+      value |= (bit << i);						\
+    }									\
+    return value;							\
+  }									\
+									\
+  DAP_CONFIG_PERFORMANCE_ATTR						\
+  static uint32_t dap_jtag_rdwr_##ver(uint32_t value, int size)		\
+  {									\
+    uint32_t rvalue = 0;						\
+    uint32_t bit;							\
+    for (int i = 0; i < size; i++)					\
+    {									\
+      DAP_CONFIG_TDI_write(value & 1);					\
+      DAP_CONFIG_SWCLK_TCK_clr();					\
+      delay(dap_clock_delay);						\
+      bit = DAP_CONFIG_TDO_read();					\
+      DAP_CONFIG_SWCLK_TCK_set();					\
+      delay(dap_clock_delay);						\
+      value >>= 1;							\
+      rvalue |= (bit << i);						\
+    }									\
+    return rvalue;							\
+  }
+
+DAP_JTAG_FN(slow, DAP_CONFIG_DELAY)
+DAP_JTAG_FN(fast, (void))
+
+//-----------------------------------------------------------------------------
+static void dap_jtag_write_ir(int ir)
+{
+  int len = dap_jtag_ir_length[dap_jtag_dev_index];
+
+  DAP_CONFIG_SWDIO_TMS_write(1);
+  dap_swj_run(2); // -> Select-IR-Scan
+  DAP_CONFIG_SWDIO_TMS_write(0);
+  dap_swj_run(2); // -> Shift-IR
+
+  DAP_CONFIG_TDI_write(1);
+  dap_swj_run(dap_jtag_ir_before[dap_jtag_dev_index]);
+
+  ir = dap_jtag_write(ir, len-1);
+
+  if (dap_jtag_ir_after[dap_jtag_dev_index])
+  {
+    dap_jtag_write(ir, 1);
+
+    DAP_CONFIG_TDI_write(1);
+    dap_swj_run(dap_jtag_ir_after[dap_jtag_dev_index]-1);
+
+    DAP_CONFIG_SWDIO_TMS_write(1);
+    dap_swj_run(1); // -> Exit1-IR
+  }
+  else
+  {
+    DAP_CONFIG_SWDIO_TMS_write(1);
+    dap_jtag_write(ir, 1); // -> Exit1-IR
+  }
+
+  dap_swj_run(1); // -> Update-IR
+  DAP_CONFIG_SWDIO_TMS_write(0);
+  dap_swj_run(1); // -> Idle
+  DAP_CONFIG_TDI_write(1);
+}
+
+//-----------------------------------------------------------------------------
+static int dap_jtag_operation(int req, uint32_t *data)
+{
+  int ack, ir;
+
+  if (DAP_TRANSFER_JTAG_ABORT == req)
+    ir = JTAG_ABORT;
+  else
+    ir = (req & DAP_TRANSFER_APnDP) ? JTAG_APACC : JTAG_DPACC;
+
+  if (ir != dap_jtag_ir)
+  {
+    dap_jtag_ir = ir;
+    dap_jtag_write_ir(ir);
+  }
+
+  DAP_CONFIG_SWDIO_TMS_write(1);
+  dap_swj_run(1); // -> Select-DR-Scan
+  DAP_CONFIG_SWDIO_TMS_write(0);
+  dap_swj_run(2 + dap_jtag_dev_index); // -> Shift-DR
+
+  ack = dap_jtag_rdwr(req >> 1, 3);
+
+  if (ack == 0x2)
+    ack = DAP_TRANSFER_OK; // or FAULT
+  else if (ack == 0x1)
+    ack = DAP_TRANSFER_WAIT;
+  else
+    ack = DAP_TRANSFER_INVALID;
+
+  if (DAP_TRANSFER_OK == ack)
+  {
+    int cnt = dap_jtag_dev_count - dap_jtag_dev_index - 1;
+    uint32_t value;
+
+    if (req & DAP_TRANSFER_RnW)
+    {
+      if (cnt)
+      {
+        value = dap_jtag_read(32);
+        dap_swj_run(cnt-1);
+        DAP_CONFIG_SWDIO_TMS_write(1);
+        dap_swj_run(1); // -> Exit1-DR
+      }
+      else
+      {
+        value = dap_jtag_read(31);
+        DAP_CONFIG_SWDIO_TMS_write(1);
+        value |= (dap_jtag_read(1) << 31); // -> Exit1-DR
+      }
+
+      if (data)
+        *data = value;
+    }
+    else
+    {
+      value = *data;
+
+      if (cnt)
+      {
+        dap_jtag_write(value, 32);
+        dap_swj_run(cnt-1);
+        DAP_CONFIG_SWDIO_TMS_write(1);
+        dap_swj_run(1); // -> Exit1-DR
+      }
+      else
+      {
+        value = dap_jtag_write(value, 31);
+        DAP_CONFIG_SWDIO_TMS_write(1);
+        dap_jtag_write(value, 1); // -> Exit1-DR
+      }
+    }
+  }
+  else // Not OK
+  {
+    DAP_CONFIG_SWDIO_TMS_write(1);
+    dap_swj_run(1); // -> Exit1-DR
+  }
+
+  dap_swj_run(1); // -> Update-DR
+  DAP_CONFIG_SWDIO_TMS_write(0);
+  dap_swj_run(1); // -> Idle
+  DAP_CONFIG_TDI_write(1);
+
+  dap_swj_run(dap_idle_cycles);
+
+  return ack;
+}
+#endif // DAP_CONFIG_ENABLE_JTAG
+
+//-----------------------------------------------------------------------------
+static void dap_setup_clock(int freq)
+{
+  if (freq > DAP_CONFIG_FAST_CLOCK)
+  {
+    dap_clock_delay = 0;
+    dap_swj_run     = dap_swj_run_fast;
+    dap_swd_write   = dap_swd_write_fast;
+    dap_swd_read    = dap_swd_read_fast;
+#ifdef DAP_CONFIG_ENABLE_JTAG
+    dap_jtag_write  = dap_jtag_write_fast;
+    dap_jtag_read   = dap_jtag_read_fast;
+    dap_jtag_rdwr   = dap_jtag_rdwr_fast;
+#endif
+  }
+  else
+  {
+    dap_clock_delay = (DAP_CONFIG_DELAY_CONSTANT * 1000) / freq;
+    dap_swj_run     = dap_swj_run_slow;
+    dap_swd_write   = dap_swd_write_slow;
+    dap_swd_read    = dap_swd_read_slow;
+#ifdef DAP_CONFIG_ENABLE_JTAG
+    dap_jtag_write  = dap_jtag_write_slow;
+    dap_jtag_read   = dap_jtag_read_slow;
+    dap_jtag_rdwr   = dap_jtag_rdwr_slow;
+#endif
+  }
+}
+
+//-----------------------------------------------------------------------------
+static bool dap_select_device(int index)
+{
+  if (DAP_PORT_SWD == dap_port)
+    return true;
+
+#ifdef DAP_CONFIG_ENABLE_JTAG
+  if (DAP_PORT_JTAG == dap_port)
+  {
+    if (index >= dap_jtag_dev_count || dap_jtag_ir_length[index] != ARM_JTAG_IR_LENGTH)
+      return false;
+
+    dap_jtag_dev_index = index;
+
+    return true;
+  }
+#endif
+
+  (void)index;
+  return false;
+}
+
+//-----------------------------------------------------------------------------
+static int dap_transfer_word(int req, uint32_t *data)
+{
+  int ack = DAP_TRANSFER_INVALID;
+
+  for (int i = 0; i < dap_retry_count; i++)
+  {
+    if (DAP_PORT_SWD == dap_port)
+      ack = dap_swd_operation(req, data);
+
+#ifdef DAP_CONFIG_ENABLE_JTAG
+    else if (DAP_PORT_JTAG == dap_port)
+      ack = dap_jtag_operation(req, data);
+#endif
+
+    if (DAP_TRANSFER_WAIT != ack || dap_abort)
+      break;
+  }
+
+  return ack;
+}
+
+//-----------------------------------------------------------------------------
+static bool dap_needs_posted_read(int request)
+{
+  if (0 == (request & DAP_TRANSFER_RnW))
+    return false;
+
+  if (DAP_PORT_SWD == dap_port)
+    return (request & DAP_TRANSFER_APnDP);
+
+#ifdef DAP_CONFIG_ENABLE_JTAG
+  if (DAP_PORT_JTAG == dap_port)
+    return true;
+#endif
+
+  return false;
+}
+
+//-----------------------------------------------------------------------------
+static void dap_buf_init(uint8_t *req, int req_size, uint8_t *resp, int resp_size)
+{
+  dap_req_buf  = req;
+  dap_req_size = req_size;
+  dap_req_ptr  = 0;
+
+  dap_resp_buf  = resp;
+  dap_resp_size = resp_size;
+  dap_resp_ptr  = 0;
+
+  dap_buf_error = false;
+}
+
+//-----------------------------------------------------------------------------
+uint8_t dap_req_get_byte(void)
+{
+  if (dap_buf_error || ((dap_req_size - dap_req_ptr) < (int)sizeof(uint8_t)))
+  {
+    dap_buf_error = true;
+    return 0;
+  }
+
+  return dap_req_buf[dap_req_ptr++];
+}
+
+//-----------------------------------------------------------------------------
+uint16_t dap_req_get_half(void)
+{
+  if (dap_buf_error || ((dap_req_size - dap_req_ptr) < (int)sizeof(uint16_t)))
+  {
+    dap_buf_error = true;
+    return 0;
+  }
+
+  uint16_t value =
+      ((uint16_t)dap_req_buf[dap_req_ptr + 1] << 8) |
+       (uint16_t)dap_req_buf[dap_req_ptr];
+  dap_req_ptr += sizeof(uint16_t);
+
+  return value;
+}
+
+//-----------------------------------------------------------------------------
+uint32_t dap_req_get_word(void)
+{
+  if (dap_buf_error || ((dap_req_size - dap_req_ptr) < (int)sizeof(uint32_t)))
+  {
+    dap_buf_error = true;
+    return 0;
+  }
+
+  uint32_t value =
+      ((uint32_t)dap_req_buf[dap_req_ptr + 3] << 24) |
+      ((uint32_t)dap_req_buf[dap_req_ptr + 2] << 16) |
+      ((uint32_t)dap_req_buf[dap_req_ptr + 1] << 8) |
+       (uint32_t)dap_req_buf[dap_req_ptr];
+  dap_req_ptr += sizeof(uint32_t);
+
+  return value;
+}
+
+//-----------------------------------------------------------------------------
+void dap_resp_add_byte(uint8_t value)
+{
+  if (dap_buf_error || ((dap_resp_size - dap_resp_ptr) < (int)sizeof(uint8_t)))
+  {
+    dap_buf_error = true;
+    return;
+  }
+
+  dap_resp_buf[dap_resp_ptr++] = value;
+}
+
+//-----------------------------------------------------------------------------
+void dap_resp_add_word(uint32_t value)
+{
+  if (dap_buf_error || ((dap_resp_size - dap_resp_ptr) < (int)sizeof(uint32_t)))
+  {
+    dap_buf_error = true;
+    return;
+  }
+
+  dap_resp_buf[dap_resp_ptr + 0] = value;
+  dap_resp_buf[dap_resp_ptr + 1] = value >> 8;
+  dap_resp_buf[dap_resp_ptr + 2] = value >> 16;
+  dap_resp_buf[dap_resp_ptr + 3] = value >> 24;
+  dap_resp_ptr += sizeof(uint32_t);
+}
+
+//-----------------------------------------------------------------------------
+void dap_resp_set_byte(int index, uint8_t value)
+{
+  if (index < dap_resp_ptr)
+    dap_resp_buf[index] = value;
+}
+
+//-----------------------------------------------------------------------------
+bool dap_is_buf_error(void)
+{
+  return dap_buf_error;
+}
+
+//-----------------------------------------------------------------------------
+static void dap_info(void)
+{
+  int index = dap_req_get_byte();
+
+  if (DAP_INFO_CAPABILITIES == index)
+  {
+    int cap = DAP_CAP_SWD;
+#ifdef DAP_CONFIG_ENABLE_JTAG
+    cap |= DAP_CAP_JTAG;
+#endif
+    dap_resp_add_byte(1);
+    dap_resp_add_byte(cap);
+  }
+  else if (DAP_INFO_PACKET_COUNT == index)
+  {
+    dap_resp_add_byte(1);
+    dap_resp_add_byte(DAP_CONFIG_PACKET_COUNT);
+  }
+  else if (DAP_INFO_PACKET_SIZE == index)
+  {
+    dap_resp_add_byte(2);
+    dap_resp_add_byte(DAP_CONFIG_PACKET_SIZE & 0xff);
+    dap_resp_add_byte((DAP_CONFIG_PACKET_SIZE >> 8) & 0xff);
+  }
+  else
+  {
+    dap_resp_add_byte(0); // Size placeholder
+
+    for (int i = 0; i < ARRAY_SIZE(dap_info_strings); i++)
+    {
+      if (dap_info_strings[i].id == index)
+      {
+        const char *str = dap_info_strings[i].str;
+
+        while (*str)
+          dap_resp_add_byte(*str++);
+        dap_resp_add_byte(0);
+
+        dap_resp_set_byte(1, dap_resp_ptr-2);
+
+        break;
+      }
+    }
+  }
+}
+
+//-----------------------------------------------------------------------------
+static void dap_host_status(void)
+{
+  int index = dap_req_get_byte();
+  int state = dap_req_get_byte();
+
+  DAP_CONFIG_LED(index, state);
+
+  dap_resp_add_byte(DAP_OK);
+}
+
+//-----------------------------------------------------------------------------
+static void dap_connect(void)
+{
+  int port = dap_req_get_byte();
+
+  if (DAP_PORT_AUTODETECT == port)
+    port = DAP_CONFIG_DEFAULT_PORT;
+
+  dap_port = DAP_PORT_DISABLED;
+
+  if (DAP_PORT_SWD == port)
+  {
+    DAP_CONFIG_CONNECT_SWD();
+    dap_port = DAP_PORT_SWD;
+  }
+
+#ifdef DAP_CONFIG_ENABLE_JTAG
+  else if (DAP_PORT_JTAG == port)
+  {
+    DAP_CONFIG_CONNECT_JTAG();
+    dap_port = DAP_PORT_JTAG;
+  }
+#endif
+
+  dap_resp_add_byte(dap_port);
+}
+
+//-----------------------------------------------------------------------------
+static void dap_disconnect(void)
+{
+  DAP_CONFIG_DISCONNECT();
+
+  dap_port = DAP_PORT_DISABLED;
+
+  dap_resp_add_byte(DAP_OK);
+}
+
+//-----------------------------------------------------------------------------
+static void dap_transfer_configure(void)
+{
+  dap_idle_cycles = dap_req_get_byte();
+  dap_retry_count = dap_req_get_half();
+  dap_match_retry_count = dap_req_get_half();
+
+  dap_resp_add_byte(DAP_OK);
+}
+
+//-----------------------------------------------------------------------------
+static void dap_transfer(void)
+{
+  int req_count, resp_count, request, ack;
+  bool posted_read, verify_write;
+  uint32_t data, match_value;
+
+  dap_resp_add_byte(0); // Count
+  dap_resp_add_byte(DAP_TRANSFER_INVALID);
+
+  if (!dap_select_device(dap_req_get_byte()))
+    return;
+
+  req_count  = dap_req_get_byte();
+  resp_count = 0;
+
+  posted_read = false;
+  verify_write = false;
+  ack = DAP_TRANSFER_INVALID;
+
+  for (; req_count && !dap_abort && !dap_buf_error; req_count--, resp_count++)
+  {
+    request = dap_req_get_byte();
+    verify_write = false;
+
+    if (posted_read)
+    {
+      if (dap_needs_posted_read(request))
+      {
+        ack = dap_transfer_word(request, &data);
+      }
+      else
+      {
+        ack = dap_transfer_word(SWD_DP_R_RDBUFF | DAP_TRANSFER_RnW, &data);
+        posted_read = false;
+      }
+
+      if (ack != DAP_TRANSFER_OK)
+        break;
+
+      dap_resp_add_word(data);
+
+      if (posted_read)
+        continue;
+    }
+
+    if (request & DAP_TRANSFER_RnW)
+    {
+      if (request & DAP_TRANSFER_MATCH_VALUE)
+      {
+        match_value = dap_req_get_word();
+
+        if (dap_needs_posted_read(request))
+          dap_transfer_word(request, NULL);
+
+        for (int i = 0; i < dap_match_retry_count; i++)
+        {
+          ack = dap_transfer_word(request, &data);
+
+          if (DAP_TRANSFER_OK != ack || (data & dap_match_mask) == match_value || dap_abort)
+            break;
+        };
+
+        if ((data & dap_match_mask) != match_value)
+          ack |= DAP_TRANSFER_MISMATCH;
+
+        if (ack != DAP_TRANSFER_OK)
+          break;
+      }
+      else if (dap_needs_posted_read(request))
+      {
+        ack = dap_transfer_word(request, NULL);
+
+        if (ack != DAP_TRANSFER_OK)
+          break;
+
+        posted_read = true;
+      }
+      else
+      {
+        ack = dap_transfer_word(request, &data);
+
+        if (DAP_TRANSFER_OK != ack)
+          break;
+
+        dap_resp_add_word(data);
+      }
+    }
+    else // Write
+    {
+      data = dap_req_get_word();
+
+      if (request & DAP_TRANSFER_MATCH_MASK)
+      {
+        ack = DAP_TRANSFER_OK;
+        dap_match_mask = data;
+      }
+      else
+      {
+        ack = dap_transfer_word(request, &data);
+
+        if (ack != DAP_TRANSFER_OK)
+          break;
+
+        verify_write = true;
+      }
+    }
+  }
+
+  if (DAP_TRANSFER_OK == ack)
+  {
+    if (posted_read)
+    {
+      ack = dap_transfer_word(SWD_DP_R_RDBUFF | DAP_TRANSFER_RnW, &data);
+      dap_resp_add_word(data);
+    }
+    else if (verify_write)
+    {
+      ack = dap_transfer_word(SWD_DP_R_RDBUFF | DAP_TRANSFER_RnW, NULL);
+    }
+  }
+
+  dap_resp_set_byte(1, resp_count);
+  dap_resp_set_byte(2, ack);
+}
+
+//-----------------------------------------------------------------------------
+static void dap_transfer_block(void)
+{
+  int req_count, resp_count, request, ack;
+  uint32_t data;
+
+  dap_resp_add_byte(0); // Count
+  dap_resp_add_byte(0); // Count
+  dap_resp_add_byte(DAP_TRANSFER_INVALID);
+
+  if (!dap_select_device(dap_req_get_byte()))
+    return;
+
+  req_count  = dap_req_get_half();
+  resp_count = 0;
+
+  if (0 == req_count)
+    return;
+
+  request = dap_req_get_byte();
+  ack = DAP_TRANSFER_INVALID;
+
+  if (request & DAP_TRANSFER_RnW)
+  {
+    bool needs_posted = dap_needs_posted_read(request);
+    int transfers = needs_posted ? (req_count + 1) : req_count;
+
+    for (int i = 0; i < transfers; i++)
+    {
+      if (i == req_count)
+        request = SWD_DP_R_RDBUFF | DAP_TRANSFER_RnW;
+
+      ack = dap_transfer_word(request, &data);
+
+      if (DAP_TRANSFER_OK != ack)
+        break;
+
+      if (needs_posted && i == 0)
+        continue;
+
+      dap_resp_add_word(data);
+      resp_count++;
+    }
+  }
+  else // Write
+  {
+    for (int i = 0; i < req_count; i++)
+    {
+      data = dap_req_get_word();
+
+      ack = dap_transfer_word(request, &data);
+
+      if (DAP_TRANSFER_OK != ack)
+        break;
+
+      resp_count++;
+    }
+
+    if (DAP_TRANSFER_OK == ack)
+      ack = dap_transfer_word(SWD_DP_R_RDBUFF | DAP_TRANSFER_RnW, NULL);
+  }
+
+  dap_resp_set_byte(1, resp_count);
+  dap_resp_set_byte(2, resp_count >> 8);
+  dap_resp_set_byte(3, ack);
+}
+
+//-----------------------------------------------------------------------------
+static void dap_transfer_abort(void)
+{
+  // This request is handled outside of the normal queue.
+  // We should never get here.
+  dap_resp_add_byte(DAP_OK);
+}
+
+//-----------------------------------------------------------------------------
+static void dap_write_abort(void)
+{
+  int status = DAP_ERROR;
+  uint32_t data;
+
+  if (!dap_select_device(dap_req_get_byte()))
+  {
+    dap_resp_add_byte(DAP_ERROR);
+    return;
+  }
+
+  data = dap_req_get_word();
+
+  if (DAP_PORT_SWD == dap_port)
+  {
+    dap_swd_operation(SWD_DP_W_ABORT, &data);
+    status = DAP_OK;
+  }
+
+#ifdef DAP_CONFIG_ENABLE_JTAG
+  else if (DAP_PORT_JTAG == dap_port)
+  {
+    dap_jtag_operation(DAP_TRANSFER_JTAG_ABORT, &data);
+    status = DAP_OK;
+  }
+#endif
+
+  dap_resp_add_byte(status);
+}
+
+//-----------------------------------------------------------------------------
+static void dap_delay(void)
+{
+  int delay = dap_req_get_half();
+  dap_delay_us(delay);
+  dap_resp_add_byte(DAP_OK);
+}
+
+//-----------------------------------------------------------------------------
+static void dap_reset_target(void)
+{
+  dap_resp_add_byte(DAP_OK);
+
+#ifdef DAP_CONFIG_RESET_TARGET_FN
+  DAP_CONFIG_RESET_TARGET_FN();
+  dap_resp_add_byte(1);
+#else
+  dap_resp_add_byte(0);
+#endif
+}
+
+//-----------------------------------------------------------------------------
+static void dap_swj_pins(void)
+{
+  int value  = dap_req_get_byte();
+  int select = dap_req_get_byte();
+  int wait   = dap_req_get_word();
+
+  if (select & DAP_SWJ_SWCLK_TCK)
+    DAP_CONFIG_SWCLK_TCK_write(value & DAP_SWJ_SWCLK_TCK);
+
+  if (select & DAP_SWJ_SWDIO_TMS)
+    DAP_CONFIG_SWDIO_TMS_write(value & DAP_SWJ_SWDIO_TMS);
+
+  if (select & DAP_SWJ_TDI)
+    DAP_CONFIG_TDI_write(value & DAP_SWJ_TDI);
+
+  if (select & DAP_SWJ_nTRST)
+    DAP_CONFIG_nTRST_write(value & DAP_SWJ_nTRST);
+
+  if (select & DAP_SWJ_nRESET)
+    DAP_CONFIG_nRESET_write(value & DAP_SWJ_nRESET);
+
+  dap_delay_us(wait * 1000);
+
+  value =
+    (DAP_CONFIG_SWCLK_TCK_read() ? DAP_SWJ_SWCLK_TCK : 0) |
+    (DAP_CONFIG_SWDIO_TMS_read() ? DAP_SWJ_SWDIO_TMS : 0) |
+    (DAP_CONFIG_TDI_read()       ? DAP_SWJ_TDI       : 0) |
+    (DAP_CONFIG_TDO_read()       ? DAP_SWJ_TDO       : 0) |
+    (DAP_CONFIG_nTRST_read()     ? DAP_SWJ_nTRST     : 0) |
+    (DAP_CONFIG_nRESET_read()    ? DAP_SWJ_nRESET    : 0);
+
+  dap_resp_add_byte(value);
+}
+
+//-----------------------------------------------------------------------------
+static void dap_swj_clock(void)
+{
+  int freq = dap_req_get_word();
+  dap_setup_clock(freq);
+  dap_resp_add_byte(DAP_OK);
+}
+
+//-----------------------------------------------------------------------------
+static void dap_swj_sequence(void)
+{
+  int size = dap_req_get_byte();
+
+  while (size)
+  {
+    int sz = (size > 8) ? 8 : size;
+    dap_swd_write(dap_req_get_byte(), sz);
+    size -= sz;
+  }
+
+  dap_resp_add_byte(DAP_OK);
+}
+
+//-----------------------------------------------------------------------------
+static void dap_swd_configure(void)
+{
+  int data = dap_req_get_byte();
+
+  dap_swd_turnaround = (data & 3) + 1;
+  dap_swd_data_phase = (data & 4) ? 1 : 0;
+
+  dap_resp_add_byte(DAP_OK);
+}
+
+//-----------------------------------------------------------------------------
+static void dap_swd_sequence(void)
+{
+  int req_count;
+
+  if (DAP_PORT_SWD != dap_port)
+  {
+    dap_resp_add_byte(DAP_ERROR);
+    return;
+  }
+
+  dap_resp_add_byte(DAP_OK);
+
+  req_count = dap_req_get_byte();
+
+  for (int i = 0; i < req_count; i++)
+  {
+    int info  = dap_req_get_byte();
+    int count = info & SWD_SEQUENCE_COUNT;
+    int din   = info & SWD_SEQUENCE_DIN;
+
+    if (count == 0)
+      count = 64U;
+
+    if (din)
+    {
+      DAP_CONFIG_SWDIO_TMS_in();
+
+      while (count)
+      {
+        int sz = (count > 8) ? 8 : count;
+        int value = dap_swd_read(sz);
+        dap_resp_add_byte(value);
+        count -= sz;
+      }
+    }
+    else
+    {
+      DAP_CONFIG_SWDIO_TMS_out();
+
+      while (count)
+      {
+        int sz = (count > 8) ? 8 : count;
+        dap_swd_write(dap_req_get_byte(), sz);
+        count -= sz;
+      }
+    }
+  }
+
+  DAP_CONFIG_SWDIO_TMS_out();
+}
+
+//-----------------------------------------------------------------------------
+static void dap_jtag_sequence(void)
+{
+#ifdef DAP_CONFIG_ENABLE_JTAG
+  int req_count;
+
+  if (DAP_PORT_JTAG != dap_port)
+  {
+    dap_resp_add_byte(DAP_ERROR);
+    return;
+  }
+
+  dap_resp_add_byte(DAP_OK);
+
+  req_count = dap_req_get_byte();
+
+  for (int i = 0; i < req_count; i++)
+  {
+    int info  = dap_req_get_byte();
+    int count = info & JTAG_SEQUENCE_COUNT;
+    int tms   = info & JTAG_SEQUENCE_TMS;
+    int tdo   = info & JTAG_SEQUENCE_TDO;
+
+    if (count == 0)
+      count = 64;
+
+    DAP_CONFIG_SWDIO_TMS_write(tms);
+
+    while (count)
+    {
+      int sz = (count > 8) ? 8 : count;
+
+      if (tdo)
+      {
+        int value = dap_jtag_rdwr(dap_req_get_byte(), sz);
+        dap_resp_add_byte(value);
+      }
+      else
+      {
+        dap_jtag_write(dap_req_get_byte(), sz);
+      }
+
+      count -= sz;
+    }
+  }
+#else
+  dap_resp_add_byte(DAP_ERROR);
+#endif
+}
+
+//-----------------------------------------------------------------------------
+static void dap_jtag_configure(void)
+{
+#ifdef DAP_CONFIG_ENABLE_JTAG
+  int count = dap_req_get_byte();
+  int bits = 0;
+
+  if (count > DAP_CONFIG_JTAG_DEV_COUNT)
+  {
+    dap_resp_add_byte(DAP_ERROR);
+    return;
+  }
+
+  dap_jtag_dev_count = count;
+  dap_jtag_dev_index = 0;
+
+  for (int i = 0; i < dap_jtag_dev_count; i++)
+  {
+    dap_jtag_ir_length[i] = dap_req_get_byte();
+    dap_jtag_ir_before[i] = bits;
+    bits += dap_jtag_ir_length[i];
+  }
+
+  for (int i = 0; i < dap_jtag_dev_count; i++)
+  {
+    bits -= dap_jtag_ir_length[i];
+    dap_jtag_ir_after[i] = bits;
+  }
+
+  dap_resp_add_byte(DAP_OK);
+#else
+  dap_resp_add_byte(DAP_ERROR);
+#endif
+}
+
+//-----------------------------------------------------------------------------
+static void dap_jtag_idcode(void)
+{
+#ifdef DAP_CONFIG_ENABLE_JTAG
+  uint32_t data;
+
+  if (DAP_PORT_JTAG != dap_port || !dap_select_device(dap_req_get_byte()))
+  {
+    dap_resp_add_byte(DAP_ERROR);
+    return;
+  }
+
+  dap_jtag_write_ir(JTAG_IDCODE);
+
+  DAP_CONFIG_SWDIO_TMS_write(1);
+  dap_swj_run(1); // -> Select-DR-Scan
+  DAP_CONFIG_SWDIO_TMS_write(0);
+  dap_swj_run(2 + dap_jtag_dev_index); // -> Shift-DR
+
+  data = dap_jtag_read(31);
+
+  DAP_CONFIG_SWDIO_TMS_write(1);
+  data |= (dap_jtag_read(1) << 31); // -> Exit1-DR
+
+  dap_swj_run(1); // -> Update-DR
+  DAP_CONFIG_SWDIO_TMS_write(0);
+  dap_swj_run(1); // -> Idle
+  DAP_CONFIG_TDI_write(1);
+
+  dap_resp_add_byte(DAP_OK);
+  dap_resp_add_word(data);
+#endif
+}
+
+//-----------------------------------------------------------------------------
+void dap_init(void)
+{
+  dap_port              = DAP_PORT_DISABLED;
+  dap_abort             = false;
+  dap_match_mask        = 0;
+  dap_idle_cycles       = 0;
+  dap_retry_count       = 100;
+  dap_match_retry_count = 100;
+  dap_swd_turnaround    = 1;
+  dap_swd_data_phase    = false;
+#ifdef DAP_CONFIG_ENABLE_JTAG
+  dap_jtag_dev_count = 0;
+#endif
+
+  dap_setup_clock(DAP_CONFIG_DEFAULT_CLOCK);
+
+  DAP_CONFIG_SETUP();
+}
+
+//-----------------------------------------------------------------------------
+bool dap_filter_request(uint8_t *req)
+{
+  int cmd = req[0];
+
+  if (ID_DAP_TRANSFER_ABORT == cmd)
+  {
+    dap_abort = true;
+    return false;
+  }
+
+  return true;
+}
+
+//-----------------------------------------------------------------------------
+int dap_process_request(uint8_t *req, int req_size, uint8_t *resp, int resp_size)
+{
+  static const struct
+  {
+    int    cmd;
+    void   (*handler)(void);
+  } handlers[] =
+  {
+    { ID_DAP_INFO,			dap_info },
+    { ID_DAP_HOST_STATUS,		dap_host_status },
+    { ID_DAP_CONNECT,			dap_connect },
+    { ID_DAP_DISCONNECT,		dap_disconnect },
+    { ID_DAP_TRANSFER_CONFIGURE,	dap_transfer_configure },
+    { ID_DAP_TRANSFER,			dap_transfer },
+    { ID_DAP_TRANSFER_BLOCK,		dap_transfer_block },
+    { ID_DAP_TRANSFER_ABORT,		dap_transfer_abort },
+    { ID_DAP_WRITE_ABORT,		dap_write_abort },
+    { ID_DAP_DELAY,			dap_delay },
+    { ID_DAP_RESET_TARGET,		dap_reset_target },
+    { ID_DAP_SWJ_PINS,			dap_swj_pins },
+    { ID_DAP_SWJ_CLOCK,			dap_swj_clock },
+    { ID_DAP_SWJ_SEQUENCE,		dap_swj_sequence },
+    { ID_DAP_SWD_CONFIGURE,		dap_swd_configure },
+    { ID_DAP_SWD_SEQUENCE,		dap_swd_sequence },
+    { ID_DAP_JTAG_SEQUENCE,		dap_jtag_sequence },
+    { ID_DAP_JTAG_CONFIGURE,		dap_jtag_configure },
+    { ID_DAP_JTAG_IDCODE,		dap_jtag_idcode },
+  };
+  int cmd;
+
+  dap_buf_init(req, req_size, resp, resp_size);
+
+  dap_abort = false;
+
+#ifdef DAP_CONFIG_ENABLE_JTAG
+  dap_jtag_ir = JTAG_INVALID;
+#endif
+
+  cmd = dap_req_get_byte();
+  dap_resp_add_byte(cmd);
+
+  for (int i = 0; i < ARRAY_SIZE(handlers); i++)
+  {
+    if (cmd == handlers[i].cmd)
+    {
+      handlers[i].handler();
+      return dap_resp_ptr;
+    }
+  }
+
+  if (ID_DAP_VENDOR_0 <= cmd && cmd <= ID_DAP_VENDOR_31)
+  {
+#ifdef DAP_CONFIG_VENDOR_FN
+    DAP_CONFIG_VENDOR_FN(cmd - ID_DAP_VENDOR_0);
+#else
+    dap_resp_add_byte(DAP_ERROR);
+#endif
+    return dap_resp_ptr;
+  }
+
+  dap_resp_set_byte(0, ID_DAP_INVALID);
+
+  return dap_resp_ptr;
+}
+
+//-----------------------------------------------------------------------------
+void dap_clock_test(int delay)
+{
+  DAP_CONFIG_CONNECT_SWD();
+
+  if (delay)
+  {
+    dap_clock_delay = delay;
+
+    while (1)
+      dap_swj_run_slow(1<<30);
+  }
+  else
+  {
+    while (1)
+      dap_swj_run_fast(1<<30);
+  }
+}

dap_link/lib/free-dap/dap.h

@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2016, Alex Taradov <alex@taradov.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _DAP_H_
+#define _DAP_H_
+
+/*- Includes ----------------------------------------------------------------*/
+#include <stdint.h>
+#include <stdbool.h>
+
+/*- Prototypes --------------------------------------------------------------*/
+void dap_init(void);
+uint8_t dap_req_get_byte(void);
+uint16_t dap_req_get_half(void);
+uint32_t dap_req_get_word(void);
+void dap_resp_add_byte(uint8_t value);
+void dap_resp_add_word(uint32_t value);
+void dap_resp_set_byte(int index, uint8_t value);
+bool dap_is_buf_error(void);
+bool dap_filter_request(uint8_t *req);
+int dap_process_request(uint8_t *req, int req_size, uint8_t *resp, int resp_size);
+void dap_clock_test(int delay);
+
+#endif // _DAP_H_
+

dap_link/lib/free-dap/hardware/d11-nano-dbg/.gitignore

@@ -0,0 +1,3 @@
+output/
+fp-info-cache
+

dap_link/lib/free-dap/hardware/d11-nano-dbg/d11-nano-dbg.kicad_pcb

@@ -0,0 +1,4933 @@
+(kicad_pcb (version 20211014) (generator pcbnew)
+
+  (general
+    (thickness 1.6)
+  )
+
+  (paper "User" 99.9998 99.9998)
+  (layers
+    (0 "F.Cu" signal)
+    (31 "B.Cu" signal)
+    (32 "B.Adhes" user "B.Adhesive")
+    (33 "F.Adhes" user "F.Adhesive")
+    (34 "B.Paste" user)
+    (35 "F.Paste" user)
+    (36 "B.SilkS" user "B.Silkscreen")
+    (37 "F.SilkS" user "F.Silkscreen")
+    (38 "B.Mask" user)
+    (39 "F.Mask" user)
+    (40 "Dwgs.User" user "User.Drawings")
+    (41 "Cmts.User" user "User.Comments")
+    (42 "Eco1.User" user "User.Eco1")
+    (43 "Eco2.User" user "User.Eco2")
+    (44 "Edge.Cuts" user)
+    (45 "Margin" user)
+    (46 "B.CrtYd" user "B.Courtyard")
+    (47 "F.CrtYd" user "F.Courtyard")
+    (48 "B.Fab" user)
+    (49 "F.Fab" user)
+    (50 "User.1" user)
+    (51 "User.2" user)
+    (52 "User.3" user)
+    (53 "User.4" user)
+    (54 "User.5" user)
+    (55 "User.6" user)
+    (56 "User.7" user)
+    (57 "User.8" user)
+    (58 "User.9" user)
+  )
+
+  (setup
+    (stackup
+      (layer "F.SilkS" (type "Top Silk Screen"))
+      (layer "F.Paste" (type "Top Solder Paste"))
+      (layer "F.Mask" (type "Top Solder Mask") (thickness 0.01))
+      (layer "F.Cu" (type "copper") (thickness 0.035))
+      (layer "dielectric 1" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
+      (layer "B.Cu" (type "copper") (thickness 0.035))
+      (layer "B.Mask" (type "Bottom Solder Mask") (thickness 0.01))
+      (layer "B.Paste" (type "Bottom Solder Paste"))
+      (layer "B.SilkS" (type "Bottom Silk Screen"))
+      (copper_finish "None")
+      (dielectric_constraints no)
+    )
+    (pad_to_mask_clearance 0)
+    (pcbplotparams
+      (layerselection 0x00010f0_ffffffff)
+      (disableapertmacros true)
+      (usegerberextensions true)
+      (usegerberattributes false)
+      (usegerberadvancedattributes false)
+      (creategerberjobfile false)
+      (svguseinch false)
+      (svgprecision 6)
+      (excludeedgelayer true)
+      (plotframeref false)
+      (viasonmask false)
+      (mode 1)
+      (useauxorigin false)
+      (hpglpennumber 1)
+      (hpglpenspeed 20)
+      (hpglpendiameter 15.000000)
+      (dxfpolygonmode true)
+      (dxfimperialunits true)
+      (dxfusepcbnewfont true)
+      (psnegative false)
+      (psa4output false)
+      (plotreference true)
+      (plotvalue true)
+      (plotinvisibletext false)
+      (sketchpadsonfab false)
+      (subtractmaskfromsilk true)
+      (outputformat 1)
+      (mirror false)
+      (drillshape 0)
+      (scaleselection 1)
+      (outputdirectory "output/")
+    )
+  )
+
+  (net 0 "")
+  (net 1 "+3V3")
+  (net 2 "VBUS")
+  (net 3 "/USB_DP")
+  (net 4 "/USB_DM")
+  (net 5 "/DBG_RESET")
+  (net 6 "/DBG_SWCLK")
+  (net 7 "/DBG_SWDIO")
+  (net 8 "/RESET")
+  (net 9 "unconnected-(IC2-Pad13)")
+  (net 10 "/DAP_STATUS")
+  (net 11 "GND")
+  (net 12 "Net-(LED1-Pad2)")
+  (net 13 "/SWDIO{slash}TMS")
+  (net 14 "/SWCLK{slash}TCK")
+  (net 15 "/TDI")
+  (net 16 "/TDO")
+  (net 17 "Net-(J1-PadCC1)")
+  (net 18 "Net-(J1-PadCC2)")
+  (net 19 "unconnected-(J1-PadSBU1)")
+  (net 20 "unconnected-(J1-PadSBU2)")
+  (net 21 "unconnected-(J2-Pad1)")
+  (net 22 "unconnected-(J2-Pad7)")
+
+  (footprint "ataradov_smd:0603" (layer "F.Cu")
+    (tedit 619DC0BD) (tstamp 32e1aed6-e06d-402f-b13b-cddeae58cd61)
+    (at 39.624 44.323)
+    (property "Sheetfile" "d11-nano-dbg.kicad_sch")
+    (property "Sheetname" "")
+    (path "/c594dcf2-f562-4ebf-9380-711463f31929")
+    (attr smd)
+    (fp_text reference "R3" (at 0 -1.905) (layer "F.SilkS")
+      (effects (font (size 1 1) (thickness 0.127)))
+      (tstamp a668461f-2467-4c7c-b09b-d27c45a5dab4)
+    )
+    (fp_text value "20K" (at 0 -0.016 unlocked) (layer "F.Fab")
+      (effects (font (size 0.5 0.5) (thickness 0.05)))
+      (tstamp 4362e285-ed61-4b80-8026-78eb23805bf7)
+    )
+    (fp_rect (start -1.55 -0.75) (end 1.55 0.75) (layer "F.SilkS") (width 0.127) (fill none) (tstamp ce03023a-ec3d-46b0-9a45-d078469826e8))
+    (pad "1" smd roundrect (at 0.8 0 90) (size 0.9 0.9) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+      (net 11 "GND") (pinfunction "1") (pintype "passive") (tstamp ae545ba3-9447-46ee-95c9-5c85b1932c57))
+    (pad "2" smd roundrect (at -0.8 0 90) (size 0.9 0.9) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+      (net 12 "Net-(LED1-Pad2)") (pinfunction "2") (pintype "passive") (tstamp 53c27afa-f7df-4f37-82a2-3dd3ba22a7ec))
+  )
+
+  (footprint "ataradov_conn:Header-5x2-1.27mm-SMD" (layer "F.Cu")
+    (tedit 61AE8C8C) (tstamp 7a194d1a-1282-4094-9dcc-620cb8f217b0)
+    (at 38.354 48.768 90)
+    (property "Sheetfile" "d11-nano-dbg.kicad_sch")
+    (property "Sheetname" "")
+    (path "/906df0a0-5839-47c0-b332-cec00bfc8d50")
+    (attr smd)
+    (fp_text reference "J2" (at 0 0 90) (layer "F.SilkS")
+      (effects (font (size 1 1) (thickness 0.127)))
+      (tstamp 6df354e5-0ed8-486f-aaba-922f1d8df851)
+    )
+    (fp_text value "Conn-5x2" (at 0 3.048 90) (layer "F.SilkS") hide
+      (effects (font (size 1 1) (thickness 0.127)))
+      (tstamp 70baef17-e834-4128-ab71-7a0e5bb0e8be)
+    )
+    (fp_line (start -3.175 -1.7) (end -3.175 1.7) (layer "F.SilkS") (width 0.127) (tstamp 29247d4e-2970-4492-af98-cbe5a7c43fda))
+    (fp_line (start -3.302 -0.0372) (end -3.302 1.6256) (layer "F.SilkS") (width 0.3) (tstamp 66d971b9-10a0-41f4-91b7-1d6842ea0b4d))
+    (fp_line (start 3.175 -1.7) (end 3.175 1.7) (layer "F.SilkS") (width 0.127) (tstamp 9e7cb52f-3bca-40b3-a79f-340d11cdb039))
+    (fp_line (start -3.175 -1.7) (end 3.175 -1.7) (layer "F.Fab") (width 0.127) (tstamp 75e89c98-f890-426a-8fa1-7783981e0a3c))
+    (fp_line (start -3.175 1.7) (end 3.175 1.7) (layer "F.Fab") (width 0.127) (tstamp ed9fa7f1-c410-42e5-9bc1-ad6bd344391f))
+    (pad "1" smd roundrect (at -2.54 1.95 90) (size 0.74 2.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+      (net 21 "unconnected-(J2-Pad1)") (pinfunction "1") (pintype "passive") (tstamp cb7a5af0-8d51-414d-8e4c-5f9db1141b2f))
+    (pad "2" smd roundrect (at -2.54 -1.95 90) (size 0.74 2.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+      (net 13 "/SWDIO{slash}TMS") (pinfunction "2") (pintype "passive") (tstamp 37fcecfd-ba35-4df5-a71d-0e7a66bc74fb))
+    (pad "3" smd roundrect (at -1.27 1.95 90) (size 0.74 2.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+      (net 11 "GND") (pinfunction "3") (pintype "passive") (tstamp 4c728ffb-f86b-4b12-90f5-72928eba4635))
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dap_link/lib/free-dap/hardware/d11-nano-dbg/d11-nano-dbg.kicad_prl

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dap_link/lib/free-dap/hardware/d11-nano-dbg/d11-nano-dbg.kicad_pro

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+}

dap_link/lib/free-dap/hardware/d11-nano-dbg/d11-nano-dbg.kicad_sch

@@ -0,0 +1,1673 @@
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+
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+  (title_block
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+    (rev "1")
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+
+  (symbol (lib_id "ataradov_pwr:VBUS") (at 123.19 54.61 0) (unit 1)
+    (in_bom yes) (on_board yes)
+    (uuid fdfdc927-8119-42ff-858e-0c98d51b2e84)
+    (property "Reference" "#PWR02" (id 0) (at 123.19 50.165 0)
+      (effects (font (size 1.27 1.27)) hide)
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+      (effects (font (size 1.27 1.27)) hide)
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+    (pin "1" (uuid d245a507-8a19-481d-a05d-417eb2477646))
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+  (sheet_instances
+    (path "/" (page "1"))
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+  (symbol_instances
+    (path "/65803744-5fc3-48eb-aeb5-74da1b7d8a05"
+      (reference "#FLG01") (unit 1) (value "PWR_FLAG") (footprint "")
+    )
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+      (reference "#FLG02") (unit 1) (value "PWR_FLAG") (footprint "")
+    )
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+      (reference "#PWR02") (unit 1) (value "VBUS") (footprint "")
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+      (reference "#PWR03") (unit 1) (value "+3V3") (footprint "")
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+      (reference "#PWR04") (unit 1) (value "VBUS") (footprint "")
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+    (path "/a4dc6caf-b167-4179-b6fc-f87da0aed1f2"
+      (reference "#PWR05") (unit 1) (value "GND") (footprint "")
+    )
+    (path "/739b591f-ee89-4e4b-a089-6321966edc77"
+      (reference "#PWR06") (unit 1) (value "GND") (footprint "")
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+    (path "/c860c4e9-3ddd-4065-857c-b9aedc01e6ad"
+      (reference "#PWR07") (unit 1) (value "GND") (footprint "")
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+      (reference "#PWR08") (unit 1) (value "GND") (footprint "")
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+    (path "/d2299eed-477d-40aa-a7fd-92b8ce1c4acf"
+      (reference "#PWR09") (unit 1) (value "GND") (footprint "")
+    )
+    (path "/05e9ef89-9155-44fd-8508-5e0c3fb064ae"
+      (reference "#PWR010") (unit 1) (value "GND") (footprint "")
+    )
+    (path "/dd61e408-7346-40a4-9cb9-99cd36090419"
+      (reference "#PWR011") (unit 1) (value "GND") (footprint "")
+    )
+    (path "/7e3716c6-bd4b-4b73-bf20-cfdce2a449e5"
+      (reference "#PWR012") (unit 1) (value "+3V3") (footprint "")
+    )
+    (path "/0757abbd-54c6-4c08-a50f-6bd1d1a846df"
+      (reference "#PWR013") (unit 1) (value "GND") (footprint "")
+    )
+    (path "/7374bcb7-15af-4d0f-999a-8281ae765e32"
+      (reference "#PWR015") (unit 1) (value "GND") (footprint "")
+    )
+    (path "/ec2382c6-f67b-4899-959e-d04de4aba0e2"
+      (reference "#PWR016") (unit 1) (value "GND") (footprint "")
+    )
+    (path "/e06501c8-2845-4054-9787-05ce88080176"
+      (reference "C1") (unit 1) (value "1uF") (footprint "ataradov_smd:0603")
+    )
+    (path "/03c058db-b9f4-404f-9c24-1f1dab858e28"
+      (reference "C2") (unit 1) (value "1uF") (footprint "ataradov_smd:0603")
+    )
+    (path "/e254f06c-00a2-4056-b804-b955996fa3d5"
+      (reference "IC1") (unit 1) (value "SC662K-3.3") (footprint "ataradov_ic:SOT-23")
+    )
+    (path "/e9485002-0b5c-4f78-8d49-67004f0e4d8e"
+      (reference "IC2") (unit 1) (value "ATSAMD11C") (footprint "ataradov_ic:SOIC-14")
+    )
+    (path "/9b533e2a-a396-4b85-abf3-b4e562338c74"
+      (reference "J1") (unit 1) (value "USB-C") (footprint "ataradov_conn:USB-C")
+    )
+    (path "/906df0a0-5839-47c0-b332-cec00bfc8d50"
+      (reference "J2") (unit 1) (value "Conn-5x2") (footprint "ataradov_conn:Header-5x2-1.27mm-SMD")
+    )
+    (path "/6bc6f722-72ae-42d6-be95-2b8bf65cd61e"
+      (reference "LED1") (unit 1) (value "Orange") (footprint "ataradov_smd:0603")
+    )
+    (path "/35477d2d-d398-4f18-becb-e7baa5331236"
+      (reference "R1") (unit 1) (value "5.1K") (footprint "ataradov_smd:0603")
+    )
+    (path "/6e18622d-ab16-46d3-8547-8e9d6c8c3481"
+      (reference "R2") (unit 1) (value "5.1K") (footprint "ataradov_smd:0603")
+    )
+    (path "/c594dcf2-f562-4ebf-9380-711463f31929"
+      (reference "R3") (unit 1) (value "20K") (footprint "ataradov_smd:0603")
+    )
+    (path "/bc214495-6305-49a3-bba3-3efe658c8dd7"
+      (reference "TP1") (unit 1) (value "SCK") (footprint "ataradov_misc:TestPoint-1.27mm-SMD")
+    )
+    (path "/6173c660-2127-4241-96b1-bfeb7449ff5f"
+      (reference "TP2") (unit 1) (value "RST") (footprint "ataradov_misc:TestPoint-1.27mm-SMD")
+    )
+    (path "/87a0447f-dae7-4542-8125-f968e31d4a91"
+      (reference "TP3") (unit 1) (value "SIO") (footprint "ataradov_misc:TestPoint-1.27mm-SMD")
+    )
+  )
+)

dap_link/lib/free-dap/hardware/d11-nano-dbg/pcb.kicad_wks

@@ -0,0 +1,5 @@
+(kicad_wks (version 20210606) (generator pl_editor)
+  (setup (textsize 1.5 1.5)(linewidth 0.15)(textlinewidth 0.15)
+  (left_margin 10)(right_margin 10)(top_margin 10)(bottom_margin 10))
+  (line (name "segm1:Line") (start 0 0) (end 0 0))
+)

dap_link/lib/free-dap/hardware/d11-nano-dbg/sch.kicad_wks

@@ -0,0 +1,15 @@
+(kicad_wks (version 20210606) (generator pl_editor)
+  (setup (textsize 1.5 1.5)(linewidth 0.15)(textlinewidth 0.15)
+  (left_margin 10)(right_margin 10)(top_margin 10)(bottom_margin 10))
+  (rect (name "") (start 0 0 ltcorner) (end 0 0) (repeat 2) (incrx 2) (incry 2))
+  (line (name "") (start 50 2 ltcorner) (end 50 0 ltcorner) (repeat 30) (incrx 50))
+  (tbtext "1" (name "") (pos 25 1 ltcorner) (font (size 1.3 1.3)) (repeat 100) (incrx 50))
+  (line (name "") (start 50 2 lbcorner) (end 50 0 lbcorner) (repeat 30) (incrx 50))
+  (tbtext "1" (name "") (pos 25 1 lbcorner) (font (size 1.3 1.3)) (repeat 100) (incrx 50))
+  (line (name "") (start 0 50 ltcorner) (end 2 50 ltcorner) (repeat 30) (incry 50))
+  (tbtext "A" (name "") (pos 1 25 ltcorner) (font (size 1.3 1.3)) (justify center) (repeat 100) (incry 50))
+  (line (name "") (start 0 50 rtcorner) (end 2 50 rtcorner) (repeat 30) (incry 50))
+  (tbtext "A" (name "") (pos 1 25 rtcorner) (font (size 1.3 1.3)) (justify center) (repeat 100) (incry 50))
+  (tbtext "${TITLE}${SHEETNAME} ${FILENAME}, rev ${REVISION} (${ISSUE_DATE}), page ${#} of ${##}" (name "") (pos 3 4) (justify right) (comment "Sheet id")
+)
+)

dap_link/lib/free-dap/hardware/d11_micro_std_vcp/d11_micro_std_vcp.brd

@@ -0,0 +1,700 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="7.3.0">
+<drawing>
+<settings>
+<setting alwaysvectorfont="no"/>
+<setting verticaltext="up"/>
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+<grid distance="0.01" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.025" altunitdist="inch" altunit="inch"/>
+<layers>
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+<layer number="92" name="Busses" color="1" fill="1" visible="no" active="no"/>
+<layer number="93" name="Pins" color="2" fill="1" visible="no" active="no"/>
+<layer number="94" name="Symbols" color="4" fill="1" visible="no" active="no"/>
+<layer number="95" name="Names" color="7" fill="1" visible="no" active="no"/>
+<layer number="96" name="Values" color="7" fill="1" visible="no" active="no"/>
+<layer number="97" name="Info" color="7" fill="1" visible="no" active="no"/>
+<layer number="98" name="Guide" color="6" fill="1" visible="no" active="no"/>
+</layers>
+<board>
+<plain>
+<wire x1="0" y1="0" x2="26.086" y2="0" width="0.1524" layer="20"/>
+<wire x1="26.086" y1="0" x2="26.086" y2="11.166" width="0.1524" layer="20"/>
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+<text x="19.05" y="10.414" size="0.762" layer="28" font="vector" rot="MR180" align="bottom-center">4/13/19</text>
+<text x="20.574" y="1.27" size="1.27" layer="27" font="vector" rot="R90" align="bottom-center">1</text>
+<text x="16.51" y="3.302" size="1.27" layer="28" font="vector" rot="MR270" align="bottom-center">AT</text>
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+<circle x="21.336" y="1.27" radius="0.254" width="0.508" layer="28"/>
+</plain>
+<libraries>
+<library name="ataradov_mcu">
+<description>Alex Taradov Library (MCUs)</description>
+<packages>
+<package name="SO-14">
+<description>SO-14</description>
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+<rectangle x1="1.0249" y1="2" x2="1.5151" y2="3.1001" layer="51"/>
+</package>
+</packages>
+</library>
+<library name="ataradov_conn">
+<description>Alex Taradov Library (Connectors)</description>
+<packages>
+<package name="HEADER-5X2-1.27MM">
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+</package>
+<package name="USB-B-MICRO-SMT-SHELL-TH">
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+<pad name="M2" x="2.15" y="3.6" drill="1.397"/>
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+<rectangle x1="4.1" y1="0.4" x2="5.55" y2="0.9" layer="29"/>
+<rectangle x1="4.1" y1="-0.25" x2="5.55" y2="0.25" layer="29"/>
+<rectangle x1="4.1" y1="-0.9" x2="5.55" y2="-0.4" layer="29"/>
+<rectangle x1="4.1" y1="-1.55" x2="5.55" y2="-1.05" layer="29"/>
+<wire x1="-0.5" y1="4" x2="-0.6" y2="3.8" width="0.1524" layer="21"/>
+<wire x1="-0.6" y1="3.8" x2="0" y2="3.5" width="0.1524" layer="21"/>
+<wire x1="0" y1="3.5" x2="0" y2="3.1" width="0.1524" layer="21"/>
+<wire x1="0" y1="3.1" x2="-0.6" y2="3.1" width="0.1524" layer="21"/>
+<wire x1="-0.6" y1="3.1" x2="-0.6" y2="-3.1" width="0.1524" layer="21"/>
+<wire x1="-0.6" y1="-3.1" x2="0" y2="-3.1" width="0.1524" layer="21"/>
+<wire x1="0" y1="-3.1" x2="0" y2="-3.5" width="0.1524" layer="21"/>
+<wire x1="0" y1="-3.5" x2="-0.6" y2="-3.8" width="0.1524" layer="21"/>
+<wire x1="-0.6" y1="-3.8" x2="-0.5" y2="-4" width="0.1524" layer="21"/>
+<wire x1="-0.5" y1="-4" x2="0" y2="-3.75" width="0.1524" layer="21"/>
+<wire x1="0" y1="-3.75" x2="5" y2="-3.75" width="0.1524" layer="21"/>
+<wire x1="5" y1="-3.75" x2="5" y2="-3.16" width="0.1524" layer="21"/>
+<wire x1="-0.5" y1="4" x2="0" y2="3.75" width="0.1524" layer="21"/>
+<wire x1="0" y1="3.75" x2="5" y2="3.75" width="0.1524" layer="21"/>
+<wire x1="5" y1="3.75" x2="5" y2="3.16" width="0.1524" layer="21"/>
+</package>
+<package name="PIN-TH">
+<wire x1="-0.635" y1="1.27" x2="0.635" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="0.635" y1="1.27" x2="1.27" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="1.27" y1="0.635" x2="1.27" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="1.27" y1="-0.635" x2="0.635" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-1.27" y1="0.635" x2="-1.27" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-0.635" y1="1.27" x2="-1.27" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-1.27" y1="-0.635" x2="-0.635" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="0.635" y1="-1.27" x2="-0.635" y2="-1.27" width="0.1524" layer="21"/>
+<rectangle x1="-0.254" y1="-0.254" x2="0.254" y2="0.254" layer="51"/>
+<pad name="1" x="0" y="0" drill="1.016" shape="octagon"/>
+<text x="0" y="1.524" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-2.794" size="1.27" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+</packages>
+</library>
+<library name="ataradov_rlc">
+<description>Alex Taradov Library (R, L and C)</description>
+<packages>
+<package name="SMD0603">
+<wire x1="-1.5" y1="0.75" x2="1.5" y2="0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="0.75" x2="1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="-0.75" x2="-1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="-1.5" y1="-0.75" x2="-1.5" y2="0.75" width="0.1" layer="21"/>
+<smd name="1" x="-0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<smd name="2" x="0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SMD0603-X4">
+<smd name="1" x="-1.2" y="-0.625" dx="0.5" dy="0.65" layer="1"/>
+<smd name="2" x="-0.4" y="-0.625" dx="0.5" dy="0.65" layer="1"/>
+<smd name="3" x="0.4" y="-0.625" dx="0.5" dy="0.65" layer="1"/>
+<smd name="4" x="1.2" y="-0.625" dx="0.5" dy="0.65" layer="1"/>
+<smd name="5" x="1.2" y="0.625" dx="0.5" dy="0.65" layer="1"/>
+<smd name="6" x="0.4" y="0.625" dx="0.5" dy="0.65" layer="1"/>
+<smd name="7" x="-0.4" y="0.625" dx="0.5" dy="0.65" layer="1"/>
+<smd name="8" x="-1.2" y="0.625" dx="0.5" dy="0.65" layer="1"/>
+<text x="0" y="1.524" size="1.27" layer="25" font="vector" ratio="10" align="bottom-center">&gt;NAME</text>
+<wire x1="1.778" y1="1.258" x2="1.778" y2="-1.258" width="0.1016" layer="21"/>
+<wire x1="-1.778" y1="1.258" x2="-1.778" y2="-1.258" width="0.1016" layer="21"/>
+<wire x1="-1.766" y1="1.27" x2="1.766" y2="1.27" width="0.1016" layer="21"/>
+<wire x1="-1.766" y1="-1.27" x2="1.766" y2="-1.27" width="0.1016" layer="21"/>
+</package>
+</packages>
+</library>
+<library name="ataradov_vreg">
+<description>Alex Taradov Library (Voltage Regulators)</description>
+<packages>
+<package name="SOT23-5">
+<description>SOT23-5</description>
+<wire x1="1.422" y1="0.81" x2="1.422" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="1.422" y1="-0.81" x2="-1.422" y2="-0.81" width="0.1524" layer="51"/>
+<wire x1="-1.422" y1="-0.81" x2="-1.422" y2="0.81" width="0.1524" layer="21"/>
+<wire x1="-1.422" y1="0.81" x2="1.422" y2="0.81" width="0.1524" layer="51"/>
+<wire x1="-0.522" y1="0.81" x2="0.522" y2="0.81" width="0.1524" layer="21"/>
+<wire x1="-0.428" y1="-0.81" x2="-0.522" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="0.522" y1="-0.81" x2="0.428" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="-1.328" y1="-0.81" x2="-1.422" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="1.422" y1="-0.81" x2="1.328" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="1.328" y1="0.81" x2="1.422" y2="0.81" width="0.1524" layer="21"/>
+<wire x1="-1.422" y1="0.81" x2="-1.328" y2="0.81" width="0.1524" layer="21"/>
+<smd name="1" x="-0.95" y="-1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="2" x="0" y="-1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="3" x="0.95" y="-1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="4" x="0.95" y="1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="5" x="-0.95" y="1.3" dx="0.55" dy="1.2" layer="1"/>
+<text x="0" y="2.286" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-3.556" size="1.27" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+<rectangle x1="-1.2" y1="-1.5" x2="-0.7" y2="-0.85" layer="51"/>
+<rectangle x1="-0.25" y1="-1.5" x2="0.25" y2="-0.85" layer="51"/>
+<rectangle x1="0.7" y1="-1.5" x2="1.2" y2="-0.85" layer="51"/>
+<rectangle x1="0.7" y1="0.85" x2="1.2" y2="1.5" layer="51"/>
+<rectangle x1="-1.2" y1="0.85" x2="-0.7" y2="1.5" layer="51"/>
+</package>
+</packages>
+</library>
+<library name="ataradov_misc">
+<description>Alex Taradov Library (Miscellaneous stuff)</description>
+<packages>
+<package name="TP-1.27MM">
+<smd name="1" x="0" y="0" dx="1.27" dy="1.27" layer="1" roundness="100" cream="no"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+</packages>
+</library>
+<library name="ataradov_led">
+<description>Alex Taradov Library (LEDs and other indication devices)</description>
+<packages>
+<package name="SMD0603">
+<wire x1="-1.5" y1="0.75" x2="1.5" y2="0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="0.75" x2="1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="-0.75" x2="-1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="-1.5" y1="-0.75" x2="-1.5" y2="0.75" width="0.1" layer="21"/>
+<smd name="1" x="-0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<smd name="2" x="0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+</packages>
+</library>
+</libraries>
+<attributes>
+</attributes>
+<variantdefs>
+</variantdefs>
+<classes>
+<class number="0" name="default" width="0" drill="0">
+</class>
+</classes>
+<designrules name="OSHPark *">
+<description language="de">&lt;b&gt;EAGLE Design Rules&lt;/b&gt;
+&lt;p&gt;
+Die Standard-Design-Rules sind so gewählt, dass sie für 
+die meisten Anwendungen passen. Sollte ihre Platine 
+besondere Anforderungen haben, treffen Sie die erforderlichen
+Einstellungen hier und speichern die Design Rules unter 
+einem neuen Namen ab.</description>
+<description language="en">&lt;b&gt;Laen's PCB Order Design Rules&lt;/b&gt;
+&lt;p&gt;
+Please make sure your boards conform to these design rules.</description>
+<param name="layerSetup" value="(1*16)"/>
+<param name="mtCopper" value="0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm"/>
+<param name="mtIsolate" value="1.5011mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm"/>
+<param name="mdWireWire" value="6mil"/>
+<param name="mdWirePad" value="6mil"/>
+<param name="mdWireVia" value="6mil"/>
+<param name="mdPadPad" value="6mil"/>
+<param name="mdPadVia" value="6mil"/>
+<param name="mdViaVia" value="6mil"/>
+<param name="mdSmdPad" value="6mil"/>
+<param name="mdSmdVia" value="6mil"/>
+<param name="mdSmdSmd" value="6mil"/>
+<param name="mdViaViaSameLayer" value="8mil"/>
+<param name="mnLayersViaInSmd" value="2"/>
+<param name="mdCopperDimension" value="15mil"/>
+<param name="mdDrill" value="6mil"/>
+<param name="mdSmdStop" value="0mil"/>
+<param name="msWidth" value="6mil"/>
+<param name="msDrill" value="13mil"/>
+<param name="msMicroVia" value="13mil"/>
+<param name="msBlindViaRatio" value="0.5"/>
+<param name="rvPadTop" value="0.25"/>
+<param name="rvPadInner" value="0.25"/>
+<param name="rvPadBottom" value="0.25"/>
+<param name="rvViaOuter" value="0.25"/>
+<param name="rvViaInner" value="0.25"/>
+<param name="rvMicroViaOuter" value="0.25"/>
+<param name="rvMicroViaInner" value="0.25"/>
+<param name="rlMinPadTop" value="7mil"/>
+<param name="rlMaxPadTop" value="20mil"/>
+<param name="rlMinPadInner" value="7mil"/>
+<param name="rlMaxPadInner" value="20mil"/>
+<param name="rlMinPadBottom" value="7mil"/>
+<param name="rlMaxPadBottom" value="20mil"/>
+<param name="rlMinViaOuter" value="7mil"/>
+<param name="rlMaxViaOuter" value="20mil"/>
+<param name="rlMinViaInner" value="7mil"/>
+<param name="rlMaxViaInner" value="20mil"/>
+<param name="rlMinMicroViaOuter" value="4mil"/>
+<param name="rlMaxMicroViaOuter" value="20mil"/>
+<param name="rlMinMicroViaInner" value="4mil"/>
+<param name="rlMaxMicroViaInner" value="20mil"/>
+<param name="psTop" value="-1"/>
+<param name="psBottom" value="-1"/>
+<param name="psFirst" value="-1"/>
+<param name="psElongationLong" value="100"/>
+<param name="psElongationOffset" value="100"/>
+<param name="mvStopFrame" value="1"/>
+<param name="mvCreamFrame" value="0"/>
+<param name="mlMinStopFrame" value="3mil"/>
+<param name="mlMaxStopFrame" value="3mil"/>
+<param name="mlMinCreamFrame" value="0mil"/>
+<param name="mlMaxCreamFrame" value="0mil"/>
+<param name="mlViaStopLimit" value="100mil"/>
+<param name="srRoundness" value="0"/>
+<param name="srMinRoundness" value="0mil"/>
+<param name="srMaxRoundness" value="0mil"/>
+<param name="slThermalIsolate" value="10mil"/>
+<param name="slThermalsForVias" value="0"/>
+<param name="dpMaxLengthDifference" value="10mm"/>
+<param name="dpGapFactor" value="2.5"/>
+<param name="checkGrid" value="0"/>
+<param name="checkAngle" value="0"/>
+<param name="checkFont" value="1"/>
+<param name="checkRestrict" value="1"/>
+<param name="useDiameter" value="13"/>
+<param name="maxErrors" value="50"/>
+</designrules>
+<autorouter>
+<pass name="Default">
+<param name="RoutingGrid" value="50mil"/>
+<param name="AutoGrid" value="1"/>
+<param name="Efforts" value="0"/>
+<param name="TopRouterVariant" value="1"/>
+<param name="tpViaShape" value="round"/>
+<param name="PrefDir.1" value="a"/>
+<param name="PrefDir.2" value="0"/>
+<param name="PrefDir.3" value="0"/>
+<param name="PrefDir.4" value="0"/>
+<param name="PrefDir.5" value="0"/>
+<param name="PrefDir.6" value="0"/>
+<param name="PrefDir.7" value="0"/>
+<param name="PrefDir.8" value="0"/>
+<param name="PrefDir.9" value="0"/>
+<param name="PrefDir.10" value="0"/>
+<param name="PrefDir.11" value="0"/>
+<param name="PrefDir.12" value="0"/>
+<param name="PrefDir.13" value="0"/>
+<param name="PrefDir.14" value="0"/>
+<param name="PrefDir.15" value="0"/>
+<param name="PrefDir.16" value="a"/>
+<param name="cfVia" value="8"/>
+<param name="cfNonPref" value="5"/>
+<param name="cfChangeDir" value="2"/>
+<param name="cfOrthStep" value="2"/>
+<param name="cfDiagStep" value="3"/>
+<param name="cfExtdStep" value="0"/>
+<param name="cfBonusStep" value="1"/>
+<param name="cfMalusStep" value="1"/>
+<param name="cfPadImpact" value="4"/>
+<param name="cfSmdImpact" value="4"/>
+<param name="cfBusImpact" value="0"/>
+<param name="cfHugging" value="3"/>
+<param name="cfAvoid" value="4"/>
+<param name="cfPolygon" value="10"/>
+<param name="cfBase.1" value="0"/>
+<param name="cfBase.2" value="1"/>
+<param name="cfBase.3" value="1"/>
+<param name="cfBase.4" value="1"/>
+<param name="cfBase.5" value="1"/>
+<param name="cfBase.6" value="1"/>
+<param name="cfBase.7" value="1"/>
+<param name="cfBase.8" value="1"/>
+<param name="cfBase.9" value="1"/>
+<param name="cfBase.10" value="1"/>
+<param name="cfBase.11" value="1"/>
+<param name="cfBase.12" value="1"/>
+<param name="cfBase.13" value="1"/>
+<param name="cfBase.14" value="1"/>
+<param name="cfBase.15" value="1"/>
+<param name="cfBase.16" value="0"/>
+<param name="mnVias" value="20"/>
+<param name="mnSegments" value="9999"/>
+<param name="mnExtdSteps" value="9999"/>
+<param name="mnRipupLevel" value="10"/>
+<param name="mnRipupSteps" value="100"/>
+<param name="mnRipupTotal" value="100"/>
+</pass>
+<pass name="Follow-me" refer="Default" active="yes">
+</pass>
+<pass name="Busses" refer="Default" active="yes">
+<param name="cfNonPref" value="4"/>
+<param name="cfBusImpact" value="4"/>
+<param name="cfHugging" value="0"/>
+<param name="mnVias" value="0"/>
+</pass>
+<pass name="Route" refer="Default" active="yes">
+</pass>
+<pass name="Optimize1" refer="Default" active="yes">
+<param name="cfVia" value="99"/>
+<param name="cfExtdStep" value="10"/>
+<param name="cfHugging" value="1"/>
+<param name="mnExtdSteps" value="1"/>
+<param name="mnRipupLevel" value="0"/>
+</pass>
+<pass name="Optimize2" refer="Optimize1" active="yes">
+<param name="cfNonPref" value="0"/>
+<param name="cfChangeDir" value="6"/>
+<param name="cfExtdStep" value="0"/>
+<param name="cfBonusStep" value="2"/>
+<param name="cfMalusStep" value="2"/>
+<param name="cfPadImpact" value="2"/>
+<param name="cfSmdImpact" value="2"/>
+<param name="cfHugging" value="0"/>
+</pass>
+<pass name="Optimize3" refer="Optimize2" active="yes">
+<param name="cfChangeDir" value="8"/>
+<param name="cfPadImpact" value="0"/>
+<param name="cfSmdImpact" value="0"/>
+</pass>
+<pass name="Optimize4" refer="Optimize3" active="yes">
+<param name="cfChangeDir" value="25"/>
+</pass>
+</autorouter>
+<elements>
+<element name="IC2" library="ataradov_mcu" package="SO-14" value="ATSAMD11C" x="10.414" y="6.35" smashed="yes" rot="MR270">
+<attribute name="NAME" x="10.414" y="11.176" size="1.27" layer="26" font="vector" rot="MR0" align="bottom-center"/>
+</element>
+<element name="C1" library="ataradov_rlc" package="SMD0603" value="1uF" x="15.494" y="8.636" rot="R90"/>
+<element name="C2" library="ataradov_rlc" package="SMD0603" value="1uF" x="8.128" y="8.636" smashed="yes" rot="R270">
+<attribute name="NAME" x="9.144" y="8.636" size="1.27" layer="25" font="vector" rot="R270" align="bottom-center"/>
+</element>
+<element name="IC1" library="ataradov_vreg" package="SOT23-5" value="MIC5504-3.3" x="11.938" y="8.636" smashed="yes" rot="R90">
+<attribute name="NAME" x="9.652" y="8.636" size="1.27" layer="25" font="vector" rot="R90" align="bottom-center"/>
+</element>
+<element name="TP1" library="ataradov_misc" package="TP-1.27MM" value="SIO" x="7.874" y="1.524" rot="MR0"/>
+<element name="TP2" library="ataradov_misc" package="TP-1.27MM" value="" x="12.954" y="1.524" rot="MR0"/>
+<element name="TP3" library="ataradov_misc" package="TP-1.27MM" value="" x="10.414" y="1.524" rot="MR0"/>
+<element name="TP4" library="ataradov_misc" package="TP-1.27MM" value="" x="5.334" y="1.524" rot="MR0"/>
+<element name="J1" library="ataradov_conn" package="HEADER-5X2-1.27MM" value="HEADER-5X2-TH-1.27" x="19.304" y="5.588" rot="R90"/>
+<element name="J2" library="ataradov_conn" package="USB-B-MICRO-SMT-SHELL-TH" value="" x="0" y="5.588"/>
+<element name="R1" library="ataradov_rlc" package="SMD0603" value="470" x="9.398" y="3.048" rot="R270"/>
+<element name="LED1" library="ataradov_led" package="SMD0603" value="" x="7.366" y="3.048" rot="R90"/>
+<element name="R2" library="ataradov_rlc" package="SMD0603" value="470" x="11.43" y="3.048" rot="R270"/>
+<element name="LED2" library="ataradov_led" package="SMD0603" value="" x="13.462" y="3.048" rot="R90"/>
+<element name="J3" library="ataradov_conn" package="PIN-TH" value="RX" x="22.606" y="8.128" smashed="yes" rot="R90">
+<attribute name="NAME" x="21.082" y="8.128" size="1.27" layer="25" font="vector" rot="R90" align="bottom-center"/>
+<attribute name="VALUE" x="25.654" y="8.89" size="1.27" layer="27" font="vector" rot="R90" align="bottom-center"/>
+</element>
+<element name="J4" library="ataradov_conn" package="PIN-TH" value="TX" x="22.606" y="5.588" smashed="yes" rot="R90">
+<attribute name="NAME" x="21.082" y="5.588" size="1.27" layer="25" font="vector" rot="R90" align="bottom-center"/>
+<attribute name="VALUE" x="25.654" y="5.588" size="1.27" layer="27" font="vector" rot="R90" align="bottom-center"/>
+</element>
+<element name="J5" library="ataradov_conn" package="PIN-TH" value="GND" x="22.606" y="3.048" smashed="yes" rot="R90">
+<attribute name="NAME" x="21.082" y="3.048" size="1.27" layer="25" font="vector" rot="R90" align="bottom-center"/>
+<attribute name="VALUE" x="25.654" y="2.286" size="1.27" layer="27" font="vector" rot="R90" align="bottom-center"/>
+</element>
+<element name="RN1" library="ataradov_rlc" package="SMD0603-X4" value="100" x="15.748" y="6.858" rot="MR90"/>
+</elements>
+<signals>
+<signal name="GND">
+<contactref element="IC1" pad="2"/>
+<contactref element="C1" pad="1"/>
+<contactref element="C2" pad="1"/>
+<contactref element="IC2" pad="11"/>
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+</signal>
+<signal name="V_USB">
+<contactref element="IC1" pad="3"/>
+<contactref element="IC1" pad="1"/>
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+</signal>
+<signal name="SWDIO">
+<contactref element="IC2" pad="8"/>
+<contactref element="TP1" pad="1"/>
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+</signal>
+<signal name="PA02">
+<contactref element="IC2" pad="13"/>
+<contactref element="R1" pad="1"/>
+<via x="10.16" y="4.826" extent="1-16" drill="0.508" diameter="0.508"/>
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+</signal>
+<signal name="PA04">
+<contactref element="IC2" pad="14"/>
+<contactref element="R2" pad="1"/>
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+</signal>
+<signal name="SWCLK">
+<contactref element="IC2" pad="7"/>
+<contactref element="TP2" pad="1"/>
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+</signal>
+<signal name="RESET">
+<contactref element="IC2" pad="6"/>
+<contactref element="TP3" pad="1"/>
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+</signal>
+<signal name="N$8">
+</signal>
+<signal name="T_SWDIO">
+<contactref element="J1" pad="2"/>
+<contactref element="RN1" pad="8"/>
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+<wire x1="16.373" y1="3.947" x2="16.373" y2="5.658" width="0.254" layer="16"/>
+</signal>
+<signal name="T_SWCLK">
+<contactref element="J1" pad="4"/>
+<contactref element="RN1" pad="7"/>
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+</signal>
+<signal name="T_RESET">
+<contactref element="J1" pad="10"/>
+<contactref element="RN1" pad="6"/>
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+</signal>
+<signal name="PA14">
+<contactref element="IC2" pad="4"/>
+<contactref element="RN1" pad="2"/>
+<wire x1="13.014" y1="6.35" x2="13.122" y2="6.458" width="0.254" layer="16"/>
+<wire x1="13.122" y1="6.458" x2="15.123" y2="6.458" width="0.254" layer="16"/>
+</signal>
+<signal name="PA15">
+<contactref element="IC2" pad="5"/>
+<contactref element="RN1" pad="1"/>
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+</signal>
+<signal name="PA09">
+<contactref element="IC2" pad="3"/>
+<contactref element="RN1" pad="3"/>
+<wire x1="13.014" y1="7.62" x2="14.224" y2="7.62" width="0.254" layer="16"/>
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+</signal>
+<signal name="PA08">
+<contactref element="IC2" pad="2"/>
+<contactref element="RN1" pad="4"/>
+<wire x1="13.014" y1="8.89" x2="14.732" y2="8.89" width="0.254" layer="16"/>
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+<wire x1="15.123" y1="8.499" x2="15.123" y2="8.058" width="0.254" layer="16"/>
+</signal>
+<signal name="N$4">
+<contactref element="R1" pad="2"/>
+<contactref element="LED1" pad="1"/>
+<wire x1="7.366" y1="2.248" x2="9.398" y2="2.248" width="0.254" layer="1"/>
+</signal>
+<signal name="N$6">
+<contactref element="R2" pad="2"/>
+<contactref element="LED2" pad="1"/>
+<wire x1="11.43" y1="2.248" x2="13.462" y2="2.248" width="0.254" layer="1"/>
+</signal>
+<signal name="UART_TX">
+<contactref element="J4" pad="1"/>
+<contactref element="RN1" pad="5"/>
+<wire x1="22.606" y1="5.588" x2="21.336" y2="6.858" width="0.254" layer="16"/>
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+<wire x1="16.51" y1="8.195" x2="16.373" y2="8.058" width="0.254" layer="16"/>
+</signal>
+<signal name="N$11">
+</signal>
+<signal name="UART_RX">
+<contactref element="J3" pad="1"/>
+<contactref element="IC2" pad="1"/>
+<wire x1="13.014" y1="10.16" x2="21.082" y2="10.16" width="0.254" layer="16"/>
+<wire x1="21.082" y1="10.16" x2="22.606" y2="8.636" width="0.254" layer="16"/>
+<wire x1="22.606" y1="8.636" x2="22.606" y2="8.128" width="0.254" layer="16"/>
+</signal>
+</signals>
+</board>
+</drawing>
+</eagle>

dap_link/lib/free-dap/hardware/d11_micro_std_vcp/d11_micro_std_vcp.sch

@@ -0,0 +1,1314 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="7.3.0">
+<drawing>
+<settings>
+<setting alwaysvectorfont="no"/>
+<setting verticaltext="up"/>
+</settings>
+<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>
+<layers>
+<layer number="1" name="Top" color="4" fill="1" visible="no" active="no"/>
+<layer number="16" name="Bottom" color="1" fill="1" visible="no" active="no"/>
+<layer number="17" name="Pads" color="2" fill="1" visible="no" active="no"/>
+<layer number="18" name="Vias" color="2" fill="1" visible="no" active="no"/>
+<layer number="19" name="Unrouted" color="6" fill="1" visible="no" active="no"/>
+<layer number="20" name="Dimension" color="15" fill="1" visible="no" active="no"/>
+<layer number="21" name="tPlace" color="7" fill="1" visible="no" active="no"/>
+<layer number="22" name="bPlace" color="7" fill="1" visible="no" active="no"/>
+<layer number="23" name="tOrigins" color="15" fill="1" visible="no" active="no"/>
+<layer number="24" name="bOrigins" color="15" fill="1" visible="no" active="no"/>
+<layer number="25" name="tNames" color="7" fill="1" visible="no" active="no"/>
+<layer number="26" name="bNames" color="7" fill="1" visible="no" active="no"/>
+<layer number="27" name="tValues" color="7" fill="1" visible="no" active="no"/>
+<layer number="28" name="bValues" color="7" fill="1" visible="no" active="no"/>
+<layer number="29" name="tStop" color="7" fill="3" visible="no" active="no"/>
+<layer number="30" name="bStop" color="7" fill="6" visible="no" active="no"/>
+<layer number="31" name="tCream" color="7" fill="4" visible="no" active="no"/>
+<layer number="32" name="bCream" color="7" fill="5" visible="no" active="no"/>
+<layer number="33" name="tFinish" color="6" fill="3" visible="no" active="no"/>
+<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="no"/>
+<layer number="35" name="tGlue" color="7" fill="4" visible="no" active="no"/>
+<layer number="36" name="bGlue" color="7" fill="5" visible="no" active="no"/>
+<layer number="37" name="tTest" color="7" fill="1" visible="no" active="no"/>
+<layer number="38" name="bTest" color="7" fill="1" visible="no" active="no"/>
+<layer number="39" name="tKeepout" color="4" fill="11" visible="no" active="no"/>
+<layer number="40" name="bKeepout" color="1" fill="11" visible="no" active="no"/>
+<layer number="41" name="tRestrict" color="4" fill="10" visible="no" active="no"/>
+<layer number="42" name="bRestrict" color="1" fill="10" visible="no" active="no"/>
+<layer number="43" name="vRestrict" color="2" fill="10" visible="no" active="no"/>
+<layer number="44" name="Drills" color="7" fill="1" visible="no" active="no"/>
+<layer number="45" name="Holes" color="7" fill="1" visible="no" active="no"/>
+<layer number="46" name="Milling" color="3" fill="1" visible="no" active="no"/>
+<layer number="47" name="Measures" color="7" fill="1" visible="no" active="no"/>
+<layer number="48" name="Document" color="7" fill="1" visible="no" active="no"/>
+<layer number="49" name="Reference" color="7" fill="1" visible="no" active="no"/>
+<layer number="51" name="tDocu" color="6" fill="1" visible="no" active="no"/>
+<layer number="52" name="bDocu" color="7" fill="1" visible="no" active="no"/>
+<layer number="90" name="Modules" color="5" fill="1" visible="yes" active="yes"/>
+<layer number="91" name="Nets" color="2" fill="1" visible="yes" active="yes"/>
+<layer number="92" name="Busses" color="1" fill="1" visible="yes" active="yes"/>
+<layer number="93" name="Pins" color="2" fill="1" visible="no" active="yes"/>
+<layer number="94" name="Symbols" color="4" fill="1" visible="yes" active="yes"/>
+<layer number="95" name="Names" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="96" name="Values" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="97" name="Info" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/>
+</layers>
+<schematic xreflabel="%F%N/%S.%C%R" xrefpart="/%S.%C%R">
+<libraries>
+<library name="ataradov_mcu">
+<description>Alex Taradov Library (MCUs)</description>
+<packages>
+<package name="SO-14">
+<description>SO-14</description>
+<wire x1="4.305" y1="-1.9" x2="-4.305" y2="-1.9" width="0.2032" layer="51"/>
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+<smd name="8" x="3.81" y="2.6" dx="0.6" dy="2.2" layer="1"/>
+<text x="-4.826" y="0" size="1.27" layer="25" font="vector" rot="R90" align="bottom-center">&gt;NAME</text>
+<text x="6.096" y="0" size="1.27" layer="27" font="vector" rot="R90" align="bottom-center">&gt;VALUE</text>
+<rectangle x1="-4.0551" y1="-3.1001" x2="-3.5649" y2="-2" layer="51"/>
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+<rectangle x1="-1.5151" y1="-3.1001" x2="-1.0249" y2="-2" layer="51"/>
+<rectangle x1="-0.2451" y1="-3.1001" x2="0.2451" y2="-2" layer="51"/>
+<rectangle x1="-0.2451" y1="2" x2="0.2451" y2="3.1001" layer="51"/>
+<rectangle x1="-1.5151" y1="2" x2="-1.0249" y2="3.1001" layer="51"/>
+<rectangle x1="-2.7851" y1="2" x2="-2.2949" y2="3.1001" layer="51"/>
+<rectangle x1="-4.0551" y1="2" x2="-3.5649" y2="3.1001" layer="51"/>
+<rectangle x1="1.0249" y1="-3.1001" x2="1.5151" y2="-2" layer="51"/>
+<rectangle x1="2.2949" y1="-3.1001" x2="2.7851" y2="-2" layer="51"/>
+<rectangle x1="3.5649" y1="-3.1001" x2="4.0551" y2="-2" layer="51"/>
+<rectangle x1="3.5649" y1="2" x2="4.0551" y2="3.1001" layer="51"/>
+<rectangle x1="2.2949" y1="2" x2="2.7851" y2="3.1001" layer="51"/>
+<rectangle x1="1.0249" y1="2" x2="1.5151" y2="3.1001" layer="51"/>
+</package>
+</packages>
+<symbols>
+<symbol name="ATSAMDXXC">
+<description>Atmel SAM D09C/D10C/D11C Cortex-M0+ microcontroller</description>
+<wire x1="-12.7" y1="10.16" x2="12.7" y2="10.16" width="0.254" layer="94"/>
+<wire x1="12.7" y1="10.16" x2="12.7" y2="-10.16" width="0.254" layer="94"/>
+<wire x1="12.7" y1="-10.16" x2="-12.7" y2="-10.16" width="0.254" layer="94"/>
+<wire x1="-12.7" y1="-10.16" x2="-12.7" y2="10.16" width="0.254" layer="94"/>
+<pin name="PA28/RST" x="-17.78" y="-5.08" length="middle"/>
+<pin name="PA8" x="-17.78" y="5.08" length="middle"/>
+<pin name="PA9" x="-17.78" y="2.54" length="middle"/>
+<pin name="PA14" x="-17.78" y="0" length="middle"/>
+<pin name="PA15" x="-17.78" y="-2.54" length="middle"/>
+<pin name="PA5" x="-17.78" y="7.62" length="middle"/>
+<pin name="PA04" x="17.78" y="7.62" length="middle" rot="R180"/>
+<pin name="PA02" x="17.78" y="5.08" length="middle" rot="R180"/>
+<text x="0" y="10.922" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-12.192" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+<pin name="PA30/SCK" x="-17.78" y="-7.62" length="middle"/>
+<pin name="VDD" x="17.78" y="2.54" length="middle" rot="R180"/>
+<pin name="GND" x="17.78" y="0" length="middle" rot="R180"/>
+<pin name="PA25" x="17.78" y="-2.54" length="middle" rot="R180"/>
+<pin name="PA24" x="17.78" y="-5.08" length="middle" rot="R180"/>
+<pin name="PA31/SIO" x="17.78" y="-7.62" length="middle" rot="R180"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="ATSAMD11C" prefix="IC">
+<gates>
+<gate name="G$1" symbol="ATSAMDXXC" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="SO-14">
+<connects>
+<connect gate="G$1" pin="GND" pad="11"/>
+<connect gate="G$1" pin="PA02" pad="13"/>
+<connect gate="G$1" pin="PA04" pad="14"/>
+<connect gate="G$1" pin="PA14" pad="4"/>
+<connect gate="G$1" pin="PA15" pad="5"/>
+<connect gate="G$1" pin="PA24" pad="9"/>
+<connect gate="G$1" pin="PA25" pad="10"/>
+<connect gate="G$1" pin="PA28/RST" pad="6"/>
+<connect gate="G$1" pin="PA30/SCK" pad="7"/>
+<connect gate="G$1" pin="PA31/SIO" pad="8"/>
+<connect gate="G$1" pin="PA5" pad="1"/>
+<connect gate="G$1" pin="PA8" pad="2"/>
+<connect gate="G$1" pin="PA9" pad="3"/>
+<connect gate="G$1" pin="VDD" pad="12"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_pwr">
+<description>Alex Taradov Library (Power Symbols)</description>
+<packages>
+</packages>
+<symbols>
+<symbol name="+3V3">
+<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/>
+<text x="0" y="0.762" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+<pin name="+3V3" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/>
+</symbol>
+<symbol name="GND">
+<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/>
+<text x="0" y="-2.032" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+<pin name="GND" x="0" y="2.54" visible="off" length="short" direction="sup" rot="R270"/>
+</symbol>
+<symbol name="V_USB">
+<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/>
+<text x="0" y="0.762" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+<pin name="V_USB" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="+3V3" prefix="P_">
+<gates>
+<gate name="1" symbol="+3V3" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="GND" prefix="P_">
+<gates>
+<gate name="1" symbol="GND" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="V_USB" prefix="P_">
+<gates>
+<gate name="1" symbol="V_USB" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_conn">
+<description>Alex Taradov Library (Connectors)</description>
+<packages>
+<package name="HEADER-5X2-1.27MM">
+<wire x1="-3.81" y1="1.905" x2="3.81" y2="1.905" width="0.127" layer="21"/>
+<wire x1="3.81" y1="1.905" x2="3.81" y2="-1.905" width="0.127" layer="21"/>
+<wire x1="3.81" y1="-1.905" x2="-3.175" y2="-1.905" width="0.127" layer="21"/>
+<wire x1="-3.175" y1="-1.905" x2="-3.81" y2="-1.27" width="0.127" layer="21"/>
+<wire x1="-3.81" y1="-1.27" x2="-3.81" y2="1.905" width="0.127" layer="21"/>
+<pad name="1" x="-2.54" y="-0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="2" x="-2.54" y="0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="3" x="-1.27" y="-0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="4" x="-1.27" y="0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="5" x="0" y="-0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="6" x="0" y="0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="7" x="1.27" y="-0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="8" x="1.27" y="0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="9" x="2.54" y="-0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="10" x="2.54" y="0.635" drill="0.6604" diameter="1.0668"/>
+<text x="0" y="2.54" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="HEADER-5X2-2.54MM">
+<wire x1="-6.35" y1="0" x2="-3.81" y2="0" width="0.127" layer="21"/>
+<wire x1="-3.81" y1="0" x2="-3.81" y2="-2.54" width="0.127" layer="21"/>
+<wire x1="-6.35" y1="2.54" x2="6.35" y2="2.54" width="0.127" layer="21"/>
+<wire x1="6.35" y1="2.54" x2="6.35" y2="-2.54" width="0.127" layer="21"/>
+<wire x1="6.35" y1="-2.54" x2="-6.35" y2="-2.54" width="0.127" layer="21"/>
+<wire x1="-6.35" y1="-2.54" x2="-6.35" y2="2.54" width="0.127" layer="21"/>
+<pad name="1" x="-5.08" y="-1.27" drill="1.016" shape="square"/>
+<pad name="2" x="-5.08" y="1.27" drill="1.016"/>
+<pad name="3" x="-2.54" y="-1.27" drill="1.016"/>
+<pad name="4" x="-2.54" y="1.27" drill="1.016"/>
+<pad name="5" x="0" y="-1.27" drill="1.016"/>
+<pad name="6" x="0" y="1.27" drill="1.016"/>
+<pad name="7" x="2.54" y="-1.27" drill="1.016"/>
+<pad name="8" x="2.54" y="1.27" drill="1.016"/>
+<pad name="9" x="5.08" y="-1.27" drill="1.016"/>
+<pad name="10" x="5.08" y="1.27" drill="1.016"/>
+<text x="0" y="3.175" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="USB-B-MICRO-SMT-SHELL-TH">
+<pad name="M1" x="2.15" y="-3.6" drill="1.397"/>
+<pad name="M2" x="2.15" y="3.6" drill="1.397"/>
+<smd name="1" x="4.825" y="1.3" dx="1.35" dy="0.4" layer="1" stop="no"/>
+<smd name="2" x="4.825" y="0.65" dx="1.35" dy="0.4" layer="1" stop="no"/>
+<smd name="3" x="4.825" y="0" dx="1.35" dy="0.4" layer="1" stop="no"/>
+<smd name="4" x="4.825" y="-0.65" dx="1.35" dy="0.4" layer="1" stop="no"/>
+<smd name="5" x="4.825" y="-1.3" dx="1.35" dy="0.4" layer="1" stop="no"/>
+<text x="3.175" y="0" size="1.27" layer="25" font="vector" rot="R90" align="bottom-center">&gt;NAME</text>
+<rectangle x1="4.1" y1="1.05" x2="5.55" y2="1.55" layer="29"/>
+<pad name="M3" x="5.05" y="2.425" drill="0.7" shape="long"/>
+<pad name="M4" x="5.05" y="-2.425" drill="0.7" shape="long"/>
+<rectangle x1="4.1" y1="0.4" x2="5.55" y2="0.9" layer="29"/>
+<rectangle x1="4.1" y1="-0.25" x2="5.55" y2="0.25" layer="29"/>
+<rectangle x1="4.1" y1="-0.9" x2="5.55" y2="-0.4" layer="29"/>
+<rectangle x1="4.1" y1="-1.55" x2="5.55" y2="-1.05" layer="29"/>
+<wire x1="-0.5" y1="4" x2="-0.6" y2="3.8" width="0.1524" layer="21"/>
+<wire x1="-0.6" y1="3.8" x2="0" y2="3.5" width="0.1524" layer="21"/>
+<wire x1="0" y1="3.5" x2="0" y2="3.1" width="0.1524" layer="21"/>
+<wire x1="0" y1="3.1" x2="-0.6" y2="3.1" width="0.1524" layer="21"/>
+<wire x1="-0.6" y1="3.1" x2="-0.6" y2="-3.1" width="0.1524" layer="21"/>
+<wire x1="-0.6" y1="-3.1" x2="0" y2="-3.1" width="0.1524" layer="21"/>
+<wire x1="0" y1="-3.1" x2="0" y2="-3.5" width="0.1524" layer="21"/>
+<wire x1="0" y1="-3.5" x2="-0.6" y2="-3.8" width="0.1524" layer="21"/>
+<wire x1="-0.6" y1="-3.8" x2="-0.5" y2="-4" width="0.1524" layer="21"/>
+<wire x1="-0.5" y1="-4" x2="0" y2="-3.75" width="0.1524" layer="21"/>
+<wire x1="0" y1="-3.75" x2="5" y2="-3.75" width="0.1524" layer="21"/>
+<wire x1="5" y1="-3.75" x2="5" y2="-3.16" width="0.1524" layer="21"/>
+<wire x1="-0.5" y1="4" x2="0" y2="3.75" width="0.1524" layer="21"/>
+<wire x1="0" y1="3.75" x2="5" y2="3.75" width="0.1524" layer="21"/>
+<wire x1="5" y1="3.75" x2="5" y2="3.16" width="0.1524" layer="21"/>
+</package>
+<package name="PIN-TH">
+<wire x1="-0.635" y1="1.27" x2="0.635" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="0.635" y1="1.27" x2="1.27" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="1.27" y1="0.635" x2="1.27" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="1.27" y1="-0.635" x2="0.635" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-1.27" y1="0.635" x2="-1.27" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-0.635" y1="1.27" x2="-1.27" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-1.27" y1="-0.635" x2="-0.635" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="0.635" y1="-1.27" x2="-0.635" y2="-1.27" width="0.1524" layer="21"/>
+<rectangle x1="-0.254" y1="-0.254" x2="0.254" y2="0.254" layer="51"/>
+<pad name="1" x="0" y="0" drill="1.016" shape="octagon"/>
+<text x="0" y="1.524" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-2.794" size="1.27" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+</packages>
+<symbols>
+<symbol name="HEADER-5X2">
+<wire x1="-5.08" y1="7.62" x2="-5.08" y2="-7.62" width="0.254" layer="94"/>
+<wire x1="-5.08" y1="-7.62" x2="5.08" y2="-7.62" width="0.254" layer="94"/>
+<wire x1="5.08" y1="-7.62" x2="5.08" y2="7.62" width="0.254" layer="94"/>
+<wire x1="5.08" y1="7.62" x2="-5.08" y2="7.62" width="0.254" layer="94"/>
+<pin name="1" x="-7.62" y="5.08" length="short" direction="pas"/>
+<pin name="2" x="7.62" y="5.08" length="short" direction="pas" rot="R180"/>
+<pin name="3" x="-7.62" y="2.54" length="short" direction="pas"/>
+<pin name="4" x="7.62" y="2.54" length="short" direction="pas" rot="R180"/>
+<pin name="5" x="-7.62" y="0" length="short" direction="pas"/>
+<pin name="6" x="7.62" y="0" length="short" direction="pas" rot="R180"/>
+<pin name="7" x="-7.62" y="-2.54" length="short" direction="pas"/>
+<pin name="8" x="7.62" y="-2.54" length="short" direction="pas" rot="R180"/>
+<pin name="9" x="-7.62" y="-5.08" length="short" direction="pas"/>
+<pin name="10" x="7.62" y="-5.08" length="short" direction="pas" rot="R180"/>
+<text x="0" y="8.382" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+</symbol>
+<symbol name="MICRO-USB-5">
+<wire x1="-5.08" y1="7.62" x2="-5.08" y2="-10.16" width="0.254" layer="94"/>
+<text x="0.762" y="8.382" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<pin name="VBUS" x="-7.62" y="5.08" visible="pin" length="short" direction="pas"/>
+<pin name="DM" x="-7.62" y="2.54" visible="pin" length="short" direction="pas"/>
+<pin name="DP" x="-7.62" y="0" visible="pin" length="short" direction="pas"/>
+<pin name="ID" x="-7.62" y="-2.54" visible="pin" length="short" direction="pas"/>
+<pin name="GND" x="-7.62" y="-5.08" visible="pin" length="short" direction="pas"/>
+<wire x1="7.62" y1="7.62" x2="7.62" y2="-10.16" width="0.254" layer="94"/>
+<wire x1="-5.08" y1="7.62" x2="7.62" y2="7.62" width="0.254" layer="94"/>
+<wire x1="-5.08" y1="-10.16" x2="7.62" y2="-10.16" width="0.254" layer="94"/>
+<pin name="SHIELD" x="-7.62" y="-7.62" visible="pin" length="short" direction="pas"/>
+<text x="0.762" y="-12.192" size="1.27" layer="95" align="bottom-center">&gt;VALUE</text>
+</symbol>
+<symbol name="CONN-SINGLE">
+<wire x1="-2.54" y1="0.762" x2="0.127" y2="0" width="0.254" layer="94"/>
+<wire x1="0.127" y1="0" x2="-2.4765" y2="-0.762" width="0.254" layer="94"/>
+<pin name="1" x="-2.54" y="0" visible="off" length="short" direction="pas" swaplevel="1"/>
+<text x="1.27" y="-0.508" size="1.27" layer="95">&gt;NAME</text>
+<text x="6.096" y="-0.508" size="1.27" layer="96">&gt;VALUE</text>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="HEADER-5X2" prefix="J">
+<gates>
+<gate name="G$1" symbol="HEADER-5X2" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-TH-1.27" package="HEADER-5X2-1.27MM">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="10" pad="10"/>
+<connect gate="G$1" pin="2" pad="2"/>
+<connect gate="G$1" pin="3" pad="3"/>
+<connect gate="G$1" pin="4" pad="4"/>
+<connect gate="G$1" pin="5" pad="5"/>
+<connect gate="G$1" pin="6" pad="6"/>
+<connect gate="G$1" pin="7" pad="7"/>
+<connect gate="G$1" pin="8" pad="8"/>
+<connect gate="G$1" pin="9" pad="9"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-TH-2.54" package="HEADER-5X2-2.54MM">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="10" pad="10"/>
+<connect gate="G$1" pin="2" pad="2"/>
+<connect gate="G$1" pin="3" pad="3"/>
+<connect gate="G$1" pin="4" pad="4"/>
+<connect gate="G$1" pin="5" pad="5"/>
+<connect gate="G$1" pin="6" pad="6"/>
+<connect gate="G$1" pin="7" pad="7"/>
+<connect gate="G$1" pin="8" pad="8"/>
+<connect gate="G$1" pin="9" pad="9"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="USB-B-MICRO" prefix="J" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="MICRO-USB-5" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-SMT" package="USB-B-MICRO-SMT-SHELL-TH">
+<connects>
+<connect gate="G$1" pin="DM" pad="2"/>
+<connect gate="G$1" pin="DP" pad="3"/>
+<connect gate="G$1" pin="GND" pad="5"/>
+<connect gate="G$1" pin="ID" pad="4"/>
+<connect gate="G$1" pin="SHIELD" pad="M1 M2 M3 M4" route="any"/>
+<connect gate="G$1" pin="VBUS" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="CONN-SINGLE" prefix="J" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="CONN-SINGLE" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-TH" package="PIN-TH">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_rlc">
+<description>Alex Taradov Library (R, L and C)</description>
+<packages>
+<package name="SMD0402">
+<wire x1="-1" y1="0.5" x2="1" y2="0.5" width="0.1" layer="21"/>
+<wire x1="1" y1="0.5" x2="1" y2="-0.5" width="0.1" layer="21"/>
+<wire x1="1" y1="-0.5" x2="-1" y2="-0.5" width="0.1" layer="21"/>
+<wire x1="-1" y1="-0.5" x2="-1" y2="0.5" width="0.1" layer="21"/>
+<smd name="1" x="-0.5" y="0" dx="0.6" dy="0.6" layer="1"/>
+<smd name="2" x="0.5" y="0" dx="0.6" dy="0.6" layer="1"/>
+<text x="0" y="0.762" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SMD0508">
+<wire x1="-1" y1="1.25" x2="1" y2="1.25" width="0.1" layer="21"/>
+<wire x1="1" y1="1.25" x2="1" y2="-1.25" width="0.1" layer="21"/>
+<wire x1="1" y1="-1.25" x2="-1" y2="-1.25" width="0.1" layer="21"/>
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+<devices>
+<device name="-0402" package="SMD0402">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0508" package="SMD0508">
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+<connect gate="G$1" pin="2" pad="2"/>
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+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0603" package="SMD0603">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0612" package="SMD0612">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0805" package="SMD0805">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-1206" package="SMD1206">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-2512" package="SMD2512">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="R" prefix="R" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="R" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-0402" package="SMD0402">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0508" package="SMD0508">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0603" package="SMD0603">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0612" package="SMD0612">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0805" package="SMD0805">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-1206" package="SMD1206">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-2512" package="SMD2512">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="RN-4" prefix="RN" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="RN-4" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-0603-X4" package="SMD0603-X4">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+<connect gate="G$1" pin="3" pad="3"/>
+<connect gate="G$1" pin="4" pad="4"/>
+<connect gate="G$1" pin="5" pad="5"/>
+<connect gate="G$1" pin="6" pad="6"/>
+<connect gate="G$1" pin="7" pad="7"/>
+<connect gate="G$1" pin="8" pad="8"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_vreg">
+<description>Alex Taradov Library (Voltage Regulators)</description>
+<packages>
+<package name="SOT23-5">
+<description>SOT23-5</description>
+<wire x1="1.422" y1="0.81" x2="1.422" y2="-0.81" width="0.1524" layer="21"/>
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+<smd name="2" x="0" y="-1.3" dx="0.55" dy="1.2" layer="1"/>
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+<smd name="4" x="0.95" y="1.3" dx="0.55" dy="1.2" layer="1"/>
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+<text x="0" y="2.286" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-3.556" size="1.27" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+<rectangle x1="-1.2" y1="-1.5" x2="-0.7" y2="-0.85" layer="51"/>
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+<rectangle x1="-1.2" y1="0.85" x2="-0.7" y2="1.5" layer="51"/>
+</package>
+</packages>
+<symbols>
+<symbol name="VREG-3-EN">
+<wire x1="-7.62" y1="5.08" x2="7.62" y2="5.08" width="0.254" layer="94"/>
+<wire x1="7.62" y1="5.08" x2="7.62" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="7.62" y1="-2.54" x2="-7.62" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="-7.62" y1="-2.54" x2="-7.62" y2="5.08" width="0.254" layer="94"/>
+<text x="-2.032" y="-1.524" size="1.524" layer="95">GND</text>
+<text x="0" y="5.842" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<text x="1.524" y="-4.318" size="1.27" layer="96">&gt;VALUE</text>
+<pin name="IN" x="-10.16" y="2.54" length="short" direction="sup"/>
+<pin name="OUT" x="10.16" y="2.54" length="short" direction="sup" rot="R180"/>
+<pin name="GND" x="0" y="-5.08" visible="pad" length="short" direction="pwr" rot="R90"/>
+<pin name="EN" x="-10.16" y="0" length="short" direction="in"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="MIC5504" prefix="IC" uservalue="yes">
+<description>LM1117 voltage regulator</description>
+<gates>
+<gate name="G$1" symbol="VREG-3-EN" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-SOT23-5" package="SOT23-5">
+<connects>
+<connect gate="G$1" pin="EN" pad="3"/>
+<connect gate="G$1" pin="GND" pad="2"/>
+<connect gate="G$1" pin="IN" pad="1"/>
+<connect gate="G$1" pin="OUT" pad="5"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_misc">
+<description>Alex Taradov Library (Miscellaneous stuff)</description>
+<packages>
+<package name="TP-1.27MM">
+<smd name="1" x="0" y="0" dx="1.27" dy="1.27" layer="1" roundness="100" cream="no"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="TP-2.54MM">
+<smd name="1" x="0" y="0" dx="2.54" dy="2.54" layer="1" roundness="100" cream="no"/>
+<text x="0" y="1.778" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+</packages>
+<symbols>
+<symbol name="TP">
+<text x="4.064" y="-0.508" size="1.27" layer="95">&gt;NAME</text>
+<pin name="1" x="0" y="0" visible="off" length="short" direction="pas"/>
+<circle x="3.048" y="0" radius="0.508" width="0" layer="94"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="TEST-POINT" prefix="TP" uservalue="yes">
+<description>Test Point</description>
+<gates>
+<gate name="G$1" symbol="TP" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-1.27MM" package="TP-1.27MM">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-2.54MM" package="TP-2.54MM">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_led">
+<description>Alex Taradov Library (LEDs and other indication devices)</description>
+<packages>
+<package name="SMD0603">
+<wire x1="-1.5" y1="0.75" x2="1.5" y2="0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="0.75" x2="1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="-0.75" x2="-1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="-1.5" y1="-0.75" x2="-1.5" y2="0.75" width="0.1" layer="21"/>
+<smd name="1" x="-0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<smd name="2" x="0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SMD0805">
+<wire x1="-2" y1="1" x2="2" y2="1" width="0.1" layer="21"/>
+<wire x1="2" y1="1" x2="2" y2="-1" width="0.1" layer="21"/>
+<wire x1="2" y1="-1" x2="-2" y2="-1" width="0.1" layer="21"/>
+<wire x1="-2" y1="-1" x2="-2" y2="1" width="0.1" layer="21"/>
+<smd name="1" x="-0.95" y="0" dx="1.3" dy="1.5" layer="1"/>
+<smd name="2" x="0.95" y="0" dx="1.3" dy="1.5" layer="1"/>
+<text x="0" y="1.27" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+</packages>
+<symbols>
+<symbol name="LED">
+<wire x1="1.27" y1="0" x2="0" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="0" y1="-2.54" x2="-1.27" y2="0" width="0.254" layer="94"/>
+<wire x1="1.27" y1="-2.54" x2="0" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="0" y1="-2.54" x2="-1.27" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="1.27" y1="0" x2="0" y2="0" width="0.254" layer="94"/>
+<wire x1="0" y1="0" x2="-1.27" y2="0" width="0.254" layer="94"/>
+<wire x1="-2.032" y1="-0.762" x2="-3.429" y2="-2.159" width="0.1524" layer="94"/>
+<wire x1="-1.905" y1="-1.905" x2="-3.302" y2="-3.302" width="0.1524" layer="94"/>
+<text x="3.556" y="-2.032" size="1.27" layer="95" rot="R90" align="bottom-center">&gt;NAME</text>
+<text x="5.715" y="-2.032" size="1.27" layer="96" rot="R90" align="bottom-center">&gt;VALUE</text>
+<pin name="C" x="0" y="-5.08" visible="off" length="short" direction="pas" rot="R90"/>
+<pin name="A" x="0" y="2.54" visible="off" length="short" direction="pas" rot="R270"/>
+<polygon width="0.1524" layer="94">
+<vertex x="-3.429" y="-2.159"/>
+<vertex x="-3.048" y="-1.27"/>
+<vertex x="-2.54" y="-1.778"/>
+</polygon>
+<polygon width="0.1524" layer="94">
+<vertex x="-3.302" y="-3.302"/>
+<vertex x="-2.921" y="-2.413"/>
+<vertex x="-2.413" y="-2.921"/>
+</polygon>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="LED_SMD" prefix="LED" uservalue="yes">
+<description>SMD_LED</description>
+<gates>
+<gate name="G$1" symbol="LED" x="0" y="0"/>
+</gates>
+<devices>
+<device name="LED_0603" package="SMD0603">
+<connects>
+<connect gate="G$1" pin="A" pad="1"/>
+<connect gate="G$1" pin="C" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="LED_0805" package="SMD0805">
+<connects>
+<connect gate="G$1" pin="A" pad="1"/>
+<connect gate="G$1" pin="C" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+</libraries>
+<attributes>
+</attributes>
+<variantdefs>
+</variantdefs>
+<classes>
+<class number="0" name="default" width="0" drill="0">
+</class>
+</classes>
+<parts>
+<part name="IC2" library="ataradov_mcu" deviceset="ATSAMD11C" device=""/>
+<part name="P_5" library="ataradov_pwr" deviceset="+3V3" device=""/>
+<part name="P_8" library="ataradov_pwr" deviceset="+3V3" device=""/>
+<part name="P_11" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_9" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_10" library="ataradov_pwr" deviceset="V_USB" device=""/>
+<part name="P_3" library="ataradov_pwr" deviceset="V_USB" device=""/>
+<part name="C1" library="ataradov_rlc" deviceset="C" device="-0603" value="1uF"/>
+<part name="C2" library="ataradov_rlc" deviceset="C" device="-0603" value="1uF"/>
+<part name="IC1" library="ataradov_vreg" deviceset="MIC5504" device="-SOT23-5" value="MIC5504-3.3"/>
+<part name="P_4" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_6" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_1" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_2" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="TP1" library="ataradov_misc" deviceset="TEST-POINT" device="-1.27MM" value="SIO"/>
+<part name="TP2" library="ataradov_misc" deviceset="TEST-POINT" device="-1.27MM"/>
+<part name="TP3" library="ataradov_misc" deviceset="TEST-POINT" device="-1.27MM"/>
+<part name="TP4" library="ataradov_misc" deviceset="TEST-POINT" device="-1.27MM"/>
+<part name="J1" library="ataradov_conn" deviceset="HEADER-5X2" device="-TH-1.27"/>
+<part name="P_7" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="J2" library="ataradov_conn" deviceset="USB-B-MICRO" device="-SMT"/>
+<part name="R1" library="ataradov_rlc" deviceset="R" device="-0603" value="470"/>
+<part name="LED1" library="ataradov_led" deviceset="LED_SMD" device="LED_0603"/>
+<part name="R2" library="ataradov_rlc" deviceset="R" device="-0603" value="470"/>
+<part name="LED2" library="ataradov_led" deviceset="LED_SMD" device="LED_0603"/>
+<part name="P_13" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="J3" library="ataradov_conn" deviceset="CONN-SINGLE" device="-TH" value="RX"/>
+<part name="J4" library="ataradov_conn" deviceset="CONN-SINGLE" device="-TH" value="TX"/>
+<part name="J5" library="ataradov_conn" deviceset="CONN-SINGLE" device="-TH" value="GND"/>
+<part name="P_12" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="RN1" library="ataradov_rlc" deviceset="RN-4" device="-0603-X4" value="100"/>
+</parts>
+<sheets>
+<sheet>
+<plain>
+<frame x1="0" y1="0" x2="152.4" y2="119.38" columns="8" rows="5" layer="97"/>
+<text x="27.94" y="106.68" size="1.778" layer="97" align="bottom-center">Program</text>
+<text x="76.2" y="106.68" size="1.778" layer="97" align="bottom-center">Target</text>
+<text x="60.96" y="15.24" size="1.778" layer="97">Copyright (c) 2016-2019, Alex Taradov &lt;alex@taradov.com&gt;
+
+MCU firmware source code is available at https://github.com/ataradov/free-dap</text>
+<text x="124.46" y="106.68" size="1.778" layer="97" align="bottom-center">UART</text>
+</plain>
+<instances>
+<instance part="IC2" gate="G$1" x="40.64" y="53.34"/>
+<instance part="P_5" gate="1" x="53.34" y="27.94"/>
+<instance part="P_8" gate="1" x="60.96" y="66.04"/>
+<instance part="P_11" gate="1" x="76.2" y="40.64"/>
+<instance part="P_9" gate="1" x="60.96" y="40.64"/>
+<instance part="P_10" gate="1" x="76.2" y="60.96"/>
+<instance part="P_3" gate="1" x="25.4" y="27.94"/>
+<instance part="C1" gate="G$1" x="20.32" y="17.78" rot="R90"/>
+<instance part="C2" gate="G$1" x="53.34" y="17.78" rot="R90"/>
+<instance part="IC1" gate="G$1" x="38.1" y="20.32"/>
+<instance part="P_4" gate="1" x="38.1" y="12.7"/>
+<instance part="P_6" gate="1" x="53.34" y="12.7"/>
+<instance part="P_1" gate="1" x="20.32" y="12.7"/>
+<instance part="P_2" gate="1" x="25.4" y="86.36"/>
+<instance part="TP1" gate="G$1" x="27.94" y="96.52"/>
+<instance part="TP2" gate="G$1" x="27.94" y="93.98"/>
+<instance part="TP3" gate="G$1" x="27.94" y="91.44"/>
+<instance part="TP4" gate="G$1" x="27.94" y="88.9"/>
+<instance part="J1" gate="G$1" x="71.12" y="91.44"/>
+<instance part="P_7" gate="1" x="60.96" y="81.28"/>
+<instance part="J2" gate="G$1" x="86.36" y="50.8"/>
+<instance part="R1" gate="G$1" x="119.38" y="53.34"/>
+<instance part="LED1" gate="G$1" x="129.54" y="53.34" rot="MR270"/>
+<instance part="R2" gate="G$1" x="119.38" y="45.72"/>
+<instance part="LED2" gate="G$1" x="129.54" y="45.72" rot="MR270"/>
+<instance part="P_13" gate="1" x="137.16" y="40.64"/>
+<instance part="J3" gate="G$1" x="127" y="96.52"/>
+<instance part="J4" gate="G$1" x="127" y="93.98"/>
+<instance part="J5" gate="G$1" x="127" y="91.44"/>
+<instance part="P_12" gate="1" x="121.92" y="86.36"/>
+<instance part="RN1" gate="G$1" x="121.92" y="71.12"/>
+</instances>
+<busses>
+</busses>
+<nets>
+<net name="N$1" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA24"/>
+<wire x1="58.42" y1="48.26" x2="76.2" y2="48.26" width="0.1524" layer="91"/>
+<wire x1="76.2" y1="48.26" x2="76.2" y2="53.34" width="0.1524" layer="91"/>
+<wire x1="76.2" y1="53.34" x2="78.74" y2="53.34" width="0.1524" layer="91"/>
+<pinref part="J2" gate="G$1" pin="DM"/>
+</segment>
+</net>
+<net name="N$2" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA25"/>
+<wire x1="58.42" y1="50.8" x2="78.74" y2="50.8" width="0.1524" layer="91"/>
+<pinref part="J2" gate="G$1" pin="DP"/>
+</segment>
+</net>
+<net name="GND" class="0">
+<segment>
+<pinref part="P_11" gate="1" pin="GND"/>
+<wire x1="76.2" y1="43.18" x2="76.2" y2="45.72" width="0.1524" layer="91"/>
+<wire x1="76.2" y1="45.72" x2="78.74" y2="45.72" width="0.1524" layer="91"/>
+<pinref part="J2" gate="G$1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="IC1" gate="G$1" pin="GND"/>
+<pinref part="P_4" gate="1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="C1" gate="G$1" pin="1"/>
+<pinref part="P_1" gate="1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="C2" gate="G$1" pin="1"/>
+<pinref part="P_6" gate="1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="GND"/>
+<pinref part="P_9" gate="1" pin="GND"/>
+<wire x1="58.42" y1="53.34" x2="60.96" y2="53.34" width="0.1524" layer="91"/>
+<wire x1="60.96" y1="53.34" x2="60.96" y2="43.18" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="P_2" gate="1" pin="GND"/>
+<wire x1="25.4" y1="88.9" x2="27.94" y2="88.9" width="0.1524" layer="91"/>
+<pinref part="TP4" gate="G$1" pin="1"/>
+</segment>
+<segment>
+<pinref part="J1" gate="G$1" pin="3"/>
+<wire x1="63.5" y1="93.98" x2="60.96" y2="93.98" width="0.1524" layer="91"/>
+<pinref part="P_7" gate="1" pin="GND"/>
+<wire x1="60.96" y1="93.98" x2="60.96" y2="91.44" width="0.1524" layer="91"/>
+<pinref part="J1" gate="G$1" pin="5"/>
+<wire x1="60.96" y1="91.44" x2="60.96" y2="86.36" width="0.1524" layer="91"/>
+<wire x1="60.96" y1="86.36" x2="60.96" y2="83.82" width="0.1524" layer="91"/>
+<wire x1="63.5" y1="91.44" x2="60.96" y2="91.44" width="0.1524" layer="91"/>
+<junction x="60.96" y="91.44"/>
+<pinref part="J1" gate="G$1" pin="9"/>
+<wire x1="63.5" y1="86.36" x2="60.96" y2="86.36" width="0.1524" layer="91"/>
+<junction x="60.96" y="86.36"/>
+</segment>
+<segment>
+<pinref part="P_13" gate="1" pin="GND"/>
+<wire x1="137.16" y1="43.18" x2="137.16" y2="45.72" width="0.1524" layer="91"/>
+<wire x1="137.16" y1="45.72" x2="134.62" y2="45.72" width="0.1524" layer="91"/>
+<pinref part="LED2" gate="G$1" pin="C"/>
+<pinref part="LED1" gate="G$1" pin="C"/>
+<wire x1="137.16" y1="53.34" x2="137.16" y2="45.72" width="0.1524" layer="91"/>
+<wire x1="134.62" y1="53.34" x2="137.16" y2="53.34" width="0.1524" layer="91"/>
+<junction x="137.16" y="45.72"/>
+</segment>
+<segment>
+<pinref part="J5" gate="G$1" pin="1"/>
+<pinref part="P_12" gate="1" pin="GND"/>
+<wire x1="121.92" y1="88.9" x2="121.92" y2="91.44" width="0.1524" layer="91"/>
+<wire x1="121.92" y1="91.44" x2="124.46" y2="91.44" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="V_USB" class="0">
+<segment>
+<pinref part="P_10" gate="1" pin="V_USB"/>
+<wire x1="76.2" y1="58.42" x2="76.2" y2="55.88" width="0.1524" layer="91"/>
+<wire x1="76.2" y1="55.88" x2="78.74" y2="55.88" width="0.1524" layer="91"/>
+<pinref part="J2" gate="G$1" pin="VBUS"/>
+</segment>
+<segment>
+<pinref part="IC1" gate="G$1" pin="EN"/>
+<pinref part="P_3" gate="1" pin="V_USB"/>
+<wire x1="27.94" y1="20.32" x2="25.4" y2="20.32" width="0.1524" layer="91"/>
+<wire x1="25.4" y1="20.32" x2="25.4" y2="22.86" width="0.1524" layer="91"/>
+<pinref part="IC1" gate="G$1" pin="IN"/>
+<wire x1="25.4" y1="22.86" x2="25.4" y2="25.4" width="0.1524" layer="91"/>
+<wire x1="27.94" y1="22.86" x2="25.4" y2="22.86" width="0.1524" layer="91"/>
+<junction x="25.4" y="22.86"/>
+<pinref part="C1" gate="G$1" pin="2"/>
+<wire x1="25.4" y1="22.86" x2="20.32" y2="22.86" width="0.1524" layer="91"/>
+<wire x1="20.32" y1="22.86" x2="20.32" y2="20.32" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="+3V3" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="OUT"/>
+<wire x1="48.26" y1="22.86" x2="53.34" y2="22.86" width="0.1524" layer="91"/>
+<pinref part="C2" gate="G$1" pin="2"/>
+<wire x1="53.34" y1="20.32" x2="53.34" y2="22.86" width="0.1524" layer="91"/>
+<junction x="53.34" y="22.86"/>
+<pinref part="P_5" gate="1" pin="+3V3"/>
+<wire x1="53.34" y1="25.4" x2="53.34" y2="22.86" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="VDD"/>
+<pinref part="P_8" gate="1" pin="+3V3"/>
+<wire x1="58.42" y1="55.88" x2="60.96" y2="55.88" width="0.1524" layer="91"/>
+<wire x1="60.96" y1="55.88" x2="60.96" y2="63.5" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="SWDIO" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA31/SIO"/>
+<wire x1="58.42" y1="45.72" x2="63.5" y2="45.72" width="0.1524" layer="91"/>
+<label x="63.5" y="45.72" size="1.27" layer="95"/>
+</segment>
+<segment>
+<wire x1="27.94" y1="96.52" x2="25.4" y2="96.52" width="0.1524" layer="91"/>
+<label x="25.4" y="96.52" size="1.27" layer="95" rot="MR0"/>
+<pinref part="TP1" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="PA02" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA02"/>
+<wire x1="58.42" y1="58.42" x2="63.5" y2="58.42" width="0.1524" layer="91"/>
+<label x="63.5" y="58.42" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="R1" gate="G$1" pin="1"/>
+<wire x1="114.3" y1="53.34" x2="111.76" y2="53.34" width="0.1524" layer="91"/>
+<label x="111.76" y="53.34" size="1.27" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="PA04" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA04"/>
+<wire x1="58.42" y1="60.96" x2="63.5" y2="60.96" width="0.1524" layer="91"/>
+<label x="63.5" y="60.96" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="R2" gate="G$1" pin="1"/>
+<wire x1="114.3" y1="45.72" x2="111.76" y2="45.72" width="0.1524" layer="91"/>
+<label x="111.76" y="45.72" size="1.27" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="SWCLK" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA30/SCK"/>
+<wire x1="22.86" y1="45.72" x2="20.32" y2="45.72" width="0.1524" layer="91"/>
+<label x="20.32" y="45.72" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<label x="25.4" y="93.98" size="1.27" layer="95" rot="MR0"/>
+<wire x1="27.94" y1="93.98" x2="25.4" y2="93.98" width="0.1524" layer="91"/>
+<pinref part="TP2" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="RESET" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA28/RST"/>
+<wire x1="22.86" y1="48.26" x2="20.32" y2="48.26" width="0.1524" layer="91"/>
+<label x="20.32" y="48.26" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<label x="25.4" y="91.44" size="1.27" layer="95" rot="MR0"/>
+<wire x1="27.94" y1="91.44" x2="25.4" y2="91.44" width="0.1524" layer="91"/>
+<pinref part="TP3" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="T_SWDIO" class="0">
+<segment>
+<pinref part="J1" gate="G$1" pin="2"/>
+<wire x1="78.74" y1="96.52" x2="81.28" y2="96.52" width="0.1524" layer="91"/>
+<label x="81.28" y="96.52" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="RN1" gate="G$1" pin="8"/>
+<wire x1="127" y1="73.66" x2="129.54" y2="73.66" width="0.1524" layer="91"/>
+<label x="129.54" y="73.66" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="T_SWCLK" class="0">
+<segment>
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dap_link/lib/free-dap/hardware/d11_micro_std_vcp_v2/d11_micro_std_vcp_v2.brd

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+<rectangle x1="4.1" y1="-1.55" x2="5.55" y2="-1.05" layer="29"/>
+<wire x1="-0.5" y1="4" x2="-0.6" y2="3.8" width="0.1524" layer="21"/>
+<wire x1="-0.6" y1="3.8" x2="0" y2="3.5" width="0.1524" layer="21"/>
+<wire x1="0" y1="3.5" x2="0" y2="3.1" width="0.1524" layer="21"/>
+<wire x1="0" y1="3.1" x2="-0.6" y2="3.1" width="0.1524" layer="21"/>
+<wire x1="-0.6" y1="3.1" x2="-0.6" y2="-3.1" width="0.1524" layer="21"/>
+<wire x1="-0.6" y1="-3.1" x2="0" y2="-3.1" width="0.1524" layer="21"/>
+<wire x1="0" y1="-3.1" x2="0" y2="-3.5" width="0.1524" layer="21"/>
+<wire x1="0" y1="-3.5" x2="-0.6" y2="-3.8" width="0.1524" layer="21"/>
+<wire x1="-0.6" y1="-3.8" x2="-0.5" y2="-4" width="0.1524" layer="21"/>
+<wire x1="-0.5" y1="-4" x2="0" y2="-3.75" width="0.1524" layer="21"/>
+<wire x1="0" y1="-3.75" x2="5" y2="-3.75" width="0.1524" layer="21"/>
+<wire x1="5" y1="-3.75" x2="5" y2="-3.16" width="0.1524" layer="21"/>
+<wire x1="-0.5" y1="4" x2="0" y2="3.75" width="0.1524" layer="21"/>
+<wire x1="0" y1="3.75" x2="5" y2="3.75" width="0.1524" layer="21"/>
+<wire x1="5" y1="3.75" x2="5" y2="3.16" width="0.1524" layer="21"/>
+</package>
+<package name="PIN-TH">
+<wire x1="-0.635" y1="1.27" x2="0.635" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="0.635" y1="1.27" x2="1.27" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="1.27" y1="0.635" x2="1.27" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="1.27" y1="-0.635" x2="0.635" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-1.27" y1="0.635" x2="-1.27" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-0.635" y1="1.27" x2="-1.27" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-1.27" y1="-0.635" x2="-0.635" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="0.635" y1="-1.27" x2="-0.635" y2="-1.27" width="0.1524" layer="21"/>
+<pad name="1" x="0" y="0" drill="1.016"/>
+<text x="0" y="1.524" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-2.794" size="1.27" layer="21" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+</packages>
+</library>
+<library name="ataradov_rlc">
+<description>Alex Taradov Library (R, L and C)</description>
+<packages>
+<package name="SMD0603">
+<wire x1="-1.5" y1="0.75" x2="1.5" y2="0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="0.75" x2="1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="-0.75" x2="-1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="-1.5" y1="-0.75" x2="-1.5" y2="0.75" width="0.1" layer="21"/>
+<smd name="1" x="-0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<smd name="2" x="0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+<package name="SMD0603-X4">
+<smd name="1" x="-1.2" y="-0.752" dx="0.5" dy="0.889" layer="1"/>
+<smd name="2" x="-0.4" y="-0.752" dx="0.5" dy="0.889" layer="1"/>
+<smd name="3" x="0.4" y="-0.752" dx="0.5" dy="0.889" layer="1"/>
+<smd name="4" x="1.2" y="-0.752" dx="0.5" dy="0.889" layer="1"/>
+<smd name="5" x="1.2" y="0.752" dx="0.5" dy="0.889" layer="1"/>
+<smd name="6" x="0.4" y="0.752" dx="0.5" dy="0.889" layer="1"/>
+<smd name="7" x="-0.4" y="0.752" dx="0.5" dy="0.889" layer="1"/>
+<smd name="8" x="-1.2" y="0.752" dx="0.5" dy="0.889" layer="1"/>
+<text x="0" y="1.778" size="1.27" layer="25" font="vector" ratio="10" align="bottom-center">&gt;NAME</text>
+<wire x1="1.778" y1="1.4986" x2="1.778" y2="-1.524" width="0.1016" layer="21"/>
+<wire x1="-1.778" y1="1.4986" x2="-1.778" y2="-1.524" width="0.1016" layer="21"/>
+<wire x1="-1.778" y1="1.4986" x2="1.778" y2="1.4986" width="0.1016" layer="21"/>
+<wire x1="-1.778" y1="-1.524" x2="1.778" y2="-1.524" width="0.1016" layer="21"/>
+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" ratio="10" align="bottom-center">&gt;VALUE</text>
+</package>
+</packages>
+</library>
+<library name="ataradov_vreg">
+<description>Alex Taradov Library (Voltage Regulators)</description>
+<packages>
+<package name="SOT23-5">
+<description>SOT23-5</description>
+<wire x1="1.422" y1="0.81" x2="1.422" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="1.422" y1="-0.81" x2="-1.422" y2="-0.81" width="0.1524" layer="51"/>
+<wire x1="-1.422" y1="-0.81" x2="-1.422" y2="0.81" width="0.1524" layer="21"/>
+<wire x1="-1.422" y1="0.81" x2="1.422" y2="0.81" width="0.1524" layer="51"/>
+<wire x1="-0.522" y1="0.81" x2="0.522" y2="0.81" width="0.1524" layer="21"/>
+<wire x1="-0.428" y1="-0.81" x2="-0.522" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="0.522" y1="-0.81" x2="0.428" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="-1.328" y1="-0.81" x2="-1.422" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="1.422" y1="-0.81" x2="1.328" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="1.328" y1="0.81" x2="1.422" y2="0.81" width="0.1524" layer="21"/>
+<wire x1="-1.422" y1="0.81" x2="-1.328" y2="0.81" width="0.1524" layer="21"/>
+<smd name="1" x="-0.95" y="-1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="2" x="0" y="-1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="3" x="0.95" y="-1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="4" x="0.95" y="1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="5" x="-0.95" y="1.3" dx="0.55" dy="1.2" layer="1"/>
+<text x="0" y="2.286" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+</packages>
+</library>
+<library name="ataradov_misc">
+<description>Alex Taradov Library (Miscellaneous stuff)</description>
+<packages>
+<package name="TP-1.27MM">
+<smd name="1" x="0" y="0" dx="1.27" dy="1.27" layer="1" roundness="100" cream="no"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SB-1.27MM-NO">
+<smd name="1" x="-0.508" y="0" dx="0.762" dy="1.27" layer="1" cream="no"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-2.286" size="1.27" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+<smd name="2" x="0.508" y="0" dx="0.762" dy="1.27" layer="1" cream="no"/>
+<rectangle x1="-1.016" y1="-0.762" x2="1.016" y2="0.762" layer="29"/>
+</package>
+</packages>
+</library>
+<library name="ataradov_led">
+<description>Alex Taradov Library (LEDs and other indication devices)</description>
+<packages>
+<package name="SMD0603">
+<wire x1="-1.5" y1="0.75" x2="1.5" y2="0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="0.75" x2="1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="-0.75" x2="-1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="-1.5" y1="-0.75" x2="-1.5" y2="0.75" width="0.1" layer="21"/>
+<smd name="1" x="-0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<smd name="2" x="0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+</packages>
+</library>
+</libraries>
+<attributes>
+</attributes>
+<variantdefs>
+</variantdefs>
+<classes>
+<class number="0" name="default" width="0" drill="0">
+</class>
+</classes>
+<designrules name="std-tented-new">
+<description language="de">&lt;b&gt;EAGLE Design Rules&lt;/b&gt;
+&lt;p&gt;
+Die Standard-Design-Rules sind so gewählt, dass sie für 
+die meisten Anwendungen passen. Sollte ihre Platine 
+besondere Anforderungen haben, treffen Sie die erforderlichen
+Einstellungen hier und speichern die Design Rules unter 
+einem neuen Namen ab.</description>
+<description language="en">&lt;b&gt;Laen's PCB Order Design Rules&lt;/b&gt;
+&lt;p&gt;
+Please make sure your boards conform to these design rules.</description>
+<param name="layerSetup" value="(1*16)"/>
+<param name="mtCopper" value="0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm"/>
+<param name="mtIsolate" value="1.5011mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm"/>
+<param name="mdWireWire" value="6mil"/>
+<param name="mdWirePad" value="6mil"/>
+<param name="mdWireVia" value="6mil"/>
+<param name="mdPadPad" value="6mil"/>
+<param name="mdPadVia" value="6mil"/>
+<param name="mdViaVia" value="6mil"/>
+<param name="mdSmdPad" value="0mil"/>
+<param name="mdSmdVia" value="0mil"/>
+<param name="mdSmdSmd" value="0mil"/>
+<param name="mdViaViaSameLayer" value="8mil"/>
+<param name="mnLayersViaInSmd" value="2"/>
+<param name="mdCopperDimension" value="10mil"/>
+<param name="mdDrill" value="6mil"/>
+<param name="mdSmdStop" value="0mil"/>
+<param name="msWidth" value="8mil"/>
+<param name="msDrill" value="13mil"/>
+<param name="msMicroVia" value="13mil"/>
+<param name="msBlindViaRatio" value="0.5"/>
+<param name="rvPadTop" value="0.25"/>
+<param name="rvPadInner" value="0.25"/>
+<param name="rvPadBottom" value="0.25"/>
+<param name="rvViaOuter" value="0.25"/>
+<param name="rvViaInner" value="0.25"/>
+<param name="rvMicroViaOuter" value="0.25"/>
+<param name="rvMicroViaInner" value="0.25"/>
+<param name="rlMinPadTop" value="7mil"/>
+<param name="rlMaxPadTop" value="20mil"/>
+<param name="rlMinPadInner" value="7mil"/>
+<param name="rlMaxPadInner" value="20mil"/>
+<param name="rlMinPadBottom" value="7mil"/>
+<param name="rlMaxPadBottom" value="20mil"/>
+<param name="rlMinViaOuter" value="7mil"/>
+<param name="rlMaxViaOuter" value="20mil"/>
+<param name="rlMinViaInner" value="7mil"/>
+<param name="rlMaxViaInner" value="20mil"/>
+<param name="rlMinMicroViaOuter" value="4mil"/>
+<param name="rlMaxMicroViaOuter" value="20mil"/>
+<param name="rlMinMicroViaInner" value="4mil"/>
+<param name="rlMaxMicroViaInner" value="20mil"/>
+<param name="psTop" value="-1"/>
+<param name="psBottom" value="-1"/>
+<param name="psFirst" value="-1"/>
+<param name="psElongationLong" value="100"/>
+<param name="psElongationOffset" value="100"/>
+<param name="mvStopFrame" value="1"/>
+<param name="mvCreamFrame" value="0"/>
+<param name="mlMinStopFrame" value="3mil"/>
+<param name="mlMaxStopFrame" value="3mil"/>
+<param name="mlMinCreamFrame" value="0mil"/>
+<param name="mlMaxCreamFrame" value="0mil"/>
+<param name="mlViaStopLimit" value="25mil"/>
+<param name="srRoundness" value="0"/>
+<param name="srMinRoundness" value="0mil"/>
+<param name="srMaxRoundness" value="0mil"/>
+<param name="slThermalIsolate" value="6mil"/>
+<param name="slThermalsForVias" value="0"/>
+<param name="dpMaxLengthDifference" value="10mm"/>
+<param name="dpGapFactor" value="2.5"/>
+<param name="checkGrid" value="0"/>
+<param name="checkAngle" value="0"/>
+<param name="checkFont" value="1"/>
+<param name="checkRestrict" value="1"/>
+<param name="useDiameter" value="13"/>
+<param name="maxErrors" value="50"/>
+</designrules>
+<autorouter>
+<pass name="Default">
+<param name="RoutingGrid" value="50mil"/>
+<param name="AutoGrid" value="1"/>
+<param name="Efforts" value="0"/>
+<param name="TopRouterVariant" value="1"/>
+<param name="tpViaShape" value="round"/>
+<param name="PrefDir.1" value="a"/>
+<param name="PrefDir.2" value="0"/>
+<param name="PrefDir.3" value="0"/>
+<param name="PrefDir.4" value="0"/>
+<param name="PrefDir.5" value="0"/>
+<param name="PrefDir.6" value="0"/>
+<param name="PrefDir.7" value="0"/>
+<param name="PrefDir.8" value="0"/>
+<param name="PrefDir.9" value="0"/>
+<param name="PrefDir.10" value="0"/>
+<param name="PrefDir.11" value="0"/>
+<param name="PrefDir.12" value="0"/>
+<param name="PrefDir.13" value="0"/>
+<param name="PrefDir.14" value="0"/>
+<param name="PrefDir.15" value="0"/>
+<param name="PrefDir.16" value="a"/>
+<param name="cfVia" value="8"/>
+<param name="cfNonPref" value="5"/>
+<param name="cfChangeDir" value="2"/>
+<param name="cfOrthStep" value="2"/>
+<param name="cfDiagStep" value="3"/>
+<param name="cfExtdStep" value="0"/>
+<param name="cfBonusStep" value="1"/>
+<param name="cfMalusStep" value="1"/>
+<param name="cfPadImpact" value="4"/>
+<param name="cfSmdImpact" value="4"/>
+<param name="cfBusImpact" value="0"/>
+<param name="cfHugging" value="3"/>
+<param name="cfAvoid" value="4"/>
+<param name="cfPolygon" value="10"/>
+<param name="cfBase.1" value="0"/>
+<param name="cfBase.2" value="1"/>
+<param name="cfBase.3" value="1"/>
+<param name="cfBase.4" value="1"/>
+<param name="cfBase.5" value="1"/>
+<param name="cfBase.6" value="1"/>
+<param name="cfBase.7" value="1"/>
+<param name="cfBase.8" value="1"/>
+<param name="cfBase.9" value="1"/>
+<param name="cfBase.10" value="1"/>
+<param name="cfBase.11" value="1"/>
+<param name="cfBase.12" value="1"/>
+<param name="cfBase.13" value="1"/>
+<param name="cfBase.14" value="1"/>
+<param name="cfBase.15" value="1"/>
+<param name="cfBase.16" value="0"/>
+<param name="mnVias" value="20"/>
+<param name="mnSegments" value="9999"/>
+<param name="mnExtdSteps" value="9999"/>
+<param name="mnRipupLevel" value="10"/>
+<param name="mnRipupSteps" value="100"/>
+<param name="mnRipupTotal" value="100"/>
+</pass>
+<pass name="Follow-me" refer="Default" active="yes">
+</pass>
+<pass name="Busses" refer="Default" active="yes">
+<param name="cfNonPref" value="4"/>
+<param name="cfBusImpact" value="4"/>
+<param name="cfHugging" value="0"/>
+<param name="mnVias" value="0"/>
+</pass>
+<pass name="Route" refer="Default" active="yes">
+</pass>
+<pass name="Optimize1" refer="Default" active="yes">
+<param name="cfVia" value="99"/>
+<param name="cfExtdStep" value="10"/>
+<param name="cfHugging" value="1"/>
+<param name="mnExtdSteps" value="1"/>
+<param name="mnRipupLevel" value="0"/>
+</pass>
+<pass name="Optimize2" refer="Optimize1" active="yes">
+<param name="cfNonPref" value="0"/>
+<param name="cfChangeDir" value="6"/>
+<param name="cfExtdStep" value="0"/>
+<param name="cfBonusStep" value="2"/>
+<param name="cfMalusStep" value="2"/>
+<param name="cfPadImpact" value="2"/>
+<param name="cfSmdImpact" value="2"/>
+<param name="cfHugging" value="0"/>
+</pass>
+<pass name="Optimize3" refer="Optimize2" active="yes">
+<param name="cfChangeDir" value="8"/>
+<param name="cfPadImpact" value="0"/>
+<param name="cfSmdImpact" value="0"/>
+</pass>
+<pass name="Optimize4" refer="Optimize3" active="yes">
+<param name="cfChangeDir" value="25"/>
+</pass>
+</autorouter>
+<elements>
+<element name="C1" library="ataradov_rlc" package="SMD0603" value="1uF" x="1.27" y="5.588" rot="MR270"/>
+<element name="C2" library="ataradov_rlc" package="SMD0603" value="1uF" x="6.858" y="5.588" smashed="yes" rot="MR270">
+<attribute name="NAME" x="5.842" y="5.588" size="1.27" layer="26" font="vector" rot="MR270" align="bottom-center"/>
+</element>
+<element name="IC2" library="ataradov_vreg" package="SOT23-5" value="MIC5504-3.3" x="4.064" y="5.588" smashed="yes" rot="MR90">
+<attribute name="NAME" x="6.35" y="5.588" size="1.27" layer="26" font="vector" rot="MR90" align="bottom-center"/>
+</element>
+<element name="TP1" library="ataradov_misc" package="TP-1.27MM" value="SIO" x="6.604" y="9.652" rot="MR0"/>
+<element name="TP2" library="ataradov_misc" package="TP-1.27MM" value="" x="11.684" y="9.652" rot="MR0"/>
+<element name="TP3" library="ataradov_misc" package="TP-1.27MM" value="" x="9.144" y="9.652" rot="MR0"/>
+<element name="TP4" library="ataradov_misc" package="TP-1.27MM" value="" x="4.064" y="9.652" rot="MR0"/>
+<element name="J2" library="ataradov_conn" package="HEADER-5X2-1.27MM" value="HEADER-5X2-TH-1.27" x="17.018" y="5.588" rot="R90"/>
+<element name="J1" library="ataradov_conn" package="USB-B-MICRO-SMT-SHELL-TH" value="" x="0" y="5.588"/>
+<element name="R1" library="ataradov_rlc" package="SMD0603" value="10K" x="8.382" y="2.286" rot="MR90"/>
+<element name="LED1" library="ataradov_led" package="SMD0603" value="ORANGE" x="8.382" y="2.286" rot="R270"/>
+<element name="R2" library="ataradov_rlc" package="SMD0603" value="10K" x="9.906" y="2.286" rot="MR90"/>
+<element name="LED2" library="ataradov_led" package="SMD0603" value="GREEN" x="9.906" y="2.286" rot="R270"/>
+<element name="J3" library="ataradov_conn" package="PIN-TH" value="RX" x="19.812" y="8.128" smashed="yes" rot="R90">
+<attribute name="NAME" x="18.288" y="8.128" size="1.27" layer="25" font="vector" rot="R90" align="bottom-center"/>
+<attribute name="VALUE" x="22.606" y="8.89" size="1.27" layer="22" font="vector" rot="MR270" align="bottom-center"/>
+</element>
+<element name="J4" library="ataradov_conn" package="PIN-TH" value="TX" x="19.812" y="5.588" smashed="yes" rot="R90">
+<attribute name="NAME" x="18.288" y="5.588" size="1.27" layer="25" font="vector" rot="R90" align="bottom-center"/>
+<attribute name="VALUE" x="22.606" y="5.842" size="1.27" layer="22" font="vector" rot="MR270" align="bottom-center"/>
+</element>
+<element name="J5" library="ataradov_conn" package="PIN-TH" value="GND" x="19.812" y="3.048" smashed="yes" rot="R90">
+<attribute name="NAME" x="18.288" y="3.048" size="1.27" layer="25" font="vector" rot="R90" align="bottom-center"/>
+<attribute name="VALUE" x="22.606" y="2.54" size="1.27" layer="22" font="vector" rot="MR270" align="bottom-center"/>
+</element>
+<element name="RN1" library="ataradov_rlc" package="SMD0603-X4" value="100" x="13.462" y="8.128" rot="R90"/>
+<element name="SB1" library="ataradov_misc" package="SB-1.27MM-NO" value="" x="12.7" y="1.524"/>
+<element name="IC1" library="ataradov_mcu" package="QFN24" value="ATSAMD11D" x="9.144" y="6.35" rot="R90"/>
+<element name="RN2" library="ataradov_rlc" package="SMD0603-X4" value="100" x="13.462" y="4.572" rot="R90"/>
+</elements>
+<signals>
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+</signal>
+<signal name="USB_DM">
+<contactref element="J1" pad="2"/>
+<contactref element="IC1" pad="21"/>
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+</signal>
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+<contactref element="J1" pad="3"/>
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+</signal>
+<signal name="V_USB">
+<contactref element="IC2" pad="3"/>
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+<contactref element="C1" pad="2"/>
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+</signal>
+<signal name="SWDIO">
+<contactref element="TP1" pad="1"/>
+<contactref element="IC1" pad="20"/>
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+<wire x1="6.604" y1="8.636" x2="6.604" y2="9.652" width="0.254" layer="16"/>
+</signal>
+<signal name="SWCLK">
+<contactref element="TP2" pad="1"/>
+<contactref element="IC1" pad="19"/>
+<wire x1="7.294" y1="7.6" x2="7.294" y2="9.326" width="0.254" layer="1"/>
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+<wire x1="10.668" y1="9.652" x2="11.684" y2="9.652" width="0.254" layer="16"/>
+</signal>
+<signal name="RESET">
+<contactref element="TP3" pad="1"/>
+<contactref element="IC1" pad="18"/>
+<via x="8.128" y="9.144" extent="1-16" drill="0.3302"/>
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+</signal>
+<signal name="N$8">
+</signal>
+<signal name="T_SWDIO_TMS">
+<contactref element="J2" pad="2"/>
+<contactref element="RN2" pad="2"/>
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+</signal>
+<signal name="T_SWCLK_TCK">
+<contactref element="J2" pad="4"/>
+<contactref element="RN2" pad="3"/>
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+</signal>
+<signal name="T_RESET">
+<contactref element="J2" pad="10"/>
+<contactref element="RN1" pad="2"/>
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+</signal>
+<signal name="UART_TX">
+<contactref element="J4" pad="1"/>
+<contactref element="RN1" pad="3"/>
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+<wire x1="18.542" y1="6.858" x2="19.812" y2="5.588" width="0.254" layer="1"/>
+</signal>
+<signal name="N$11">
+</signal>
+<signal name="UART_RX">
+<contactref element="J3" pad="1"/>
+<contactref element="RN1" pad="4"/>
+<wire x1="14.214" y1="9.328" x2="15.424" y2="9.328" width="0.254" layer="1"/>
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+<wire x1="18.288" y1="9.652" x2="19.812" y2="8.128" width="0.254" layer="1"/>
+</signal>
+<signal name="T_TDO">
+<contactref element="J2" pad="6"/>
+<contactref element="RN2" pad="4"/>
+<wire x1="14.214" y1="5.772" x2="16.199" y2="5.772" width="0.254" layer="1"/>
+<wire x1="16.199" y1="5.772" x2="16.383" y2="5.588" width="0.254" layer="1"/>
+</signal>
+<signal name="T_TDI">
+<contactref element="J2" pad="8"/>
+<contactref element="RN1" pad="1"/>
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+<wire x1="16.313" y1="6.928" x2="16.383" y2="6.858" width="0.254" layer="1"/>
+</signal>
+<signal name="N$2">
+<contactref element="R1" pad="1"/>
+<contactref element="LED1" pad="2"/>
+<via x="7.62" y="1.524" extent="1-16" drill="0.3302"/>
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+<wire x1="7.658" y1="1.486" x2="7.62" y2="1.524" width="0.254" layer="16"/>
+</signal>
+<signal name="N$3">
+<contactref element="R2" pad="1"/>
+<contactref element="LED2" pad="2"/>
+<via x="10.668" y="1.524" extent="1-16" drill="0.3302"/>
+<wire x1="9.906" y1="1.486" x2="10.63" y2="1.486" width="0.254" layer="16"/>
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+<wire x1="10.63" y1="1.486" x2="10.668" y2="1.524" width="0.254" layer="1"/>
+</signal>
+<signal name="LED_A">
+<contactref element="LED1" pad="1"/>
+<contactref element="IC1" pad="2"/>
+<wire x1="8.394" y1="4.5" x2="8.394" y2="3.098" width="0.254" layer="1"/>
+<wire x1="8.394" y1="3.098" x2="8.382" y2="3.086" width="0.254" layer="1"/>
+</signal>
+<signal name="LED_B">
+<contactref element="LED2" pad="1"/>
+<contactref element="IC1" pad="5"/>
+<wire x1="9.894" y1="4.5" x2="9.894" y2="3.098" width="0.254" layer="1"/>
+<wire x1="9.894" y1="3.098" x2="9.906" y2="3.086" width="0.254" layer="1"/>
+</signal>
+<signal name="I_TX">
+<contactref element="IC1" pad="13"/>
+<contactref element="RN1" pad="6"/>
+<wire x1="12.71" y1="8.528" x2="12.084" y2="8.528" width="0.254" layer="1"/>
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+<wire x1="11.756" y1="8.2" x2="10.394" y2="8.2" width="0.254" layer="1"/>
+</signal>
+<signal name="I_RX">
+<contactref element="IC1" pad="14"/>
+<contactref element="RN1" pad="5"/>
+<wire x1="12.71" y1="9.328" x2="11.868" y2="9.328" width="0.254" layer="1"/>
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+<wire x1="9.894" y1="8.878" x2="9.894" y2="8.2" width="0.254" layer="1"/>
+</signal>
+<signal name="T_VREF">
+<contactref element="J2" pad="1"/>
+<contactref element="SB1" pad="2"/>
+<contactref element="RN2" pad="1"/>
+<wire x1="16.764" y1="1.524" x2="14.224" y2="1.524" width="0.254" layer="1"/>
+<wire x1="14.224" y1="1.524" x2="13.208" y2="1.524" width="0.254" layer="1"/>
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+<wire x1="14.224" y1="3.362" x2="14.224" y2="1.524" width="0.254" layer="1"/>
+</signal>
+<signal name="I_TDI">
+<contactref element="RN1" pad="8"/>
+<contactref element="IC1" pad="11"/>
+<wire x1="10.994" y1="7.1" x2="11.95" y2="7.1" width="0.254" layer="1"/>
+<wire x1="11.95" y1="7.1" x2="12.122" y2="6.928" width="0.254" layer="1"/>
+<wire x1="12.122" y1="6.928" x2="12.71" y2="6.928" width="0.254" layer="1"/>
+</signal>
+<signal name="I_RESET">
+<contactref element="RN1" pad="7"/>
+<contactref element="IC1" pad="12"/>
+<wire x1="10.994" y1="7.6" x2="11.918" y2="7.6" width="0.254" layer="1"/>
+<wire x1="11.918" y1="7.6" x2="12.046" y2="7.728" width="0.254" layer="1"/>
+<wire x1="12.046" y1="7.728" x2="12.71" y2="7.728" width="0.254" layer="1"/>
+</signal>
+<signal name="I_VREF">
+<contactref element="RN2" pad="8"/>
+<contactref element="IC1" pad="6"/>
+<wire x1="12.122" y1="3.372" x2="10.994" y2="4.5" width="0.254" layer="1"/>
+<wire x1="10.994" y1="4.5" x2="10.394" y2="4.5" width="0.254" layer="1"/>
+<wire x1="12.122" y1="3.372" x2="12.71" y2="3.372" width="0.254" layer="1"/>
+</signal>
+<signal name="I_SWDIO_TMS">
+<contactref element="RN2" pad="7"/>
+<contactref element="IC1" pad="7"/>
+<wire x1="10.994" y1="5.1" x2="11.41" y2="5.1" width="0.254" layer="1"/>
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+<wire x1="12.084" y1="4.172" x2="12.71" y2="4.172" width="0.254" layer="1"/>
+</signal>
+<signal name="I_SWCLK_TCK">
+<contactref element="RN2" pad="6"/>
+<contactref element="IC1" pad="8"/>
+<wire x1="10.994" y1="5.6" x2="11.672" y2="5.6" width="0.254" layer="1"/>
+<wire x1="11.672" y1="5.6" x2="12.3" y2="4.972" width="0.254" layer="1"/>
+<wire x1="12.3" y1="4.972" x2="12.71" y2="4.972" width="0.254" layer="1"/>
+</signal>
+<signal name="I_TDO">
+<contactref element="RN2" pad="5"/>
+<contactref element="IC1" pad="9"/>
+<wire x1="10.994" y1="6.1" x2="11.874" y2="6.1" width="0.254" layer="1"/>
+<wire x1="11.874" y1="6.1" x2="12.202" y2="5.772" width="0.254" layer="1"/>
+<wire x1="12.202" y1="5.772" x2="12.71" y2="5.772" width="0.254" layer="1"/>
+</signal>
+</signals>
+</board>
+</drawing>
+</eagle>

dap_link/lib/free-dap/hardware/d11_micro_std_vcp_v2/d11_micro_std_vcp_v2.sch

@@ -0,0 +1,1620 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="7.3.0">
+<drawing>
+<settings>
+<setting alwaysvectorfont="no"/>
+<setting verticaltext="up"/>
+</settings>
+<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>
+<layers>
+<layer number="1" name="Top" color="4" fill="1" visible="no" active="no"/>
+<layer number="16" name="Bottom" color="1" fill="1" visible="no" active="no"/>
+<layer number="17" name="Pads" color="2" fill="1" visible="no" active="no"/>
+<layer number="18" name="Vias" color="2" fill="1" visible="no" active="no"/>
+<layer number="19" name="Unrouted" color="6" fill="1" visible="no" active="no"/>
+<layer number="20" name="Dimension" color="15" fill="1" visible="no" active="no"/>
+<layer number="21" name="tPlace" color="7" fill="1" visible="no" active="no"/>
+<layer number="22" name="bPlace" color="7" fill="1" visible="no" active="no"/>
+<layer number="23" name="tOrigins" color="15" fill="1" visible="no" active="no"/>
+<layer number="24" name="bOrigins" color="15" fill="1" visible="no" active="no"/>
+<layer number="25" name="tNames" color="7" fill="1" visible="no" active="no"/>
+<layer number="26" name="bNames" color="7" fill="1" visible="no" active="no"/>
+<layer number="27" name="tValues" color="7" fill="1" visible="no" active="no"/>
+<layer number="28" name="bValues" color="7" fill="1" visible="no" active="no"/>
+<layer number="29" name="tStop" color="7" fill="3" visible="no" active="no"/>
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+<layer number="97" name="Info" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/>
+</layers>
+<schematic xreflabel="%F%N/%S.%C%R" xrefpart="/%S.%C%R">
+<libraries>
+<library name="ataradov_mcu">
+<description>Alex Taradov Library (MCUs)</description>
+<packages>
+<package name="QFN24">
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+<text x="0" y="2.54" size="1.27" layer="25" font="vector" ratio="10" align="bottom-center">&gt;NAME</text>
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+</packages>
+<symbols>
+<symbol name="ATSAMDXXD">
+<description>Atmel SAM D09D/D10D/D11D Cortex-M0+ microcontroller</description>
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+<pin name="PA02" x="-17.78" y="15.24" length="middle" direction="pas"/>
+<text x="0" y="18.542" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-19.812" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+<pin name="PA30/SCK" x="17.78" y="-7.62" length="middle" direction="pas" rot="R180"/>
+<pin name="VDD" x="17.78" y="15.24" length="middle" direction="pas" rot="R180"/>
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+<pin name="PAD" x="17.78" y="-15.24" length="middle" direction="pas" rot="R180"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="ATSAMD11D" prefix="IC">
+<gates>
+<gate name="G$1" symbol="ATSAMDXXD" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="QFN24">
+<connects>
+<connect gate="G$1" pin="GND" pad="23"/>
+<connect gate="G$1" pin="PA02" pad="1"/>
+<connect gate="G$1" pin="PA03" pad="2"/>
+<connect gate="G$1" pin="PA04" pad="3"/>
+<connect gate="G$1" pin="PA05" pad="4"/>
+<connect gate="G$1" pin="PA06" pad="5"/>
+<connect gate="G$1" pin="PA07" pad="6"/>
+<connect gate="G$1" pin="PA08" pad="7"/>
+<connect gate="G$1" pin="PA09" pad="8"/>
+<connect gate="G$1" pin="PA10" pad="9"/>
+<connect gate="G$1" pin="PA11" pad="10"/>
+<connect gate="G$1" pin="PA14" pad="11"/>
+<connect gate="G$1" pin="PA15" pad="12"/>
+<connect gate="G$1" pin="PA16" pad="13"/>
+<connect gate="G$1" pin="PA17" pad="14"/>
+<connect gate="G$1" pin="PA22" pad="15"/>
+<connect gate="G$1" pin="PA23" pad="16"/>
+<connect gate="G$1" pin="PA24/DM" pad="21"/>
+<connect gate="G$1" pin="PA25/DP" pad="22"/>
+<connect gate="G$1" pin="PA27" pad="17"/>
+<connect gate="G$1" pin="PA28/RST" pad="18"/>
+<connect gate="G$1" pin="PA30/SCK" pad="19"/>
+<connect gate="G$1" pin="PA31/SIO" pad="20"/>
+<connect gate="G$1" pin="PAD" pad="PAD"/>
+<connect gate="G$1" pin="VDD" pad="24"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_pwr">
+<description>Alex Taradov Library (Power Symbols)</description>
+<packages>
+</packages>
+<symbols>
+<symbol name="+3V3">
+<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/>
+<text x="0" y="0.762" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+<pin name="+3V3" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/>
+</symbol>
+<symbol name="GND">
+<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/>
+<text x="0" y="-2.032" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+<pin name="GND" x="0" y="2.54" visible="off" length="short" direction="sup" rot="R270"/>
+</symbol>
+<symbol name="V_USB">
+<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/>
+<text x="0" y="0.762" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+<pin name="V_USB" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="+3V3" prefix="P_">
+<gates>
+<gate name="1" symbol="+3V3" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="GND" prefix="P_">
+<gates>
+<gate name="1" symbol="GND" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="V_USB" prefix="P_">
+<gates>
+<gate name="1" symbol="V_USB" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_conn">
+<description>Alex Taradov Library (Connectors)</description>
+<packages>
+<package name="HEADER-5X2-1.27MM">
+<wire x1="-3.81" y1="1.905" x2="3.81" y2="1.905" width="0.127" layer="21"/>
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+<text x="0" y="2.54" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="HEADER-5X2-2.54MM">
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+<text x="0" y="3.175" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="USB-B-MICRO-SMT-SHELL-TH">
+<pad name="M1" x="2.15" y="-3.6" drill="1.143"/>
+<pad name="M2" x="2.15" y="3.6" drill="1.143"/>
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+<text x="3.175" y="0" size="1.27" layer="25" font="vector" rot="R90" align="bottom-center">&gt;NAME</text>
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+</package>
+<package name="PIN-TH-SMALL">
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+<pad name="1" x="0" y="0" drill="0.9"/>
+<text x="0" y="1.524" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-2.794" size="1.27" layer="21" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+</packages>
+<symbols>
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+<pin name="10" x="7.62" y="-5.08" length="short" direction="pas" rot="R180"/>
+<text x="0" y="8.382" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+</symbol>
+<symbol name="MICRO-USB-5">
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+<text x="0.762" y="8.382" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
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+<pin name="DM" x="-7.62" y="2.54" visible="pin" length="short" direction="pas"/>
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+<pin name="SHIELD" x="-7.62" y="-7.62" visible="pin" length="short" direction="pas"/>
+<text x="0.762" y="-12.192" size="1.27" layer="95" align="bottom-center">&gt;VALUE</text>
+</symbol>
+<symbol name="CONN-SINGLE">
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+<pin name="1" x="-2.54" y="0" visible="off" length="short" direction="pas" swaplevel="1"/>
+<text x="1.27" y="-0.508" size="1.27" layer="95">&gt;NAME</text>
+<text x="6.096" y="-0.508" size="1.27" layer="96">&gt;VALUE</text>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="HEADER-5X2" prefix="J">
+<gates>
+<gate name="G$1" symbol="HEADER-5X2" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-TH-1.27" package="HEADER-5X2-1.27MM">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="10" pad="10"/>
+<connect gate="G$1" pin="2" pad="2"/>
+<connect gate="G$1" pin="3" pad="3"/>
+<connect gate="G$1" pin="4" pad="4"/>
+<connect gate="G$1" pin="5" pad="5"/>
+<connect gate="G$1" pin="6" pad="6"/>
+<connect gate="G$1" pin="7" pad="7"/>
+<connect gate="G$1" pin="8" pad="8"/>
+<connect gate="G$1" pin="9" pad="9"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-TH-1.27-SHR" package="HEADER-5X2-1.27MM-SHR">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="10" pad="10"/>
+<connect gate="G$1" pin="2" pad="2"/>
+<connect gate="G$1" pin="3" pad="3"/>
+<connect gate="G$1" pin="4" pad="4"/>
+<connect gate="G$1" pin="5" pad="5"/>
+<connect gate="G$1" pin="6" pad="6"/>
+<connect gate="G$1" pin="7" pad="7"/>
+<connect gate="G$1" pin="8" pad="8"/>
+<connect gate="G$1" pin="9" pad="9"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-TH-2.54-SHR-RA" package="HEADER-5X2-2.54MM-SHR-RA">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="10" pad="10"/>
+<connect gate="G$1" pin="2" pad="2"/>
+<connect gate="G$1" pin="3" pad="3"/>
+<connect gate="G$1" pin="4" pad="4"/>
+<connect gate="G$1" pin="5" pad="5"/>
+<connect gate="G$1" pin="6" pad="6"/>
+<connect gate="G$1" pin="7" pad="7"/>
+<connect gate="G$1" pin="8" pad="8"/>
+<connect gate="G$1" pin="9" pad="9"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-TH-2.54" package="HEADER-5X2-2.54MM">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="10" pad="10"/>
+<connect gate="G$1" pin="2" pad="2"/>
+<connect gate="G$1" pin="3" pad="3"/>
+<connect gate="G$1" pin="4" pad="4"/>
+<connect gate="G$1" pin="5" pad="5"/>
+<connect gate="G$1" pin="6" pad="6"/>
+<connect gate="G$1" pin="7" pad="7"/>
+<connect gate="G$1" pin="8" pad="8"/>
+<connect gate="G$1" pin="9" pad="9"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="USB-B-MICRO" prefix="J" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="MICRO-USB-5" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-SMT" package="USB-B-MICRO-SMT-SHELL-TH">
+<connects>
+<connect gate="G$1" pin="DM" pad="2"/>
+<connect gate="G$1" pin="DP" pad="3"/>
+<connect gate="G$1" pin="GND" pad="5"/>
+<connect gate="G$1" pin="ID" pad="4"/>
+<connect gate="G$1" pin="SHIELD" pad="M1 M2 M3 M4" route="any"/>
+<connect gate="G$1" pin="VBUS" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="CONN-SINGLE" prefix="J" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="CONN-SINGLE" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-TH" package="PIN-TH">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-TH-LARGE" package="PIN-TH-LARGE">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-TH-SMALL" package="PIN-TH-SMALL">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_rlc">
+<description>Alex Taradov Library (R, L and C)</description>
+<packages>
+<package name="SMD0508">
+<wire x1="-1" y1="1.25" x2="1" y2="1.25" width="0.1" layer="21"/>
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+<smd name="1" x="-0.5" y="0" dx="2" dy="0.5" layer="1" rot="R90"/>
+<smd name="2" x="0.5" y="0" dx="2" dy="0.5" layer="1" rot="R90"/>
+<text x="0" y="1.524" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SMD0603">
+<wire x1="-1.5" y1="0.75" x2="1.5" y2="0.75" width="0.1" layer="21"/>
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+<smd name="1" x="-0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<smd name="2" x="0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+<package name="SMD0612">
+<wire x1="-1.8" y1="1.4" x2="1.8" y2="1.4" width="0.1" layer="21"/>
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+<smd name="1" x="0" y="0.8" dx="3.2" dy="0.8" layer="1"/>
+<smd name="2" x="0" y="-0.8" dx="3.2" dy="0.8" layer="1"/>
+<text x="0" y="1.778" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SMD1206">
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+<smd name="1" x="-1.4" y="0" dx="1.6" dy="2" layer="1"/>
+<smd name="2" x="1.4" y="0" dx="1.6" dy="2" layer="1"/>
+<text x="0" y="1.778" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SMD2512">
+<wire x1="-5.5" y1="2.5" x2="5.5" y2="2.5" width="0.1" layer="21"/>
+<wire x1="5.5" y1="2.5" x2="5.5" y2="-2.5" width="0.1" layer="21"/>
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+<text x="0" y="2.794" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
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+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" ratio="10" align="bottom-center">&gt;VALUE</text>
+</package>
+<package name="SMD0402">
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+<text x="0" y="0.762" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+<package name="SMD0805">
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+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+</packages>
+<symbols>
+<symbol name="C">
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+<text x="0" y="2.413" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-3.683" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
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+<symbol name="R">
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+<text x="0" y="1.524" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<text x="0" y="0" size="1.016" layer="96" align="center">&gt;VALUE</text>
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+<symbol name="RN-4">
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+<pin name="1" x="-5.08" y="2.54" visible="off" length="short" direction="pas"/>
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+<text x="0" y="4.572" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<wire x1="2.54" y1="1.524" x2="2.54" y2="3.556" width="0.254" layer="94"/>
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+<pin name="5" x="5.08" y="-5.08" visible="off" length="short" direction="pas" rot="R180"/>
+<text x="0" y="2.54" size="1.016" layer="96" align="center">&gt;VALUE</text>
+<wire x1="2.54" y1="-6.096" x2="2.54" y2="-4.064" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="-4.064" x2="2.54" y2="-4.064" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="-6.096" x2="2.54" y2="-6.096" width="0.254" layer="94"/>
+<wire x1="-3.048" y1="-6.604" x2="-3.048" y2="4.064" width="0.127" layer="94" style="shortdash"/>
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+<wire x1="3.048" y1="4.064" x2="-3.048" y2="4.064" width="0.127" layer="94" style="shortdash"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="C" prefix="C" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="C" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-0402" package="SMD0402">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0508" package="SMD0508">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0603" package="SMD0603">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0612" package="SMD0612">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0805" package="SMD0805">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-1206" package="SMD1206">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-2512" package="SMD2512">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="R" prefix="R" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="R" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-0402" package="SMD0402">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0508" package="SMD0508">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0603" package="SMD0603">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0612" package="SMD0612">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0805" package="SMD0805">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-1206" package="SMD1206">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-2512" package="SMD2512">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="RN-4" prefix="RN" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="RN-4" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-0603-X4" package="SMD0603-X4">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+<connect gate="G$1" pin="3" pad="3"/>
+<connect gate="G$1" pin="4" pad="4"/>
+<connect gate="G$1" pin="5" pad="5"/>
+<connect gate="G$1" pin="6" pad="6"/>
+<connect gate="G$1" pin="7" pad="7"/>
+<connect gate="G$1" pin="8" pad="8"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_vreg">
+<description>Alex Taradov Library (Voltage Regulators)</description>
+<packages>
+<package name="SOT23-5">
+<description>SOT23-5</description>
+<wire x1="1.422" y1="0.81" x2="1.422" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="1.422" y1="-0.81" x2="-1.422" y2="-0.81" width="0.1524" layer="51"/>
+<wire x1="-1.422" y1="-0.81" x2="-1.422" y2="0.81" width="0.1524" layer="21"/>
+<wire x1="-1.422" y1="0.81" x2="1.422" y2="0.81" width="0.1524" layer="51"/>
+<wire x1="-0.522" y1="0.81" x2="0.522" y2="0.81" width="0.1524" layer="21"/>
+<wire x1="-0.428" y1="-0.81" x2="-0.522" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="0.522" y1="-0.81" x2="0.428" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="-1.328" y1="-0.81" x2="-1.422" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="1.422" y1="-0.81" x2="1.328" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="1.328" y1="0.81" x2="1.422" y2="0.81" width="0.1524" layer="21"/>
+<wire x1="-1.422" y1="0.81" x2="-1.328" y2="0.81" width="0.1524" layer="21"/>
+<smd name="1" x="-0.95" y="-1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="2" x="0" y="-1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="3" x="0.95" y="-1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="4" x="0.95" y="1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="5" x="-0.95" y="1.3" dx="0.55" dy="1.2" layer="1"/>
+<text x="0" y="2.286" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+</packages>
+<symbols>
+<symbol name="VREG-3-EN">
+<wire x1="-7.62" y1="5.08" x2="7.62" y2="5.08" width="0.254" layer="94"/>
+<wire x1="7.62" y1="5.08" x2="7.62" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="7.62" y1="-2.54" x2="-7.62" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="-7.62" y1="-2.54" x2="-7.62" y2="5.08" width="0.254" layer="94"/>
+<text x="-2.032" y="-1.524" size="1.524" layer="95">GND</text>
+<text x="0" y="5.842" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<text x="1.524" y="-4.318" size="1.27" layer="96">&gt;VALUE</text>
+<pin name="IN" x="-10.16" y="2.54" length="short" direction="pas"/>
+<pin name="OUT" x="10.16" y="2.54" length="short" direction="pas" rot="R180"/>
+<pin name="GND" x="0" y="-5.08" visible="pad" length="short" direction="pas" rot="R90"/>
+<pin name="EN" x="-10.16" y="0" length="short" direction="pas"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="MIC5504" prefix="IC" uservalue="yes">
+<description>LM1117 voltage regulator</description>
+<gates>
+<gate name="G$1" symbol="VREG-3-EN" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-SOT23-5" package="SOT23-5">
+<connects>
+<connect gate="G$1" pin="EN" pad="3"/>
+<connect gate="G$1" pin="GND" pad="2"/>
+<connect gate="G$1" pin="IN" pad="1"/>
+<connect gate="G$1" pin="OUT" pad="5"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_misc">
+<description>Alex Taradov Library (Miscellaneous stuff)</description>
+<packages>
+<package name="TP-1.27MM">
+<smd name="1" x="0" y="0" dx="1.27" dy="1.27" layer="1" roundness="100" cream="no"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="TP-2.54MM">
+<smd name="1" x="0" y="0" dx="2.54" dy="2.54" layer="1" roundness="100" cream="no"/>
+<text x="0" y="1.778" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SB-1.27MM-NO">
+<smd name="1" x="-0.508" y="0" dx="0.762" dy="1.27" layer="1" cream="no"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-2.286" size="1.27" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+<smd name="2" x="0.508" y="0" dx="0.762" dy="1.27" layer="1" cream="no"/>
+<rectangle x1="-1.016" y1="-0.762" x2="1.016" y2="0.762" layer="29"/>
+</package>
+<package name="TP-0.635MM">
+<smd name="1" x="0" y="0" dx="0.635" dy="0.635" layer="1" roundness="100" cream="no"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="TP-0.5MM">
+<smd name="1" x="0" y="0" dx="0.5" dy="0.5" layer="1" roundness="100" cream="no"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="TP-1.27MM-TH">
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<pad name="1" x="0" y="0" drill="0.762" diameter="1.27"/>
+</package>
+</packages>
+<symbols>
+<symbol name="TP">
+<text x="4.064" y="-0.508" size="1.27" layer="95">&gt;NAME</text>
+<pin name="1" x="0" y="0" visible="off" length="short" direction="pas"/>
+<circle x="3.048" y="0" radius="0.508" width="0" layer="94"/>
+</symbol>
+<symbol name="SB">
+<wire x1="0.381" y1="0.381" x2="0.381" y2="-0.381" width="0.762" layer="94" curve="-180" cap="flat"/>
+<wire x1="-0.381" y1="-0.381" x2="-0.381" y2="0.381" width="0.762" layer="94" curve="-180" cap="flat"/>
+<wire x1="2.54" y1="0" x2="1.143" y2="0" width="0.1524" layer="94"/>
+<wire x1="-2.54" y1="0" x2="-1.143" y2="0" width="0.1524" layer="94"/>
+<text x="0" y="1.778" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<pin name="2" x="2.54" y="0" visible="off" length="point" direction="pas" swaplevel="1" rot="R180"/>
+<pin name="1" x="-2.54" y="0" visible="off" length="point" direction="pas" swaplevel="1"/>
+<text x="0" y="-3.048" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="TEST-POINT" prefix="TP" uservalue="yes">
+<description>Test Point</description>
+<gates>
+<gate name="G$1" symbol="TP" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-1.27MM" package="TP-1.27MM">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0.635MM" package="TP-0.635MM">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0.5MM" package="TP-0.5MM">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-2.54MM" package="TP-2.54MM">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-1.27MM-TH" package="TP-1.27MM-TH">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="SOLDER-BRIDGE" prefix="SB" uservalue="yes">
+<description>Solder Bridge</description>
+<gates>
+<gate name="G$1" symbol="SB" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-1.27MM-NO" package="SB-1.27MM-NO">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_led">
+<description>Alex Taradov Library (LEDs and other indication devices)</description>
+<packages>
+<package name="SMD0603">
+<wire x1="-1.5" y1="0.75" x2="1.5" y2="0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="0.75" x2="1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="-0.75" x2="-1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="-1.5" y1="-0.75" x2="-1.5" y2="0.75" width="0.1" layer="21"/>
+<smd name="1" x="-0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<smd name="2" x="0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+<package name="SMD0805">
+<wire x1="-2" y1="1" x2="2" y2="1" width="0.1" layer="21"/>
+<wire x1="2" y1="1" x2="2" y2="-1" width="0.1" layer="21"/>
+<wire x1="2" y1="-1" x2="-2" y2="-1" width="0.1" layer="21"/>
+<wire x1="-2" y1="-1" x2="-2" y2="1" width="0.1" layer="21"/>
+<smd name="1" x="-0.95" y="0" dx="1.3" dy="1.5" layer="1"/>
+<smd name="2" x="0.95" y="0" dx="1.3" dy="1.5" layer="1"/>
+<text x="0" y="1.27" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+</packages>
+<symbols>
+<symbol name="LED">
+<wire x1="1.27" y1="0" x2="0" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="0" y1="-2.54" x2="-1.27" y2="0" width="0.254" layer="94"/>
+<wire x1="1.27" y1="-2.54" x2="0" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="0" y1="-2.54" x2="-1.27" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="1.27" y1="0" x2="0" y2="0" width="0.254" layer="94"/>
+<wire x1="0" y1="0" x2="-1.27" y2="0" width="0.254" layer="94"/>
+<wire x1="-2.032" y1="-0.762" x2="-3.429" y2="-2.159" width="0.1524" layer="94"/>
+<wire x1="-1.905" y1="-1.905" x2="-3.302" y2="-3.302" width="0.1524" layer="94"/>
+<text x="3.556" y="-2.032" size="1.27" layer="95" rot="R90" align="bottom-center">&gt;NAME</text>
+<text x="5.715" y="-2.032" size="1.27" layer="96" rot="R90" align="bottom-center">&gt;VALUE</text>
+<pin name="C" x="0" y="-5.08" visible="off" length="short" direction="pas" rot="R90"/>
+<pin name="A" x="0" y="2.54" visible="off" length="short" direction="pas" rot="R270"/>
+<polygon width="0.1524" layer="94">
+<vertex x="-3.429" y="-2.159"/>
+<vertex x="-3.048" y="-1.27"/>
+<vertex x="-2.54" y="-1.778"/>
+</polygon>
+<polygon width="0.1524" layer="94">
+<vertex x="-3.302" y="-3.302"/>
+<vertex x="-2.921" y="-2.413"/>
+<vertex x="-2.413" y="-2.921"/>
+</polygon>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="LED_SMD" prefix="LED" uservalue="yes">
+<description>SMD_LED</description>
+<gates>
+<gate name="G$1" symbol="LED" x="0" y="0"/>
+</gates>
+<devices>
+<device name="LED_0603" package="SMD0603">
+<connects>
+<connect gate="G$1" pin="A" pad="1"/>
+<connect gate="G$1" pin="C" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="LED_0805" package="SMD0805">
+<connects>
+<connect gate="G$1" pin="A" pad="1"/>
+<connect gate="G$1" pin="C" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+</libraries>
+<attributes>
+</attributes>
+<variantdefs>
+</variantdefs>
+<classes>
+<class number="0" name="default" width="0" drill="0">
+</class>
+</classes>
+<parts>
+<part name="P_8" library="ataradov_pwr" deviceset="+3V3" device=""/>
+<part name="P_2" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_1" library="ataradov_pwr" deviceset="V_USB" device=""/>
+<part name="P_3" library="ataradov_pwr" deviceset="V_USB" device=""/>
+<part name="C1" library="ataradov_rlc" deviceset="C" device="-0603" value="1uF"/>
+<part name="C2" library="ataradov_rlc" deviceset="C" device="-0603" value="1uF"/>
+<part name="IC2" library="ataradov_vreg" deviceset="MIC5504" device="-SOT23-5" value="MIC5504-3.3"/>
+<part name="P_5" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_9" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_4" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="TP1" library="ataradov_misc" deviceset="TEST-POINT" device="-1.27MM" value="SIO"/>
+<part name="TP2" library="ataradov_misc" deviceset="TEST-POINT" device="-1.27MM"/>
+<part name="TP3" library="ataradov_misc" deviceset="TEST-POINT" device="-1.27MM"/>
+<part name="TP4" library="ataradov_misc" deviceset="TEST-POINT" device="-1.27MM"/>
+<part name="J2" library="ataradov_conn" deviceset="HEADER-5X2" device="-TH-1.27"/>
+<part name="P_11" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="J1" library="ataradov_conn" deviceset="USB-B-MICRO" device="-SMT"/>
+<part name="R1" library="ataradov_rlc" deviceset="R" device="-0603" value="10K"/>
+<part name="LED1" library="ataradov_led" deviceset="LED_SMD" device="LED_0603" value="ORANGE"/>
+<part name="R2" library="ataradov_rlc" deviceset="R" device="-0603" value="10K"/>
+<part name="LED2" library="ataradov_led" deviceset="LED_SMD" device="LED_0603" value="GREEN"/>
+<part name="P_12" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="J3" library="ataradov_conn" deviceset="CONN-SINGLE" device="-TH" value="RX"/>
+<part name="J4" library="ataradov_conn" deviceset="CONN-SINGLE" device="-TH" value="TX"/>
+<part name="J5" library="ataradov_conn" deviceset="CONN-SINGLE" device="-TH" value="GND"/>
+<part name="P_13" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="RN1" library="ataradov_rlc" deviceset="RN-4" device="-0603-X4" value="100"/>
+<part name="SB1" library="ataradov_misc" deviceset="SOLDER-BRIDGE" device="-1.27MM-NO"/>
+<part name="IC1" library="ataradov_mcu" deviceset="ATSAMD11D" device=""/>
+<part name="P_6" library="ataradov_pwr" deviceset="+3V3" device=""/>
+<part name="P_7" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="RN2" library="ataradov_rlc" deviceset="RN-4" device="-0603-X4" value="100"/>
+<part name="P_10" library="ataradov_pwr" deviceset="+3V3" device=""/>
+</parts>
+<sheets>
+<sheet>
+<plain>
+<frame x1="0" y1="0" x2="165.1" y2="114.3" columns="8" rows="5" layer="97"/>
+<text x="68.58" y="7.62" size="1.778" layer="97">Copyright (c) 2021, Alex Taradov &lt;alex@taradov.com&gt;
+MCU firmware source code is available at https://github.com/ataradov/free-dap</text>
+</plain>
+<instances>
+<instance part="P_8" gate="1" x="76.2" y="35.56"/>
+<instance part="P_2" gate="1" x="30.48" y="17.78" rot="MR0"/>
+<instance part="P_1" gate="1" x="30.48" y="35.56" rot="MR0"/>
+<instance part="P_3" gate="1" x="48.26" y="35.56"/>
+<instance part="C1" gate="G$1" x="48.26" y="27.94" rot="R90"/>
+<instance part="C2" gate="G$1" x="76.2" y="27.94" rot="R90"/>
+<instance part="IC2" gate="G$1" x="60.96" y="30.48"/>
+<instance part="P_5" gate="1" x="60.96" y="22.86"/>
+<instance part="P_9" gate="1" x="76.2" y="22.86"/>
+<instance part="P_4" gate="1" x="48.26" y="22.86"/>
+<instance part="TP1" gate="G$1" x="68.58" y="66.04"/>
+<instance part="TP2" gate="G$1" x="68.58" y="68.58"/>
+<instance part="TP3" gate="G$1" x="68.58" y="71.12"/>
+<instance part="TP4" gate="G$1" x="68.58" y="63.5"/>
+<instance part="J2" gate="G$1" x="111.76" y="60.96"/>
+<instance part="P_11" gate="1" x="101.6" y="50.8"/>
+<instance part="J1" gate="G$1" x="20.32" y="27.94" rot="MR0"/>
+<instance part="R1" gate="G$1" x="109.22" y="35.56"/>
+<instance part="LED1" gate="G$1" x="99.06" y="35.56" rot="MR270"/>
+<instance part="R2" gate="G$1" x="109.22" y="25.4"/>
+<instance part="LED2" gate="G$1" x="99.06" y="25.4" rot="MR270"/>
+<instance part="P_12" gate="1" x="114.3" y="22.86"/>
+<instance part="J3" gate="G$1" x="134.62" y="35.56"/>
+<instance part="J4" gate="G$1" x="134.62" y="33.02"/>
+<instance part="J5" gate="G$1" x="134.62" y="30.48"/>
+<instance part="P_13" gate="1" x="129.54" y="27.94"/>
+<instance part="RN1" gate="G$1" x="111.76" y="99.06" rot="MR0"/>
+<instance part="SB1" gate="G$1" x="101.6" y="68.58" rot="R270"/>
+<instance part="IC1" gate="G$1" x="48.26" y="76.2"/>
+<instance part="P_6" gate="1" x="66.04" y="93.98"/>
+<instance part="P_7" gate="1" x="66.04" y="58.42"/>
+<instance part="RN2" gate="G$1" x="111.76" y="86.36" rot="MR0"/>
+<instance part="P_10" gate="1" x="101.6" y="73.66"/>
+</instances>
+<busses>
+</busses>
+<nets>
+<net name="USB_DM" class="0">
+<segment>
+<wire x1="30.48" y1="30.48" x2="27.94" y2="30.48" width="0.1524" layer="91"/>
+<pinref part="J1" gate="G$1" pin="DM"/>
+<label x="30.48" y="30.48" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC1" gate="G$1" pin="PA24/DM"/>
+<wire x1="66.04" y1="78.74" x2="68.58" y2="78.74" width="0.1524" layer="91"/>
+<label x="68.58" y="78.74" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="USB_DP" class="0">
+<segment>
+<wire x1="30.48" y1="27.94" x2="27.94" y2="27.94" width="0.1524" layer="91"/>
+<pinref part="J1" gate="G$1" pin="DP"/>
+<label x="30.48" y="27.94" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC1" gate="G$1" pin="PA25/DP"/>
+<wire x1="66.04" y1="76.2" x2="68.58" y2="76.2" width="0.1524" layer="91"/>
+<label x="68.58" y="76.2" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="GND" class="0">
+<segment>
+<pinref part="P_2" gate="1" pin="GND"/>
+<wire x1="30.48" y1="20.32" x2="30.48" y2="22.86" width="0.1524" layer="91"/>
+<wire x1="30.48" y1="22.86" x2="27.94" y2="22.86" width="0.1524" layer="91"/>
+<pinref part="J1" gate="G$1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="GND"/>
+<pinref part="P_5" gate="1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="C1" gate="G$1" pin="1"/>
+<pinref part="P_4" gate="1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="C2" gate="G$1" pin="1"/>
+<pinref part="P_9" gate="1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="TP4" gate="G$1" pin="1"/>
+<pinref part="IC1" gate="G$1" pin="PAD"/>
+<pinref part="P_7" gate="1" pin="GND"/>
+<pinref part="IC1" gate="G$1" pin="GND"/>
+<wire x1="66.04" y1="60.96" x2="66.04" y2="63.5" width="0.1524" layer="91"/>
+<junction x="66.04" y="60.96"/>
+<wire x1="68.58" y1="63.5" x2="66.04" y2="63.5" width="0.1524" layer="91"/>
+<junction x="66.04" y="63.5"/>
+</segment>
+<segment>
+<pinref part="J2" gate="G$1" pin="3"/>
+<wire x1="104.14" y1="63.5" x2="101.6" y2="63.5" width="0.1524" layer="91"/>
+<pinref part="P_11" gate="1" pin="GND"/>
+<wire x1="101.6" y1="63.5" x2="101.6" y2="60.96" width="0.1524" layer="91"/>
+<pinref part="J2" gate="G$1" pin="5"/>
+<wire x1="101.6" y1="60.96" x2="101.6" y2="55.88" width="0.1524" layer="91"/>
+<wire x1="101.6" y1="55.88" x2="101.6" y2="53.34" width="0.1524" layer="91"/>
+<wire x1="104.14" y1="60.96" x2="101.6" y2="60.96" width="0.1524" layer="91"/>
+<junction x="101.6" y="60.96"/>
+<pinref part="J2" gate="G$1" pin="9"/>
+<wire x1="104.14" y1="55.88" x2="101.6" y2="55.88" width="0.1524" layer="91"/>
+<junction x="101.6" y="55.88"/>
+</segment>
+<segment>
+<pinref part="P_12" gate="1" pin="GND"/>
+<wire x1="114.3" y1="35.56" x2="114.3" y2="25.4" width="0.1524" layer="91"/>
+<pinref part="R1" gate="G$1" pin="2"/>
+<pinref part="R2" gate="G$1" pin="2"/>
+<junction x="114.3" y="25.4"/>
+</segment>
+<segment>
+<pinref part="J5" gate="G$1" pin="1"/>
+<pinref part="P_13" gate="1" pin="GND"/>
+<wire x1="129.54" y1="30.48" x2="132.08" y2="30.48" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="V_USB" class="0">
+<segment>
+<pinref part="P_1" gate="1" pin="V_USB"/>
+<wire x1="30.48" y1="33.02" x2="27.94" y2="33.02" width="0.1524" layer="91"/>
+<pinref part="J1" gate="G$1" pin="VBUS"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="EN"/>
+<pinref part="P_3" gate="1" pin="V_USB"/>
+<wire x1="50.8" y1="30.48" x2="48.26" y2="30.48" width="0.1524" layer="91"/>
+<pinref part="IC2" gate="G$1" pin="IN"/>
+<wire x1="50.8" y1="33.02" x2="48.26" y2="33.02" width="0.1524" layer="91"/>
+<junction x="48.26" y="33.02"/>
+<pinref part="C1" gate="G$1" pin="2"/>
+<wire x1="48.26" y1="33.02" x2="48.26" y2="30.48" width="0.1524" layer="91"/>
+<junction x="48.26" y="30.48"/>
+</segment>
+</net>
+<net name="+3V3" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="OUT"/>
+<wire x1="71.12" y1="33.02" x2="76.2" y2="33.02" width="0.1524" layer="91"/>
+<pinref part="C2" gate="G$1" pin="2"/>
+<wire x1="76.2" y1="30.48" x2="76.2" y2="33.02" width="0.1524" layer="91"/>
+<junction x="76.2" y="33.02"/>
+<pinref part="P_8" gate="1" pin="+3V3"/>
+</segment>
+<segment>
+<pinref part="IC1" gate="G$1" pin="VDD"/>
+<pinref part="P_6" gate="1" pin="+3V3"/>
+</segment>
+<segment>
+<pinref part="SB1" gate="G$1" pin="1"/>
+<pinref part="P_10" gate="1" pin="+3V3"/>
+</segment>
+</net>
+<net name="SWDIO" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="PA31/SIO"/>
+<pinref part="TP1" gate="G$1" pin="1"/>
+<wire x1="66.04" y1="66.04" x2="68.58" y2="66.04" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="SWCLK" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="PA30/SCK"/>
+<pinref part="TP2" gate="G$1" pin="1"/>
+<wire x1="66.04" y1="68.58" x2="68.58" y2="68.58" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="RESET" class="0">
+<segment>
+<pinref part="TP3" gate="G$1" pin="1"/>
+<pinref part="IC1" gate="G$1" pin="PA28/RST"/>
+<wire x1="68.58" y1="71.12" x2="66.04" y2="71.12" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="T_SWDIO_TMS" class="0">
+<segment>
+<pinref part="J2" gate="G$1" pin="2"/>
+<wire x1="119.38" y1="66.04" x2="121.92" y2="66.04" width="0.1524" layer="91"/>
+<label x="121.92" y="66.04" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="RN2" gate="G$1" pin="2"/>
+<wire x1="116.84" y1="86.36" x2="119.38" y2="86.36" width="0.1524" layer="91"/>
+<label x="119.38" y="86.36" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="T_SWCLK_TCK" class="0">
+<segment>
+<pinref part="J2" gate="G$1" pin="4"/>
+<wire x1="121.92" y1="63.5" x2="119.38" y2="63.5" width="0.1524" layer="91"/>
+<label x="121.92" y="63.5" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="RN2" gate="G$1" pin="3"/>
+<wire x1="116.84" y1="83.82" x2="119.38" y2="83.82" width="0.1524" layer="91"/>
+<label x="119.38" y="83.82" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="T_RESET" class="0">
+<segment>
+<pinref part="J2" gate="G$1" pin="10"/>
+<wire x1="119.38" y1="55.88" x2="121.92" y2="55.88" width="0.1524" layer="91"/>
+<label x="121.92" y="55.88" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="RN1" gate="G$1" pin="2"/>
+<wire x1="116.84" y1="99.06" x2="119.38" y2="99.06" width="0.1524" layer="91"/>
+<label x="119.38" y="99.06" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="UART_TX" class="0">
+<segment>
+<pinref part="J4" gate="G$1" pin="1"/>
+<wire x1="132.08" y1="33.02" x2="127" y2="33.02" width="0.1524" layer="91"/>
+<label x="127" y="33.02" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="RN1" gate="G$1" pin="3"/>
+<wire x1="116.84" y1="96.52" x2="119.38" y2="96.52" width="0.1524" layer="91"/>
+<label x="119.38" y="96.52" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="UART_RX" class="0">
+<segment>
+<pinref part="J3" gate="G$1" pin="1"/>
+<wire x1="132.08" y1="35.56" x2="127" y2="35.56" width="0.1524" layer="91"/>
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dap_link/lib/free-dap/hardware/d11_micro_std_vcp_v3/d11_micro_std_vcp_v3.brd

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+<rectangle x1="0.875" y1="1.675" x2="1.625" y2="2.025" layer="29" rot="R270"/>
+<rectangle x1="0.375" y1="1.675" x2="1.125" y2="2.025" layer="29" rot="R270"/>
+<rectangle x1="-0.125" y1="1.675" x2="0.625" y2="2.025" layer="29" rot="R270"/>
+<rectangle x1="-0.625" y1="1.675" x2="0.125" y2="2.025" layer="29" rot="R270"/>
+<rectangle x1="-1.125" y1="1.675" x2="-0.375" y2="2.025" layer="29" rot="R270"/>
+<rectangle x1="-1.625" y1="1.675" x2="-0.875" y2="2.025" layer="29" rot="R270"/>
+</package>
+</packages>
+</library>
+<library name="ataradov_conn">
+<description>Alex Taradov Library (Connectors)</description>
+<packages>
+<package name="HEADER-5X2-1.27MM">
+<wire x1="-3.81" y1="1.905" x2="3.81" y2="1.905" width="0.127" layer="21"/>
+<wire x1="3.81" y1="1.905" x2="3.81" y2="-1.905" width="0.127" layer="21"/>
+<wire x1="3.81" y1="-1.905" x2="-3.175" y2="-1.905" width="0.127" layer="21"/>
+<wire x1="-3.175" y1="-1.905" x2="-3.81" y2="-1.27" width="0.127" layer="21"/>
+<wire x1="-3.81" y1="-1.27" x2="-3.81" y2="1.905" width="0.127" layer="21"/>
+<pad name="1" x="-2.54" y="-0.635" drill="0.6096" diameter="1.016"/>
+<pad name="2" x="-2.54" y="0.635" drill="0.6096" diameter="1.016"/>
+<pad name="3" x="-1.27" y="-0.635" drill="0.6096" diameter="1.016"/>
+<pad name="4" x="-1.27" y="0.635" drill="0.6096" diameter="1.016"/>
+<pad name="5" x="0" y="-0.635" drill="0.6096" diameter="1.016"/>
+<pad name="6" x="0" y="0.635" drill="0.6096" diameter="1.016"/>
+<pad name="7" x="1.27" y="-0.635" drill="0.6096" diameter="1.016"/>
+<pad name="8" x="1.27" y="0.635" drill="0.6096" diameter="1.016"/>
+<pad name="9" x="2.54" y="-0.635" drill="0.6096" diameter="1.016"/>
+<pad name="10" x="2.54" y="0.635" drill="0.6096" diameter="1.016"/>
+<text x="0" y="2.54" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="USB-B-MICRO-SMT-SHELL-TH">
+<pad name="M1" x="2.15" y="-3.6" drill="1.143"/>
+<pad name="M2" x="2.15" y="3.6" drill="1.143"/>
+<smd name="1" x="4.825" y="1.3" dx="1.35" dy="0.4" layer="1" stop="no"/>
+<smd name="2" x="4.825" y="0.65" dx="1.35" dy="0.4" layer="1" stop="no"/>
+<smd name="3" x="4.825" y="0" dx="1.35" dy="0.4" layer="1" stop="no"/>
+<smd name="4" x="4.825" y="-0.65" dx="1.35" dy="0.4" layer="1" stop="no"/>
+<smd name="5" x="4.825" y="-1.3" dx="1.35" dy="0.4" layer="1" stop="no"/>
+<text x="3.175" y="0" size="1.27" layer="25" font="vector" rot="R90" align="bottom-center">&gt;NAME</text>
+<rectangle x1="4.1" y1="1.05" x2="5.55" y2="1.55" layer="29"/>
+<pad name="M3" x="5.05" y="2.425" drill="0.635" shape="long"/>
+<pad name="M4" x="5.05" y="-2.425" drill="0.635" shape="long"/>
+<rectangle x1="4.1" y1="0.4" x2="5.55" y2="0.9" layer="29"/>
+<rectangle x1="4.1" y1="-0.25" x2="5.55" y2="0.25" layer="29"/>
+<rectangle x1="4.1" y1="-0.9" x2="5.55" y2="-0.4" layer="29"/>
+<rectangle x1="4.1" y1="-1.55" x2="5.55" y2="-1.05" layer="29"/>
+<wire x1="-0.5" y1="4" x2="-0.6" y2="3.8" width="0.1524" layer="21"/>
+<wire x1="-0.6" y1="3.8" x2="0" y2="3.5" width="0.1524" layer="21"/>
+<wire x1="0" y1="3.5" x2="0" y2="3.1" width="0.1524" layer="21"/>
+<wire x1="0" y1="3.1" x2="-0.6" y2="3.1" width="0.1524" layer="21"/>
+<wire x1="-0.6" y1="3.1" x2="-0.6" y2="-3.1" width="0.1524" layer="21"/>
+<wire x1="-0.6" y1="-3.1" x2="0" y2="-3.1" width="0.1524" layer="21"/>
+<wire x1="0" y1="-3.1" x2="0" y2="-3.5" width="0.1524" layer="21"/>
+<wire x1="0" y1="-3.5" x2="-0.6" y2="-3.8" width="0.1524" layer="21"/>
+<wire x1="-0.6" y1="-3.8" x2="-0.5" y2="-4" width="0.1524" layer="21"/>
+<wire x1="-0.5" y1="-4" x2="0" y2="-3.75" width="0.1524" layer="21"/>
+<wire x1="0" y1="-3.75" x2="5" y2="-3.75" width="0.1524" layer="21"/>
+<wire x1="5" y1="-3.75" x2="5" y2="-3.16" width="0.1524" layer="21"/>
+<wire x1="-0.5" y1="4" x2="0" y2="3.75" width="0.1524" layer="21"/>
+<wire x1="0" y1="3.75" x2="5" y2="3.75" width="0.1524" layer="21"/>
+<wire x1="5" y1="3.75" x2="5" y2="3.16" width="0.1524" layer="21"/>
+</package>
+<package name="PIN-TH">
+<wire x1="-0.635" y1="1.27" x2="0.635" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="0.635" y1="1.27" x2="1.27" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="1.27" y1="0.635" x2="1.27" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="1.27" y1="-0.635" x2="0.635" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-1.27" y1="0.635" x2="-1.27" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-0.635" y1="1.27" x2="-1.27" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-1.27" y1="-0.635" x2="-0.635" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="0.635" y1="-1.27" x2="-0.635" y2="-1.27" width="0.1524" layer="21"/>
+<pad name="1" x="0" y="0" drill="1.016"/>
+<text x="0" y="1.524" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-2.794" size="1.27" layer="21" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+</packages>
+</library>
+<library name="ataradov_rlc">
+<description>Alex Taradov Library (R, L and C)</description>
+<packages>
+<package name="SMD0603">
+<wire x1="-1.5" y1="0.75" x2="1.5" y2="0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="0.75" x2="1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="-0.75" x2="-1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="-1.5" y1="-0.75" x2="-1.5" y2="0.75" width="0.1" layer="21"/>
+<smd name="1" x="-0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<smd name="2" x="0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+</packages>
+</library>
+<library name="ataradov_vreg">
+<description>Alex Taradov Library (Voltage Regulators)</description>
+<packages>
+<package name="SOT23-5">
+<description>SOT23-5</description>
+<wire x1="1.422" y1="0.81" x2="1.422" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="1.422" y1="-0.81" x2="-1.422" y2="-0.81" width="0.1524" layer="51"/>
+<wire x1="-1.422" y1="-0.81" x2="-1.422" y2="0.81" width="0.1524" layer="21"/>
+<wire x1="-1.422" y1="0.81" x2="1.422" y2="0.81" width="0.1524" layer="51"/>
+<wire x1="-0.522" y1="0.81" x2="0.522" y2="0.81" width="0.1524" layer="21"/>
+<wire x1="-0.428" y1="-0.81" x2="-0.522" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="0.522" y1="-0.81" x2="0.428" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="-1.328" y1="-0.81" x2="-1.422" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="1.422" y1="-0.81" x2="1.328" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="1.328" y1="0.81" x2="1.422" y2="0.81" width="0.1524" layer="21"/>
+<wire x1="-1.422" y1="0.81" x2="-1.328" y2="0.81" width="0.1524" layer="21"/>
+<smd name="1" x="-0.95" y="-1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="2" x="0" y="-1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="3" x="0.95" y="-1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="4" x="0.95" y="1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="5" x="-0.95" y="1.3" dx="0.55" dy="1.2" layer="1"/>
+<text x="0" y="2.286" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+</packages>
+</library>
+<library name="ataradov_misc">
+<description>Alex Taradov Library (Miscellaneous stuff)</description>
+<packages>
+<package name="TP-1.27MM">
+<smd name="1" x="0" y="0" dx="1.27" dy="1.27" layer="1" roundness="100" cream="no"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SB-1.27MM-NO">
+<smd name="1" x="-0.508" y="0" dx="0.762" dy="1.27" layer="1" cream="no"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-2.286" size="1.27" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+<smd name="2" x="0.508" y="0" dx="0.762" dy="1.27" layer="1" cream="no"/>
+<rectangle x1="-1.016" y1="-0.762" x2="1.016" y2="0.762" layer="29"/>
+</package>
+</packages>
+</library>
+<library name="ataradov_led">
+<description>Alex Taradov Library (LEDs and other indication devices)</description>
+<packages>
+<package name="SMD0603">
+<wire x1="-1.5" y1="0.75" x2="1.5" y2="0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="0.75" x2="1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="-0.75" x2="-1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="-1.5" y1="-0.75" x2="-1.5" y2="0.75" width="0.1" layer="21"/>
+<smd name="1" x="-0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<smd name="2" x="0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+</packages>
+</library>
+</libraries>
+<attributes>
+</attributes>
+<variantdefs>
+</variantdefs>
+<classes>
+<class number="0" name="default" width="0" drill="0">
+</class>
+</classes>
+<designrules name="std-tented-new">
+<description language="de">&lt;b&gt;EAGLE Design Rules&lt;/b&gt;
+&lt;p&gt;
+Die Standard-Design-Rules sind so gewählt, dass sie für 
+die meisten Anwendungen passen. Sollte ihre Platine 
+besondere Anforderungen haben, treffen Sie die erforderlichen
+Einstellungen hier und speichern die Design Rules unter 
+einem neuen Namen ab.</description>
+<description language="en">&lt;b&gt;Laen's PCB Order Design Rules&lt;/b&gt;
+&lt;p&gt;
+Please make sure your boards conform to these design rules.</description>
+<param name="layerSetup" value="(1*16)"/>
+<param name="mtCopper" value="0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm"/>
+<param name="mtIsolate" value="1.5011mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm"/>
+<param name="mdWireWire" value="6mil"/>
+<param name="mdWirePad" value="6mil"/>
+<param name="mdWireVia" value="6mil"/>
+<param name="mdPadPad" value="6mil"/>
+<param name="mdPadVia" value="6mil"/>
+<param name="mdViaVia" value="6mil"/>
+<param name="mdSmdPad" value="0mil"/>
+<param name="mdSmdVia" value="0mil"/>
+<param name="mdSmdSmd" value="0mil"/>
+<param name="mdViaViaSameLayer" value="8mil"/>
+<param name="mnLayersViaInSmd" value="2"/>
+<param name="mdCopperDimension" value="10mil"/>
+<param name="mdDrill" value="6mil"/>
+<param name="mdSmdStop" value="0mil"/>
+<param name="msWidth" value="8mil"/>
+<param name="msDrill" value="13mil"/>
+<param name="msMicroVia" value="13mil"/>
+<param name="msBlindViaRatio" value="0.5"/>
+<param name="rvPadTop" value="0.25"/>
+<param name="rvPadInner" value="0.25"/>
+<param name="rvPadBottom" value="0.25"/>
+<param name="rvViaOuter" value="0.25"/>
+<param name="rvViaInner" value="0.25"/>
+<param name="rvMicroViaOuter" value="0.25"/>
+<param name="rvMicroViaInner" value="0.25"/>
+<param name="rlMinPadTop" value="7mil"/>
+<param name="rlMaxPadTop" value="20mil"/>
+<param name="rlMinPadInner" value="7mil"/>
+<param name="rlMaxPadInner" value="20mil"/>
+<param name="rlMinPadBottom" value="7mil"/>
+<param name="rlMaxPadBottom" value="20mil"/>
+<param name="rlMinViaOuter" value="7mil"/>
+<param name="rlMaxViaOuter" value="20mil"/>
+<param name="rlMinViaInner" value="7mil"/>
+<param name="rlMaxViaInner" value="20mil"/>
+<param name="rlMinMicroViaOuter" value="4mil"/>
+<param name="rlMaxMicroViaOuter" value="20mil"/>
+<param name="rlMinMicroViaInner" value="4mil"/>
+<param name="rlMaxMicroViaInner" value="20mil"/>
+<param name="psTop" value="-1"/>
+<param name="psBottom" value="-1"/>
+<param name="psFirst" value="-1"/>
+<param name="psElongationLong" value="100"/>
+<param name="psElongationOffset" value="100"/>
+<param name="mvStopFrame" value="1"/>
+<param name="mvCreamFrame" value="0"/>
+<param name="mlMinStopFrame" value="3mil"/>
+<param name="mlMaxStopFrame" value="3mil"/>
+<param name="mlMinCreamFrame" value="0mil"/>
+<param name="mlMaxCreamFrame" value="0mil"/>
+<param name="mlViaStopLimit" value="25mil"/>
+<param name="srRoundness" value="0"/>
+<param name="srMinRoundness" value="0mil"/>
+<param name="srMaxRoundness" value="0mil"/>
+<param name="slThermalIsolate" value="6mil"/>
+<param name="slThermalsForVias" value="0"/>
+<param name="dpMaxLengthDifference" value="10mm"/>
+<param name="dpGapFactor" value="2.5"/>
+<param name="checkGrid" value="0"/>
+<param name="checkAngle" value="0"/>
+<param name="checkFont" value="1"/>
+<param name="checkRestrict" value="1"/>
+<param name="useDiameter" value="13"/>
+<param name="maxErrors" value="50"/>
+</designrules>
+<autorouter>
+<pass name="Default">
+<param name="RoutingGrid" value="50mil"/>
+<param name="AutoGrid" value="1"/>
+<param name="Efforts" value="0"/>
+<param name="TopRouterVariant" value="1"/>
+<param name="tpViaShape" value="round"/>
+<param name="PrefDir.1" value="a"/>
+<param name="PrefDir.2" value="0"/>
+<param name="PrefDir.3" value="0"/>
+<param name="PrefDir.4" value="0"/>
+<param name="PrefDir.5" value="0"/>
+<param name="PrefDir.6" value="0"/>
+<param name="PrefDir.7" value="0"/>
+<param name="PrefDir.8" value="0"/>
+<param name="PrefDir.9" value="0"/>
+<param name="PrefDir.10" value="0"/>
+<param name="PrefDir.11" value="0"/>
+<param name="PrefDir.12" value="0"/>
+<param name="PrefDir.13" value="0"/>
+<param name="PrefDir.14" value="0"/>
+<param name="PrefDir.15" value="0"/>
+<param name="PrefDir.16" value="a"/>
+<param name="cfVia" value="8"/>
+<param name="cfNonPref" value="5"/>
+<param name="cfChangeDir" value="2"/>
+<param name="cfOrthStep" value="2"/>
+<param name="cfDiagStep" value="3"/>
+<param name="cfExtdStep" value="0"/>
+<param name="cfBonusStep" value="1"/>
+<param name="cfMalusStep" value="1"/>
+<param name="cfPadImpact" value="4"/>
+<param name="cfSmdImpact" value="4"/>
+<param name="cfBusImpact" value="0"/>
+<param name="cfHugging" value="3"/>
+<param name="cfAvoid" value="4"/>
+<param name="cfPolygon" value="10"/>
+<param name="cfBase.1" value="0"/>
+<param name="cfBase.2" value="1"/>
+<param name="cfBase.3" value="1"/>
+<param name="cfBase.4" value="1"/>
+<param name="cfBase.5" value="1"/>
+<param name="cfBase.6" value="1"/>
+<param name="cfBase.7" value="1"/>
+<param name="cfBase.8" value="1"/>
+<param name="cfBase.9" value="1"/>
+<param name="cfBase.10" value="1"/>
+<param name="cfBase.11" value="1"/>
+<param name="cfBase.12" value="1"/>
+<param name="cfBase.13" value="1"/>
+<param name="cfBase.14" value="1"/>
+<param name="cfBase.15" value="1"/>
+<param name="cfBase.16" value="0"/>
+<param name="mnVias" value="20"/>
+<param name="mnSegments" value="9999"/>
+<param name="mnExtdSteps" value="9999"/>
+<param name="mnRipupLevel" value="10"/>
+<param name="mnRipupSteps" value="100"/>
+<param name="mnRipupTotal" value="100"/>
+</pass>
+<pass name="Follow-me" refer="Default" active="yes">
+</pass>
+<pass name="Busses" refer="Default" active="yes">
+<param name="cfNonPref" value="4"/>
+<param name="cfBusImpact" value="4"/>
+<param name="cfHugging" value="0"/>
+<param name="mnVias" value="0"/>
+</pass>
+<pass name="Route" refer="Default" active="yes">
+</pass>
+<pass name="Optimize1" refer="Default" active="yes">
+<param name="cfVia" value="99"/>
+<param name="cfExtdStep" value="10"/>
+<param name="cfHugging" value="1"/>
+<param name="mnExtdSteps" value="1"/>
+<param name="mnRipupLevel" value="0"/>
+</pass>
+<pass name="Optimize2" refer="Optimize1" active="yes">
+<param name="cfNonPref" value="0"/>
+<param name="cfChangeDir" value="6"/>
+<param name="cfExtdStep" value="0"/>
+<param name="cfBonusStep" value="2"/>
+<param name="cfMalusStep" value="2"/>
+<param name="cfPadImpact" value="2"/>
+<param name="cfSmdImpact" value="2"/>
+<param name="cfHugging" value="0"/>
+</pass>
+<pass name="Optimize3" refer="Optimize2" active="yes">
+<param name="cfChangeDir" value="8"/>
+<param name="cfPadImpact" value="0"/>
+<param name="cfSmdImpact" value="0"/>
+</pass>
+<pass name="Optimize4" refer="Optimize3" active="yes">
+<param name="cfChangeDir" value="25"/>
+</pass>
+</autorouter>
+<elements>
+<element name="C1" library="ataradov_rlc" package="SMD0603" value="1uF" x="1.27" y="5.588" rot="MR270"/>
+<element name="C2" library="ataradov_rlc" package="SMD0603" value="1uF" x="6.858" y="5.588" smashed="yes" rot="MR270">
+<attribute name="NAME" x="5.842" y="5.588" size="1.27" layer="26" font="vector" rot="MR270" align="bottom-center"/>
+</element>
+<element name="IC2" library="ataradov_vreg" package="SOT23-5" value="MIC5504-3.3" x="4.064" y="5.588" smashed="yes" rot="MR90">
+<attribute name="NAME" x="6.35" y="5.588" size="1.27" layer="26" font="vector" rot="MR90" align="bottom-center"/>
+</element>
+<element name="TP1" library="ataradov_misc" package="TP-1.27MM" value="SIO" x="6.604" y="9.652" rot="MR0"/>
+<element name="TP2" library="ataradov_misc" package="TP-1.27MM" value="" x="11.684" y="9.652" rot="MR0"/>
+<element name="TP3" library="ataradov_misc" package="TP-1.27MM" value="" x="9.144" y="9.652" rot="MR0"/>
+<element name="TP4" library="ataradov_misc" package="TP-1.27MM" value="" x="4.064" y="9.652" rot="MR0"/>
+<element name="J2" library="ataradov_conn" package="HEADER-5X2-1.27MM" value="HEADER-5X2-TH-1.27" x="13.462" y="5.588" rot="R90"/>
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+<contactref element="TP3" pad="1"/>
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+<signal name="T_SWDIO_TMS">
+<contactref element="J2" pad="2"/>
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+<signal name="T_SWCLK_TCK">
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+</signal>
+<signal name="T_RESET">
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+<signal name="UART_TX">
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+</signal>
+<signal name="N$2">
+<contactref element="R1" pad="1"/>
+<contactref element="LED1" pad="2"/>
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+<signal name="N$3">
+<contactref element="R2" pad="1"/>
+<contactref element="LED2" pad="2"/>
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+<signal name="LED_A">
+<contactref element="LED1" pad="1"/>
+<contactref element="IC1" pad="2"/>
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+<signal name="LED_B">
+<contactref element="LED2" pad="1"/>
+<contactref element="IC1" pad="5"/>
+<wire x1="9.894" y1="4.5" x2="9.894" y2="3.098" width="0.254" layer="1"/>
+<wire x1="9.894" y1="3.098" x2="9.906" y2="3.086" width="0.254" layer="1"/>
+</signal>
+<signal name="T_VREF">
+<contactref element="J2" pad="1"/>
+<contactref element="SB1" pad="2"/>
+<wire x1="13.97" y1="1.524" x2="13.97" y2="2.921" width="0.254" layer="16"/>
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+</signal>
+</signals>
+</board>
+</drawing>
+</eagle>

dap_link/lib/free-dap/hardware/d11_micro_std_vcp_v3/d11_micro_std_vcp_v3.sch

@@ -0,0 +1,1443 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="7.3.0">
+<drawing>
+<settings>
+<setting alwaysvectorfont="no"/>
+<setting verticaltext="up"/>
+</settings>
+<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>
+<layers>
+<layer number="1" name="Top" color="4" fill="1" visible="no" active="no"/>
+<layer number="16" name="Bottom" color="1" fill="1" visible="no" active="no"/>
+<layer number="17" name="Pads" color="2" fill="1" visible="no" active="no"/>
+<layer number="18" name="Vias" color="2" fill="1" visible="no" active="no"/>
+<layer number="19" name="Unrouted" color="6" fill="1" visible="no" active="no"/>
+<layer number="20" name="Dimension" color="15" fill="1" visible="no" active="no"/>
+<layer number="21" name="tPlace" color="7" fill="1" visible="no" active="no"/>
+<layer number="22" name="bPlace" color="7" fill="1" visible="no" active="no"/>
+<layer number="23" name="tOrigins" color="15" fill="1" visible="no" active="no"/>
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+<layer number="25" name="tNames" color="7" fill="1" visible="no" active="no"/>
+<layer number="26" name="bNames" color="7" fill="1" visible="no" active="no"/>
+<layer number="27" name="tValues" color="7" fill="1" visible="no" active="no"/>
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+<layer number="30" name="bStop" color="7" fill="6" visible="no" active="no"/>
+<layer number="31" name="tCream" color="7" fill="4" visible="no" active="no"/>
+<layer number="32" name="bCream" color="7" fill="5" visible="no" active="no"/>
+<layer number="33" name="tFinish" color="6" fill="3" visible="no" active="no"/>
+<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="no"/>
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+<layer number="38" name="bTest" color="7" fill="1" visible="no" active="no"/>
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+<layer number="92" name="Busses" color="1" fill="1" visible="yes" active="yes"/>
+<layer number="93" name="Pins" color="2" fill="1" visible="no" active="yes"/>
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+<layer number="95" name="Names" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="96" name="Values" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="97" name="Info" color="7" fill="1" visible="yes" active="yes"/>
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+</layers>
+<schematic xreflabel="%F%N/%S.%C%R" xrefpart="/%S.%C%R">
+<libraries>
+<library name="ataradov_mcu">
+<description>Alex Taradov Library (MCUs)</description>
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+</package>
+</packages>
+<symbols>
+<symbol name="ATSAMDXXD">
+<description>Atmel SAM D09D/D10D/D11D Cortex-M0+ microcontroller</description>
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+<pin name="PA02" x="-17.78" y="15.24" length="middle" direction="pas"/>
+<text x="0" y="18.542" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-19.812" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+<pin name="PA30/SCK" x="17.78" y="-7.62" length="middle" direction="pas" rot="R180"/>
+<pin name="VDD" x="17.78" y="15.24" length="middle" direction="pas" rot="R180"/>
+<pin name="GND" x="17.78" y="-12.7" length="middle" direction="pas" rot="R180"/>
+<pin name="PA25/DP" x="17.78" y="0" length="middle" direction="pas" rot="R180"/>
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+<pin name="PAD" x="17.78" y="-15.24" length="middle" direction="pas" rot="R180"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="ATSAMD11D" prefix="IC">
+<gates>
+<gate name="G$1" symbol="ATSAMDXXD" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="QFN24">
+<connects>
+<connect gate="G$1" pin="GND" pad="23"/>
+<connect gate="G$1" pin="PA02" pad="1"/>
+<connect gate="G$1" pin="PA03" pad="2"/>
+<connect gate="G$1" pin="PA04" pad="3"/>
+<connect gate="G$1" pin="PA05" pad="4"/>
+<connect gate="G$1" pin="PA06" pad="5"/>
+<connect gate="G$1" pin="PA07" pad="6"/>
+<connect gate="G$1" pin="PA08" pad="7"/>
+<connect gate="G$1" pin="PA09" pad="8"/>
+<connect gate="G$1" pin="PA10" pad="9"/>
+<connect gate="G$1" pin="PA11" pad="10"/>
+<connect gate="G$1" pin="PA14" pad="11"/>
+<connect gate="G$1" pin="PA15" pad="12"/>
+<connect gate="G$1" pin="PA16" pad="13"/>
+<connect gate="G$1" pin="PA17" pad="14"/>
+<connect gate="G$1" pin="PA22" pad="15"/>
+<connect gate="G$1" pin="PA23" pad="16"/>
+<connect gate="G$1" pin="PA24/DM" pad="21"/>
+<connect gate="G$1" pin="PA25/DP" pad="22"/>
+<connect gate="G$1" pin="PA27" pad="17"/>
+<connect gate="G$1" pin="PA28/RST" pad="18"/>
+<connect gate="G$1" pin="PA30/SCK" pad="19"/>
+<connect gate="G$1" pin="PA31/SIO" pad="20"/>
+<connect gate="G$1" pin="PAD" pad="PAD"/>
+<connect gate="G$1" pin="VDD" pad="24"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_pwr">
+<description>Alex Taradov Library (Power Symbols)</description>
+<packages>
+</packages>
+<symbols>
+<symbol name="+3V3">
+<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/>
+<text x="0" y="0.762" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+<pin name="+3V3" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/>
+</symbol>
+<symbol name="GND">
+<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/>
+<text x="0" y="-2.032" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+<pin name="GND" x="0" y="2.54" visible="off" length="short" direction="sup" rot="R270"/>
+</symbol>
+<symbol name="V_USB">
+<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/>
+<text x="0" y="0.762" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+<pin name="V_USB" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="+3V3" prefix="P_">
+<gates>
+<gate name="1" symbol="+3V3" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="GND" prefix="P_">
+<gates>
+<gate name="1" symbol="GND" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="V_USB" prefix="P_">
+<gates>
+<gate name="1" symbol="V_USB" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_conn">
+<description>Alex Taradov Library (Connectors)</description>
+<packages>
+<package name="HEADER-5X2-1.27MM">
+<wire x1="-3.81" y1="1.905" x2="3.81" y2="1.905" width="0.127" layer="21"/>
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+<text x="0" y="2.54" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="HEADER-5X2-2.54MM">
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+<text x="0" y="3.175" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="USB-B-MICRO-SMT-SHELL-TH">
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+<text x="3.175" y="0" size="1.27" layer="25" font="vector" rot="R90" align="bottom-center">&gt;NAME</text>
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+<package name="PIN-TH">
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+</package>
+<package name="PIN-TH-SMALL">
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+<pad name="1" x="0" y="0" drill="0.9"/>
+<text x="0" y="1.524" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-2.794" size="1.27" layer="21" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+</packages>
+<symbols>
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+<text x="0" y="8.382" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+</symbol>
+<symbol name="MICRO-USB-5">
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+<text x="0.762" y="8.382" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<pin name="VBUS" x="-7.62" y="5.08" visible="pin" length="short" direction="pas"/>
+<pin name="DM" x="-7.62" y="2.54" visible="pin" length="short" direction="pas"/>
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+<pin name="ID" x="-7.62" y="-2.54" visible="pin" length="short" direction="pas"/>
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+<pin name="SHIELD" x="-7.62" y="-7.62" visible="pin" length="short" direction="pas"/>
+<text x="0.762" y="-12.192" size="1.27" layer="95" align="bottom-center">&gt;VALUE</text>
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+<symbol name="CONN-SINGLE">
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+<pin name="1" x="-2.54" y="0" visible="off" length="short" direction="pas" swaplevel="1"/>
+<text x="1.27" y="-0.508" size="1.27" layer="95">&gt;NAME</text>
+<text x="6.096" y="-0.508" size="1.27" layer="96">&gt;VALUE</text>
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+</symbols>
+<devicesets>
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+</gates>
+<devices>
+<device name="-TH-1.27" package="HEADER-5X2-1.27MM">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="10" pad="10"/>
+<connect gate="G$1" pin="2" pad="2"/>
+<connect gate="G$1" pin="3" pad="3"/>
+<connect gate="G$1" pin="4" pad="4"/>
+<connect gate="G$1" pin="5" pad="5"/>
+<connect gate="G$1" pin="6" pad="6"/>
+<connect gate="G$1" pin="7" pad="7"/>
+<connect gate="G$1" pin="8" pad="8"/>
+<connect gate="G$1" pin="9" pad="9"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-TH-1.27-SHR" package="HEADER-5X2-1.27MM-SHR">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="10" pad="10"/>
+<connect gate="G$1" pin="2" pad="2"/>
+<connect gate="G$1" pin="3" pad="3"/>
+<connect gate="G$1" pin="4" pad="4"/>
+<connect gate="G$1" pin="5" pad="5"/>
+<connect gate="G$1" pin="6" pad="6"/>
+<connect gate="G$1" pin="7" pad="7"/>
+<connect gate="G$1" pin="8" pad="8"/>
+<connect gate="G$1" pin="9" pad="9"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-TH-2.54-SHR-RA" package="HEADER-5X2-2.54MM-SHR-RA">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="10" pad="10"/>
+<connect gate="G$1" pin="2" pad="2"/>
+<connect gate="G$1" pin="3" pad="3"/>
+<connect gate="G$1" pin="4" pad="4"/>
+<connect gate="G$1" pin="5" pad="5"/>
+<connect gate="G$1" pin="6" pad="6"/>
+<connect gate="G$1" pin="7" pad="7"/>
+<connect gate="G$1" pin="8" pad="8"/>
+<connect gate="G$1" pin="9" pad="9"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-TH-2.54" package="HEADER-5X2-2.54MM">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="10" pad="10"/>
+<connect gate="G$1" pin="2" pad="2"/>
+<connect gate="G$1" pin="3" pad="3"/>
+<connect gate="G$1" pin="4" pad="4"/>
+<connect gate="G$1" pin="5" pad="5"/>
+<connect gate="G$1" pin="6" pad="6"/>
+<connect gate="G$1" pin="7" pad="7"/>
+<connect gate="G$1" pin="8" pad="8"/>
+<connect gate="G$1" pin="9" pad="9"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="USB-B-MICRO" prefix="J" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="MICRO-USB-5" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-SMT" package="USB-B-MICRO-SMT-SHELL-TH">
+<connects>
+<connect gate="G$1" pin="DM" pad="2"/>
+<connect gate="G$1" pin="DP" pad="3"/>
+<connect gate="G$1" pin="GND" pad="5"/>
+<connect gate="G$1" pin="ID" pad="4"/>
+<connect gate="G$1" pin="SHIELD" pad="M1 M2 M3 M4" route="any"/>
+<connect gate="G$1" pin="VBUS" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="CONN-SINGLE" prefix="J" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="CONN-SINGLE" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-TH" package="PIN-TH">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-TH-LARGE" package="PIN-TH-LARGE">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-TH-SMALL" package="PIN-TH-SMALL">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_rlc">
+<description>Alex Taradov Library (R, L and C)</description>
+<packages>
+<package name="SMD0508">
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+<text x="0" y="1.524" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
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+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+<package name="SMD0612">
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+<text x="0" y="1.778" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
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+</package>
+<package name="SMD2512">
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+<text x="0" y="2.794" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SMD0402">
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+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+<package name="SMD0805">
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+<text x="0" y="1.27" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+</packages>
+<symbols>
+<symbol name="C">
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+<wire x1="2.54" y1="0" x2="0.762" y2="0" width="0.1524" layer="94"/>
+<pin name="1" x="-2.54" y="0" visible="off" length="point" direction="pas" swaplevel="1"/>
+<pin name="2" x="2.54" y="0" visible="off" length="point" direction="pas" swaplevel="1" rot="R180"/>
+<text x="0" y="2.413" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-3.683" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+</symbol>
+<symbol name="R">
+<wire x1="-2.54" y1="-1.016" x2="-2.54" y2="1.016" width="0.254" layer="94"/>
+<pin name="1" x="-5.08" y="0" visible="off" length="short" direction="pas" swaplevel="1"/>
+<pin name="2" x="5.08" y="0" visible="off" length="short" direction="pas" swaplevel="1" rot="R180"/>
+<text x="0" y="1.524" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<text x="0" y="0" size="1.016" layer="96" align="center">&gt;VALUE</text>
+<wire x1="2.54" y1="-1.016" x2="2.54" y2="1.016" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="1.016" x2="2.54" y2="1.016" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="-1.016" x2="2.54" y2="-1.016" width="0.254" layer="94"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="C" prefix="C" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="C" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-0402" package="SMD0402">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0508" package="SMD0508">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0603" package="SMD0603">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0612" package="SMD0612">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0805" package="SMD0805">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-1206" package="SMD1206">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-2512" package="SMD2512">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="R" prefix="R" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="R" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-0402" package="SMD0402">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0508" package="SMD0508">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0603" package="SMD0603">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0612" package="SMD0612">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0805" package="SMD0805">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-1206" package="SMD1206">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-2512" package="SMD2512">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_vreg">
+<description>Alex Taradov Library (Voltage Regulators)</description>
+<packages>
+<package name="SOT23-5">
+<description>SOT23-5</description>
+<wire x1="1.422" y1="0.81" x2="1.422" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="1.422" y1="-0.81" x2="-1.422" y2="-0.81" width="0.1524" layer="51"/>
+<wire x1="-1.422" y1="-0.81" x2="-1.422" y2="0.81" width="0.1524" layer="21"/>
+<wire x1="-1.422" y1="0.81" x2="1.422" y2="0.81" width="0.1524" layer="51"/>
+<wire x1="-0.522" y1="0.81" x2="0.522" y2="0.81" width="0.1524" layer="21"/>
+<wire x1="-0.428" y1="-0.81" x2="-0.522" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="0.522" y1="-0.81" x2="0.428" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="-1.328" y1="-0.81" x2="-1.422" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="1.422" y1="-0.81" x2="1.328" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="1.328" y1="0.81" x2="1.422" y2="0.81" width="0.1524" layer="21"/>
+<wire x1="-1.422" y1="0.81" x2="-1.328" y2="0.81" width="0.1524" layer="21"/>
+<smd name="1" x="-0.95" y="-1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="2" x="0" y="-1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="3" x="0.95" y="-1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="4" x="0.95" y="1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="5" x="-0.95" y="1.3" dx="0.55" dy="1.2" layer="1"/>
+<text x="0" y="2.286" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+</packages>
+<symbols>
+<symbol name="VREG-3-EN">
+<wire x1="-7.62" y1="5.08" x2="7.62" y2="5.08" width="0.254" layer="94"/>
+<wire x1="7.62" y1="5.08" x2="7.62" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="7.62" y1="-2.54" x2="-7.62" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="-7.62" y1="-2.54" x2="-7.62" y2="5.08" width="0.254" layer="94"/>
+<text x="-2.032" y="-1.524" size="1.524" layer="95">GND</text>
+<text x="0" y="5.842" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<text x="1.524" y="-4.318" size="1.27" layer="96">&gt;VALUE</text>
+<pin name="IN" x="-10.16" y="2.54" length="short" direction="pas"/>
+<pin name="OUT" x="10.16" y="2.54" length="short" direction="pas" rot="R180"/>
+<pin name="GND" x="0" y="-5.08" visible="pad" length="short" direction="pas" rot="R90"/>
+<pin name="EN" x="-10.16" y="0" length="short" direction="pas"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="MIC5504" prefix="IC" uservalue="yes">
+<description>LM1117 voltage regulator</description>
+<gates>
+<gate name="G$1" symbol="VREG-3-EN" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-SOT23-5" package="SOT23-5">
+<connects>
+<connect gate="G$1" pin="EN" pad="3"/>
+<connect gate="G$1" pin="GND" pad="2"/>
+<connect gate="G$1" pin="IN" pad="1"/>
+<connect gate="G$1" pin="OUT" pad="5"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_misc">
+<description>Alex Taradov Library (Miscellaneous stuff)</description>
+<packages>
+<package name="TP-1.27MM">
+<smd name="1" x="0" y="0" dx="1.27" dy="1.27" layer="1" roundness="100" cream="no"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="TP-2.54MM">
+<smd name="1" x="0" y="0" dx="2.54" dy="2.54" layer="1" roundness="100" cream="no"/>
+<text x="0" y="1.778" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SB-1.27MM-NO">
+<smd name="1" x="-0.508" y="0" dx="0.762" dy="1.27" layer="1" cream="no"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-2.286" size="1.27" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+<smd name="2" x="0.508" y="0" dx="0.762" dy="1.27" layer="1" cream="no"/>
+<rectangle x1="-1.016" y1="-0.762" x2="1.016" y2="0.762" layer="29"/>
+</package>
+<package name="TP-0.635MM">
+<smd name="1" x="0" y="0" dx="0.635" dy="0.635" layer="1" roundness="100" cream="no"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="TP-0.5MM">
+<smd name="1" x="0" y="0" dx="0.5" dy="0.5" layer="1" roundness="100" cream="no"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="TP-1.27MM-TH">
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<pad name="1" x="0" y="0" drill="0.762" diameter="1.27"/>
+</package>
+</packages>
+<symbols>
+<symbol name="TP">
+<text x="4.064" y="-0.508" size="1.27" layer="95">&gt;NAME</text>
+<pin name="1" x="0" y="0" visible="off" length="short" direction="pas"/>
+<circle x="3.048" y="0" radius="0.508" width="0" layer="94"/>
+</symbol>
+<symbol name="SB">
+<wire x1="0.381" y1="0.381" x2="0.381" y2="-0.381" width="0.762" layer="94" curve="-180" cap="flat"/>
+<wire x1="-0.381" y1="-0.381" x2="-0.381" y2="0.381" width="0.762" layer="94" curve="-180" cap="flat"/>
+<wire x1="2.54" y1="0" x2="1.143" y2="0" width="0.1524" layer="94"/>
+<wire x1="-2.54" y1="0" x2="-1.143" y2="0" width="0.1524" layer="94"/>
+<text x="0" y="1.778" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<pin name="2" x="2.54" y="0" visible="off" length="point" direction="pas" swaplevel="1" rot="R180"/>
+<pin name="1" x="-2.54" y="0" visible="off" length="point" direction="pas" swaplevel="1"/>
+<text x="0" y="-3.048" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="TEST-POINT" prefix="TP" uservalue="yes">
+<description>Test Point</description>
+<gates>
+<gate name="G$1" symbol="TP" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-1.27MM" package="TP-1.27MM">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0.635MM" package="TP-0.635MM">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0.5MM" package="TP-0.5MM">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-2.54MM" package="TP-2.54MM">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-1.27MM-TH" package="TP-1.27MM-TH">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="SOLDER-BRIDGE" prefix="SB" uservalue="yes">
+<description>Solder Bridge</description>
+<gates>
+<gate name="G$1" symbol="SB" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-1.27MM-NO" package="SB-1.27MM-NO">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_led">
+<description>Alex Taradov Library (LEDs and other indication devices)</description>
+<packages>
+<package name="SMD0603">
+<wire x1="-1.5" y1="0.75" x2="1.5" y2="0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="0.75" x2="1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="-0.75" x2="-1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="-1.5" y1="-0.75" x2="-1.5" y2="0.75" width="0.1" layer="21"/>
+<smd name="1" x="-0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<smd name="2" x="0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+<package name="SMD0805">
+<wire x1="-2" y1="1" x2="2" y2="1" width="0.1" layer="21"/>
+<wire x1="2" y1="1" x2="2" y2="-1" width="0.1" layer="21"/>
+<wire x1="2" y1="-1" x2="-2" y2="-1" width="0.1" layer="21"/>
+<wire x1="-2" y1="-1" x2="-2" y2="1" width="0.1" layer="21"/>
+<smd name="1" x="-0.95" y="0" dx="1.3" dy="1.5" layer="1"/>
+<smd name="2" x="0.95" y="0" dx="1.3" dy="1.5" layer="1"/>
+<text x="0" y="1.27" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+</packages>
+<symbols>
+<symbol name="LED">
+<wire x1="1.27" y1="0" x2="0" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="0" y1="-2.54" x2="-1.27" y2="0" width="0.254" layer="94"/>
+<wire x1="1.27" y1="-2.54" x2="0" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="0" y1="-2.54" x2="-1.27" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="1.27" y1="0" x2="0" y2="0" width="0.254" layer="94"/>
+<wire x1="0" y1="0" x2="-1.27" y2="0" width="0.254" layer="94"/>
+<wire x1="-2.032" y1="-0.762" x2="-3.429" y2="-2.159" width="0.1524" layer="94"/>
+<wire x1="-1.905" y1="-1.905" x2="-3.302" y2="-3.302" width="0.1524" layer="94"/>
+<text x="3.556" y="-2.032" size="1.27" layer="95" rot="R90" align="bottom-center">&gt;NAME</text>
+<text x="5.715" y="-2.032" size="1.27" layer="96" rot="R90" align="bottom-center">&gt;VALUE</text>
+<pin name="C" x="0" y="-5.08" visible="off" length="short" direction="pas" rot="R90"/>
+<pin name="A" x="0" y="2.54" visible="off" length="short" direction="pas" rot="R270"/>
+<polygon width="0.1524" layer="94">
+<vertex x="-3.429" y="-2.159"/>
+<vertex x="-3.048" y="-1.27"/>
+<vertex x="-2.54" y="-1.778"/>
+</polygon>
+<polygon width="0.1524" layer="94">
+<vertex x="-3.302" y="-3.302"/>
+<vertex x="-2.921" y="-2.413"/>
+<vertex x="-2.413" y="-2.921"/>
+</polygon>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="LED_SMD" prefix="LED" uservalue="yes">
+<description>SMD_LED</description>
+<gates>
+<gate name="G$1" symbol="LED" x="0" y="0"/>
+</gates>
+<devices>
+<device name="LED_0603" package="SMD0603">
+<connects>
+<connect gate="G$1" pin="A" pad="1"/>
+<connect gate="G$1" pin="C" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="LED_0805" package="SMD0805">
+<connects>
+<connect gate="G$1" pin="A" pad="1"/>
+<connect gate="G$1" pin="C" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+</libraries>
+<attributes>
+</attributes>
+<variantdefs>
+</variantdefs>
+<classes>
+<class number="0" name="default" width="0" drill="0">
+</class>
+</classes>
+<parts>
+<part name="P_8" library="ataradov_pwr" deviceset="+3V3" device=""/>
+<part name="P_2" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_1" library="ataradov_pwr" deviceset="V_USB" device=""/>
+<part name="P_3" library="ataradov_pwr" deviceset="V_USB" device=""/>
+<part name="C1" library="ataradov_rlc" deviceset="C" device="-0603" value="1uF"/>
+<part name="C2" library="ataradov_rlc" deviceset="C" device="-0603" value="1uF"/>
+<part name="IC2" library="ataradov_vreg" deviceset="MIC5504" device="-SOT23-5" value="MIC5504-3.3"/>
+<part name="P_5" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_9" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_4" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="TP1" library="ataradov_misc" deviceset="TEST-POINT" device="-1.27MM" value="SIO"/>
+<part name="TP2" library="ataradov_misc" deviceset="TEST-POINT" device="-1.27MM"/>
+<part name="TP3" library="ataradov_misc" deviceset="TEST-POINT" device="-1.27MM"/>
+<part name="TP4" library="ataradov_misc" deviceset="TEST-POINT" device="-1.27MM"/>
+<part name="J2" library="ataradov_conn" deviceset="HEADER-5X2" device="-TH-1.27"/>
+<part name="P_11" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="J1" library="ataradov_conn" deviceset="USB-B-MICRO" device="-SMT"/>
+<part name="R1" library="ataradov_rlc" deviceset="R" device="-0603" value="10K"/>
+<part name="LED1" library="ataradov_led" deviceset="LED_SMD" device="LED_0603" value="ORANGE"/>
+<part name="R2" library="ataradov_rlc" deviceset="R" device="-0603" value="10K"/>
+<part name="LED2" library="ataradov_led" deviceset="LED_SMD" device="LED_0603" value="GREEN"/>
+<part name="P_12" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="J3" library="ataradov_conn" deviceset="CONN-SINGLE" device="-TH" value="RX"/>
+<part name="J4" library="ataradov_conn" deviceset="CONN-SINGLE" device="-TH" value="TX"/>
+<part name="J5" library="ataradov_conn" deviceset="CONN-SINGLE" device="-TH" value="GND"/>
+<part name="P_13" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="SB1" library="ataradov_misc" deviceset="SOLDER-BRIDGE" device="-1.27MM-NO"/>
+<part name="IC1" library="ataradov_mcu" deviceset="ATSAMD11D" device=""/>
+<part name="P_6" library="ataradov_pwr" deviceset="+3V3" device=""/>
+<part name="P_7" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_10" library="ataradov_pwr" deviceset="+3V3" device=""/>
+</parts>
+<sheets>
+<sheet>
+<plain>
+<frame x1="0" y1="0" x2="139.7" y2="114.3" columns="8" rows="5" layer="97"/>
+<text x="35.56" y="7.62" size="1.778" layer="97">d11_micro_std_vcp_v3
+Copyright (c) 2021, Alex Taradov &lt;alex@taradov.com&gt;
+MCU firmware source code is available at https://github.com/ataradov/free-dap</text>
+</plain>
+<instances>
+<instance part="P_8" gate="1" x="76.2" y="35.56"/>
+<instance part="P_2" gate="1" x="30.48" y="17.78" rot="MR0"/>
+<instance part="P_1" gate="1" x="30.48" y="35.56" rot="MR0"/>
+<instance part="P_3" gate="1" x="48.26" y="35.56"/>
+<instance part="C1" gate="G$1" x="48.26" y="27.94" rot="R90"/>
+<instance part="C2" gate="G$1" x="76.2" y="27.94" rot="R90"/>
+<instance part="IC2" gate="G$1" x="60.96" y="30.48"/>
+<instance part="P_5" gate="1" x="60.96" y="22.86"/>
+<instance part="P_9" gate="1" x="76.2" y="22.86"/>
+<instance part="P_4" gate="1" x="48.26" y="22.86"/>
+<instance part="TP1" gate="G$1" x="63.5" y="66.04"/>
+<instance part="TP2" gate="G$1" x="63.5" y="68.58"/>
+<instance part="TP3" gate="G$1" x="63.5" y="71.12"/>
+<instance part="TP4" gate="G$1" x="63.5" y="63.5"/>
+<instance part="J2" gate="G$1" x="99.06" y="81.28"/>
+<instance part="P_11" gate="1" x="88.9" y="71.12"/>
+<instance part="J1" gate="G$1" x="20.32" y="27.94" rot="MR0"/>
+<instance part="R1" gate="G$1" x="109.22" y="35.56"/>
+<instance part="LED1" gate="G$1" x="99.06" y="35.56" rot="MR270"/>
+<instance part="R2" gate="G$1" x="109.22" y="25.4"/>
+<instance part="LED2" gate="G$1" x="99.06" y="25.4" rot="MR270"/>
+<instance part="P_12" gate="1" x="114.3" y="22.86"/>
+<instance part="J3" gate="G$1" x="104.14" y="53.34"/>
+<instance part="J4" gate="G$1" x="104.14" y="50.8"/>
+<instance part="J5" gate="G$1" x="104.14" y="48.26"/>
+<instance part="P_13" gate="1" x="99.06" y="45.72"/>
+<instance part="SB1" gate="G$1" x="88.9" y="88.9" rot="R270"/>
+<instance part="IC1" gate="G$1" x="43.18" y="76.2"/>
+<instance part="P_6" gate="1" x="60.96" y="93.98"/>
+<instance part="P_7" gate="1" x="60.96" y="58.42"/>
+<instance part="P_10" gate="1" x="88.9" y="93.98"/>
+</instances>
+<busses>
+</busses>
+<nets>
+<net name="USB_DM" class="0">
+<segment>
+<wire x1="30.48" y1="30.48" x2="27.94" y2="30.48" width="0.1524" layer="91"/>
+<pinref part="J1" gate="G$1" pin="DM"/>
+<label x="30.48" y="30.48" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC1" gate="G$1" pin="PA24/DM"/>
+<wire x1="60.96" y1="78.74" x2="63.5" y2="78.74" width="0.1524" layer="91"/>
+<label x="63.5" y="78.74" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="USB_DP" class="0">
+<segment>
+<wire x1="30.48" y1="27.94" x2="27.94" y2="27.94" width="0.1524" layer="91"/>
+<pinref part="J1" gate="G$1" pin="DP"/>
+<label x="30.48" y="27.94" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC1" gate="G$1" pin="PA25/DP"/>
+<wire x1="60.96" y1="76.2" x2="63.5" y2="76.2" width="0.1524" layer="91"/>
+<label x="63.5" y="76.2" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="GND" class="0">
+<segment>
+<pinref part="P_2" gate="1" pin="GND"/>
+<wire x1="30.48" y1="20.32" x2="30.48" y2="22.86" width="0.1524" layer="91"/>
+<wire x1="30.48" y1="22.86" x2="27.94" y2="22.86" width="0.1524" layer="91"/>
+<pinref part="J1" gate="G$1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="GND"/>
+<pinref part="P_5" gate="1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="C1" gate="G$1" pin="1"/>
+<pinref part="P_4" gate="1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="C2" gate="G$1" pin="1"/>
+<pinref part="P_9" gate="1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="TP4" gate="G$1" pin="1"/>
+<pinref part="IC1" gate="G$1" pin="PAD"/>
+<pinref part="P_7" gate="1" pin="GND"/>
+<pinref part="IC1" gate="G$1" pin="GND"/>
+<wire x1="60.96" y1="60.96" x2="60.96" y2="63.5" width="0.1524" layer="91"/>
+<junction x="60.96" y="60.96"/>
+<wire x1="63.5" y1="63.5" x2="60.96" y2="63.5" width="0.1524" layer="91"/>
+<junction x="60.96" y="63.5"/>
+</segment>
+<segment>
+<pinref part="J2" gate="G$1" pin="3"/>
+<wire x1="91.44" y1="83.82" x2="88.9" y2="83.82" width="0.1524" layer="91"/>
+<pinref part="P_11" gate="1" pin="GND"/>
+<wire x1="88.9" y1="83.82" x2="88.9" y2="81.28" width="0.1524" layer="91"/>
+<pinref part="J2" gate="G$1" pin="5"/>
+<wire x1="88.9" y1="81.28" x2="88.9" y2="76.2" width="0.1524" layer="91"/>
+<wire x1="88.9" y1="76.2" x2="88.9" y2="73.66" width="0.1524" layer="91"/>
+<wire x1="91.44" y1="81.28" x2="88.9" y2="81.28" width="0.1524" layer="91"/>
+<junction x="88.9" y="81.28"/>
+<pinref part="J2" gate="G$1" pin="9"/>
+<wire x1="91.44" y1="76.2" x2="88.9" y2="76.2" width="0.1524" layer="91"/>
+<junction x="88.9" y="76.2"/>
+</segment>
+<segment>
+<pinref part="P_12" gate="1" pin="GND"/>
+<wire x1="114.3" y1="35.56" x2="114.3" y2="25.4" width="0.1524" layer="91"/>
+<pinref part="R1" gate="G$1" pin="2"/>
+<pinref part="R2" gate="G$1" pin="2"/>
+<junction x="114.3" y="25.4"/>
+</segment>
+<segment>
+<pinref part="J5" gate="G$1" pin="1"/>
+<pinref part="P_13" gate="1" pin="GND"/>
+<wire x1="99.06" y1="48.26" x2="101.6" y2="48.26" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="V_USB" class="0">
+<segment>
+<pinref part="P_1" gate="1" pin="V_USB"/>
+<wire x1="30.48" y1="33.02" x2="27.94" y2="33.02" width="0.1524" layer="91"/>
+<pinref part="J1" gate="G$1" pin="VBUS"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="EN"/>
+<pinref part="P_3" gate="1" pin="V_USB"/>
+<wire x1="50.8" y1="30.48" x2="48.26" y2="30.48" width="0.1524" layer="91"/>
+<pinref part="IC2" gate="G$1" pin="IN"/>
+<wire x1="50.8" y1="33.02" x2="48.26" y2="33.02" width="0.1524" layer="91"/>
+<junction x="48.26" y="33.02"/>
+<pinref part="C1" gate="G$1" pin="2"/>
+<wire x1="48.26" y1="33.02" x2="48.26" y2="30.48" width="0.1524" layer="91"/>
+<junction x="48.26" y="30.48"/>
+</segment>
+</net>
+<net name="+3V3" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="OUT"/>
+<wire x1="71.12" y1="33.02" x2="76.2" y2="33.02" width="0.1524" layer="91"/>
+<pinref part="C2" gate="G$1" pin="2"/>
+<wire x1="76.2" y1="30.48" x2="76.2" y2="33.02" width="0.1524" layer="91"/>
+<junction x="76.2" y="33.02"/>
+<pinref part="P_8" gate="1" pin="+3V3"/>
+</segment>
+<segment>
+<pinref part="IC1" gate="G$1" pin="VDD"/>
+<pinref part="P_6" gate="1" pin="+3V3"/>
+</segment>
+<segment>
+<pinref part="SB1" gate="G$1" pin="1"/>
+<pinref part="P_10" gate="1" pin="+3V3"/>
+</segment>
+</net>
+<net name="SWDIO" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="PA31/SIO"/>
+<pinref part="TP1" gate="G$1" pin="1"/>
+<wire x1="60.96" y1="66.04" x2="63.5" y2="66.04" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="SWCLK" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="PA30/SCK"/>
+<pinref part="TP2" gate="G$1" pin="1"/>
+<wire x1="60.96" y1="68.58" x2="63.5" y2="68.58" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="RESET" class="0">
+<segment>
+<pinref part="TP3" gate="G$1" pin="1"/>
+<pinref part="IC1" gate="G$1" pin="PA28/RST"/>
+<wire x1="63.5" y1="71.12" x2="60.96" y2="71.12" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="T_SWDIO_TMS" class="0">
+<segment>
+<pinref part="J2" gate="G$1" pin="2"/>
+<wire x1="106.68" y1="86.36" x2="109.22" y2="86.36" width="0.1524" layer="91"/>
+<label x="109.22" y="86.36" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC1" gate="G$1" pin="PA08"/>
+<wire x1="25.4" y1="76.2" x2="22.86" y2="76.2" width="0.1524" layer="91"/>
+<label x="22.86" y="76.2" size="1.27" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="T_SWCLK_TCK" class="0">
+<segment>
+<pinref part="J2" gate="G$1" pin="4"/>
+<wire x1="109.22" y1="83.82" x2="106.68" y2="83.82" width="0.1524" layer="91"/>
+<label x="109.22" y="83.82" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC1" gate="G$1" pin="PA09"/>
+<wire x1="25.4" y1="73.66" x2="22.86" y2="73.66" width="0.1524" layer="91"/>
+<label x="22.86" y="73.66" size="1.27" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="T_RESET" class="0">
+<segment>
+<pinref part="J2" gate="G$1" pin="10"/>
+<wire x1="106.68" y1="76.2" x2="109.22" y2="76.2" width="0.1524" layer="91"/>
+<label x="109.22" y="76.2" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC1" gate="G$1" pin="PA15"/>
+<wire x1="25.4" y1="63.5" x2="22.86" y2="63.5" width="0.1524" layer="91"/>
+<label x="22.86" y="63.5" size="1.27" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="UART_TX" class="0">
+<segment>
+<pinref part="J4" gate="G$1" pin="1"/>
+<wire x1="101.6" y1="50.8" x2="96.52" y2="50.8" width="0.1524" layer="91"/>
+<label x="96.52" y="50.8" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="IC1" gate="G$1" pin="PA16"/>
+<wire x1="25.4" y1="60.96" x2="22.86" y2="60.96" width="0.1524" layer="91"/>
+<label x="22.86" y="60.96" size="1.27" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="UART_RX" class="0">
+<segment>
+<pinref part="J3" gate="G$1" pin="1"/>
+<wire x1="101.6" y1="53.34" x2="96.52" y2="53.34" width="0.1524" layer="91"/>
+<label x="96.52" y="53.34" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="IC1" gate="G$1" pin="PA17"/>
+<wire x1="60.96" y1="88.9" x2="63.5" y2="88.9" width="0.1524" layer="91"/>
+<label x="63.5" y="88.9" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="T_TDO" class="0">
+<segment>
+<pinref part="J2" gate="G$1" pin="6"/>
+<wire x1="106.68" y1="81.28" x2="109.22" y2="81.28" width="0.1524" layer="91"/>
+<label x="109.22" y="81.28" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC1" gate="G$1" pin="PA10"/>
+<wire x1="25.4" y1="71.12" x2="22.86" y2="71.12" width="0.1524" layer="91"/>
+<label x="22.86" y="71.12" size="1.27" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="T_TDI" class="0">
+<segment>
+<pinref part="J2" gate="G$1" pin="8"/>
+<wire x1="106.68" y1="78.74" x2="109.22" y2="78.74" width="0.1524" layer="91"/>
+<label x="109.22" y="78.74" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC1" gate="G$1" pin="PA14"/>
+<wire x1="25.4" y1="66.04" x2="22.86" y2="66.04" width="0.1524" layer="91"/>
+<label x="22.86" y="66.04" size="1.27" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="N$2" class="0">
+<segment>
+<pinref part="R1" gate="G$1" pin="1"/>
+<pinref part="LED1" gate="G$1" pin="C"/>
+</segment>
+</net>
+<net name="N$3" class="0">
+<segment>
+<pinref part="R2" gate="G$1" pin="1"/>
+<pinref part="LED2" gate="G$1" pin="C"/>
+</segment>
+</net>
+<net name="LED_A" class="0">
+<segment>
+<pinref part="LED1" gate="G$1" pin="A"/>
+<wire x1="96.52" y1="35.56" x2="93.98" y2="35.56" width="0.1524" layer="91"/>
+<label x="93.98" y="35.56" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="IC1" gate="G$1" pin="PA03"/>
+<wire x1="25.4" y1="88.9" x2="22.86" y2="88.9" width="0.1524" layer="91"/>
+<label x="22.86" y="88.9" size="1.27" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="LED_B" class="0">
+<segment>
+<pinref part="LED2" gate="G$1" pin="A"/>
+<wire x1="96.52" y1="25.4" x2="93.98" y2="25.4" width="0.1524" layer="91"/>
+<label x="93.98" y="25.4" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="IC1" gate="G$1" pin="PA06"/>
+<wire x1="25.4" y1="81.28" x2="22.86" y2="81.28" width="0.1524" layer="91"/>
+<label x="22.86" y="81.28" size="1.27" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="T_VREF" class="0">
+<segment>
+<pinref part="J2" gate="G$1" pin="1"/>
+<pinref part="SB1" gate="G$1" pin="2"/>
+<wire x1="88.9" y1="86.36" x2="91.44" y2="86.36" width="0.1524" layer="91"/>
+</segment>
+</net>
+</nets>
+</sheet>
+</sheets>
+</schematic>
+</drawing>
+<compatibility>
+<note version="6.3" minversion="6.2.2" severity="warning">
+Since Version 6.2.2 text objects can contain more than one line,
+which will not be processed correctly with this version.
+</note>
+</compatibility>
+</eagle>

dap_link/lib/free-dap/hardware/d11_micro_std_vcp_v4/d11_micro_vcp_v4.brd

@@ -0,0 +1,769 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="7.3.0">
+<drawing>
+<settings>
+<setting alwaysvectorfont="no"/>
+<setting verticaltext="up"/>
+</settings>
+<grid distance="0.01" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.025" altunitdist="inch" altunit="inch"/>
+<layers>
+<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>
+<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="yes"/>
+<layer number="17" name="Pads" color="2" fill="1" visible="yes" active="yes"/>
+<layer number="18" name="Vias" color="2" fill="1" visible="yes" active="yes"/>
+<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="yes"/>
+<layer number="20" name="Dimension" color="15" fill="1" visible="yes" active="yes"/>
+<layer number="21" name="tPlace" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="22" name="bPlace" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="23" name="tOrigins" color="15" fill="1" visible="yes" active="yes"/>
+<layer number="24" name="bOrigins" color="15" fill="1" visible="yes" active="yes"/>
+<layer number="25" name="tNames" color="7" fill="1" visible="no" active="yes"/>
+<layer number="26" name="bNames" color="7" fill="1" visible="no" active="yes"/>
+<layer number="27" name="tValues" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="28" name="bValues" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="29" name="tStop" color="7" fill="3" visible="no" active="yes"/>
+<layer number="30" name="bStop" color="7" fill="6" visible="no" active="yes"/>
+<layer number="31" name="tCream" color="7" fill="4" visible="no" active="yes"/>
+<layer number="32" name="bCream" color="7" fill="5" visible="no" active="yes"/>
+<layer number="33" name="tFinish" color="6" fill="3" visible="no" active="yes"/>
+<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="yes"/>
+<layer number="35" name="tGlue" color="7" fill="4" visible="no" active="yes"/>
+<layer number="36" name="bGlue" color="7" fill="5" visible="no" active="yes"/>
+<layer number="37" name="tTest" color="7" fill="1" visible="no" active="yes"/>
+<layer number="38" name="bTest" color="7" fill="1" visible="no" active="yes"/>
+<layer number="39" name="tKeepout" color="4" fill="11" visible="yes" active="yes"/>
+<layer number="40" name="bKeepout" color="1" fill="11" visible="yes" active="yes"/>
+<layer number="41" name="tRestrict" color="4" fill="10" visible="yes" active="yes"/>
+<layer number="42" name="bRestrict" color="1" fill="10" visible="yes" active="yes"/>
+<layer number="43" name="vRestrict" color="2" fill="10" visible="yes" active="yes"/>
+<layer number="44" name="Drills" color="7" fill="1" visible="no" active="yes"/>
+<layer number="45" name="Holes" color="7" fill="1" visible="no" active="yes"/>
+<layer number="46" name="Milling" color="3" fill="1" visible="no" active="yes"/>
+<layer number="47" name="Measures" color="7" fill="1" visible="no" active="yes"/>
+<layer number="48" name="Document" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="49" name="Reference" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="51" name="tDocu" color="7" fill="1" visible="no" active="yes"/>
+<layer number="52" name="bDocu" color="7" fill="1" visible="no" active="yes"/>
+<layer number="90" name="Modules" color="5" fill="1" visible="no" active="no"/>
+<layer number="91" name="Nets" color="2" fill="1" visible="no" active="no"/>
+<layer number="92" name="Busses" color="1" fill="1" visible="no" active="no"/>
+<layer number="93" name="Pins" color="2" fill="1" visible="no" active="no"/>
+<layer number="94" name="Symbols" color="4" fill="1" visible="no" active="no"/>
+<layer number="95" name="Names" color="7" fill="1" visible="no" active="no"/>
+<layer number="96" name="Values" color="7" fill="1" visible="no" active="no"/>
+<layer number="97" name="Info" color="7" fill="1" visible="no" active="no"/>
+<layer number="98" name="Guide" color="6" fill="1" visible="no" active="no"/>
+</layers>
+<board>
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+<library name="ataradov_led">
+<description>Alex Taradov Library (LEDs and other indication devices)</description>
+<packages>
+<package name="SMD0603">
+<wire x1="-1.5" y1="0.75" x2="1.5" y2="0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="0.75" x2="1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="-0.75" x2="-1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="-1.5" y1="-0.75" x2="-1.5" y2="0.75" width="0.1" layer="21"/>
+<smd name="1" x="-0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<smd name="2" x="0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+</packages>
+</library>
+</libraries>
+<attributes>
+</attributes>
+<variantdefs>
+</variantdefs>
+<classes>
+<class number="0" name="default" width="0" drill="0">
+</class>
+</classes>
+<designrules name="std-tented-new">
+<description language="de">&lt;b&gt;EAGLE Design Rules&lt;/b&gt;
+&lt;p&gt;
+Die Standard-Design-Rules sind so gewählt, dass sie für 
+die meisten Anwendungen passen. Sollte ihre Platine 
+besondere Anforderungen haben, treffen Sie die erforderlichen
+Einstellungen hier und speichern die Design Rules unter 
+einem neuen Namen ab.</description>
+<description language="en">&lt;b&gt;Laen's PCB Order Design Rules&lt;/b&gt;
+&lt;p&gt;
+Please make sure your boards conform to these design rules.</description>
+<param name="layerSetup" value="(1*16)"/>
+<param name="mtCopper" value="0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm"/>
+<param name="mtIsolate" value="1.5011mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm"/>
+<param name="mdWireWire" value="6mil"/>
+<param name="mdWirePad" value="6mil"/>
+<param name="mdWireVia" value="6mil"/>
+<param name="mdPadPad" value="6mil"/>
+<param name="mdPadVia" value="6mil"/>
+<param name="mdViaVia" value="6mil"/>
+<param name="mdSmdPad" value="0mil"/>
+<param name="mdSmdVia" value="0mil"/>
+<param name="mdSmdSmd" value="0mil"/>
+<param name="mdViaViaSameLayer" value="8mil"/>
+<param name="mnLayersViaInSmd" value="2"/>
+<param name="mdCopperDimension" value="10mil"/>
+<param name="mdDrill" value="6mil"/>
+<param name="mdSmdStop" value="0mil"/>
+<param name="msWidth" value="8mil"/>
+<param name="msDrill" value="12mil"/>
+<param name="msMicroVia" value="12mil"/>
+<param name="msBlindViaRatio" value="0.5"/>
+<param name="rvPadTop" value="0.25"/>
+<param name="rvPadInner" value="0.25"/>
+<param name="rvPadBottom" value="0.25"/>
+<param name="rvViaOuter" value="0.25"/>
+<param name="rvViaInner" value="0.25"/>
+<param name="rvMicroViaOuter" value="0.25"/>
+<param name="rvMicroViaInner" value="0.25"/>
+<param name="rlMinPadTop" value="7mil"/>
+<param name="rlMaxPadTop" value="20mil"/>
+<param name="rlMinPadInner" value="7mil"/>
+<param name="rlMaxPadInner" value="20mil"/>
+<param name="rlMinPadBottom" value="7mil"/>
+<param name="rlMaxPadBottom" value="20mil"/>
+<param name="rlMinViaOuter" value="7mil"/>
+<param name="rlMaxViaOuter" value="20mil"/>
+<param name="rlMinViaInner" value="7mil"/>
+<param name="rlMaxViaInner" value="20mil"/>
+<param name="rlMinMicroViaOuter" value="4mil"/>
+<param name="rlMaxMicroViaOuter" value="20mil"/>
+<param name="rlMinMicroViaInner" value="4mil"/>
+<param name="rlMaxMicroViaInner" value="20mil"/>
+<param name="psTop" value="-1"/>
+<param name="psBottom" value="-1"/>
+<param name="psFirst" value="-1"/>
+<param name="psElongationLong" value="100"/>
+<param name="psElongationOffset" value="100"/>
+<param name="mvStopFrame" value="1"/>
+<param name="mvCreamFrame" value="0"/>
+<param name="mlMinStopFrame" value="3mil"/>
+<param name="mlMaxStopFrame" value="3mil"/>
+<param name="mlMinCreamFrame" value="0mil"/>
+<param name="mlMaxCreamFrame" value="0mil"/>
+<param name="mlViaStopLimit" value="25mil"/>
+<param name="srRoundness" value="0"/>
+<param name="srMinRoundness" value="0mil"/>
+<param name="srMaxRoundness" value="0mil"/>
+<param name="slThermalIsolate" value="6mil"/>
+<param name="slThermalsForVias" value="0"/>
+<param name="dpMaxLengthDifference" value="10mm"/>
+<param name="dpGapFactor" value="2.5"/>
+<param name="checkGrid" value="0"/>
+<param name="checkAngle" value="0"/>
+<param name="checkFont" value="1"/>
+<param name="checkRestrict" value="1"/>
+<param name="useDiameter" value="13"/>
+<param name="maxErrors" value="50"/>
+</designrules>
+<autorouter>
+<pass name="Default">
+<param name="RoutingGrid" value="50mil"/>
+<param name="AutoGrid" value="1"/>
+<param name="Efforts" value="0"/>
+<param name="TopRouterVariant" value="1"/>
+<param name="tpViaShape" value="round"/>
+<param name="PrefDir.1" value="a"/>
+<param name="PrefDir.2" value="0"/>
+<param name="PrefDir.3" value="0"/>
+<param name="PrefDir.4" value="0"/>
+<param name="PrefDir.5" value="0"/>
+<param name="PrefDir.6" value="0"/>
+<param name="PrefDir.7" value="0"/>
+<param name="PrefDir.8" value="0"/>
+<param name="PrefDir.9" value="0"/>
+<param name="PrefDir.10" value="0"/>
+<param name="PrefDir.11" value="0"/>
+<param name="PrefDir.12" value="0"/>
+<param name="PrefDir.13" value="0"/>
+<param name="PrefDir.14" value="0"/>
+<param name="PrefDir.15" value="0"/>
+<param name="PrefDir.16" value="a"/>
+<param name="cfVia" value="8"/>
+<param name="cfNonPref" value="5"/>
+<param name="cfChangeDir" value="2"/>
+<param name="cfOrthStep" value="2"/>
+<param name="cfDiagStep" value="3"/>
+<param name="cfExtdStep" value="0"/>
+<param name="cfBonusStep" value="1"/>
+<param name="cfMalusStep" value="1"/>
+<param name="cfPadImpact" value="4"/>
+<param name="cfSmdImpact" value="4"/>
+<param name="cfBusImpact" value="0"/>
+<param name="cfHugging" value="3"/>
+<param name="cfAvoid" value="4"/>
+<param name="cfPolygon" value="10"/>
+<param name="cfBase.1" value="0"/>
+<param name="cfBase.2" value="1"/>
+<param name="cfBase.3" value="1"/>
+<param name="cfBase.4" value="1"/>
+<param name="cfBase.5" value="1"/>
+<param name="cfBase.6" value="1"/>
+<param name="cfBase.7" value="1"/>
+<param name="cfBase.8" value="1"/>
+<param name="cfBase.9" value="1"/>
+<param name="cfBase.10" value="1"/>
+<param name="cfBase.11" value="1"/>
+<param name="cfBase.12" value="1"/>
+<param name="cfBase.13" value="1"/>
+<param name="cfBase.14" value="1"/>
+<param name="cfBase.15" value="1"/>
+<param name="cfBase.16" value="0"/>
+<param name="mnVias" value="20"/>
+<param name="mnSegments" value="9999"/>
+<param name="mnExtdSteps" value="9999"/>
+<param name="mnRipupLevel" value="10"/>
+<param name="mnRipupSteps" value="100"/>
+<param name="mnRipupTotal" value="100"/>
+</pass>
+<pass name="Follow-me" refer="Default" active="yes">
+</pass>
+<pass name="Busses" refer="Default" active="yes">
+<param name="cfNonPref" value="4"/>
+<param name="cfBusImpact" value="4"/>
+<param name="cfHugging" value="0"/>
+<param name="mnVias" value="0"/>
+</pass>
+<pass name="Route" refer="Default" active="yes">
+</pass>
+<pass name="Optimize1" refer="Default" active="yes">
+<param name="cfVia" value="99"/>
+<param name="cfExtdStep" value="10"/>
+<param name="cfHugging" value="1"/>
+<param name="mnExtdSteps" value="1"/>
+<param name="mnRipupLevel" value="0"/>
+</pass>
+<pass name="Optimize2" refer="Optimize1" active="yes">
+<param name="cfNonPref" value="0"/>
+<param name="cfChangeDir" value="6"/>
+<param name="cfExtdStep" value="0"/>
+<param name="cfBonusStep" value="2"/>
+<param name="cfMalusStep" value="2"/>
+<param name="cfPadImpact" value="2"/>
+<param name="cfSmdImpact" value="2"/>
+<param name="cfHugging" value="0"/>
+</pass>
+<pass name="Optimize3" refer="Optimize2" active="yes">
+<param name="cfChangeDir" value="8"/>
+<param name="cfPadImpact" value="0"/>
+<param name="cfSmdImpact" value="0"/>
+</pass>
+<pass name="Optimize4" refer="Optimize3" active="yes">
+<param name="cfChangeDir" value="25"/>
+</pass>
+</autorouter>
+<elements>
+<element name="IC2" library="ataradov_mcu" package="SO-14" value="ATSAMD11C" x="10.414" y="6.35" smashed="yes" rot="MR270">
+<attribute name="NAME" x="10.414" y="11.176" size="1.27" layer="26" font="vector" rot="MR0" align="bottom-center"/>
+</element>
+<element name="C1" library="ataradov_rlc" package="SMD0603" value="1uF" x="2.286" y="3.556" rot="MR180"/>
+<element name="C2" library="ataradov_rlc" package="SMD0603" value="1uF" x="4.572" y="5.588" smashed="yes" rot="MR90">
+<attribute name="NAME" x="5.588" y="5.588" size="1.27" layer="26" font="vector" rot="MR90" align="bottom-center"/>
+</element>
+<element name="IC1" library="ataradov_vreg" package="SOT23-5" value="MIC5504-3.3" x="2.286" y="6.35" smashed="yes" rot="MR0">
+<attribute name="NAME" x="2.286" y="8.636" size="1.27" layer="26" font="vector" rot="MR0" align="bottom-center"/>
+</element>
+<element name="J1" library="ataradov_conn" package="HEADER-5X2-1.27MM" value="HEADER-5X2-TH-1.27" x="16.002" y="5.588" rot="R90"/>
+<element name="J5" library="ataradov_conn" package="USB-B-MICRO-SMT-SHELL-TH" value="" x="0" y="5.588"/>
+<element name="R1" library="ataradov_rlc" package="SMD0603" value="10K" x="8.382" y="2.286" rot="R90"/>
+<element name="LED1" library="ataradov_led" package="SMD0603" value="GREEN" x="6.858" y="2.286" rot="R270"/>
+<element name="R2" library="ataradov_rlc" package="SMD0603" value="10K" x="8.382" y="8.89" rot="R90"/>
+<element name="LED2" library="ataradov_led" package="SMD0603" value="ORANGE" x="6.858" y="8.89" rot="R270"/>
+<element name="J2" library="ataradov_conn" package="PIN-TH" value="RX" x="18.542" y="5.588" smashed="yes" rot="R90">
+<attribute name="NAME" x="17.018" y="5.588" size="1.27" layer="25" font="vector" rot="R90" align="bottom-center"/>
+</element>
+<element name="J3" library="ataradov_conn" package="PIN-TH" value="TX" x="18.542" y="8.128" smashed="yes" rot="R90">
+<attribute name="NAME" x="17.018" y="8.128" size="1.27" layer="25" font="vector" rot="R90" align="bottom-center"/>
+</element>
+<element name="J4" library="ataradov_conn" package="PIN-TH" value="GND" x="18.542" y="3.048" smashed="yes" rot="R90">
+<attribute name="NAME" x="17.018" y="3.048" size="1.27" layer="25" font="vector" rot="R90" align="bottom-center"/>
+</element>
+<element name="RN2" library="ataradov_rlc" package="SMD0603-X4" value="33" x="12.446" y="4.064" rot="R270"/>
+<element name="RN1" library="ataradov_rlc" package="SMD0603-X4" value="33" x="12.446" y="8.89" rot="R270"/>
+<element name="TP1" library="ataradov_misc" package="TP-1.27MM" value="" x="7.874" y="1.524" rot="MR0"/>
+<element name="TP2" library="ataradov_misc" package="TP-1.27MM" value="" x="12.954" y="1.524" rot="MR0"/>
+<element name="TP3" library="ataradov_misc" package="TP-1.27MM" value="" x="10.414" y="1.524" rot="MR0"/>
+<element name="TP4" library="ataradov_misc" package="TP-1.27MM" value="" x="5.334" y="1.524" rot="MR0"/>
+</elements>
+<signals>
+<signal name="GND">
+<contactref element="IC1" pad="2"/>
+<contactref element="C1" pad="1"/>
+<contactref element="C2" pad="1"/>
+<contactref element="IC2" pad="11"/>
+<contactref element="J1" pad="3"/>
+<contactref element="J1" pad="5"/>
+<contactref element="J5" pad="5"/>
+<polygon width="0.254" layer="16" isolate="0.2032">
+<vertex x="0" y="11.176"/>
+<vertex x="22.098" y="11.176"/>
+<vertex x="22.098" y="0"/>
+<vertex x="0" y="0"/>
+</polygon>
+<polygon width="0.254" layer="1" isolate="0.2032">
+<vertex x="0" y="11.176"/>
+<vertex x="22.098" y="11.176"/>
+<vertex x="22.098" y="0"/>
+<vertex x="0" y="0"/>
+</polygon>
+<contactref element="LED2" pad="2"/>
+<contactref element="LED1" pad="2"/>
+<contactref element="J1" pad="9"/>
+<contactref element="J4" pad="1"/>
+<via x="3.81" y="8.89" extent="1-16" drill="0.3302" diameter="0.254"/>
+<via x="3.81" y="2.286" extent="1-16" drill="0.3302" diameter="0.254"/>
+<via x="6.096" y="4.064" extent="1-16" drill="0.3302" diameter="0.254"/>
+<via x="2.286" y="6.858" extent="1-16" drill="0.3302" diameter="0.254"/>
+<via x="5.334" y="1.524" extent="1-16" drill="0.3302" diameter="0.254"/>
+<contactref element="TP4" pad="1"/>
+<via x="1.524" y="3.556" extent="1-16" drill="0.3302" diameter="0.254"/>
+<via x="9.906" y="10.414" extent="1-16" drill="0.3302" diameter="0.254"/>
+<via x="10.668" y="6.35" extent="1-16" drill="0.3302" diameter="0.254"/>
+<via x="9.906" y="4.318" extent="1-16" drill="0.3302" diameter="0.254"/>
+<via x="17.78" y="6.858" extent="1-16" drill="0.3302" diameter="0.254"/>
+<via x="20.828" y="9.906" extent="1-16" drill="0.3302" diameter="0.254"/>
+<via x="16.002" y="1.778" extent="1-16" drill="0.3302" diameter="0.254"/>
+<via x="20.828" y="1.27" extent="1-16" drill="0.3302" diameter="0.254"/>
+<via x="5.334" y="9.652" extent="1-16" drill="0.3302" diameter="0.254"/>
+</signal>
+<signal name="N$1">
+<contactref element="IC2" pad="9"/>
+<contactref element="J5" pad="2"/>
+<via x="7.62" y="4.064" extent="1-16" drill="0.3302" diameter="0.254"/>
+<wire x1="4.825" y1="6.238" x2="5.954" y2="6.238" width="0.254" layer="1"/>
+<wire x1="5.954" y1="6.238" x2="7.62" y2="4.572" width="0.254" layer="1"/>
+<wire x1="7.62" y1="4.572" x2="7.62" y2="4.064" width="0.254" layer="1"/>
+<wire x1="7.62" y1="4.064" x2="7.62" y2="4.004" width="0.254" layer="16"/>
+<wire x1="7.62" y1="4.004" x2="7.814" y2="3.81" width="0.254" layer="16"/>
+</signal>
+<signal name="N$2">
+<contactref element="IC2" pad="10"/>
+<contactref element="J5" pad="3"/>
+<via x="6.096" y="5.08" extent="1-16" drill="0.3302" diameter="0.254"/>
+<wire x1="4.825" y1="5.588" x2="5.588" y2="5.588" width="0.254" layer="1"/>
+<wire x1="5.588" y1="5.588" x2="6.096" y2="5.08" width="0.254" layer="1"/>
+<wire x1="7.814" y1="5.08" x2="6.096" y2="5.08" width="0.254" layer="16"/>
+</signal>
+<signal name="V_USB">
+<contactref element="IC1" pad="3"/>
+<contactref element="IC1" pad="1"/>
+<contactref element="C1" pad="2"/>
+<contactref element="J5" pad="1"/>
+<wire x1="4.825" y1="6.888" x2="3.84" y2="6.888" width="0.254" layer="1"/>
+<wire x1="3.84" y1="6.888" x2="3.048" y2="6.096" width="0.254" layer="1"/>
+<via x="3.048" y="6.096" extent="1-16" drill="0.3302"/>
+<wire x1="3.048" y1="6.096" x2="1.778" y2="6.096" width="0.254" layer="16"/>
+<wire x1="1.778" y1="6.096" x2="1.336" y2="5.654" width="0.254" layer="16"/>
+<wire x1="1.336" y1="5.654" x2="1.336" y2="5.05" width="0.254" layer="16"/>
+<wire x1="3.048" y1="6.096" x2="3.236" y2="5.908" width="0.254" layer="16"/>
+<wire x1="3.236" y1="5.908" x2="3.236" y2="5.05" width="0.254" layer="16"/>
+<wire x1="3.236" y1="5.05" x2="3.236" y2="3.706" width="0.254" layer="16"/>
+<wire x1="3.236" y1="3.706" x2="3.086" y2="3.556" width="0.254" layer="16"/>
+</signal>
+<signal name="+3V3">
+<contactref element="IC1" pad="5"/>
+<contactref element="C2" pad="2"/>
+<contactref element="IC2" pad="12"/>
+<wire x1="3.236" y1="7.65" x2="3.236" y2="6.924" width="0.254" layer="16"/>
+<wire x1="3.236" y1="6.924" x2="3.772" y2="6.388" width="0.254" layer="16"/>
+<wire x1="3.772" y1="6.388" x2="4.572" y2="6.388" width="0.254" layer="16"/>
+<wire x1="7.814" y1="7.62" x2="6.604" y2="7.62" width="0.254" layer="16"/>
+<wire x1="6.604" y1="7.62" x2="5.372" y2="6.388" width="0.254" layer="16"/>
+<wire x1="5.372" y1="6.388" x2="4.572" y2="6.388" width="0.254" layer="16"/>
+</signal>
+<signal name="SWDIO">
+<contactref element="IC2" pad="8"/>
+<contactref element="R1" pad="1"/>
+<contactref element="TP1" pad="1"/>
+<via x="7.874" y="1.524" extent="1-16" drill="0.3302"/>
+<wire x1="7.814" y1="2.54" x2="7.874" y2="2.48" width="0.254" layer="16"/>
+<wire x1="7.874" y1="2.48" x2="7.874" y2="1.524" width="0.254" layer="16"/>
+<wire x1="8.382" y1="1.486" x2="8.344" y2="1.524" width="0.254" layer="1"/>
+<wire x1="8.344" y1="1.524" x2="7.874" y2="1.524" width="0.254" layer="1"/>
+</signal>
+<signal name="SWCLK">
+<contactref element="IC2" pad="7"/>
+<contactref element="R2" pad="1"/>
+<contactref element="TP2" pad="1"/>
+<via x="12.954" y="1.524" extent="1-16" drill="0.3302"/>
+<wire x1="12.954" y1="1.524" x2="11.176" y2="1.524" width="0.254" layer="1"/>
+<wire x1="11.176" y1="1.524" x2="9.144" y2="3.556" width="0.254" layer="1"/>
+<wire x1="9.144" y1="3.556" x2="9.144" y2="6.604" width="0.254" layer="1"/>
+<wire x1="9.144" y1="6.604" x2="8.382" y2="7.366" width="0.254" layer="1"/>
+<wire x1="8.382" y1="7.366" x2="8.382" y2="8.09" width="0.254" layer="1"/>
+<wire x1="13.014" y1="2.54" x2="12.954" y2="2.48" width="0.254" layer="16"/>
+<wire x1="12.954" y1="2.48" x2="12.954" y2="1.524" width="0.254" layer="16"/>
+</signal>
+<signal name="RESET">
+<contactref element="IC2" pad="6"/>
+<wire x1="13.014" y1="3.81" x2="11.684" y2="3.81" width="0.254" layer="16"/>
+<wire x1="11.684" y1="3.81" x2="10.414" y2="2.54" width="0.254" layer="16"/>
+<contactref element="TP3" pad="1"/>
+<wire x1="10.414" y1="2.54" x2="10.414" y2="1.524" width="0.254" layer="16"/>
+</signal>
+<signal name="N$8">
+</signal>
+<signal name="T_SWDIO_TMS">
+<contactref element="J1" pad="2"/>
+<contactref element="RN2" pad="6"/>
+<wire x1="13.198" y1="3.664" x2="14.751" y2="3.664" width="0.254" layer="1"/>
+<wire x1="14.751" y1="3.664" x2="15.367" y2="3.048" width="0.254" layer="1"/>
+</signal>
+<signal name="T_SWCLK_TCK">
+<contactref element="J1" pad="4"/>
+<contactref element="RN2" pad="7"/>
+<wire x1="13.198" y1="4.464" x2="15.221" y2="4.464" width="0.254" layer="1"/>
+<wire x1="15.221" y1="4.464" x2="15.367" y2="4.318" width="0.254" layer="1"/>
+</signal>
+<signal name="T_RESET">
+<contactref element="J1" pad="10"/>
+<contactref element="RN1" pad="6"/>
+<wire x1="13.198" y1="8.49" x2="15.005" y2="8.49" width="0.254" layer="1"/>
+<wire x1="15.005" y1="8.49" x2="15.367" y2="8.128" width="0.254" layer="1"/>
+</signal>
+<signal name="I_TX">
+<contactref element="IC2" pad="2"/>
+<contactref element="RN1" pad="2"/>
+<via x="10.668" y="9.652" extent="1-16" drill="0.3302"/>
+<wire x1="13.014" y1="8.89" x2="11.43" y2="8.89" width="0.254" layer="16"/>
+<wire x1="11.43" y1="8.89" x2="10.668" y2="9.652" width="0.254" layer="16"/>
+<wire x1="11.694" y1="9.29" x2="11.03" y2="9.29" width="0.254" layer="1"/>
+<wire x1="11.03" y1="9.29" x2="10.668" y2="9.652" width="0.254" layer="1"/>
+</signal>
+<signal name="N$4">
+<contactref element="R1" pad="2"/>
+<contactref element="LED1" pad="1"/>
+<wire x1="6.858" y1="3.086" x2="8.382" y2="3.086" width="0.254" layer="1"/>
+</signal>
+<signal name="N$6">
+<contactref element="R2" pad="2"/>
+<contactref element="LED2" pad="1"/>
+<wire x1="6.858" y1="9.69" x2="8.382" y2="9.69" width="0.254" layer="1"/>
+</signal>
+<signal name="N$11">
+</signal>
+<signal name="I_RESET">
+<contactref element="RN1" pad="3"/>
+<contactref element="IC2" pad="14"/>
+<via x="10.668" y="8.636" extent="1-16" drill="0.3302" diameter="0.508"/>
+<wire x1="7.814" y1="10.16" x2="9.144" y2="10.16" width="0.254" layer="16"/>
+<wire x1="9.144" y1="10.16" x2="10.668" y2="8.636" width="0.254" layer="16"/>
+<wire x1="11.694" y1="8.49" x2="10.814" y2="8.49" width="0.254" layer="1"/>
+<wire x1="10.814" y1="8.49" x2="10.668" y2="8.636" width="0.254" layer="1"/>
+</signal>
+<signal name="I_TDI">
+<contactref element="RN1" pad="4"/>
+<contactref element="IC2" pad="3"/>
+<via x="10.668" y="7.62" extent="1-16" drill="0.3302"/>
+<wire x1="11.694" y1="7.69" x2="10.738" y2="7.69" width="0.254" layer="1"/>
+<wire x1="10.738" y1="7.69" x2="10.668" y2="7.62" width="0.254" layer="1"/>
+<wire x1="13.014" y1="7.62" x2="10.668" y2="7.62" width="0.254" layer="16"/>
+</signal>
+<signal name="I_SWDIO_TMS">
+<contactref element="RN2" pad="3"/>
+<contactref element="IC2" pad="5"/>
+<via x="10.668" y="3.81" extent="1-16" drill="0.3302"/>
+<wire x1="10.668" y1="3.81" x2="11.938" y2="5.08" width="0.254" layer="16"/>
+<wire x1="11.938" y1="5.08" x2="13.014" y2="5.08" width="0.254" layer="16"/>
+<wire x1="11.694" y1="3.664" x2="10.814" y2="3.664" width="0.254" layer="1"/>
+<wire x1="10.814" y1="3.664" x2="10.668" y2="3.81" width="0.254" layer="1"/>
+</signal>
+<signal name="I_SWCLK_TCK">
+<contactref element="RN2" pad="2"/>
+<contactref element="IC2" pad="13"/>
+<via x="10.668" y="4.826" extent="1-16" drill="0.3302" diameter="0.508"/>
+<wire x1="7.814" y1="8.89" x2="9.398" y2="8.89" width="0.254" layer="16"/>
+<wire x1="9.398" y1="8.89" x2="9.906" y2="8.382" width="0.254" layer="16"/>
+<wire x1="9.906" y1="8.382" x2="9.906" y2="5.588" width="0.254" layer="16"/>
+<wire x1="11.694" y1="4.464" x2="11.03" y2="4.464" width="0.254" layer="1"/>
+<wire x1="11.03" y1="4.464" x2="10.668" y2="4.826" width="0.254" layer="1"/>
+<wire x1="9.906" y1="5.588" x2="10.668" y2="4.826" width="0.254" layer="16"/>
+</signal>
+<signal name="I_TDO">
+<contactref element="RN2" pad="1"/>
+<contactref element="IC2" pad="4"/>
+<via x="11.684" y="6.35" extent="1-16" drill="0.3302"/>
+<wire x1="11.684" y1="6.35" x2="11.684" y2="5.274" width="0.254" layer="1"/>
+<wire x1="11.684" y1="5.274" x2="11.694" y2="5.264" width="0.254" layer="1"/>
+<wire x1="13.014" y1="6.35" x2="11.684" y2="6.35" width="0.254" layer="16"/>
+</signal>
+<signal name="I_RX">
+<contactref element="IC2" pad="1"/>
+<contactref element="RN1" pad="1"/>
+<via x="11.684" y="10.16" extent="1-16" drill="0.3302"/>
+<wire x1="13.014" y1="10.16" x2="11.684" y2="10.16" width="0.254" layer="16"/>
+<wire x1="11.694" y1="10.09" x2="11.694" y2="10.15" width="0.254" layer="1"/>
+<wire x1="11.694" y1="10.15" x2="11.684" y2="10.16" width="0.254" layer="1"/>
+</signal>
+<signal name="N$18">
+<contactref element="RN2" pad="5"/>
+</signal>
+<signal name="T_RX">
+<contactref element="RN1" pad="8"/>
+<contactref element="J2" pad="1"/>
+<wire x1="13.198" y1="10.09" x2="18.104" y2="10.09" width="0.254" layer="1"/>
+<wire x1="18.104" y1="10.09" x2="19.812" y2="8.382" width="0.254" layer="1"/>
+<wire x1="19.812" y1="8.382" x2="19.812" y2="6.858" width="0.254" layer="1"/>
+<wire x1="19.812" y1="6.858" x2="18.542" y2="5.588" width="0.254" layer="1"/>
+</signal>
+<signal name="T_TX">
+<contactref element="RN1" pad="7"/>
+<contactref element="J3" pad="1"/>
+<wire x1="13.198" y1="9.29" x2="13.608" y2="9.29" width="0.254" layer="1"/>
+<wire x1="13.608" y1="9.29" x2="13.716" y2="9.398" width="0.254" layer="1"/>
+<wire x1="13.716" y1="9.398" x2="17.272" y2="9.398" width="0.254" layer="1"/>
+<wire x1="17.272" y1="9.398" x2="18.542" y2="8.128" width="0.254" layer="1"/>
+</signal>
+<signal name="T_TDO">
+<contactref element="J1" pad="6"/>
+<contactref element="RN2" pad="8"/>
+<wire x1="13.198" y1="5.264" x2="15.043" y2="5.264" width="0.254" layer="1"/>
+<wire x1="15.043" y1="5.264" x2="15.367" y2="5.588" width="0.254" layer="1"/>
+</signal>
+<signal name="T_TDI">
+<contactref element="J1" pad="8"/>
+<contactref element="RN1" pad="5"/>
+<wire x1="13.198" y1="7.69" x2="14.535" y2="7.69" width="0.254" layer="1"/>
+<wire x1="14.535" y1="7.69" x2="15.367" y2="6.858" width="0.254" layer="1"/>
+</signal>
+</signals>
+</board>
+</drawing>
+</eagle>

dap_link/lib/free-dap/hardware/d11_micro_std_vcp_v4/d11_micro_vcp_v4.sch

@@ -0,0 +1,1553 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="7.3.0">
+<drawing>
+<settings>
+<setting alwaysvectorfont="no"/>
+<setting verticaltext="up"/>
+</settings>
+<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>
+<layers>
+<layer number="1" name="Top" color="4" fill="1" visible="no" active="no"/>
+<layer number="16" name="Bottom" color="1" fill="1" visible="no" active="no"/>
+<layer number="17" name="Pads" color="2" fill="1" visible="no" active="no"/>
+<layer number="18" name="Vias" color="2" fill="1" visible="no" active="no"/>
+<layer number="19" name="Unrouted" color="6" fill="1" visible="no" active="no"/>
+<layer number="20" name="Dimension" color="15" fill="1" visible="no" active="no"/>
+<layer number="21" name="tPlace" color="7" fill="1" visible="no" active="no"/>
+<layer number="22" name="bPlace" color="7" fill="1" visible="no" active="no"/>
+<layer number="23" name="tOrigins" color="15" fill="1" visible="no" active="no"/>
+<layer number="24" name="bOrigins" color="15" fill="1" visible="no" active="no"/>
+<layer number="25" name="tNames" color="7" fill="1" visible="no" active="no"/>
+<layer number="26" name="bNames" color="7" fill="1" visible="no" active="no"/>
+<layer number="27" name="tValues" color="7" fill="1" visible="no" active="no"/>
+<layer number="28" name="bValues" color="7" fill="1" visible="no" active="no"/>
+<layer number="29" name="tStop" color="7" fill="3" visible="no" active="no"/>
+<layer number="30" name="bStop" color="7" fill="6" visible="no" active="no"/>
+<layer number="31" name="tCream" color="7" fill="4" visible="no" active="no"/>
+<layer number="32" name="bCream" color="7" fill="5" visible="no" active="no"/>
+<layer number="33" name="tFinish" color="6" fill="3" visible="no" active="no"/>
+<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="no"/>
+<layer number="35" name="tGlue" color="7" fill="4" visible="no" active="no"/>
+<layer number="36" name="bGlue" color="7" fill="5" visible="no" active="no"/>
+<layer number="37" name="tTest" color="7" fill="1" visible="no" active="no"/>
+<layer number="38" name="bTest" color="7" fill="1" visible="no" active="no"/>
+<layer number="39" name="tKeepout" color="4" fill="11" visible="no" active="no"/>
+<layer number="40" name="bKeepout" color="1" fill="11" visible="no" active="no"/>
+<layer number="41" name="tRestrict" color="4" fill="10" visible="no" active="no"/>
+<layer number="42" name="bRestrict" color="1" fill="10" visible="no" active="no"/>
+<layer number="43" name="vRestrict" color="2" fill="10" visible="no" active="no"/>
+<layer number="44" name="Drills" color="7" fill="1" visible="no" active="no"/>
+<layer number="45" name="Holes" color="7" fill="1" visible="no" active="no"/>
+<layer number="46" name="Milling" color="3" fill="1" visible="no" active="no"/>
+<layer number="47" name="Measures" color="7" fill="1" visible="no" active="no"/>
+<layer number="48" name="Document" color="7" fill="1" visible="no" active="no"/>
+<layer number="49" name="Reference" color="7" fill="1" visible="no" active="no"/>
+<layer number="51" name="tDocu" color="6" fill="1" visible="no" active="no"/>
+<layer number="52" name="bDocu" color="7" fill="1" visible="no" active="no"/>
+<layer number="90" name="Modules" color="5" fill="1" visible="yes" active="yes"/>
+<layer number="91" name="Nets" color="2" fill="1" visible="yes" active="yes"/>
+<layer number="92" name="Busses" color="1" fill="1" visible="yes" active="yes"/>
+<layer number="93" name="Pins" color="2" fill="1" visible="no" active="yes"/>
+<layer number="94" name="Symbols" color="4" fill="1" visible="yes" active="yes"/>
+<layer number="95" name="Names" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="96" name="Values" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="97" name="Info" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/>
+</layers>
+<schematic xreflabel="%F%N/%S.%C%R" xrefpart="/%S.%C%R">
+<libraries>
+<library name="ataradov_mcu">
+<description>Alex Taradov Library (MCUs)</description>
+<packages>
+<package name="SO-14">
+<description>SO-14</description>
+<wire x1="4.318" y1="-1.143" x2="-3.175" y2="-1.143" width="0.127" layer="21"/>
+<wire x1="-3.175" y1="-1.143" x2="-4.318" y2="-1.143" width="0.127" layer="21"/>
+<wire x1="-4.318" y1="-1.143" x2="-4.318" y2="0" width="0.127" layer="21"/>
+<wire x1="-4.318" y1="0" x2="-4.318" y2="1.143" width="0.127" layer="21"/>
+<wire x1="4.318" y1="1.143" x2="4.318" y2="-1.143" width="0.127" layer="21"/>
+<wire x1="-4.318" y1="1.143" x2="4.318" y2="1.143" width="0.127" layer="21"/>
+<smd name="2" x="-2.54" y="-2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="13" x="-2.54" y="2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="1" x="-3.81" y="-2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="3" x="-1.27" y="-2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="4" x="0" y="-2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="14" x="-3.81" y="2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="12" x="-1.27" y="2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="11" x="0" y="2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="6" x="2.54" y="-2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="9" x="2.54" y="2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="5" x="1.27" y="-2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="7" x="3.81" y="-2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="10" x="1.27" y="2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="8" x="3.81" y="2.6" dx="0.6" dy="2.2" layer="1"/>
+<text x="0" y="-0.635" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<wire x1="-4.318" y1="0" x2="-3.175" y2="-1.143" width="0.127" layer="21"/>
+<circle x="-4.699" y="-1.524" radius="0.127" width="0.254" layer="21"/>
+</package>
+</packages>
+<symbols>
+<symbol name="ATSAMDXXC">
+<description>Atmel SAM D09C/D10C/D11C Cortex-M0+ microcontroller</description>
+<wire x1="-12.7" y1="10.16" x2="12.7" y2="10.16" width="0.254" layer="94"/>
+<wire x1="12.7" y1="10.16" x2="12.7" y2="-10.16" width="0.254" layer="94"/>
+<wire x1="12.7" y1="-10.16" x2="-12.7" y2="-10.16" width="0.254" layer="94"/>
+<wire x1="-12.7" y1="-10.16" x2="-12.7" y2="10.16" width="0.254" layer="94"/>
+<pin name="PA28/RST" x="-17.78" y="-5.08" length="middle"/>
+<pin name="PA8" x="-17.78" y="5.08" length="middle"/>
+<pin name="PA9" x="-17.78" y="2.54" length="middle"/>
+<pin name="PA14" x="-17.78" y="0" length="middle"/>
+<pin name="PA15" x="-17.78" y="-2.54" length="middle"/>
+<pin name="PA5" x="-17.78" y="7.62" length="middle"/>
+<pin name="PA04" x="17.78" y="7.62" length="middle" rot="R180"/>
+<pin name="PA02" x="17.78" y="5.08" length="middle" rot="R180"/>
+<text x="0" y="10.922" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-12.192" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+<pin name="PA30/SCK" x="-17.78" y="-7.62" length="middle"/>
+<pin name="VDD" x="17.78" y="2.54" length="middle" rot="R180"/>
+<pin name="GND" x="17.78" y="0" length="middle" rot="R180"/>
+<pin name="PA25" x="17.78" y="-2.54" length="middle" rot="R180"/>
+<pin name="PA24" x="17.78" y="-5.08" length="middle" rot="R180"/>
+<pin name="PA31/SIO" x="17.78" y="-7.62" length="middle" rot="R180"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="ATSAMD11C" prefix="IC">
+<gates>
+<gate name="G$1" symbol="ATSAMDXXC" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="SO-14">
+<connects>
+<connect gate="G$1" pin="GND" pad="11"/>
+<connect gate="G$1" pin="PA02" pad="13"/>
+<connect gate="G$1" pin="PA04" pad="14"/>
+<connect gate="G$1" pin="PA14" pad="4"/>
+<connect gate="G$1" pin="PA15" pad="5"/>
+<connect gate="G$1" pin="PA24" pad="9"/>
+<connect gate="G$1" pin="PA25" pad="10"/>
+<connect gate="G$1" pin="PA28/RST" pad="6"/>
+<connect gate="G$1" pin="PA30/SCK" pad="7"/>
+<connect gate="G$1" pin="PA31/SIO" pad="8"/>
+<connect gate="G$1" pin="PA5" pad="1"/>
+<connect gate="G$1" pin="PA8" pad="2"/>
+<connect gate="G$1" pin="PA9" pad="3"/>
+<connect gate="G$1" pin="VDD" pad="12"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_pwr">
+<description>Alex Taradov Library (Power Symbols)</description>
+<packages>
+</packages>
+<symbols>
+<symbol name="+3V3">
+<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/>
+<text x="0" y="0.762" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+<pin name="+3V3" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/>
+</symbol>
+<symbol name="GND">
+<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/>
+<text x="0" y="-2.032" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+<pin name="GND" x="0" y="2.54" visible="off" length="short" direction="sup" rot="R270"/>
+</symbol>
+<symbol name="V_USB">
+<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/>
+<text x="0" y="0.762" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+<pin name="V_USB" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="+3V3" prefix="P_">
+<gates>
+<gate name="1" symbol="+3V3" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="GND" prefix="P_">
+<gates>
+<gate name="1" symbol="GND" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="V_USB" prefix="P_">
+<gates>
+<gate name="1" symbol="V_USB" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_conn">
+<description>Alex Taradov Library (Connectors)</description>
+<packages>
+<package name="HEADER-5X2-1.27MM">
+<wire x1="-3.81" y1="1.905" x2="3.81" y2="1.905" width="0.127" layer="21"/>
+<wire x1="3.81" y1="1.905" x2="3.81" y2="-1.905" width="0.127" layer="21"/>
+<wire x1="3.81" y1="-1.905" x2="-3.175" y2="-1.905" width="0.127" layer="21"/>
+<wire x1="-3.175" y1="-1.905" x2="-3.81" y2="-1.27" width="0.127" layer="21"/>
+<wire x1="-3.81" y1="-1.27" x2="-3.81" y2="1.905" width="0.127" layer="21"/>
+<pad name="1" x="-2.54" y="-0.635" drill="0.6096" diameter="1.016"/>
+<pad name="2" x="-2.54" y="0.635" drill="0.6096" diameter="1.016"/>
+<pad name="3" x="-1.27" y="-0.635" drill="0.6096" diameter="1.016"/>
+<pad name="4" x="-1.27" y="0.635" drill="0.6096" diameter="1.016"/>
+<pad name="5" x="0" y="-0.635" drill="0.6096" diameter="1.016"/>
+<pad name="6" x="0" y="0.635" drill="0.6096" diameter="1.016"/>
+<pad name="7" x="1.27" y="-0.635" drill="0.6096" diameter="1.016"/>
+<pad name="8" x="1.27" y="0.635" drill="0.6096" diameter="1.016"/>
+<pad name="9" x="2.54" y="-0.635" drill="0.6096" diameter="1.016"/>
+<pad name="10" x="2.54" y="0.635" drill="0.6096" diameter="1.016"/>
+<text x="0" y="2.54" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="HEADER-5X2-2.54MM">
+<wire x1="-6.35" y1="0" x2="-3.81" y2="0" width="0.127" layer="21"/>
+<wire x1="-3.81" y1="0" x2="-3.81" y2="-2.54" width="0.127" layer="21"/>
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+<connect gate="G$1" pin="9" pad="9"/>
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+<connect gate="G$1" pin="2" pad="2"/>
+<connect gate="G$1" pin="3" pad="3"/>
+<connect gate="G$1" pin="4" pad="4"/>
+<connect gate="G$1" pin="5" pad="5"/>
+<connect gate="G$1" pin="6" pad="6"/>
+<connect gate="G$1" pin="7" pad="7"/>
+<connect gate="G$1" pin="8" pad="8"/>
+<connect gate="G$1" pin="9" pad="9"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="USB-B-MICRO" prefix="J" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="MICRO-USB-5" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-SMT" package="USB-B-MICRO-SMT-SHELL-TH">
+<connects>
+<connect gate="G$1" pin="DM" pad="2"/>
+<connect gate="G$1" pin="DP" pad="3"/>
+<connect gate="G$1" pin="GND" pad="5"/>
+<connect gate="G$1" pin="ID" pad="4"/>
+<connect gate="G$1" pin="SHIELD" pad="M1 M2 M3 M4" route="any"/>
+<connect gate="G$1" pin="VBUS" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="CONN-SINGLE" prefix="J" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="CONN-SINGLE" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-TH" package="PIN-TH">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-TH-LARGE" package="PIN-TH-LARGE">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-TH-SMALL" package="PIN-TH-SMALL">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_rlc">
+<description>Alex Taradov Library (R, L and C)</description>
+<packages>
+<package name="SMD0508">
+<wire x1="-1" y1="1.25" x2="1" y2="1.25" width="0.1" layer="21"/>
+<wire x1="1" y1="1.25" x2="1" y2="-1.25" width="0.1" layer="21"/>
+<wire x1="1" y1="-1.25" x2="-1" y2="-1.25" width="0.1" layer="21"/>
+<wire x1="-1" y1="-1.25" x2="-1" y2="1.25" width="0.1" layer="21"/>
+<smd name="1" x="-0.5" y="0" dx="2" dy="0.5" layer="1" rot="R90"/>
+<smd name="2" x="0.5" y="0" dx="2" dy="0.5" layer="1" rot="R90"/>
+<text x="0" y="1.524" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SMD0603">
+<wire x1="-1.5" y1="0.75" x2="1.5" y2="0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="0.75" x2="1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="-0.75" x2="-1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="-1.5" y1="-0.75" x2="-1.5" y2="0.75" width="0.1" layer="21"/>
+<smd name="1" x="-0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<smd name="2" x="0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+<package name="SMD0612">
+<wire x1="-1.8" y1="1.4" x2="1.8" y2="1.4" width="0.1" layer="21"/>
+<wire x1="1.8" y1="1.4" x2="1.8" y2="-1.4" width="0.1" layer="21"/>
+<wire x1="1.8" y1="-1.4" x2="-1.8" y2="-1.4" width="0.1" layer="21"/>
+<wire x1="-1.8" y1="-1.4" x2="-1.8" y2="1.4" width="0.1" layer="21"/>
+<smd name="1" x="0" y="0.8" dx="3.2" dy="0.8" layer="1"/>
+<smd name="2" x="0" y="-0.8" dx="3.2" dy="0.8" layer="1"/>
+<text x="0" y="1.778" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SMD1206">
+<wire x1="-2.5" y1="1.5" x2="2.5" y2="1.5" width="0.1" layer="21"/>
+<wire x1="2.5" y1="1.5" x2="2.5" y2="-1.5" width="0.1" layer="21"/>
+<wire x1="2.5" y1="-1.5" x2="-2.5" y2="-1.5" width="0.1" layer="21"/>
+<wire x1="-2.5" y1="-1.5" x2="-2.5" y2="1.5" width="0.1" layer="21"/>
+<smd name="1" x="-1.4" y="0" dx="1.6" dy="2" layer="1"/>
+<smd name="2" x="1.4" y="0" dx="1.6" dy="2" layer="1"/>
+<text x="0" y="1.778" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SMD2512">
+<wire x1="-5.5" y1="2.5" x2="5.5" y2="2.5" width="0.1" layer="21"/>
+<wire x1="5.5" y1="2.5" x2="5.5" y2="-2.5" width="0.1" layer="21"/>
+<wire x1="5.5" y1="-2.5" x2="-5.5" y2="-2.5" width="0.1" layer="21"/>
+<wire x1="-5.5" y1="-2.5" x2="-5.5" y2="2.5" width="0.1" layer="21"/>
+<smd name="1" x="-3.25" y="0" dx="3.5" dy="3" layer="1" rot="R90"/>
+<smd name="2" x="3.25" y="0" dx="3.5" dy="3" layer="1" rot="R90"/>
+<text x="0" y="2.794" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SMD0603-X4">
+<smd name="1" x="-1.2" y="-0.752" dx="0.5" dy="0.889" layer="1"/>
+<smd name="2" x="-0.4" y="-0.752" dx="0.5" dy="0.889" layer="1"/>
+<smd name="3" x="0.4" y="-0.752" dx="0.5" dy="0.889" layer="1"/>
+<smd name="4" x="1.2" y="-0.752" dx="0.5" dy="0.889" layer="1"/>
+<smd name="5" x="1.2" y="0.752" dx="0.5" dy="0.889" layer="1"/>
+<smd name="6" x="0.4" y="0.752" dx="0.5" dy="0.889" layer="1"/>
+<smd name="7" x="-0.4" y="0.752" dx="0.5" dy="0.889" layer="1"/>
+<smd name="8" x="-1.2" y="0.752" dx="0.5" dy="0.889" layer="1"/>
+<text x="0" y="1.778" size="1.27" layer="25" font="vector" ratio="10" align="bottom-center">&gt;NAME</text>
+<wire x1="1.778" y1="1.4986" x2="1.778" y2="-1.524" width="0.1016" layer="21"/>
+<wire x1="-1.778" y1="1.4986" x2="-1.778" y2="-1.524" width="0.1016" layer="21"/>
+<wire x1="-1.778" y1="1.4986" x2="1.778" y2="1.4986" width="0.1016" layer="21"/>
+<wire x1="-1.778" y1="-1.524" x2="1.778" y2="-1.524" width="0.1016" layer="21"/>
+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" ratio="10" align="bottom-center">&gt;VALUE</text>
+</package>
+<package name="SMD0402">
+<wire x1="-1" y1="0.5" x2="1" y2="0.5" width="0.1" layer="21"/>
+<wire x1="1" y1="0.5" x2="1" y2="-0.5" width="0.1" layer="21"/>
+<wire x1="1" y1="-0.5" x2="-1" y2="-0.5" width="0.1" layer="21"/>
+<wire x1="-1" y1="-0.5" x2="-1" y2="0.5" width="0.1" layer="21"/>
+<smd name="1" x="-0.5" y="0" dx="0.6" dy="0.6" layer="1"/>
+<smd name="2" x="0.5" y="0" dx="0.6" dy="0.6" layer="1"/>
+<text x="0" y="0.762" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+<package name="SMD0805">
+<wire x1="-2" y1="1" x2="2" y2="1" width="0.1" layer="21"/>
+<wire x1="2" y1="1" x2="2" y2="-1" width="0.1" layer="21"/>
+<wire x1="2" y1="-1" x2="-2" y2="-1" width="0.1" layer="21"/>
+<wire x1="-2" y1="-1" x2="-2" y2="1" width="0.1" layer="21"/>
+<smd name="1" x="-0.95" y="0" dx="1.3" dy="1.5" layer="1"/>
+<smd name="2" x="0.95" y="0" dx="1.3" dy="1.5" layer="1"/>
+<text x="0" y="1.27" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+</packages>
+<symbols>
+<symbol name="C">
+<rectangle x1="-1.524" y1="-0.254" x2="2.54" y2="0.254" layer="94" rot="R90"/>
+<rectangle x1="-2.54" y1="-0.254" x2="1.524" y2="0.254" layer="94" rot="R90"/>
+<wire x1="-2.54" y1="0" x2="-0.762" y2="0" width="0.1524" layer="94"/>
+<wire x1="2.54" y1="0" x2="0.762" y2="0" width="0.1524" layer="94"/>
+<pin name="1" x="-2.54" y="0" visible="off" length="point" direction="pas" swaplevel="1"/>
+<pin name="2" x="2.54" y="0" visible="off" length="point" direction="pas" swaplevel="1" rot="R180"/>
+<text x="0" y="2.413" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-3.683" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+</symbol>
+<symbol name="R">
+<wire x1="-2.54" y1="-1.016" x2="-2.54" y2="1.016" width="0.254" layer="94"/>
+<pin name="1" x="-5.08" y="0" visible="off" length="short" direction="pas" swaplevel="1"/>
+<pin name="2" x="5.08" y="0" visible="off" length="short" direction="pas" swaplevel="1" rot="R180"/>
+<text x="0" y="1.524" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<text x="0" y="0" size="1.016" layer="96" align="center">&gt;VALUE</text>
+<wire x1="2.54" y1="-1.016" x2="2.54" y2="1.016" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="1.016" x2="2.54" y2="1.016" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="-1.016" x2="2.54" y2="-1.016" width="0.254" layer="94"/>
+</symbol>
+<symbol name="RN-4">
+<wire x1="-2.54" y1="1.524" x2="-2.54" y2="3.556" width="0.254" layer="94"/>
+<pin name="1" x="-5.08" y="2.54" visible="off" length="short" direction="pas"/>
+<pin name="8" x="5.08" y="2.54" visible="off" length="short" direction="pas" rot="R180"/>
+<text x="0" y="4.572" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<wire x1="2.54" y1="1.524" x2="2.54" y2="3.556" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="3.556" x2="2.54" y2="3.556" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="1.524" x2="2.54" y2="1.524" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="-1.016" x2="-2.54" y2="1.016" width="0.254" layer="94"/>
+<pin name="2" x="-5.08" y="0" visible="off" length="short" direction="pas"/>
+<pin name="7" x="5.08" y="0" visible="off" length="short" direction="pas" rot="R180"/>
+<wire x1="2.54" y1="-1.016" x2="2.54" y2="1.016" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="1.016" x2="2.54" y2="1.016" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="-1.016" x2="2.54" y2="-1.016" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="-3.556" x2="-2.54" y2="-1.524" width="0.254" layer="94"/>
+<pin name="3" x="-5.08" y="-2.54" visible="off" length="short" direction="pas"/>
+<pin name="6" x="5.08" y="-2.54" visible="off" length="short" direction="pas" rot="R180"/>
+<wire x1="2.54" y1="-3.556" x2="2.54" y2="-1.524" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="-1.524" x2="2.54" y2="-1.524" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="-3.556" x2="2.54" y2="-3.556" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="-6.096" x2="-2.54" y2="-4.064" width="0.254" layer="94"/>
+<pin name="4" x="-5.08" y="-5.08" visible="off" length="short" direction="pas"/>
+<pin name="5" x="5.08" y="-5.08" visible="off" length="short" direction="pas" rot="R180"/>
+<text x="0" y="2.54" size="1.016" layer="96" align="center">&gt;VALUE</text>
+<wire x1="2.54" y1="-6.096" x2="2.54" y2="-4.064" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="-4.064" x2="2.54" y2="-4.064" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="-6.096" x2="2.54" y2="-6.096" width="0.254" layer="94"/>
+<wire x1="-3.048" y1="-6.604" x2="-3.048" y2="4.064" width="0.127" layer="94" style="shortdash"/>
+<wire x1="3.048" y1="-6.604" x2="3.048" y2="4.064" width="0.127" layer="94" style="shortdash"/>
+<wire x1="3.048" y1="-6.604" x2="-3.048" y2="-6.604" width="0.127" layer="94" style="shortdash"/>
+<wire x1="3.048" y1="4.064" x2="-3.048" y2="4.064" width="0.127" layer="94" style="shortdash"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="C" prefix="C" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="C" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-0402" package="SMD0402">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0508" package="SMD0508">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0603" package="SMD0603">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0612" package="SMD0612">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0805" package="SMD0805">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-1206" package="SMD1206">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-2512" package="SMD2512">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="R" prefix="R" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="R" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-0402" package="SMD0402">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0508" package="SMD0508">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0603" package="SMD0603">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0612" package="SMD0612">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0805" package="SMD0805">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-1206" package="SMD1206">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-2512" package="SMD2512">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="RN-4" prefix="RN" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="RN-4" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-0603-X4" package="SMD0603-X4">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+<connect gate="G$1" pin="3" pad="3"/>
+<connect gate="G$1" pin="4" pad="4"/>
+<connect gate="G$1" pin="5" pad="5"/>
+<connect gate="G$1" pin="6" pad="6"/>
+<connect gate="G$1" pin="7" pad="7"/>
+<connect gate="G$1" pin="8" pad="8"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_vreg">
+<description>Alex Taradov Library (Voltage Regulators)</description>
+<packages>
+<package name="SOT23-5">
+<description>SOT23-5</description>
+<wire x1="1.422" y1="0.81" x2="1.422" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="1.422" y1="-0.81" x2="-1.422" y2="-0.81" width="0.1524" layer="51"/>
+<wire x1="-1.422" y1="-0.81" x2="-1.422" y2="0.81" width="0.1524" layer="21"/>
+<wire x1="-1.422" y1="0.81" x2="1.422" y2="0.81" width="0.1524" layer="51"/>
+<wire x1="-0.522" y1="0.81" x2="0.522" y2="0.81" width="0.1524" layer="21"/>
+<wire x1="-0.428" y1="-0.81" x2="-0.522" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="0.522" y1="-0.81" x2="0.428" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="-1.328" y1="-0.81" x2="-1.422" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="1.422" y1="-0.81" x2="1.328" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="1.328" y1="0.81" x2="1.422" y2="0.81" width="0.1524" layer="21"/>
+<wire x1="-1.422" y1="0.81" x2="-1.328" y2="0.81" width="0.1524" layer="21"/>
+<smd name="1" x="-0.95" y="-1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="2" x="0" y="-1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="3" x="0.95" y="-1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="4" x="0.95" y="1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="5" x="-0.95" y="1.3" dx="0.55" dy="1.2" layer="1"/>
+<text x="0" y="2.286" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+</packages>
+<symbols>
+<symbol name="VREG-3-EN">
+<wire x1="-7.62" y1="5.08" x2="7.62" y2="5.08" width="0.254" layer="94"/>
+<wire x1="7.62" y1="5.08" x2="7.62" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="7.62" y1="-2.54" x2="-7.62" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="-7.62" y1="-2.54" x2="-7.62" y2="5.08" width="0.254" layer="94"/>
+<text x="-2.032" y="-1.524" size="1.524" layer="95">GND</text>
+<text x="0" y="5.842" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<text x="1.524" y="-4.318" size="1.27" layer="96">&gt;VALUE</text>
+<pin name="IN" x="-10.16" y="2.54" length="short" direction="pas"/>
+<pin name="OUT" x="10.16" y="2.54" length="short" direction="pas" rot="R180"/>
+<pin name="GND" x="0" y="-5.08" visible="pad" length="short" direction="pas" rot="R90"/>
+<pin name="EN" x="-10.16" y="0" length="short" direction="pas"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="MIC5504" prefix="IC" uservalue="yes">
+<description>LM1117 voltage regulator</description>
+<gates>
+<gate name="G$1" symbol="VREG-3-EN" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-SOT23-5" package="SOT23-5">
+<connects>
+<connect gate="G$1" pin="EN" pad="3"/>
+<connect gate="G$1" pin="GND" pad="2"/>
+<connect gate="G$1" pin="IN" pad="1"/>
+<connect gate="G$1" pin="OUT" pad="5"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_misc">
+<description>Alex Taradov Library (Miscellaneous stuff)</description>
+<packages>
+<package name="TP-1.27MM">
+<smd name="1" x="0" y="0" dx="1.27" dy="1.27" layer="1" roundness="100" cream="no"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="TP-2.54MM">
+<smd name="1" x="0" y="0" dx="2.54" dy="2.54" layer="1" roundness="100" cream="no"/>
+<text x="0" y="1.778" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="TP-0.635MM">
+<smd name="1" x="0" y="0" dx="0.635" dy="0.635" layer="1" roundness="100" cream="no"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="TP-0.5MM">
+<smd name="1" x="0" y="0" dx="0.5" dy="0.5" layer="1" roundness="100" cream="no"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="TP-1.27MM-TH">
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<pad name="1" x="0" y="0" drill="0.762" diameter="1.27"/>
+</package>
+</packages>
+<symbols>
+<symbol name="TP">
+<text x="4.064" y="-0.508" size="1.27" layer="95">&gt;NAME</text>
+<pin name="1" x="0" y="0" visible="off" length="short" direction="pas"/>
+<circle x="3.048" y="0" radius="0.508" width="0" layer="94"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="TEST-POINT" prefix="TP" uservalue="yes">
+<description>Test Point</description>
+<gates>
+<gate name="G$1" symbol="TP" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-1.27MM" package="TP-1.27MM">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0.635MM" package="TP-0.635MM">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0.5MM" package="TP-0.5MM">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-2.54MM" package="TP-2.54MM">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-1.27MM-TH" package="TP-1.27MM-TH">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_led">
+<description>Alex Taradov Library (LEDs and other indication devices)</description>
+<packages>
+<package name="SMD0603">
+<wire x1="-1.5" y1="0.75" x2="1.5" y2="0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="0.75" x2="1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="-0.75" x2="-1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="-1.5" y1="-0.75" x2="-1.5" y2="0.75" width="0.1" layer="21"/>
+<smd name="1" x="-0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<smd name="2" x="0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+<package name="SMD0805">
+<wire x1="-2" y1="1" x2="2" y2="1" width="0.1" layer="21"/>
+<wire x1="2" y1="1" x2="2" y2="-1" width="0.1" layer="21"/>
+<wire x1="2" y1="-1" x2="-2" y2="-1" width="0.1" layer="21"/>
+<wire x1="-2" y1="-1" x2="-2" y2="1" width="0.1" layer="21"/>
+<smd name="1" x="-0.95" y="0" dx="1.3" dy="1.5" layer="1"/>
+<smd name="2" x="0.95" y="0" dx="1.3" dy="1.5" layer="1"/>
+<text x="0" y="1.27" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+</packages>
+<symbols>
+<symbol name="LED">
+<wire x1="1.27" y1="0" x2="0" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="0" y1="-2.54" x2="-1.27" y2="0" width="0.254" layer="94"/>
+<wire x1="1.27" y1="-2.54" x2="0" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="0" y1="-2.54" x2="-1.27" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="1.27" y1="0" x2="0" y2="0" width="0.254" layer="94"/>
+<wire x1="0" y1="0" x2="-1.27" y2="0" width="0.254" layer="94"/>
+<wire x1="-2.032" y1="-0.762" x2="-3.429" y2="-2.159" width="0.1524" layer="94"/>
+<wire x1="-1.905" y1="-1.905" x2="-3.302" y2="-3.302" width="0.1524" layer="94"/>
+<text x="3.556" y="-2.032" size="1.27" layer="95" rot="R90" align="bottom-center">&gt;NAME</text>
+<text x="5.715" y="-2.032" size="1.27" layer="96" rot="R90" align="bottom-center">&gt;VALUE</text>
+<pin name="C" x="0" y="-5.08" visible="off" length="short" direction="pas" rot="R90"/>
+<pin name="A" x="0" y="2.54" visible="off" length="short" direction="pas" rot="R270"/>
+<polygon width="0.1524" layer="94">
+<vertex x="-3.429" y="-2.159"/>
+<vertex x="-3.048" y="-1.27"/>
+<vertex x="-2.54" y="-1.778"/>
+</polygon>
+<polygon width="0.1524" layer="94">
+<vertex x="-3.302" y="-3.302"/>
+<vertex x="-2.921" y="-2.413"/>
+<vertex x="-2.413" y="-2.921"/>
+</polygon>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="LED_SMD" prefix="LED" uservalue="yes">
+<description>SMD_LED</description>
+<gates>
+<gate name="G$1" symbol="LED" x="0" y="0"/>
+</gates>
+<devices>
+<device name="LED_0603" package="SMD0603">
+<connects>
+<connect gate="G$1" pin="A" pad="1"/>
+<connect gate="G$1" pin="C" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="LED_0805" package="SMD0805">
+<connects>
+<connect gate="G$1" pin="A" pad="1"/>
+<connect gate="G$1" pin="C" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+</libraries>
+<attributes>
+</attributes>
+<variantdefs>
+</variantdefs>
+<classes>
+<class number="0" name="default" width="0" drill="0">
+</class>
+</classes>
+<parts>
+<part name="IC2" library="ataradov_mcu" deviceset="ATSAMD11C" device=""/>
+<part name="P_6" library="ataradov_pwr" deviceset="+3V3" device=""/>
+<part name="P_8" library="ataradov_pwr" deviceset="+3V3" device=""/>
+<part name="P_12" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_9" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_11" library="ataradov_pwr" deviceset="V_USB" device=""/>
+<part name="P_3" library="ataradov_pwr" deviceset="V_USB" device=""/>
+<part name="C1" library="ataradov_rlc" deviceset="C" device="-0603" value="1uF"/>
+<part name="C2" library="ataradov_rlc" deviceset="C" device="-0603" value="1uF"/>
+<part name="IC1" library="ataradov_vreg" deviceset="MIC5504" device="-SOT23-5" value="MIC5504-3.3"/>
+<part name="P_5" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_7" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_2" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="J1" library="ataradov_conn" deviceset="HEADER-5X2" device="-TH-1.27"/>
+<part name="P_4" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="J5" library="ataradov_conn" deviceset="USB-B-MICRO" device="-SMT"/>
+<part name="R1" library="ataradov_rlc" deviceset="R" device="-0603" value="10K"/>
+<part name="LED1" library="ataradov_led" deviceset="LED_SMD" device="LED_0603" value="GREEN"/>
+<part name="R2" library="ataradov_rlc" deviceset="R" device="-0603" value="10K"/>
+<part name="LED2" library="ataradov_led" deviceset="LED_SMD" device="LED_0603" value="ORANGE"/>
+<part name="P_13" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="J2" library="ataradov_conn" deviceset="CONN-SINGLE" device="-TH" value="RX"/>
+<part name="J3" library="ataradov_conn" deviceset="CONN-SINGLE" device="-TH" value="TX"/>
+<part name="J4" library="ataradov_conn" deviceset="CONN-SINGLE" device="-TH" value="GND"/>
+<part name="P_10" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="RN2" library="ataradov_rlc" deviceset="RN-4" device="-0603-X4" value="33"/>
+<part name="RN1" library="ataradov_rlc" deviceset="RN-4" device="-0603-X4" value="33"/>
+<part name="TP1" library="ataradov_misc" deviceset="TEST-POINT" device="-1.27MM"/>
+<part name="TP2" library="ataradov_misc" deviceset="TEST-POINT" device="-1.27MM"/>
+<part name="TP3" library="ataradov_misc" deviceset="TEST-POINT" device="-1.27MM"/>
+<part name="TP4" library="ataradov_misc" deviceset="TEST-POINT" device="-1.27MM"/>
+<part name="P_1" library="ataradov_pwr" deviceset="GND" device=""/>
+</parts>
+<sheets>
+<sheet>
+<plain>
+<frame x1="0" y1="0" x2="152.4" y2="119.38" columns="8" rows="5" layer="97"/>
+<text x="27.94" y="106.68" size="1.778" layer="97" align="bottom-center">Program</text>
+<text x="53.34" y="106.68" size="1.778" layer="97" align="bottom-center">Target</text>
+<text x="60.96" y="15.24" size="1.778" layer="97">CMSIS-DAP Debugger with VCP
+Copyright (c) 2021, Alex Taradov &lt;alex@taradov.com&gt;
+MCU firmware source code is available at https://github.com/ataradov/free-dap</text>
+<text x="86.36" y="106.68" size="1.778" layer="97" align="bottom-center">UART</text>
+</plain>
+<instances>
+<instance part="IC2" gate="G$1" x="40.64" y="53.34"/>
+<instance part="P_6" gate="1" x="53.34" y="27.94"/>
+<instance part="P_8" gate="1" x="60.96" y="66.04"/>
+<instance part="P_12" gate="1" x="83.82" y="40.64"/>
+<instance part="P_9" gate="1" x="60.96" y="40.64"/>
+<instance part="P_11" gate="1" x="83.82" y="60.96"/>
+<instance part="P_3" gate="1" x="25.4" y="27.94"/>
+<instance part="C1" gate="G$1" x="20.32" y="17.78" rot="R90"/>
+<instance part="C2" gate="G$1" x="53.34" y="17.78" rot="R90"/>
+<instance part="IC1" gate="G$1" x="38.1" y="20.32"/>
+<instance part="P_5" gate="1" x="38.1" y="12.7"/>
+<instance part="P_7" gate="1" x="53.34" y="12.7"/>
+<instance part="P_2" gate="1" x="20.32" y="12.7"/>
+<instance part="J1" gate="G$1" x="48.26" y="91.44"/>
+<instance part="P_4" gate="1" x="38.1" y="81.28"/>
+<instance part="J5" gate="G$1" x="93.98" y="50.8"/>
+<instance part="R1" gate="G$1" x="119.38" y="55.88"/>
+<instance part="LED1" gate="G$1" x="129.54" y="55.88" rot="MR270"/>
+<instance part="R2" gate="G$1" x="119.38" y="45.72"/>
+<instance part="LED2" gate="G$1" x="129.54" y="45.72" rot="MR270"/>
+<instance part="P_13" gate="1" x="137.16" y="40.64"/>
+<instance part="J2" gate="G$1" x="88.9" y="96.52"/>
+<instance part="J3" gate="G$1" x="88.9" y="93.98"/>
+<instance part="J4" gate="G$1" x="88.9" y="91.44"/>
+<instance part="P_10" gate="1" x="83.82" y="86.36"/>
+<instance part="RN2" gate="G$1" x="121.92" y="83.82"/>
+<instance part="RN1" gate="G$1" x="121.92" y="96.52"/>
+<instance part="TP1" gate="G$1" x="20.32" y="96.52"/>
+<instance part="TP2" gate="G$1" x="20.32" y="93.98"/>
+<instance part="TP3" gate="G$1" x="20.32" y="91.44"/>
+<instance part="TP4" gate="G$1" x="20.32" y="88.9"/>
+<instance part="P_1" gate="1" x="20.32" y="86.36"/>
+</instances>
+<busses>
+</busses>
+<nets>
+<net name="N$1" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA24"/>
+<wire x1="58.42" y1="48.26" x2="83.82" y2="48.26" width="0.1524" layer="91"/>
+<wire x1="83.82" y1="48.26" x2="83.82" y2="53.34" width="0.1524" layer="91"/>
+<wire x1="83.82" y1="53.34" x2="86.36" y2="53.34" width="0.1524" layer="91"/>
+<pinref part="J5" gate="G$1" pin="DM"/>
+</segment>
+</net>
+<net name="N$2" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA25"/>
+<wire x1="58.42" y1="50.8" x2="86.36" y2="50.8" width="0.1524" layer="91"/>
+<pinref part="J5" gate="G$1" pin="DP"/>
+</segment>
+</net>
+<net name="GND" class="0">
+<segment>
+<pinref part="P_12" gate="1" pin="GND"/>
+<wire x1="83.82" y1="43.18" x2="83.82" y2="45.72" width="0.1524" layer="91"/>
+<wire x1="83.82" y1="45.72" x2="86.36" y2="45.72" width="0.1524" layer="91"/>
+<pinref part="J5" gate="G$1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="IC1" gate="G$1" pin="GND"/>
+<pinref part="P_5" gate="1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="C1" gate="G$1" pin="1"/>
+<pinref part="P_2" gate="1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="C2" gate="G$1" pin="1"/>
+<pinref part="P_7" gate="1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="GND"/>
+<pinref part="P_9" gate="1" pin="GND"/>
+<wire x1="58.42" y1="53.34" x2="60.96" y2="53.34" width="0.1524" layer="91"/>
+<wire x1="60.96" y1="53.34" x2="60.96" y2="43.18" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="J1" gate="G$1" pin="3"/>
+<wire x1="40.64" y1="93.98" x2="38.1" y2="93.98" width="0.1524" layer="91"/>
+<pinref part="P_4" gate="1" pin="GND"/>
+<wire x1="38.1" y1="93.98" x2="38.1" y2="91.44" width="0.1524" layer="91"/>
+<pinref part="J1" gate="G$1" pin="5"/>
+<wire x1="38.1" y1="91.44" x2="38.1" y2="86.36" width="0.1524" layer="91"/>
+<wire x1="38.1" y1="86.36" x2="38.1" y2="83.82" width="0.1524" layer="91"/>
+<wire x1="40.64" y1="91.44" x2="38.1" y2="91.44" width="0.1524" layer="91"/>
+<junction x="38.1" y="91.44"/>
+<pinref part="J1" gate="G$1" pin="9"/>
+<wire x1="40.64" y1="86.36" x2="38.1" y2="86.36" width="0.1524" layer="91"/>
+<junction x="38.1" y="86.36"/>
+</segment>
+<segment>
+<pinref part="P_13" gate="1" pin="GND"/>
+<wire x1="137.16" y1="43.18" x2="137.16" y2="45.72" width="0.1524" layer="91"/>
+<wire x1="137.16" y1="45.72" x2="134.62" y2="45.72" width="0.1524" layer="91"/>
+<pinref part="LED2" gate="G$1" pin="C"/>
+<pinref part="LED1" gate="G$1" pin="C"/>
+<wire x1="137.16" y1="55.88" x2="137.16" y2="45.72" width="0.1524" layer="91"/>
+<wire x1="134.62" y1="55.88" x2="137.16" y2="55.88" width="0.1524" layer="91"/>
+<junction x="137.16" y="45.72"/>
+</segment>
+<segment>
+<pinref part="J4" gate="G$1" pin="1"/>
+<pinref part="P_10" gate="1" pin="GND"/>
+<wire x1="83.82" y1="88.9" x2="83.82" y2="91.44" width="0.1524" layer="91"/>
+<wire x1="83.82" y1="91.44" x2="86.36" y2="91.44" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="TP4" gate="G$1" pin="1"/>
+<pinref part="P_1" gate="1" pin="GND"/>
+</segment>
+</net>
+<net name="V_USB" class="0">
+<segment>
+<pinref part="P_11" gate="1" pin="V_USB"/>
+<wire x1="83.82" y1="58.42" x2="83.82" y2="55.88" width="0.1524" layer="91"/>
+<wire x1="83.82" y1="55.88" x2="86.36" y2="55.88" width="0.1524" layer="91"/>
+<pinref part="J5" gate="G$1" pin="VBUS"/>
+</segment>
+<segment>
+<pinref part="IC1" gate="G$1" pin="EN"/>
+<pinref part="P_3" gate="1" pin="V_USB"/>
+<wire x1="27.94" y1="20.32" x2="25.4" y2="20.32" width="0.1524" layer="91"/>
+<wire x1="25.4" y1="20.32" x2="25.4" y2="22.86" width="0.1524" layer="91"/>
+<pinref part="IC1" gate="G$1" pin="IN"/>
+<wire x1="25.4" y1="22.86" x2="25.4" y2="25.4" width="0.1524" layer="91"/>
+<wire x1="27.94" y1="22.86" x2="25.4" y2="22.86" width="0.1524" layer="91"/>
+<junction x="25.4" y="22.86"/>
+<pinref part="C1" gate="G$1" pin="2"/>
+<wire x1="25.4" y1="22.86" x2="20.32" y2="22.86" width="0.1524" layer="91"/>
+<wire x1="20.32" y1="22.86" x2="20.32" y2="20.32" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="+3V3" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="OUT"/>
+<wire x1="48.26" y1="22.86" x2="53.34" y2="22.86" width="0.1524" layer="91"/>
+<pinref part="C2" gate="G$1" pin="2"/>
+<wire x1="53.34" y1="20.32" x2="53.34" y2="22.86" width="0.1524" layer="91"/>
+<junction x="53.34" y="22.86"/>
+<pinref part="P_6" gate="1" pin="+3V3"/>
+<wire x1="53.34" y1="25.4" x2="53.34" y2="22.86" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="VDD"/>
+<pinref part="P_8" gate="1" pin="+3V3"/>
+<wire x1="58.42" y1="55.88" x2="60.96" y2="55.88" width="0.1524" layer="91"/>
+<wire x1="60.96" y1="55.88" x2="60.96" y2="63.5" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="SWDIO" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA31/SIO"/>
+<wire x1="58.42" y1="45.72" x2="63.5" y2="45.72" width="0.1524" layer="91"/>
+<label x="63.5" y="45.72" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="R1" gate="G$1" pin="1"/>
+<wire x1="114.3" y1="55.88" x2="111.76" y2="55.88" width="0.1524" layer="91"/>
+<label x="111.76" y="55.88" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="TP1" gate="G$1" pin="1"/>
+<wire x1="20.32" y1="96.52" x2="17.78" y2="96.52" width="0.1524" layer="91"/>
+<label x="17.78" y="96.52" size="1.27" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="SWCLK" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA30/SCK"/>
+<wire x1="22.86" y1="45.72" x2="20.32" y2="45.72" width="0.1524" layer="91"/>
+<label x="20.32" y="45.72" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="R2" gate="G$1" pin="1"/>
+<wire x1="114.3" y1="45.72" x2="111.76" y2="45.72" width="0.1524" layer="91"/>
+<label x="111.76" y="45.72" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="TP2" gate="G$1" pin="1"/>
+<wire x1="20.32" y1="93.98" x2="17.78" y2="93.98" width="0.1524" layer="91"/>
+<label x="17.78" y="93.98" size="1.27" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="RESET" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA28/RST"/>
+<wire x1="22.86" y1="48.26" x2="20.32" y2="48.26" width="0.1524" layer="91"/>
+<label x="20.32" y="48.26" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="TP3" gate="G$1" pin="1"/>
+<wire x1="20.32" y1="91.44" x2="17.78" y2="91.44" width="0.1524" layer="91"/>
+<label x="17.78" y="91.44" size="1.27" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="T_SWDIO_TMS" class="0">
+<segment>
+<pinref part="J1" gate="G$1" pin="2"/>
+<wire x1="55.88" y1="96.52" x2="58.42" y2="96.52" width="0.1524" layer="91"/>
+<label x="58.42" y="96.52" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="RN2" gate="G$1" pin="6"/>
+<wire x1="127" y1="81.28" x2="129.54" y2="81.28" width="0.1524" layer="91"/>
+<label x="129.54" y="81.28" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="T_SWCLK_TCK" class="0">
+<segment>
+<pinref part="J1" gate="G$1" pin="4"/>
+<wire x1="58.42" y1="93.98" x2="55.88" y2="93.98" width="0.1524" layer="91"/>
+<label x="58.42" y="93.98" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="RN2" gate="G$1" pin="7"/>
+<wire x1="127" y1="83.82" x2="129.54" y2="83.82" width="0.1524" layer="91"/>
+<label x="129.54" y="83.82" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="T_RESET" class="0">
+<segment>
+<pinref part="J1" gate="G$1" pin="10"/>
+<wire x1="55.88" y1="86.36" x2="58.42" y2="86.36" width="0.1524" layer="91"/>
+<label x="58.42" y="86.36" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="RN1" gate="G$1" pin="6"/>
+<wire x1="127" y1="93.98" x2="129.54" y2="93.98" width="0.1524" layer="91"/>
+<label x="129.54" y="93.98" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="I_TX" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA8"/>
+<wire x1="22.86" y1="58.42" x2="20.32" y2="58.42" width="0.1524" layer="91"/>
+<label x="20.32" y="58.42" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="RN1" gate="G$1" pin="2"/>
+<wire x1="116.84" y1="96.52" x2="114.3" y2="96.52" width="0.1524" layer="91"/>
+<label x="114.3" y="96.52" size="1.27" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="N$4" class="0">
+<segment>
+<pinref part="R1" gate="G$1" pin="2"/>
+<pinref part="LED1" gate="G$1" pin="A"/>
+<wire x1="124.46" y1="55.88" x2="127" y2="55.88" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="N$6" class="0">
+<segment>
+<pinref part="R2" gate="G$1" pin="2"/>
+<pinref part="LED2" gate="G$1" pin="A"/>
+<wire x1="127" y1="45.72" x2="124.46" y2="45.72" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="I_RESET" class="0">
+<segment>
+<pinref part="RN1" gate="G$1" pin="3"/>
+<wire x1="116.84" y1="93.98" x2="114.3" y2="93.98" width="0.1524" layer="91"/>
+<label x="114.3" y="93.98" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA04"/>
+<wire x1="58.42" y1="60.96" x2="63.5" y2="60.96" width="0.1524" layer="91"/>
+<label x="63.5" y="60.96" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="I_TDI" class="0">
+<segment>
+<pinref part="RN1" gate="G$1" pin="4"/>
+<wire x1="116.84" y1="91.44" x2="114.3" y2="91.44" width="0.1524" layer="91"/>
+<label x="114.3" y="91.44" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA9"/>
+<wire x1="22.86" y1="55.88" x2="20.32" y2="55.88" width="0.1524" layer="91"/>
+<label x="20.32" y="55.88" size="1.27" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="I_SWDIO_TMS" class="0">
+<segment>
+<pinref part="RN2" gate="G$1" pin="3"/>
+<wire x1="116.84" y1="81.28" x2="114.3" y2="81.28" width="0.1524" layer="91"/>
+<label x="114.3" y="81.28" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA15"/>
+<wire x1="22.86" y1="50.8" x2="20.32" y2="50.8" width="0.1524" layer="91"/>
+<label x="20.32" y="50.8" size="1.27" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="I_SWCLK_TCK" class="0">
+<segment>
+<pinref part="RN2" gate="G$1" pin="2"/>
+<wire x1="116.84" y1="83.82" x2="114.3" y2="83.82" width="0.1524" layer="91"/>
+<label x="114.3" y="83.82" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA02"/>
+<wire x1="58.42" y1="58.42" x2="63.5" y2="58.42" width="0.1524" layer="91"/>
+<label x="63.5" y="58.42" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="I_TDO" class="0">
+<segment>
+<pinref part="RN2" gate="G$1" pin="1"/>
+<wire x1="116.84" y1="86.36" x2="114.3" y2="86.36" width="0.1524" layer="91"/>
+<label x="114.3" y="86.36" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA14"/>
+<wire x1="20.32" y1="53.34" x2="22.86" y2="53.34" width="0.1524" layer="91"/>
+<label x="20.32" y="53.34" size="1.27" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="I_RX" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA5"/>
+<wire x1="22.86" y1="60.96" x2="20.32" y2="60.96" width="0.1524" layer="91"/>
+<label x="20.32" y="60.96" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="RN1" gate="G$1" pin="1"/>
+<wire x1="114.3" y1="99.06" x2="116.84" y2="99.06" width="0.1524" layer="91"/>
+<label x="114.3" y="99.06" size="1.27" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="N$18" class="0">
+<segment>
+<pinref part="RN2" gate="G$1" pin="5"/>
+<wire x1="127" y1="78.74" x2="129.54" y2="78.74" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="T_RX" class="0">
+<segment>
+<pinref part="RN1" gate="G$1" pin="8"/>
+<wire x1="127" y1="99.06" x2="129.54" y2="99.06" width="0.1524" layer="91"/>
+<label x="129.54" y="99.06" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="J2" gate="G$1" pin="1"/>
+<wire x1="86.36" y1="96.52" x2="81.28" y2="96.52" width="0.1524" layer="91"/>
+<label x="81.28" y="96.52" size="1.27" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="T_TX" class="0">
+<segment>
+<pinref part="RN1" gate="G$1" pin="7"/>
+<wire x1="127" y1="96.52" x2="129.54" y2="96.52" width="0.1524" layer="91"/>
+<label x="129.54" y="96.52" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="J3" gate="G$1" pin="1"/>
+<wire x1="86.36" y1="93.98" x2="81.28" y2="93.98" width="0.1524" layer="91"/>
+<label x="81.28" y="93.98" size="1.27" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="T_TDO" class="0">
+<segment>
+<pinref part="J1" gate="G$1" pin="6"/>
+<wire x1="55.88" y1="91.44" x2="58.42" y2="91.44" width="0.1524" layer="91"/>
+<label x="58.42" y="91.44" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="RN2" gate="G$1" pin="8"/>
+<wire x1="127" y1="86.36" x2="129.54" y2="86.36" width="0.1524" layer="91"/>
+<label x="129.54" y="86.36" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="T_TDI" class="0">
+<segment>
+<pinref part="J1" gate="G$1" pin="8"/>
+<wire x1="55.88" y1="88.9" x2="58.42" y2="88.9" width="0.1524" layer="91"/>
+<label x="58.42" y="88.9" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="RN1" gate="G$1" pin="5"/>
+<wire x1="127" y1="91.44" x2="129.54" y2="91.44" width="0.1524" layer="91"/>
+<label x="129.54" y="91.44" size="1.27" layer="95"/>
+</segment>
+</net>
+</nets>
+</sheet>
+</sheets>
+</schematic>
+</drawing>
+<compatibility>
+<note version="6.3" minversion="6.2.2" severity="warning">
+Since Version 6.2.2 text objects can contain more than one line,
+which will not be processed correctly with this version.
+</note>
+</compatibility>
+</eagle>

dap_link/lib/free-dap/hardware/d11_micro_usb_std/d11_micro_usb_std.brd

@@ -0,0 +1,626 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="7.3.0">
+<drawing>
+<settings>
+<setting alwaysvectorfont="no"/>
+<setting verticaltext="up"/>
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+<layer number="92" name="Busses" color="1" fill="1" visible="no" active="no"/>
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+<layer number="98" name="Guide" color="6" fill="1" visible="no" active="no"/>
+</layers>
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+<circle x="20.574" y="1.524" radius="0.254" width="0.508" layer="28"/>
+</plain>
+<libraries>
+<library name="ataradov_mcu">
+<description>Alex Taradov Library (MCUs)</description>
+<packages>
+<package name="SO-14">
+<description>SO-14</description>
+<wire x1="4.305" y1="-1.9" x2="-4.305" y2="-1.9" width="0.2032" layer="51"/>
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+<text x="-4.826" y="0" size="1.27" layer="25" font="vector" rot="R90" align="bottom-center">&gt;NAME</text>
+<text x="6.096" y="0" size="1.27" layer="27" font="vector" rot="R90" align="bottom-center">&gt;VALUE</text>
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+<rectangle x1="-1.5151" y1="-3.1001" x2="-1.0249" y2="-2" layer="51"/>
+<rectangle x1="-0.2451" y1="-3.1001" x2="0.2451" y2="-2" layer="51"/>
+<rectangle x1="-0.2451" y1="2" x2="0.2451" y2="3.1001" layer="51"/>
+<rectangle x1="-1.5151" y1="2" x2="-1.0249" y2="3.1001" layer="51"/>
+<rectangle x1="-2.7851" y1="2" x2="-2.2949" y2="3.1001" layer="51"/>
+<rectangle x1="-4.0551" y1="2" x2="-3.5649" y2="3.1001" layer="51"/>
+<rectangle x1="1.0249" y1="-3.1001" x2="1.5151" y2="-2" layer="51"/>
+<rectangle x1="2.2949" y1="-3.1001" x2="2.7851" y2="-2" layer="51"/>
+<rectangle x1="3.5649" y1="-3.1001" x2="4.0551" y2="-2" layer="51"/>
+<rectangle x1="3.5649" y1="2" x2="4.0551" y2="3.1001" layer="51"/>
+<rectangle x1="2.2949" y1="2" x2="2.7851" y2="3.1001" layer="51"/>
+<rectangle x1="1.0249" y1="2" x2="1.5151" y2="3.1001" layer="51"/>
+</package>
+</packages>
+</library>
+<library name="ataradov_conn">
+<description>Alex Taradov Library (Connectors)</description>
+<packages>
+<package name="HEADER-5X2-1.27MM">
+<wire x1="-3.81" y1="1.905" x2="3.81" y2="1.905" width="0.127" layer="21"/>
+<wire x1="3.81" y1="1.905" x2="3.81" y2="-1.905" width="0.127" layer="21"/>
+<wire x1="3.81" y1="-1.905" x2="-3.175" y2="-1.905" width="0.127" layer="21"/>
+<wire x1="-3.175" y1="-1.905" x2="-3.81" y2="-1.27" width="0.127" layer="21"/>
+<wire x1="-3.81" y1="-1.27" x2="-3.81" y2="1.905" width="0.127" layer="21"/>
+<pad name="1" x="-2.54" y="-0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="2" x="-2.54" y="0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="3" x="-1.27" y="-0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="4" x="-1.27" y="0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="5" x="0" y="-0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="6" x="0" y="0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="7" x="1.27" y="-0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="8" x="1.27" y="0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="9" x="2.54" y="-0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="10" x="2.54" y="0.635" drill="0.6604" diameter="1.0668"/>
+<text x="0" y="2.54" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="USB-B-MICRO-SMT-SHELL-TH">
+<pad name="M1" x="2.15" y="-3.6" drill="1.397"/>
+<pad name="M2" x="2.15" y="3.6" drill="1.397"/>
+<smd name="1" x="4.825" y="1.3" dx="1.35" dy="0.4" layer="1" stop="no"/>
+<smd name="2" x="4.825" y="0.65" dx="1.35" dy="0.4" layer="1" stop="no"/>
+<smd name="3" x="4.825" y="0" dx="1.35" dy="0.4" layer="1" stop="no"/>
+<smd name="4" x="4.825" y="-0.65" dx="1.35" dy="0.4" layer="1" stop="no"/>
+<smd name="5" x="4.825" y="-1.3" dx="1.35" dy="0.4" layer="1" stop="no"/>
+<text x="3.175" y="0" size="1.27" layer="25" font="vector" rot="R90" align="bottom-center">&gt;NAME</text>
+<rectangle x1="4.1" y1="1.05" x2="5.55" y2="1.55" layer="29"/>
+<pad name="M3" x="5.05" y="2.425" drill="0.7" shape="long"/>
+<pad name="M4" x="5.05" y="-2.425" drill="0.7" shape="long"/>
+<rectangle x1="4.1" y1="0.4" x2="5.55" y2="0.9" layer="29"/>
+<rectangle x1="4.1" y1="-0.25" x2="5.55" y2="0.25" layer="29"/>
+<rectangle x1="4.1" y1="-0.9" x2="5.55" y2="-0.4" layer="29"/>
+<rectangle x1="4.1" y1="-1.55" x2="5.55" y2="-1.05" layer="29"/>
+<wire x1="-0.5" y1="4" x2="-0.6" y2="3.8" width="0.1524" layer="21"/>
+<wire x1="-0.6" y1="3.8" x2="0" y2="3.5" width="0.1524" layer="21"/>
+<wire x1="0" y1="3.5" x2="0" y2="3.1" width="0.1524" layer="21"/>
+<wire x1="0" y1="3.1" x2="-0.6" y2="3.1" width="0.1524" layer="21"/>
+<wire x1="-0.6" y1="3.1" x2="-0.6" y2="-3.1" width="0.1524" layer="21"/>
+<wire x1="-0.6" y1="-3.1" x2="0" y2="-3.1" width="0.1524" layer="21"/>
+<wire x1="0" y1="-3.1" x2="0" y2="-3.5" width="0.1524" layer="21"/>
+<wire x1="0" y1="-3.5" x2="-0.6" y2="-3.8" width="0.1524" layer="21"/>
+<wire x1="-0.6" y1="-3.8" x2="-0.5" y2="-4" width="0.1524" layer="21"/>
+<wire x1="-0.5" y1="-4" x2="0" y2="-3.75" width="0.1524" layer="21"/>
+<wire x1="0" y1="-3.75" x2="5" y2="-3.75" width="0.1524" layer="21"/>
+<wire x1="5" y1="-3.75" x2="5" y2="-3.16" width="0.1524" layer="21"/>
+<wire x1="-0.5" y1="4" x2="0" y2="3.75" width="0.1524" layer="21"/>
+<wire x1="0" y1="3.75" x2="5" y2="3.75" width="0.1524" layer="21"/>
+<wire x1="5" y1="3.75" x2="5" y2="3.16" width="0.1524" layer="21"/>
+</package>
+</packages>
+</library>
+<library name="ataradov_rlc">
+<description>Alex Taradov Library (R, L and C)</description>
+<packages>
+<package name="SMD0603">
+<wire x1="-1.5" y1="0.75" x2="1.5" y2="0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="0.75" x2="1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="-0.75" x2="-1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="-1.5" y1="-0.75" x2="-1.5" y2="0.75" width="0.1" layer="21"/>
+<smd name="1" x="-0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<smd name="2" x="0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+</packages>
+</library>
+<library name="ataradov_vreg">
+<description>Alex Taradov Library (Voltage Regulators)</description>
+<packages>
+<package name="SOT23-5">
+<description>SOT23-5</description>
+<wire x1="1.422" y1="0.81" x2="1.422" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="1.422" y1="-0.81" x2="-1.422" y2="-0.81" width="0.1524" layer="51"/>
+<wire x1="-1.422" y1="-0.81" x2="-1.422" y2="0.81" width="0.1524" layer="21"/>
+<wire x1="-1.422" y1="0.81" x2="1.422" y2="0.81" width="0.1524" layer="51"/>
+<wire x1="-0.522" y1="0.81" x2="0.522" y2="0.81" width="0.1524" layer="21"/>
+<wire x1="-0.428" y1="-0.81" x2="-0.522" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="0.522" y1="-0.81" x2="0.428" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="-1.328" y1="-0.81" x2="-1.422" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="1.422" y1="-0.81" x2="1.328" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="1.328" y1="0.81" x2="1.422" y2="0.81" width="0.1524" layer="21"/>
+<wire x1="-1.422" y1="0.81" x2="-1.328" y2="0.81" width="0.1524" layer="21"/>
+<smd name="1" x="-0.95" y="-1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="2" x="0" y="-1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="3" x="0.95" y="-1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="4" x="0.95" y="1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="5" x="-0.95" y="1.3" dx="0.55" dy="1.2" layer="1"/>
+<text x="0" y="2.286" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-3.556" size="1.27" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+<rectangle x1="-1.2" y1="-1.5" x2="-0.7" y2="-0.85" layer="51"/>
+<rectangle x1="-0.25" y1="-1.5" x2="0.25" y2="-0.85" layer="51"/>
+<rectangle x1="0.7" y1="-1.5" x2="1.2" y2="-0.85" layer="51"/>
+<rectangle x1="0.7" y1="0.85" x2="1.2" y2="1.5" layer="51"/>
+<rectangle x1="-1.2" y1="0.85" x2="-0.7" y2="1.5" layer="51"/>
+</package>
+</packages>
+</library>
+<library name="ataradov_misc">
+<description>Alex Taradov Library (Miscellaneous stuff)</description>
+<packages>
+<package name="TP-1.27MM">
+<smd name="1" x="0" y="0" dx="1.27" dy="1.27" layer="1" roundness="100" cream="no"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+</packages>
+</library>
+<library name="ataradov_led">
+<description>Alex Taradov Library (LEDs and other indication devices)</description>
+<packages>
+<package name="SMD0603">
+<wire x1="-1.5" y1="0.75" x2="1.5" y2="0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="0.75" x2="1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="-0.75" x2="-1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="-1.5" y1="-0.75" x2="-1.5" y2="0.75" width="0.1" layer="21"/>
+<smd name="1" x="-0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<smd name="2" x="0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+</packages>
+</library>
+</libraries>
+<attributes>
+</attributes>
+<variantdefs>
+</variantdefs>
+<classes>
+<class number="0" name="default" width="0" drill="0">
+</class>
+</classes>
+<designrules name="OSHPark *">
+<description language="de">&lt;b&gt;EAGLE Design Rules&lt;/b&gt;
+&lt;p&gt;
+Die Standard-Design-Rules sind so gewählt, dass sie für 
+die meisten Anwendungen passen. Sollte ihre Platine 
+besondere Anforderungen haben, treffen Sie die erforderlichen
+Einstellungen hier und speichern die Design Rules unter 
+einem neuen Namen ab.</description>
+<description language="en">&lt;b&gt;Laen's PCB Order Design Rules&lt;/b&gt;
+&lt;p&gt;
+Please make sure your boards conform to these design rules.</description>
+<param name="layerSetup" value="(1*16)"/>
+<param name="mtCopper" value="0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm"/>
+<param name="mtIsolate" value="1.5011mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm"/>
+<param name="mdWireWire" value="6mil"/>
+<param name="mdWirePad" value="6mil"/>
+<param name="mdWireVia" value="6mil"/>
+<param name="mdPadPad" value="6mil"/>
+<param name="mdPadVia" value="6mil"/>
+<param name="mdViaVia" value="6mil"/>
+<param name="mdSmdPad" value="6mil"/>
+<param name="mdSmdVia" value="6mil"/>
+<param name="mdSmdSmd" value="6mil"/>
+<param name="mdViaViaSameLayer" value="8mil"/>
+<param name="mnLayersViaInSmd" value="2"/>
+<param name="mdCopperDimension" value="15mil"/>
+<param name="mdDrill" value="6mil"/>
+<param name="mdSmdStop" value="0mil"/>
+<param name="msWidth" value="6mil"/>
+<param name="msDrill" value="13mil"/>
+<param name="msMicroVia" value="13mil"/>
+<param name="msBlindViaRatio" value="0.5"/>
+<param name="rvPadTop" value="0.25"/>
+<param name="rvPadInner" value="0.25"/>
+<param name="rvPadBottom" value="0.25"/>
+<param name="rvViaOuter" value="0.25"/>
+<param name="rvViaInner" value="0.25"/>
+<param name="rvMicroViaOuter" value="0.25"/>
+<param name="rvMicroViaInner" value="0.25"/>
+<param name="rlMinPadTop" value="7mil"/>
+<param name="rlMaxPadTop" value="20mil"/>
+<param name="rlMinPadInner" value="7mil"/>
+<param name="rlMaxPadInner" value="20mil"/>
+<param name="rlMinPadBottom" value="7mil"/>
+<param name="rlMaxPadBottom" value="20mil"/>
+<param name="rlMinViaOuter" value="7mil"/>
+<param name="rlMaxViaOuter" value="20mil"/>
+<param name="rlMinViaInner" value="7mil"/>
+<param name="rlMaxViaInner" value="20mil"/>
+<param name="rlMinMicroViaOuter" value="4mil"/>
+<param name="rlMaxMicroViaOuter" value="20mil"/>
+<param name="rlMinMicroViaInner" value="4mil"/>
+<param name="rlMaxMicroViaInner" value="20mil"/>
+<param name="psTop" value="-1"/>
+<param name="psBottom" value="-1"/>
+<param name="psFirst" value="-1"/>
+<param name="psElongationLong" value="100"/>
+<param name="psElongationOffset" value="100"/>
+<param name="mvStopFrame" value="1"/>
+<param name="mvCreamFrame" value="0"/>
+<param name="mlMinStopFrame" value="3mil"/>
+<param name="mlMaxStopFrame" value="3mil"/>
+<param name="mlMinCreamFrame" value="0mil"/>
+<param name="mlMaxCreamFrame" value="0mil"/>
+<param name="mlViaStopLimit" value="100mil"/>
+<param name="srRoundness" value="0"/>
+<param name="srMinRoundness" value="0mil"/>
+<param name="srMaxRoundness" value="0mil"/>
+<param name="slThermalIsolate" value="10mil"/>
+<param name="slThermalsForVias" value="0"/>
+<param name="dpMaxLengthDifference" value="10mm"/>
+<param name="dpGapFactor" value="2.5"/>
+<param name="checkGrid" value="0"/>
+<param name="checkAngle" value="0"/>
+<param name="checkFont" value="1"/>
+<param name="checkRestrict" value="1"/>
+<param name="useDiameter" value="13"/>
+<param name="maxErrors" value="50"/>
+</designrules>
+<autorouter>
+<pass name="Default">
+<param name="RoutingGrid" value="50mil"/>
+<param name="AutoGrid" value="1"/>
+<param name="Efforts" value="0"/>
+<param name="TopRouterVariant" value="1"/>
+<param name="tpViaShape" value="round"/>
+<param name="PrefDir.1" value="a"/>
+<param name="PrefDir.2" value="0"/>
+<param name="PrefDir.3" value="0"/>
+<param name="PrefDir.4" value="0"/>
+<param name="PrefDir.5" value="0"/>
+<param name="PrefDir.6" value="0"/>
+<param name="PrefDir.7" value="0"/>
+<param name="PrefDir.8" value="0"/>
+<param name="PrefDir.9" value="0"/>
+<param name="PrefDir.10" value="0"/>
+<param name="PrefDir.11" value="0"/>
+<param name="PrefDir.12" value="0"/>
+<param name="PrefDir.13" value="0"/>
+<param name="PrefDir.14" value="0"/>
+<param name="PrefDir.15" value="0"/>
+<param name="PrefDir.16" value="a"/>
+<param name="cfVia" value="8"/>
+<param name="cfNonPref" value="5"/>
+<param name="cfChangeDir" value="2"/>
+<param name="cfOrthStep" value="2"/>
+<param name="cfDiagStep" value="3"/>
+<param name="cfExtdStep" value="0"/>
+<param name="cfBonusStep" value="1"/>
+<param name="cfMalusStep" value="1"/>
+<param name="cfPadImpact" value="4"/>
+<param name="cfSmdImpact" value="4"/>
+<param name="cfBusImpact" value="0"/>
+<param name="cfHugging" value="3"/>
+<param name="cfAvoid" value="4"/>
+<param name="cfPolygon" value="10"/>
+<param name="cfBase.1" value="0"/>
+<param name="cfBase.2" value="1"/>
+<param name="cfBase.3" value="1"/>
+<param name="cfBase.4" value="1"/>
+<param name="cfBase.5" value="1"/>
+<param name="cfBase.6" value="1"/>
+<param name="cfBase.7" value="1"/>
+<param name="cfBase.8" value="1"/>
+<param name="cfBase.9" value="1"/>
+<param name="cfBase.10" value="1"/>
+<param name="cfBase.11" value="1"/>
+<param name="cfBase.12" value="1"/>
+<param name="cfBase.13" value="1"/>
+<param name="cfBase.14" value="1"/>
+<param name="cfBase.15" value="1"/>
+<param name="cfBase.16" value="0"/>
+<param name="mnVias" value="20"/>
+<param name="mnSegments" value="9999"/>
+<param name="mnExtdSteps" value="9999"/>
+<param name="mnRipupLevel" value="10"/>
+<param name="mnRipupSteps" value="100"/>
+<param name="mnRipupTotal" value="100"/>
+</pass>
+<pass name="Follow-me" refer="Default" active="yes">
+</pass>
+<pass name="Busses" refer="Default" active="yes">
+<param name="cfNonPref" value="4"/>
+<param name="cfBusImpact" value="4"/>
+<param name="cfHugging" value="0"/>
+<param name="mnVias" value="0"/>
+</pass>
+<pass name="Route" refer="Default" active="yes">
+</pass>
+<pass name="Optimize1" refer="Default" active="yes">
+<param name="cfVia" value="99"/>
+<param name="cfExtdStep" value="10"/>
+<param name="cfHugging" value="1"/>
+<param name="mnExtdSteps" value="1"/>
+<param name="mnRipupLevel" value="0"/>
+</pass>
+<pass name="Optimize2" refer="Optimize1" active="yes">
+<param name="cfNonPref" value="0"/>
+<param name="cfChangeDir" value="6"/>
+<param name="cfExtdStep" value="0"/>
+<param name="cfBonusStep" value="2"/>
+<param name="cfMalusStep" value="2"/>
+<param name="cfPadImpact" value="2"/>
+<param name="cfSmdImpact" value="2"/>
+<param name="cfHugging" value="0"/>
+</pass>
+<pass name="Optimize3" refer="Optimize2" active="yes">
+<param name="cfChangeDir" value="8"/>
+<param name="cfPadImpact" value="0"/>
+<param name="cfSmdImpact" value="0"/>
+</pass>
+<pass name="Optimize4" refer="Optimize3" active="yes">
+<param name="cfChangeDir" value="25"/>
+</pass>
+</autorouter>
+<elements>
+<element name="IC2" library="ataradov_mcu" package="SO-14" value="ATSAMD11C" x="10.414" y="6.35" smashed="yes" rot="MR270">
+<attribute name="NAME" x="10.414" y="11.176" size="1.27" layer="26" font="vector" rot="MR0" align="bottom-center"/>
+</element>
+<element name="C1" library="ataradov_rlc" package="SMD0603" value="1uF" x="9.398" y="2.032"/>
+<element name="C2" library="ataradov_rlc" package="SMD0603" value="1uF" x="9.398" y="9.144" smashed="yes" rot="R180">
+<attribute name="NAME" x="9.398" y="8.128" size="1.27" layer="25" font="vector" rot="R180" align="bottom-center"/>
+</element>
+<element name="R2" library="ataradov_rlc" package="SMD0603" value="100" x="16.256" y="3.81" rot="MR0"/>
+<element name="R3" library="ataradov_rlc" package="SMD0603" value="100" x="16.256" y="5.334" rot="MR0"/>
+<element name="R4" library="ataradov_rlc" package="SMD0603" value="100" x="16.256" y="6.858" rot="MR0"/>
+<element name="IC1" library="ataradov_vreg" package="SOT23-5" value="MIC5504-3.3" x="9.398" y="5.588" smashed="yes">
+<attribute name="NAME" x="9.398" y="7.874" size="1.27" layer="25" font="vector" align="bottom-center"/>
+</element>
+<element name="R7" library="ataradov_rlc" package="SMD0603" value="470" x="12.7" y="9.144" rot="R270"/>
+<element name="TP1" library="ataradov_misc" package="TP-1.27MM" value="SIO" x="7.874" y="1.524" rot="MR0"/>
+<element name="TP2" library="ataradov_misc" package="TP-1.27MM" value="" x="12.954" y="1.524" rot="MR0"/>
+<element name="TP3" library="ataradov_misc" package="TP-1.27MM" value="" x="10.414" y="1.524" rot="MR0"/>
+<element name="TP4" library="ataradov_misc" package="TP-1.27MM" value="" x="5.334" y="1.524" rot="MR0"/>
+<element name="LED1" library="ataradov_led" package="SMD0603" value="" x="12.7" y="5.588" rot="R270"/>
+<element name="J1" library="ataradov_conn" package="HEADER-5X2-1.27MM" value="HEADER-5X2-TH-1.27" x="19.812" y="5.588" rot="R90"/>
+<element name="R1" library="ataradov_rlc" package="SMD0603" value="100" x="16.256" y="8.382" rot="MR0"/>
+<element name="R8" library="ataradov_rlc" package="SMD0603" value="100" x="16.256" y="9.906" rot="MR0"/>
+<element name="J2" library="ataradov_conn" package="USB-B-MICRO-SMT-SHELL-TH" value="" x="0" y="5.588"/>
+</elements>
+<signals>
+<signal name="GND">
+<contactref element="IC1" pad="2"/>
+<contactref element="C1" pad="1"/>
+<contactref element="C2" pad="1"/>
+<contactref element="IC2" pad="11"/>
+<contactref element="TP4" pad="1"/>
+<contactref element="J1" pad="3"/>
+<contactref element="J1" pad="5"/>
+<contactref element="LED1" pad="2"/>
+<contactref element="J2" pad="5"/>
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+<via x="1.27" y="7.366" extent="1-16" drill="0.508" diameter="0.254"/>
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+<via x="11.176" y="8.128" extent="1-16" drill="0.508" diameter="0.254"/>
+</signal>
+<signal name="N$1">
+<contactref element="IC2" pad="9"/>
+<contactref element="J2" pad="2"/>
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+</signal>
+<signal name="N$2">
+<contactref element="IC2" pad="10"/>
+<contactref element="J2" pad="3"/>
+<via x="3.302" y="5.334" extent="1-16" drill="0.508" diameter="0.254"/>
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+<wire x1="3.556" y1="5.588" x2="3.302" y2="5.334" width="0.254" layer="1"/>
+</signal>
+<signal name="V_USB">
+<contactref element="IC1" pad="3"/>
+<contactref element="IC1" pad="1"/>
+<contactref element="C1" pad="2"/>
+<contactref element="J2" pad="1"/>
+<wire x1="10.348" y1="4.288" x2="10.348" y2="2.436" width="0.254" layer="1"/>
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+<wire x1="8.448" y1="5.268" x2="8.382" y2="5.334" width="0.254" layer="1"/>
+</signal>
+<signal name="+3V3">
+<contactref element="IC1" pad="5"/>
+<contactref element="C2" pad="2"/>
+<contactref element="IC2" pad="12"/>
+<via x="9.398" y="7.874" extent="1-16" drill="0.508" diameter="0.254"/>
+<wire x1="7.814" y1="7.62" x2="9.144" y2="7.62" width="0.254" layer="16"/>
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+<wire x1="9.398" y1="7.874" x2="8.448" y2="7.874" width="0.254" layer="1"/>
+</signal>
+<signal name="SWDIO">
+<contactref element="IC2" pad="8"/>
+<contactref element="TP1" pad="1"/>
+<wire x1="7.814" y1="2.54" x2="7.874" y2="2.48" width="0.254" layer="16"/>
+<wire x1="7.874" y1="2.48" x2="7.874" y2="1.524" width="0.254" layer="16"/>
+</signal>
+<signal name="PA02">
+<contactref element="IC2" pad="13"/>
+</signal>
+<signal name="PA04">
+<contactref element="IC2" pad="14"/>
+<contactref element="R7" pad="1"/>
+<wire x1="7.814" y1="10.16" x2="11.176" y2="10.16" width="0.254" layer="16"/>
+<via x="11.176" y="10.16" extent="1-16" drill="0.508" diameter="0.254"/>
+<wire x1="11.176" y1="10.16" x2="12.23" y2="10.16" width="0.254" layer="1"/>
+<wire x1="12.23" y1="10.16" x2="12.7" y2="9.944" width="0.254" layer="1"/>
+</signal>
+<signal name="SWCLK">
+<contactref element="IC2" pad="7"/>
+<contactref element="TP2" pad="1"/>
+<wire x1="13.014" y1="2.54" x2="12.954" y2="2.48" width="0.254" layer="16"/>
+<wire x1="12.954" y1="2.48" x2="12.954" y2="1.524" width="0.254" layer="16"/>
+</signal>
+<signal name="RESET">
+<contactref element="IC2" pad="6"/>
+<contactref element="TP3" pad="1"/>
+<wire x1="13.014" y1="3.81" x2="11.684" y2="3.81" width="0.254" layer="16"/>
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+<wire x1="10.414" y1="2.54" x2="10.414" y2="1.524" width="0.254" layer="16"/>
+</signal>
+<signal name="N$8">
+</signal>
+<signal name="N$5">
+<contactref element="J1" pad="2"/>
+<contactref element="R2" pad="1"/>
+<wire x1="17.056" y1="3.81" x2="17.818" y2="3.048" width="0.254" layer="16"/>
+<wire x1="17.818" y1="3.048" x2="19.177" y2="3.048" width="0.254" layer="16"/>
+</signal>
+<signal name="N$9">
+<contactref element="R3" pad="1"/>
+<contactref element="J1" pad="4"/>
+<wire x1="17.056" y1="5.334" x2="18.072" y2="4.318" width="0.254" layer="16"/>
+<wire x1="18.072" y1="4.318" x2="19.177" y2="4.318" width="0.254" layer="16"/>
+</signal>
+<signal name="N$10">
+<contactref element="J1" pad="6"/>
+<contactref element="R4" pad="1"/>
+<wire x1="17.056" y1="6.858" x2="18.326" y2="5.588" width="0.254" layer="16"/>
+<wire x1="18.326" y1="5.588" x2="19.177" y2="5.588" width="0.254" layer="16"/>
+</signal>
+<signal name="N$11">
+<contactref element="R1" pad="1"/>
+<contactref element="J1" pad="8"/>
+<wire x1="17.056" y1="8.382" x2="18.58" y2="6.858" width="0.254" layer="16"/>
+<wire x1="18.58" y1="6.858" x2="19.177" y2="6.858" width="0.254" layer="16"/>
+</signal>
+<signal name="N$12">
+<contactref element="J1" pad="10"/>
+<contactref element="R8" pad="1"/>
+<wire x1="17.056" y1="9.906" x2="18.542" y2="9.906" width="0.254" layer="16"/>
+<wire x1="18.542" y1="9.906" x2="19.177" y2="9.271" width="0.254" layer="16"/>
+<wire x1="19.177" y1="9.271" x2="19.177" y2="8.128" width="0.254" layer="16"/>
+</signal>
+<signal name="PA14">
+<contactref element="IC2" pad="4"/>
+<contactref element="R3" pad="2"/>
+<wire x1="13.014" y1="6.35" x2="14.44" y2="6.35" width="0.254" layer="16"/>
+<wire x1="14.44" y1="6.35" x2="15.456" y2="5.334" width="0.254" layer="16"/>
+</signal>
+<signal name="PA15">
+<contactref element="IC2" pad="5"/>
+<contactref element="R2" pad="2"/>
+<wire x1="13.014" y1="5.08" x2="14.186" y2="5.08" width="0.254" layer="16"/>
+<wire x1="14.186" y1="5.08" x2="15.456" y2="3.81" width="0.254" layer="16"/>
+</signal>
+<signal name="N$3">
+<contactref element="R7" pad="2"/>
+<contactref element="LED1" pad="1"/>
+<wire x1="12.7" y1="6.388" x2="12.7" y2="8.344" width="0.254" layer="1"/>
+</signal>
+<signal name="PA09">
+<contactref element="IC2" pad="3"/>
+<contactref element="R4" pad="2"/>
+<wire x1="13.014" y1="7.62" x2="14.694" y2="7.62" width="0.254" layer="16"/>
+<wire x1="14.694" y1="7.62" x2="15.456" y2="6.858" width="0.254" layer="16"/>
+</signal>
+<signal name="PA08">
+<contactref element="IC2" pad="2"/>
+<contactref element="R1" pad="2"/>
+<wire x1="13.014" y1="8.89" x2="14.948" y2="8.89" width="0.254" layer="16"/>
+<wire x1="14.948" y1="8.89" x2="15.456" y2="8.382" width="0.254" layer="16"/>
+</signal>
+<signal name="PA05">
+<contactref element="IC2" pad="1"/>
+<contactref element="R8" pad="2"/>
+<wire x1="13.014" y1="10.16" x2="15.202" y2="10.16" width="0.254" layer="16"/>
+<wire x1="15.202" y1="10.16" x2="15.456" y2="9.906" width="0.254" layer="16"/>
+</signal>
+</signals>
+</board>
+</drawing>
+</eagle>

dap_link/lib/free-dap/hardware/d11_micro_usb_std/d11_micro_usb_std.sch

@@ -0,0 +1,1172 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="7.3.0">
+<drawing>
+<settings>
+<setting alwaysvectorfont="no"/>
+<setting verticaltext="up"/>
+</settings>
+<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>
+<layers>
+<layer number="1" name="Top" color="4" fill="1" visible="no" active="no"/>
+<layer number="16" name="Bottom" color="1" fill="1" visible="no" active="no"/>
+<layer number="17" name="Pads" color="2" fill="1" visible="no" active="no"/>
+<layer number="18" name="Vias" color="2" fill="1" visible="no" active="no"/>
+<layer number="19" name="Unrouted" color="6" fill="1" visible="no" active="no"/>
+<layer number="20" name="Dimension" color="15" fill="1" visible="no" active="no"/>
+<layer number="21" name="tPlace" color="7" fill="1" visible="no" active="no"/>
+<layer number="22" name="bPlace" color="7" fill="1" visible="no" active="no"/>
+<layer number="23" name="tOrigins" color="15" fill="1" visible="no" active="no"/>
+<layer number="24" name="bOrigins" color="15" fill="1" visible="no" active="no"/>
+<layer number="25" name="tNames" color="7" fill="1" visible="no" active="no"/>
+<layer number="26" name="bNames" color="7" fill="1" visible="no" active="no"/>
+<layer number="27" name="tValues" color="7" fill="1" visible="no" active="no"/>
+<layer number="28" name="bValues" color="7" fill="1" visible="no" active="no"/>
+<layer number="29" name="tStop" color="7" fill="3" visible="no" active="no"/>
+<layer number="30" name="bStop" color="7" fill="6" visible="no" active="no"/>
+<layer number="31" name="tCream" color="7" fill="4" visible="no" active="no"/>
+<layer number="32" name="bCream" color="7" fill="5" visible="no" active="no"/>
+<layer number="33" name="tFinish" color="6" fill="3" visible="no" active="no"/>
+<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="no"/>
+<layer number="35" name="tGlue" color="7" fill="4" visible="no" active="no"/>
+<layer number="36" name="bGlue" color="7" fill="5" visible="no" active="no"/>
+<layer number="37" name="tTest" color="7" fill="1" visible="no" active="no"/>
+<layer number="38" name="bTest" color="7" fill="1" visible="no" active="no"/>
+<layer number="39" name="tKeepout" color="4" fill="11" visible="no" active="no"/>
+<layer number="40" name="bKeepout" color="1" fill="11" visible="no" active="no"/>
+<layer number="41" name="tRestrict" color="4" fill="10" visible="no" active="no"/>
+<layer number="42" name="bRestrict" color="1" fill="10" visible="no" active="no"/>
+<layer number="43" name="vRestrict" color="2" fill="10" visible="no" active="no"/>
+<layer number="44" name="Drills" color="7" fill="1" visible="no" active="no"/>
+<layer number="45" name="Holes" color="7" fill="1" visible="no" active="no"/>
+<layer number="46" name="Milling" color="3" fill="1" visible="no" active="no"/>
+<layer number="47" name="Measures" color="7" fill="1" visible="no" active="no"/>
+<layer number="48" name="Document" color="7" fill="1" visible="no" active="no"/>
+<layer number="49" name="Reference" color="7" fill="1" visible="no" active="no"/>
+<layer number="51" name="tDocu" color="6" fill="1" visible="no" active="no"/>
+<layer number="52" name="bDocu" color="7" fill="1" visible="no" active="no"/>
+<layer number="90" name="Modules" color="5" fill="1" visible="yes" active="yes"/>
+<layer number="91" name="Nets" color="2" fill="1" visible="yes" active="yes"/>
+<layer number="92" name="Busses" color="1" fill="1" visible="yes" active="yes"/>
+<layer number="93" name="Pins" color="2" fill="1" visible="no" active="yes"/>
+<layer number="94" name="Symbols" color="4" fill="1" visible="yes" active="yes"/>
+<layer number="95" name="Names" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="96" name="Values" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="97" name="Info" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/>
+</layers>
+<schematic xreflabel="%F%N/%S.%C%R" xrefpart="/%S.%C%R">
+<libraries>
+<library name="ataradov_mcu">
+<description>Alex Taradov Library (MCUs)</description>
+<packages>
+<package name="SO-14">
+<description>SO-14</description>
+<wire x1="4.305" y1="-1.9" x2="-4.305" y2="-1.9" width="0.2032" layer="51"/>
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+<wire x1="4.305" y1="-1.4" x2="-4.305" y2="-1.4" width="0.2032" layer="51"/>
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+<smd name="8" x="3.81" y="2.6" dx="0.6" dy="2.2" layer="1"/>
+<text x="-4.826" y="0" size="1.27" layer="25" font="vector" rot="R90" align="bottom-center">&gt;NAME</text>
+<text x="6.096" y="0" size="1.27" layer="27" font="vector" rot="R90" align="bottom-center">&gt;VALUE</text>
+<rectangle x1="-4.0551" y1="-3.1001" x2="-3.5649" y2="-2" layer="51"/>
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+<rectangle x1="1.0249" y1="2" x2="1.5151" y2="3.1001" layer="51"/>
+</package>
+</packages>
+<symbols>
+<symbol name="ATSAMDXXC">
+<description>Atmel SAM D09C/D10C/D11C Cortex-M0+ microcontroller</description>
+<wire x1="-12.7" y1="10.16" x2="12.7" y2="10.16" width="0.254" layer="94"/>
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+<wire x1="-12.7" y1="-10.16" x2="-12.7" y2="10.16" width="0.254" layer="94"/>
+<pin name="PA28/RST" x="-17.78" y="-5.08" length="middle"/>
+<pin name="PA8" x="-17.78" y="5.08" length="middle"/>
+<pin name="PA9" x="-17.78" y="2.54" length="middle"/>
+<pin name="PA14" x="-17.78" y="0" length="middle"/>
+<pin name="PA15" x="-17.78" y="-2.54" length="middle"/>
+<pin name="PA5" x="-17.78" y="7.62" length="middle"/>
+<pin name="PA04" x="17.78" y="7.62" length="middle" rot="R180"/>
+<pin name="PA02" x="17.78" y="5.08" length="middle" rot="R180"/>
+<text x="0" y="10.922" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-12.192" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+<pin name="PA30/SCK" x="-17.78" y="-7.62" length="middle"/>
+<pin name="VDD" x="17.78" y="2.54" length="middle" rot="R180"/>
+<pin name="GND" x="17.78" y="0" length="middle" rot="R180"/>
+<pin name="PA25" x="17.78" y="-2.54" length="middle" rot="R180"/>
+<pin name="PA24" x="17.78" y="-5.08" length="middle" rot="R180"/>
+<pin name="PA31/SIO" x="17.78" y="-7.62" length="middle" rot="R180"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="ATSAMD11C" prefix="IC">
+<gates>
+<gate name="G$1" symbol="ATSAMDXXC" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="SO-14">
+<connects>
+<connect gate="G$1" pin="GND" pad="11"/>
+<connect gate="G$1" pin="PA02" pad="13"/>
+<connect gate="G$1" pin="PA04" pad="14"/>
+<connect gate="G$1" pin="PA14" pad="4"/>
+<connect gate="G$1" pin="PA15" pad="5"/>
+<connect gate="G$1" pin="PA24" pad="9"/>
+<connect gate="G$1" pin="PA25" pad="10"/>
+<connect gate="G$1" pin="PA28/RST" pad="6"/>
+<connect gate="G$1" pin="PA30/SCK" pad="7"/>
+<connect gate="G$1" pin="PA31/SIO" pad="8"/>
+<connect gate="G$1" pin="PA5" pad="1"/>
+<connect gate="G$1" pin="PA8" pad="2"/>
+<connect gate="G$1" pin="PA9" pad="3"/>
+<connect gate="G$1" pin="VDD" pad="12"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_pwr">
+<description>Alex Taradov Library (Power Symbols)</description>
+<packages>
+</packages>
+<symbols>
+<symbol name="+3V3">
+<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/>
+<text x="0" y="0.762" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+<pin name="+3V3" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/>
+</symbol>
+<symbol name="GND">
+<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/>
+<text x="0" y="-2.032" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+<pin name="GND" x="0" y="2.54" visible="off" length="short" direction="sup" rot="R270"/>
+</symbol>
+<symbol name="V_USB">
+<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/>
+<text x="0" y="0.762" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+<pin name="V_USB" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="+3V3" prefix="P_">
+<gates>
+<gate name="1" symbol="+3V3" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="GND" prefix="P_">
+<gates>
+<gate name="1" symbol="GND" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="V_USB" prefix="P_">
+<gates>
+<gate name="1" symbol="V_USB" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_conn">
+<description>Alex Taradov Library (Connectors)</description>
+<packages>
+<package name="HEADER-5X2-1.27MM">
+<wire x1="-3.81" y1="1.905" x2="3.81" y2="1.905" width="0.127" layer="21"/>
+<wire x1="3.81" y1="1.905" x2="3.81" y2="-1.905" width="0.127" layer="21"/>
+<wire x1="3.81" y1="-1.905" x2="-3.175" y2="-1.905" width="0.127" layer="21"/>
+<wire x1="-3.175" y1="-1.905" x2="-3.81" y2="-1.27" width="0.127" layer="21"/>
+<wire x1="-3.81" y1="-1.27" x2="-3.81" y2="1.905" width="0.127" layer="21"/>
+<pad name="1" x="-2.54" y="-0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="2" x="-2.54" y="0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="3" x="-1.27" y="-0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="4" x="-1.27" y="0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="5" x="0" y="-0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="6" x="0" y="0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="7" x="1.27" y="-0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="8" x="1.27" y="0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="9" x="2.54" y="-0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="10" x="2.54" y="0.635" drill="0.6604" diameter="1.0668"/>
+<text x="0" y="2.54" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="HEADER-5X2-2.54MM">
+<wire x1="-6.35" y1="0" x2="-3.81" y2="0" width="0.127" layer="21"/>
+<wire x1="-3.81" y1="0" x2="-3.81" y2="-2.54" width="0.127" layer="21"/>
+<wire x1="-6.35" y1="2.54" x2="6.35" y2="2.54" width="0.127" layer="21"/>
+<wire x1="6.35" y1="2.54" x2="6.35" y2="-2.54" width="0.127" layer="21"/>
+<wire x1="6.35" y1="-2.54" x2="-6.35" y2="-2.54" width="0.127" layer="21"/>
+<wire x1="-6.35" y1="-2.54" x2="-6.35" y2="2.54" width="0.127" layer="21"/>
+<pad name="1" x="-5.08" y="-1.27" drill="1.016" shape="square"/>
+<pad name="2" x="-5.08" y="1.27" drill="1.016"/>
+<pad name="3" x="-2.54" y="-1.27" drill="1.016"/>
+<pad name="4" x="-2.54" y="1.27" drill="1.016"/>
+<pad name="5" x="0" y="-1.27" drill="1.016"/>
+<pad name="6" x="0" y="1.27" drill="1.016"/>
+<pad name="7" x="2.54" y="-1.27" drill="1.016"/>
+<pad name="8" x="2.54" y="1.27" drill="1.016"/>
+<pad name="9" x="5.08" y="-1.27" drill="1.016"/>
+<pad name="10" x="5.08" y="1.27" drill="1.016"/>
+<text x="0" y="3.175" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="USB-B-MICRO-SMT-SHELL-TH">
+<pad name="M1" x="2.15" y="-3.6" drill="1.397"/>
+<pad name="M2" x="2.15" y="3.6" drill="1.397"/>
+<smd name="1" x="4.825" y="1.3" dx="1.35" dy="0.4" layer="1" stop="no"/>
+<smd name="2" x="4.825" y="0.65" dx="1.35" dy="0.4" layer="1" stop="no"/>
+<smd name="3" x="4.825" y="0" dx="1.35" dy="0.4" layer="1" stop="no"/>
+<smd name="4" x="4.825" y="-0.65" dx="1.35" dy="0.4" layer="1" stop="no"/>
+<smd name="5" x="4.825" y="-1.3" dx="1.35" dy="0.4" layer="1" stop="no"/>
+<text x="3.175" y="0" size="1.27" layer="25" font="vector" rot="R90" align="bottom-center">&gt;NAME</text>
+<rectangle x1="4.1" y1="1.05" x2="5.55" y2="1.55" layer="29"/>
+<pad name="M3" x="5.05" y="2.425" drill="0.7" shape="long"/>
+<pad name="M4" x="5.05" y="-2.425" drill="0.7" shape="long"/>
+<rectangle x1="4.1" y1="0.4" x2="5.55" y2="0.9" layer="29"/>
+<rectangle x1="4.1" y1="-0.25" x2="5.55" y2="0.25" layer="29"/>
+<rectangle x1="4.1" y1="-0.9" x2="5.55" y2="-0.4" layer="29"/>
+<rectangle x1="4.1" y1="-1.55" x2="5.55" y2="-1.05" layer="29"/>
+<wire x1="-0.5" y1="4" x2="-0.6" y2="3.8" width="0.1524" layer="21"/>
+<wire x1="-0.6" y1="3.8" x2="0" y2="3.5" width="0.1524" layer="21"/>
+<wire x1="0" y1="3.5" x2="0" y2="3.1" width="0.1524" layer="21"/>
+<wire x1="0" y1="3.1" x2="-0.6" y2="3.1" width="0.1524" layer="21"/>
+<wire x1="-0.6" y1="3.1" x2="-0.6" y2="-3.1" width="0.1524" layer="21"/>
+<wire x1="-0.6" y1="-3.1" x2="0" y2="-3.1" width="0.1524" layer="21"/>
+<wire x1="0" y1="-3.1" x2="0" y2="-3.5" width="0.1524" layer="21"/>
+<wire x1="0" y1="-3.5" x2="-0.6" y2="-3.8" width="0.1524" layer="21"/>
+<wire x1="-0.6" y1="-3.8" x2="-0.5" y2="-4" width="0.1524" layer="21"/>
+<wire x1="-0.5" y1="-4" x2="0" y2="-3.75" width="0.1524" layer="21"/>
+<wire x1="0" y1="-3.75" x2="5" y2="-3.75" width="0.1524" layer="21"/>
+<wire x1="5" y1="-3.75" x2="5" y2="-3.16" width="0.1524" layer="21"/>
+<wire x1="-0.5" y1="4" x2="0" y2="3.75" width="0.1524" layer="21"/>
+<wire x1="0" y1="3.75" x2="5" y2="3.75" width="0.1524" layer="21"/>
+<wire x1="5" y1="3.75" x2="5" y2="3.16" width="0.1524" layer="21"/>
+</package>
+</packages>
+<symbols>
+<symbol name="HEADER-5X2">
+<wire x1="-5.08" y1="7.62" x2="-5.08" y2="-7.62" width="0.254" layer="94"/>
+<wire x1="-5.08" y1="-7.62" x2="5.08" y2="-7.62" width="0.254" layer="94"/>
+<wire x1="5.08" y1="-7.62" x2="5.08" y2="7.62" width="0.254" layer="94"/>
+<wire x1="5.08" y1="7.62" x2="-5.08" y2="7.62" width="0.254" layer="94"/>
+<pin name="1" x="-7.62" y="5.08" length="short" direction="pas"/>
+<pin name="2" x="7.62" y="5.08" length="short" direction="pas" rot="R180"/>
+<pin name="3" x="-7.62" y="2.54" length="short" direction="pas"/>
+<pin name="4" x="7.62" y="2.54" length="short" direction="pas" rot="R180"/>
+<pin name="5" x="-7.62" y="0" length="short" direction="pas"/>
+<pin name="6" x="7.62" y="0" length="short" direction="pas" rot="R180"/>
+<pin name="7" x="-7.62" y="-2.54" length="short" direction="pas"/>
+<pin name="8" x="7.62" y="-2.54" length="short" direction="pas" rot="R180"/>
+<pin name="9" x="-7.62" y="-5.08" length="short" direction="pas"/>
+<pin name="10" x="7.62" y="-5.08" length="short" direction="pas" rot="R180"/>
+<text x="0" y="8.382" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+</symbol>
+<symbol name="MICRO-USB-5">
+<wire x1="-5.08" y1="7.62" x2="-5.08" y2="-10.16" width="0.254" layer="94"/>
+<text x="0.762" y="8.382" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<pin name="VBUS" x="-7.62" y="5.08" visible="pin" length="short" direction="pas"/>
+<pin name="DM" x="-7.62" y="2.54" visible="pin" length="short" direction="pas"/>
+<pin name="DP" x="-7.62" y="0" visible="pin" length="short" direction="pas"/>
+<pin name="ID" x="-7.62" y="-2.54" visible="pin" length="short" direction="pas"/>
+<pin name="GND" x="-7.62" y="-5.08" visible="pin" length="short" direction="pas"/>
+<wire x1="7.62" y1="7.62" x2="7.62" y2="-10.16" width="0.254" layer="94"/>
+<wire x1="-5.08" y1="7.62" x2="7.62" y2="7.62" width="0.254" layer="94"/>
+<wire x1="-5.08" y1="-10.16" x2="7.62" y2="-10.16" width="0.254" layer="94"/>
+<pin name="SHIELD" x="-7.62" y="-7.62" visible="pin" length="short" direction="pas"/>
+<text x="0.762" y="-12.192" size="1.27" layer="95" align="bottom-center">&gt;VALUE</text>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="HEADER-5X2" prefix="J">
+<gates>
+<gate name="G$1" symbol="HEADER-5X2" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-TH-1.27" package="HEADER-5X2-1.27MM">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="10" pad="10"/>
+<connect gate="G$1" pin="2" pad="2"/>
+<connect gate="G$1" pin="3" pad="3"/>
+<connect gate="G$1" pin="4" pad="4"/>
+<connect gate="G$1" pin="5" pad="5"/>
+<connect gate="G$1" pin="6" pad="6"/>
+<connect gate="G$1" pin="7" pad="7"/>
+<connect gate="G$1" pin="8" pad="8"/>
+<connect gate="G$1" pin="9" pad="9"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-TH-2.54" package="HEADER-5X2-2.54MM">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="10" pad="10"/>
+<connect gate="G$1" pin="2" pad="2"/>
+<connect gate="G$1" pin="3" pad="3"/>
+<connect gate="G$1" pin="4" pad="4"/>
+<connect gate="G$1" pin="5" pad="5"/>
+<connect gate="G$1" pin="6" pad="6"/>
+<connect gate="G$1" pin="7" pad="7"/>
+<connect gate="G$1" pin="8" pad="8"/>
+<connect gate="G$1" pin="9" pad="9"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="USB-B-MICRO" prefix="J" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="MICRO-USB-5" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-SMT" package="USB-B-MICRO-SMT-SHELL-TH">
+<connects>
+<connect gate="G$1" pin="DM" pad="2"/>
+<connect gate="G$1" pin="DP" pad="3"/>
+<connect gate="G$1" pin="GND" pad="5"/>
+<connect gate="G$1" pin="ID" pad="4"/>
+<connect gate="G$1" pin="SHIELD" pad="M1 M2 M3 M4" route="any"/>
+<connect gate="G$1" pin="VBUS" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_rlc">
+<description>Alex Taradov Library (R, L and C)</description>
+<packages>
+<package name="SMD0402">
+<wire x1="-1" y1="0.5" x2="1" y2="0.5" width="0.1" layer="21"/>
+<wire x1="1" y1="0.5" x2="1" y2="-0.5" width="0.1" layer="21"/>
+<wire x1="1" y1="-0.5" x2="-1" y2="-0.5" width="0.1" layer="21"/>
+<wire x1="-1" y1="-0.5" x2="-1" y2="0.5" width="0.1" layer="21"/>
+<smd name="1" x="-0.5" y="0" dx="0.6" dy="0.6" layer="1"/>
+<smd name="2" x="0.5" y="0" dx="0.6" dy="0.6" layer="1"/>
+<text x="0" y="0.762" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SMD0508">
+<wire x1="-1" y1="1.25" x2="1" y2="1.25" width="0.1" layer="21"/>
+<wire x1="1" y1="1.25" x2="1" y2="-1.25" width="0.1" layer="21"/>
+<wire x1="1" y1="-1.25" x2="-1" y2="-1.25" width="0.1" layer="21"/>
+<wire x1="-1" y1="-1.25" x2="-1" y2="1.25" width="0.1" layer="21"/>
+<smd name="1" x="-0.5" y="0" dx="2" dy="0.5" layer="1" rot="R90"/>
+<smd name="2" x="0.5" y="0" dx="2" dy="0.5" layer="1" rot="R90"/>
+<text x="0" y="1.524" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SMD0603">
+<wire x1="-1.5" y1="0.75" x2="1.5" y2="0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="0.75" x2="1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="-0.75" x2="-1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="-1.5" y1="-0.75" x2="-1.5" y2="0.75" width="0.1" layer="21"/>
+<smd name="1" x="-0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<smd name="2" x="0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SMD0612">
+<wire x1="-1.8" y1="1.4" x2="1.8" y2="1.4" width="0.1" layer="21"/>
+<wire x1="1.8" y1="1.4" x2="1.8" y2="-1.4" width="0.1" layer="21"/>
+<wire x1="1.8" y1="-1.4" x2="-1.8" y2="-1.4" width="0.1" layer="21"/>
+<wire x1="-1.8" y1="-1.4" x2="-1.8" y2="1.4" width="0.1" layer="21"/>
+<smd name="1" x="0" y="0.8" dx="3.2" dy="0.8" layer="1"/>
+<smd name="2" x="0" y="-0.8" dx="3.2" dy="0.8" layer="1"/>
+<text x="0" y="1.778" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SMD0805">
+<wire x1="-2" y1="1" x2="2" y2="1" width="0.1" layer="21"/>
+<wire x1="2" y1="1" x2="2" y2="-1" width="0.1" layer="21"/>
+<wire x1="2" y1="-1" x2="-2" y2="-1" width="0.1" layer="21"/>
+<wire x1="-2" y1="-1" x2="-2" y2="1" width="0.1" layer="21"/>
+<smd name="1" x="-0.95" y="0" dx="1.3" dy="1.5" layer="1"/>
+<smd name="2" x="0.95" y="0" dx="1.3" dy="1.5" layer="1"/>
+<text x="0" y="1.27" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SMD1206">
+<wire x1="-2.5" y1="1.5" x2="2.5" y2="1.5" width="0.1" layer="21"/>
+<wire x1="2.5" y1="1.5" x2="2.5" y2="-1.5" width="0.1" layer="21"/>
+<wire x1="2.5" y1="-1.5" x2="-2.5" y2="-1.5" width="0.1" layer="21"/>
+<wire x1="-2.5" y1="-1.5" x2="-2.5" y2="1.5" width="0.1" layer="21"/>
+<smd name="1" x="-1.4" y="0" dx="1.6" dy="2" layer="1"/>
+<smd name="2" x="1.4" y="0" dx="1.6" dy="2" layer="1"/>
+<text x="0" y="1.778" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SMD2512">
+<wire x1="-5.5" y1="2.5" x2="5.5" y2="2.5" width="0.1" layer="21"/>
+<wire x1="5.5" y1="2.5" x2="5.5" y2="-2.5" width="0.1" layer="21"/>
+<wire x1="5.5" y1="-2.5" x2="-5.5" y2="-2.5" width="0.1" layer="21"/>
+<wire x1="-5.5" y1="-2.5" x2="-5.5" y2="2.5" width="0.1" layer="21"/>
+<smd name="1" x="-3.25" y="0" dx="3.5" dy="3" layer="1" rot="R90"/>
+<smd name="2" x="3.25" y="0" dx="3.5" dy="3" layer="1" rot="R90"/>
+<text x="0" y="2.794" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+</packages>
+<symbols>
+<symbol name="C">
+<rectangle x1="-1.524" y1="-0.254" x2="2.54" y2="0.254" layer="94" rot="R90"/>
+<rectangle x1="-2.54" y1="-0.254" x2="1.524" y2="0.254" layer="94" rot="R90"/>
+<wire x1="-2.54" y1="0" x2="-0.762" y2="0" width="0.1524" layer="94"/>
+<wire x1="2.54" y1="0" x2="0.762" y2="0" width="0.1524" layer="94"/>
+<pin name="1" x="-2.54" y="0" visible="off" length="point" direction="pas" swaplevel="1"/>
+<pin name="2" x="2.54" y="0" visible="off" length="point" direction="pas" swaplevel="1" rot="R180"/>
+<text x="0" y="2.413" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-3.683" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+</symbol>
+<symbol name="R">
+<wire x1="-2.54" y1="-1.016" x2="-2.54" y2="1.016" width="0.254" layer="94"/>
+<pin name="1" x="-5.08" y="0" visible="off" length="short" direction="pas" swaplevel="1"/>
+<pin name="2" x="5.08" y="0" visible="off" length="short" direction="pas" swaplevel="1" rot="R180"/>
+<text x="0" y="1.524" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<text x="0" y="0" size="1.016" layer="96" align="center">&gt;VALUE</text>
+<wire x1="2.54" y1="-1.016" x2="2.54" y2="1.016" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="1.016" x2="2.54" y2="1.016" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="-1.016" x2="2.54" y2="-1.016" width="0.254" layer="94"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="C" prefix="C" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="C" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-0402" package="SMD0402">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0508" package="SMD0508">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0603" package="SMD0603">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0612" package="SMD0612">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0805" package="SMD0805">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-1206" package="SMD1206">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-2512" package="SMD2512">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="R" prefix="R" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="R" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-0402" package="SMD0402">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0508" package="SMD0508">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0603" package="SMD0603">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0612" package="SMD0612">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0805" package="SMD0805">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-1206" package="SMD1206">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-2512" package="SMD2512">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_vreg">
+<description>Alex Taradov Library (Voltage Regulators)</description>
+<packages>
+<package name="SOT23-5">
+<description>SOT23-5</description>
+<wire x1="1.422" y1="0.81" x2="1.422" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="1.422" y1="-0.81" x2="-1.422" y2="-0.81" width="0.1524" layer="51"/>
+<wire x1="-1.422" y1="-0.81" x2="-1.422" y2="0.81" width="0.1524" layer="21"/>
+<wire x1="-1.422" y1="0.81" x2="1.422" y2="0.81" width="0.1524" layer="51"/>
+<wire x1="-0.522" y1="0.81" x2="0.522" y2="0.81" width="0.1524" layer="21"/>
+<wire x1="-0.428" y1="-0.81" x2="-0.522" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="0.522" y1="-0.81" x2="0.428" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="-1.328" y1="-0.81" x2="-1.422" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="1.422" y1="-0.81" x2="1.328" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="1.328" y1="0.81" x2="1.422" y2="0.81" width="0.1524" layer="21"/>
+<wire x1="-1.422" y1="0.81" x2="-1.328" y2="0.81" width="0.1524" layer="21"/>
+<smd name="1" x="-0.95" y="-1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="2" x="0" y="-1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="3" x="0.95" y="-1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="4" x="0.95" y="1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="5" x="-0.95" y="1.3" dx="0.55" dy="1.2" layer="1"/>
+<text x="0" y="2.286" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-3.556" size="1.27" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+<rectangle x1="-1.2" y1="-1.5" x2="-0.7" y2="-0.85" layer="51"/>
+<rectangle x1="-0.25" y1="-1.5" x2="0.25" y2="-0.85" layer="51"/>
+<rectangle x1="0.7" y1="-1.5" x2="1.2" y2="-0.85" layer="51"/>
+<rectangle x1="0.7" y1="0.85" x2="1.2" y2="1.5" layer="51"/>
+<rectangle x1="-1.2" y1="0.85" x2="-0.7" y2="1.5" layer="51"/>
+</package>
+</packages>
+<symbols>
+<symbol name="VREG-3-EN">
+<wire x1="-7.62" y1="5.08" x2="7.62" y2="5.08" width="0.254" layer="94"/>
+<wire x1="7.62" y1="5.08" x2="7.62" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="7.62" y1="-2.54" x2="-7.62" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="-7.62" y1="-2.54" x2="-7.62" y2="5.08" width="0.254" layer="94"/>
+<text x="-2.032" y="-1.524" size="1.524" layer="95">GND</text>
+<text x="0" y="5.842" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<text x="1.524" y="-4.318" size="1.27" layer="96">&gt;VALUE</text>
+<pin name="IN" x="-10.16" y="2.54" length="short" direction="sup"/>
+<pin name="OUT" x="10.16" y="2.54" length="short" direction="sup" rot="R180"/>
+<pin name="GND" x="0" y="-5.08" visible="pad" length="short" direction="pwr" rot="R90"/>
+<pin name="EN" x="-10.16" y="0" length="short" direction="in"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="MIC5504" prefix="IC" uservalue="yes">
+<description>LM1117 voltage regulator</description>
+<gates>
+<gate name="G$1" symbol="VREG-3-EN" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-SOT23-5" package="SOT23-5">
+<connects>
+<connect gate="G$1" pin="EN" pad="3"/>
+<connect gate="G$1" pin="GND" pad="2"/>
+<connect gate="G$1" pin="IN" pad="1"/>
+<connect gate="G$1" pin="OUT" pad="5"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_misc">
+<description>Alex Taradov Library (Miscellaneous stuff)</description>
+<packages>
+<package name="TP-1.27MM">
+<smd name="1" x="0" y="0" dx="1.27" dy="1.27" layer="1" roundness="100" cream="no"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="TP-2.54MM">
+<smd name="1" x="0" y="0" dx="2.54" dy="2.54" layer="1" roundness="100" cream="no"/>
+<text x="0" y="1.778" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+</packages>
+<symbols>
+<symbol name="TP">
+<text x="4.064" y="-0.508" size="1.27" layer="95">&gt;NAME</text>
+<pin name="1" x="0" y="0" visible="off" length="short" direction="pas"/>
+<circle x="3.048" y="0" radius="0.508" width="0" layer="94"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="TEST-POINT" prefix="TP" uservalue="yes">
+<description>Test Point</description>
+<gates>
+<gate name="G$1" symbol="TP" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-1.27MM" package="TP-1.27MM">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-2.54MM" package="TP-2.54MM">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_led">
+<description>Alex Taradov Library (LEDs and other indication devices)</description>
+<packages>
+<package name="SMD0603">
+<wire x1="-1.5" y1="0.75" x2="1.5" y2="0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="0.75" x2="1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="-0.75" x2="-1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="-1.5" y1="-0.75" x2="-1.5" y2="0.75" width="0.1" layer="21"/>
+<smd name="1" x="-0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<smd name="2" x="0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SMD0805">
+<wire x1="-2" y1="1" x2="2" y2="1" width="0.1" layer="21"/>
+<wire x1="2" y1="1" x2="2" y2="-1" width="0.1" layer="21"/>
+<wire x1="2" y1="-1" x2="-2" y2="-1" width="0.1" layer="21"/>
+<wire x1="-2" y1="-1" x2="-2" y2="1" width="0.1" layer="21"/>
+<smd name="1" x="-0.95" y="0" dx="1.3" dy="1.5" layer="1"/>
+<smd name="2" x="0.95" y="0" dx="1.3" dy="1.5" layer="1"/>
+<text x="0" y="1.27" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+</packages>
+<symbols>
+<symbol name="LED">
+<wire x1="1.27" y1="0" x2="0" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="0" y1="-2.54" x2="-1.27" y2="0" width="0.254" layer="94"/>
+<wire x1="1.27" y1="-2.54" x2="0" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="0" y1="-2.54" x2="-1.27" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="1.27" y1="0" x2="0" y2="0" width="0.254" layer="94"/>
+<wire x1="0" y1="0" x2="-1.27" y2="0" width="0.254" layer="94"/>
+<wire x1="-2.032" y1="-0.762" x2="-3.429" y2="-2.159" width="0.1524" layer="94"/>
+<wire x1="-1.905" y1="-1.905" x2="-3.302" y2="-3.302" width="0.1524" layer="94"/>
+<text x="3.556" y="-2.032" size="1.27" layer="95" rot="R90" align="bottom-center">&gt;NAME</text>
+<text x="5.715" y="-2.032" size="1.27" layer="96" rot="R90" align="bottom-center">&gt;VALUE</text>
+<pin name="C" x="0" y="-5.08" visible="off" length="short" direction="pas" rot="R90"/>
+<pin name="A" x="0" y="2.54" visible="off" length="short" direction="pas" rot="R270"/>
+<polygon width="0.1524" layer="94">
+<vertex x="-3.429" y="-2.159"/>
+<vertex x="-3.048" y="-1.27"/>
+<vertex x="-2.54" y="-1.778"/>
+</polygon>
+<polygon width="0.1524" layer="94">
+<vertex x="-3.302" y="-3.302"/>
+<vertex x="-2.921" y="-2.413"/>
+<vertex x="-2.413" y="-2.921"/>
+</polygon>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="LED_SMD" prefix="LED" uservalue="yes">
+<description>SMD_LED</description>
+<gates>
+<gate name="G$1" symbol="LED" x="0" y="0"/>
+</gates>
+<devices>
+<device name="LED_0603" package="SMD0603">
+<connects>
+<connect gate="G$1" pin="A" pad="1"/>
+<connect gate="G$1" pin="C" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="LED_0805" package="SMD0805">
+<connects>
+<connect gate="G$1" pin="A" pad="1"/>
+<connect gate="G$1" pin="C" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+</libraries>
+<attributes>
+</attributes>
+<variantdefs>
+</variantdefs>
+<classes>
+<class number="0" name="default" width="0" drill="0">
+</class>
+</classes>
+<parts>
+<part name="IC2" library="ataradov_mcu" deviceset="ATSAMD11C" device=""/>
+<part name="P_9" library="ataradov_pwr" deviceset="+3V3" device=""/>
+<part name="P_7" library="ataradov_pwr" deviceset="+3V3" device=""/>
+<part name="P_17" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_8" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_16" library="ataradov_pwr" deviceset="V_USB" device=""/>
+<part name="P_3" library="ataradov_pwr" deviceset="V_USB" device=""/>
+<part name="C1" library="ataradov_rlc" deviceset="C" device="-0603" value="1uF"/>
+<part name="C2" library="ataradov_rlc" deviceset="C" device="-0603" value="1uF"/>
+<part name="R2" library="ataradov_rlc" deviceset="R" device="-0603" value="100"/>
+<part name="R3" library="ataradov_rlc" deviceset="R" device="-0603" value="100"/>
+<part name="R4" library="ataradov_rlc" deviceset="R" device="-0603" value="100"/>
+<part name="IC1" library="ataradov_vreg" deviceset="MIC5504" device="-SOT23-5" value="MIC5504-3.3"/>
+<part name="P_4" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_6" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_1" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_2" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="R7" library="ataradov_rlc" deviceset="R" device="-0603" value="470"/>
+<part name="TP1" library="ataradov_misc" deviceset="TEST-POINT" device="-1.27MM" value="SIO"/>
+<part name="TP2" library="ataradov_misc" deviceset="TEST-POINT" device="-1.27MM"/>
+<part name="TP3" library="ataradov_misc" deviceset="TEST-POINT" device="-1.27MM"/>
+<part name="TP4" library="ataradov_misc" deviceset="TEST-POINT" device="-1.27MM"/>
+<part name="LED1" library="ataradov_led" deviceset="LED_SMD" device="LED_0603"/>
+<part name="J1" library="ataradov_conn" deviceset="HEADER-5X2" device="-TH-1.27"/>
+<part name="P_11" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="R1" library="ataradov_rlc" deviceset="R" device="-0603" value="100"/>
+<part name="R8" library="ataradov_rlc" deviceset="R" device="-0603" value="100"/>
+<part name="P_5" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="J2" library="ataradov_conn" deviceset="USB-B-MICRO" device="-SMT"/>
+</parts>
+<sheets>
+<sheet>
+<plain>
+<frame x1="0" y1="0" x2="152.4" y2="119.38" columns="8" rows="5" layer="97"/>
+<text x="35.56" y="106.68" size="1.778" layer="97" align="bottom-center">Program</text>
+<text x="93.98" y="106.68" size="1.778" layer="97" align="bottom-center">Target</text>
+<text x="60.96" y="15.24" size="1.778" layer="97">Copyright (c) 2016-2018, Alex Taradov &lt;alex@taradov.com&gt;
+
+MCU firmware source code is available at https://github.com/ataradov/free-dap</text>
+</plain>
+<instances>
+<instance part="IC2" gate="G$1" x="40.64" y="53.34"/>
+<instance part="P_9" gate="1" x="53.34" y="27.94"/>
+<instance part="P_7" gate="1" x="60.96" y="66.04"/>
+<instance part="P_17" gate="1" x="76.2" y="40.64"/>
+<instance part="P_8" gate="1" x="60.96" y="40.64"/>
+<instance part="P_16" gate="1" x="76.2" y="60.96"/>
+<instance part="P_3" gate="1" x="25.4" y="27.94"/>
+<instance part="C1" gate="G$1" x="20.32" y="17.78" rot="R90"/>
+<instance part="C2" gate="G$1" x="53.34" y="17.78" rot="R90"/>
+<instance part="R2" gate="G$1" x="111.76" y="96.52"/>
+<instance part="R3" gate="G$1" x="111.76" y="91.44"/>
+<instance part="R4" gate="G$1" x="111.76" y="86.36"/>
+<instance part="IC1" gate="G$1" x="38.1" y="20.32"/>
+<instance part="P_4" gate="1" x="38.1" y="12.7"/>
+<instance part="P_6" gate="1" x="53.34" y="12.7"/>
+<instance part="P_1" gate="1" x="20.32" y="12.7"/>
+<instance part="P_2" gate="1" x="33.02" y="86.36"/>
+<instance part="R7" gate="G$1" x="114.3" y="53.34"/>
+<instance part="TP1" gate="G$1" x="35.56" y="96.52"/>
+<instance part="TP2" gate="G$1" x="35.56" y="93.98"/>
+<instance part="TP3" gate="G$1" x="35.56" y="91.44"/>
+<instance part="TP4" gate="G$1" x="35.56" y="88.9"/>
+<instance part="LED1" gate="G$1" x="124.46" y="53.34" rot="MR270"/>
+<instance part="J1" gate="G$1" x="88.9" y="91.44"/>
+<instance part="P_11" gate="1" x="78.74" y="81.28"/>
+<instance part="R1" gate="G$1" x="111.76" y="81.28"/>
+<instance part="R8" gate="G$1" x="111.76" y="76.2"/>
+<instance part="P_5" gate="1" x="132.08" y="48.26"/>
+<instance part="J2" gate="G$1" x="86.36" y="50.8"/>
+</instances>
+<busses>
+</busses>
+<nets>
+<net name="N$1" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA24"/>
+<wire x1="58.42" y1="48.26" x2="76.2" y2="48.26" width="0.1524" layer="91"/>
+<wire x1="76.2" y1="48.26" x2="76.2" y2="53.34" width="0.1524" layer="91"/>
+<wire x1="76.2" y1="53.34" x2="78.74" y2="53.34" width="0.1524" layer="91"/>
+<pinref part="J2" gate="G$1" pin="DM"/>
+</segment>
+</net>
+<net name="N$2" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA25"/>
+<wire x1="58.42" y1="50.8" x2="78.74" y2="50.8" width="0.1524" layer="91"/>
+<pinref part="J2" gate="G$1" pin="DP"/>
+</segment>
+</net>
+<net name="GND" class="0">
+<segment>
+<pinref part="P_17" gate="1" pin="GND"/>
+<wire x1="76.2" y1="43.18" x2="76.2" y2="45.72" width="0.1524" layer="91"/>
+<wire x1="76.2" y1="45.72" x2="78.74" y2="45.72" width="0.1524" layer="91"/>
+<pinref part="J2" gate="G$1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="IC1" gate="G$1" pin="GND"/>
+<pinref part="P_4" gate="1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="C1" gate="G$1" pin="1"/>
+<pinref part="P_1" gate="1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="C2" gate="G$1" pin="1"/>
+<pinref part="P_6" gate="1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="GND"/>
+<pinref part="P_8" gate="1" pin="GND"/>
+<wire x1="58.42" y1="53.34" x2="60.96" y2="53.34" width="0.1524" layer="91"/>
+<wire x1="60.96" y1="53.34" x2="60.96" y2="43.18" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="P_2" gate="1" pin="GND"/>
+<wire x1="33.02" y1="88.9" x2="35.56" y2="88.9" width="0.1524" layer="91"/>
+<pinref part="TP4" gate="G$1" pin="1"/>
+</segment>
+<segment>
+<pinref part="J1" gate="G$1" pin="3"/>
+<wire x1="81.28" y1="93.98" x2="78.74" y2="93.98" width="0.1524" layer="91"/>
+<pinref part="P_11" gate="1" pin="GND"/>
+<wire x1="78.74" y1="93.98" x2="78.74" y2="91.44" width="0.1524" layer="91"/>
+<pinref part="J1" gate="G$1" pin="5"/>
+<wire x1="78.74" y1="91.44" x2="78.74" y2="83.82" width="0.1524" layer="91"/>
+<wire x1="81.28" y1="91.44" x2="78.74" y2="91.44" width="0.1524" layer="91"/>
+<junction x="78.74" y="91.44"/>
+</segment>
+<segment>
+<pinref part="P_5" gate="1" pin="GND"/>
+<wire x1="132.08" y1="50.8" x2="132.08" y2="53.34" width="0.1524" layer="91"/>
+<wire x1="132.08" y1="53.34" x2="129.54" y2="53.34" width="0.1524" layer="91"/>
+<pinref part="LED1" gate="G$1" pin="C"/>
+</segment>
+</net>
+<net name="V_USB" class="0">
+<segment>
+<pinref part="P_16" gate="1" pin="V_USB"/>
+<wire x1="76.2" y1="58.42" x2="76.2" y2="55.88" width="0.1524" layer="91"/>
+<wire x1="76.2" y1="55.88" x2="78.74" y2="55.88" width="0.1524" layer="91"/>
+<pinref part="J2" gate="G$1" pin="VBUS"/>
+</segment>
+<segment>
+<pinref part="IC1" gate="G$1" pin="EN"/>
+<pinref part="P_3" gate="1" pin="V_USB"/>
+<wire x1="27.94" y1="20.32" x2="25.4" y2="20.32" width="0.1524" layer="91"/>
+<wire x1="25.4" y1="20.32" x2="25.4" y2="22.86" width="0.1524" layer="91"/>
+<pinref part="IC1" gate="G$1" pin="IN"/>
+<wire x1="25.4" y1="22.86" x2="25.4" y2="25.4" width="0.1524" layer="91"/>
+<wire x1="27.94" y1="22.86" x2="25.4" y2="22.86" width="0.1524" layer="91"/>
+<junction x="25.4" y="22.86"/>
+<pinref part="C1" gate="G$1" pin="2"/>
+<wire x1="25.4" y1="22.86" x2="20.32" y2="22.86" width="0.1524" layer="91"/>
+<wire x1="20.32" y1="22.86" x2="20.32" y2="20.32" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="+3V3" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="OUT"/>
+<wire x1="48.26" y1="22.86" x2="53.34" y2="22.86" width="0.1524" layer="91"/>
+<pinref part="C2" gate="G$1" pin="2"/>
+<wire x1="53.34" y1="20.32" x2="53.34" y2="22.86" width="0.1524" layer="91"/>
+<junction x="53.34" y="22.86"/>
+<pinref part="P_9" gate="1" pin="+3V3"/>
+<wire x1="53.34" y1="25.4" x2="53.34" y2="22.86" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="VDD"/>
+<pinref part="P_7" gate="1" pin="+3V3"/>
+<wire x1="58.42" y1="55.88" x2="60.96" y2="55.88" width="0.1524" layer="91"/>
+<wire x1="60.96" y1="55.88" x2="60.96" y2="63.5" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="SWDIO" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA31/SIO"/>
+<wire x1="58.42" y1="45.72" x2="63.5" y2="45.72" width="0.1524" layer="91"/>
+<label x="63.5" y="45.72" size="1.27" layer="95"/>
+</segment>
+<segment>
+<wire x1="35.56" y1="96.52" x2="33.02" y2="96.52" width="0.1524" layer="91"/>
+<label x="33.02" y="96.52" size="1.27" layer="95" rot="MR0"/>
+<pinref part="TP1" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="PA02" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA02"/>
+<wire x1="58.42" y1="58.42" x2="63.5" y2="58.42" width="0.1524" layer="91"/>
+<label x="63.5" y="58.42" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="PA04" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA04"/>
+<wire x1="58.42" y1="60.96" x2="63.5" y2="60.96" width="0.1524" layer="91"/>
+<label x="63.5" y="60.96" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="R7" gate="G$1" pin="1"/>
+<wire x1="109.22" y1="53.34" x2="106.68" y2="53.34" width="0.1524" layer="91"/>
+<label x="106.68" y="53.34" size="1.27" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="SWCLK" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA30/SCK"/>
+<wire x1="22.86" y1="45.72" x2="20.32" y2="45.72" width="0.1524" layer="91"/>
+<label x="20.32" y="45.72" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<label x="33.02" y="93.98" size="1.27" layer="95" rot="MR0"/>
+<wire x1="35.56" y1="93.98" x2="33.02" y2="93.98" width="0.1524" layer="91"/>
+<pinref part="TP2" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="RESET" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA28/RST"/>
+<wire x1="22.86" y1="48.26" x2="20.32" y2="48.26" width="0.1524" layer="91"/>
+<label x="20.32" y="48.26" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<label x="33.02" y="91.44" size="1.27" layer="95" rot="MR0"/>
+<wire x1="35.56" y1="91.44" x2="33.02" y2="91.44" width="0.1524" layer="91"/>
+<pinref part="TP3" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="N$5" class="0">
+<segment>
+<pinref part="J1" gate="G$1" pin="2"/>
+<pinref part="R2" gate="G$1" pin="1"/>
+<wire x1="96.52" y1="96.52" x2="106.68" y2="96.52" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="N$9" class="0">
+<segment>
+<pinref part="R3" gate="G$1" pin="1"/>
+<wire x1="106.68" y1="91.44" x2="106.68" y2="93.98" width="0.1524" layer="91"/>
+<pinref part="J1" gate="G$1" pin="4"/>
+<wire x1="106.68" y1="93.98" x2="96.52" y2="93.98" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="N$10" class="0">
+<segment>
+<pinref part="J1" gate="G$1" pin="6"/>
+<wire x1="96.52" y1="91.44" x2="104.14" y2="91.44" width="0.1524" layer="91"/>
+<wire x1="104.14" y1="91.44" x2="104.14" y2="86.36" width="0.1524" layer="91"/>
+<pinref part="R4" gate="G$1" pin="1"/>
+<wire x1="104.14" y1="86.36" x2="106.68" y2="86.36" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="N$11" class="0">
+<segment>
+<pinref part="R1" gate="G$1" pin="1"/>
+<wire x1="106.68" y1="81.28" x2="101.6" y2="81.28" width="0.1524" layer="91"/>
+<wire x1="101.6" y1="81.28" x2="101.6" y2="88.9" width="0.1524" layer="91"/>
+<pinref part="J1" gate="G$1" pin="8"/>
+<wire x1="101.6" y1="88.9" x2="96.52" y2="88.9" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="N$12" class="0">
+<segment>
+<pinref part="J1" gate="G$1" pin="10"/>
+<wire x1="96.52" y1="86.36" x2="99.06" y2="86.36" width="0.1524" layer="91"/>
+<wire x1="99.06" y1="86.36" x2="99.06" y2="76.2" width="0.1524" layer="91"/>
+<pinref part="R8" gate="G$1" pin="1"/>
+<wire x1="99.06" y1="76.2" x2="106.68" y2="76.2" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="PA14" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA14"/>
+<wire x1="20.32" y1="53.34" x2="22.86" y2="53.34" width="0.1524" layer="91"/>
+<label x="20.32" y="53.34" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="R3" gate="G$1" pin="2"/>
+<wire x1="119.38" y1="91.44" x2="116.84" y2="91.44" width="0.1524" layer="91"/>
+<label x="119.38" y="91.44" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="PA15" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA15"/>
+<wire x1="22.86" y1="50.8" x2="20.32" y2="50.8" width="0.1524" layer="91"/>
+<label x="20.32" y="50.8" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="R2" gate="G$1" pin="2"/>
+<wire x1="119.38" y1="96.52" x2="116.84" y2="96.52" width="0.1524" layer="91"/>
+<label x="119.38" y="96.52" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="N$3" class="0">
+<segment>
+<pinref part="R7" gate="G$1" pin="2"/>
+<pinref part="LED1" gate="G$1" pin="A"/>
+<wire x1="121.92" y1="53.34" x2="119.38" y2="53.34" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="PA09" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA9"/>
+<wire x1="22.86" y1="55.88" x2="20.32" y2="55.88" width="0.1524" layer="91"/>
+<label x="20.32" y="55.88" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="R4" gate="G$1" pin="2"/>
+<wire x1="119.38" y1="86.36" x2="116.84" y2="86.36" width="0.1524" layer="91"/>
+<label x="119.38" y="86.36" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="PA08" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA8"/>
+<wire x1="22.86" y1="58.42" x2="20.32" y2="58.42" width="0.1524" layer="91"/>
+<label x="20.32" y="58.42" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="R1" gate="G$1" pin="2"/>
+<wire x1="116.84" y1="81.28" x2="119.38" y2="81.28" width="0.1524" layer="91"/>
+<label x="119.38" y="81.28" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="PA05" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA5"/>
+<wire x1="22.86" y1="60.96" x2="20.32" y2="60.96" width="0.1524" layer="91"/>
+<label x="20.32" y="60.96" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="R8" gate="G$1" pin="2"/>
+<wire x1="119.38" y1="76.2" x2="116.84" y2="76.2" width="0.1524" layer="91"/>
+<label x="119.38" y="76.2" size="1.27" layer="95"/>
+</segment>
+</net>
+</nets>
+</sheet>
+</sheets>
+</schematic>
+</drawing>
+<compatibility>
+<note version="6.3" minversion="6.2.2" severity="warning">
+Since Version 6.2.2 text objects can contain more than one line,
+which will not be processed correctly with this version.
+</note>
+</compatibility>
+</eagle>

dap_link/lib/free-dap/hardware/d11_micro_usb_std_v2/d11_micro_usb_std_v2.brd

@@ -0,0 +1,640 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="7.3.0">
+<drawing>
+<settings>
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+<setting verticaltext="up"/>
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+<layer number="91" name="Nets" color="2" fill="1" visible="no" active="no"/>
+<layer number="92" name="Busses" color="1" fill="1" visible="no" active="no"/>
+<layer number="93" name="Pins" color="2" fill="1" visible="no" active="no"/>
+<layer number="94" name="Symbols" color="4" fill="1" visible="no" active="no"/>
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+<layer number="96" name="Values" color="7" fill="1" visible="no" active="no"/>
+<layer number="97" name="Info" color="7" fill="1" visible="no" active="no"/>
+<layer number="98" name="Guide" color="6" fill="1" visible="no" active="no"/>
+</layers>
+<board>
+<plain>
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+<circle x="16.256" y="1.524" radius="0.254" width="0.508" layer="22"/>
+</plain>
+<libraries>
+<library name="ataradov_mcu">
+<description>Alex Taradov Library (MCUs)</description>
+<packages>
+<package name="SO-14">
+<description>SO-14</description>
+<wire x1="4.318" y1="-1.143" x2="-3.175" y2="-1.143" width="0.127" layer="21"/>
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+<smd name="12" x="-1.27" y="2.6" dx="0.6" dy="1.778" layer="1"/>
+<smd name="11" x="0" y="2.6" dx="0.6" dy="1.778" layer="1"/>
+<smd name="6" x="2.54" y="-2.6" dx="0.6" dy="1.778" layer="1"/>
+<smd name="9" x="2.54" y="2.6" dx="0.6" dy="1.778" layer="1"/>
+<smd name="5" x="1.27" y="-2.6" dx="0.6" dy="1.778" layer="1"/>
+<smd name="7" x="3.81" y="-2.6" dx="0.6" dy="1.778" layer="1"/>
+<smd name="10" x="1.27" y="2.6" dx="0.6" dy="1.778" layer="1"/>
+<smd name="8" x="3.81" y="2.6" dx="0.6" dy="1.778" layer="1"/>
+<text x="0" y="-0.635" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<wire x1="-4.318" y1="0" x2="-3.175" y2="-1.143" width="0.127" layer="21"/>
+</package>
+</packages>
+</library>
+<library name="ataradov_conn">
+<description>Alex Taradov Library (Connectors)</description>
+<packages>
+<package name="HEADER-5X2-1.27MM">
+<wire x1="-3.81" y1="1.905" x2="3.81" y2="1.905" width="0.127" layer="21"/>
+<wire x1="3.81" y1="1.905" x2="3.81" y2="-1.905" width="0.127" layer="21"/>
+<wire x1="3.81" y1="-1.905" x2="-3.175" y2="-1.905" width="0.127" layer="21"/>
+<wire x1="-3.175" y1="-1.905" x2="-3.81" y2="-1.27" width="0.127" layer="21"/>
+<wire x1="-3.81" y1="-1.27" x2="-3.81" y2="1.905" width="0.127" layer="21"/>
+<pad name="1" x="-2.54" y="-0.635" drill="0.6096" diameter="1.016"/>
+<pad name="2" x="-2.54" y="0.635" drill="0.6096" diameter="1.016"/>
+<pad name="3" x="-1.27" y="-0.635" drill="0.6096" diameter="1.016"/>
+<pad name="4" x="-1.27" y="0.635" drill="0.6096" diameter="1.016"/>
+<pad name="5" x="0" y="-0.635" drill="0.6096" diameter="1.016"/>
+<pad name="6" x="0" y="0.635" drill="0.6096" diameter="1.016"/>
+<pad name="7" x="1.27" y="-0.635" drill="0.6096" diameter="1.016"/>
+<pad name="8" x="1.27" y="0.635" drill="0.6096" diameter="1.016"/>
+<pad name="9" x="2.54" y="-0.635" drill="0.6096" diameter="1.016"/>
+<pad name="10" x="2.54" y="0.635" drill="0.6096" diameter="1.016"/>
+<text x="0" y="2.54" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="USB-B-MICRO-SMT-SHELL-TH">
+<pad name="M1" x="2.15" y="-3.6" drill="1.143"/>
+<pad name="M2" x="2.15" y="3.6" drill="1.143"/>
+<smd name="1" x="4.825" y="1.3" dx="1.35" dy="0.4" layer="1" stop="no"/>
+<smd name="2" x="4.825" y="0.65" dx="1.35" dy="0.4" layer="1" stop="no"/>
+<smd name="3" x="4.825" y="0" dx="1.35" dy="0.4" layer="1" stop="no"/>
+<smd name="4" x="4.825" y="-0.65" dx="1.35" dy="0.4" layer="1" stop="no"/>
+<smd name="5" x="4.825" y="-1.3" dx="1.35" dy="0.4" layer="1" stop="no"/>
+<text x="3.175" y="0" size="1.27" layer="25" font="vector" rot="R90" align="bottom-center">&gt;NAME</text>
+<rectangle x1="4.1" y1="1.05" x2="5.55" y2="1.55" layer="29"/>
+<pad name="M3" x="5.05" y="2.425" drill="0.635" shape="long"/>
+<pad name="M4" x="5.05" y="-2.425" drill="0.635" shape="long"/>
+<rectangle x1="4.1" y1="0.4" x2="5.55" y2="0.9" layer="29"/>
+<rectangle x1="4.1" y1="-0.25" x2="5.55" y2="0.25" layer="29"/>
+<rectangle x1="4.1" y1="-0.9" x2="5.55" y2="-0.4" layer="29"/>
+<rectangle x1="4.1" y1="-1.55" x2="5.55" y2="-1.05" layer="29"/>
+<wire x1="-0.5" y1="4" x2="-0.6" y2="3.8" width="0.1524" layer="21"/>
+<wire x1="-0.6" y1="3.8" x2="0" y2="3.5" width="0.1524" layer="21"/>
+<wire x1="0" y1="3.5" x2="0" y2="3.1" width="0.1524" layer="21"/>
+<wire x1="0" y1="3.1" x2="-0.6" y2="3.1" width="0.1524" layer="21"/>
+<wire x1="-0.6" y1="3.1" x2="-0.6" y2="-3.1" width="0.1524" layer="21"/>
+<wire x1="-0.6" y1="-3.1" x2="0" y2="-3.1" width="0.1524" layer="21"/>
+<wire x1="0" y1="-3.1" x2="0" y2="-3.5" width="0.1524" layer="21"/>
+<wire x1="0" y1="-3.5" x2="-0.6" y2="-3.8" width="0.1524" layer="21"/>
+<wire x1="-0.6" y1="-3.8" x2="-0.5" y2="-4" width="0.1524" layer="21"/>
+<wire x1="-0.5" y1="-4" x2="0" y2="-3.75" width="0.1524" layer="21"/>
+<wire x1="0" y1="-3.75" x2="5" y2="-3.75" width="0.1524" layer="21"/>
+<wire x1="5" y1="-3.75" x2="5" y2="-3.16" width="0.1524" layer="21"/>
+<wire x1="-0.5" y1="4" x2="0" y2="3.75" width="0.1524" layer="21"/>
+<wire x1="0" y1="3.75" x2="5" y2="3.75" width="0.1524" layer="21"/>
+<wire x1="5" y1="3.75" x2="5" y2="3.16" width="0.1524" layer="21"/>
+</package>
+</packages>
+</library>
+<library name="ataradov_rlc">
+<description>Alex Taradov Library (R, L and C)</description>
+<packages>
+<package name="SMD0603">
+<wire x1="-1.5" y1="0.75" x2="1.5" y2="0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="0.75" x2="1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="-0.75" x2="-1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="-1.5" y1="-0.75" x2="-1.5" y2="0.75" width="0.1" layer="21"/>
+<smd name="1" x="-0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<smd name="2" x="0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+<package name="SMD0603-X4">
+<smd name="1" x="-1.2" y="-0.752" dx="0.5" dy="0.889" layer="1"/>
+<smd name="2" x="-0.4" y="-0.752" dx="0.5" dy="0.889" layer="1"/>
+<smd name="3" x="0.4" y="-0.752" dx="0.5" dy="0.889" layer="1"/>
+<smd name="4" x="1.2" y="-0.752" dx="0.5" dy="0.889" layer="1"/>
+<smd name="5" x="1.2" y="0.752" dx="0.5" dy="0.889" layer="1"/>
+<smd name="6" x="0.4" y="0.752" dx="0.5" dy="0.889" layer="1"/>
+<smd name="7" x="-0.4" y="0.752" dx="0.5" dy="0.889" layer="1"/>
+<smd name="8" x="-1.2" y="0.752" dx="0.5" dy="0.889" layer="1"/>
+<text x="0" y="1.778" size="1.27" layer="25" font="vector" ratio="10" align="bottom-center">&gt;NAME</text>
+<wire x1="1.778" y1="1.4986" x2="1.778" y2="-1.524" width="0.1016" layer="21"/>
+<wire x1="-1.778" y1="1.4986" x2="-1.778" y2="-1.524" width="0.1016" layer="21"/>
+<wire x1="-1.778" y1="1.4986" x2="1.778" y2="1.4986" width="0.1016" layer="21"/>
+<wire x1="-1.778" y1="-1.524" x2="1.778" y2="-1.524" width="0.1016" layer="21"/>
+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" ratio="10" align="bottom-center">&gt;VALUE</text>
+</package>
+</packages>
+</library>
+<library name="ataradov_vreg">
+<description>Alex Taradov Library (Voltage Regulators)</description>
+<packages>
+<package name="SOT23-5">
+<description>SOT23-5</description>
+<wire x1="1.422" y1="0.81" x2="1.422" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="1.422" y1="-0.81" x2="-1.422" y2="-0.81" width="0.1524" layer="51"/>
+<wire x1="-1.422" y1="-0.81" x2="-1.422" y2="0.81" width="0.1524" layer="21"/>
+<wire x1="-1.422" y1="0.81" x2="1.422" y2="0.81" width="0.1524" layer="51"/>
+<wire x1="-0.522" y1="0.81" x2="0.522" y2="0.81" width="0.1524" layer="21"/>
+<wire x1="-0.428" y1="-0.81" x2="-0.522" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="0.522" y1="-0.81" x2="0.428" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="-1.328" y1="-0.81" x2="-1.422" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="1.422" y1="-0.81" x2="1.328" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="1.328" y1="0.81" x2="1.422" y2="0.81" width="0.1524" layer="21"/>
+<wire x1="-1.422" y1="0.81" x2="-1.328" y2="0.81" width="0.1524" layer="21"/>
+<smd name="1" x="-0.95" y="-1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="2" x="0" y="-1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="3" x="0.95" y="-1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="4" x="0.95" y="1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="5" x="-0.95" y="1.3" dx="0.55" dy="1.2" layer="1"/>
+<text x="0" y="2.286" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+</packages>
+</library>
+<library name="ataradov_misc">
+<description>Alex Taradov Library (Miscellaneous stuff)</description>
+<packages>
+<package name="TP-1.27MM">
+<smd name="1" x="0" y="0" dx="1.27" dy="1.27" layer="1" roundness="100" cream="no"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+</packages>
+</library>
+<library name="ataradov_led">
+<description>Alex Taradov Library (LEDs and other indication devices)</description>
+<packages>
+<package name="SMD0603">
+<wire x1="-1.5" y1="0.75" x2="1.5" y2="0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="0.75" x2="1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="-0.75" x2="-1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="-1.5" y1="-0.75" x2="-1.5" y2="0.75" width="0.1" layer="21"/>
+<smd name="1" x="-0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<smd name="2" x="0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+</packages>
+</library>
+</libraries>
+<attributes>
+</attributes>
+<variantdefs>
+</variantdefs>
+<classes>
+<class number="0" name="default" width="0" drill="0">
+</class>
+</classes>
+<designrules name="std-tented-new">
+<description language="de">&lt;b&gt;EAGLE Design Rules&lt;/b&gt;
+&lt;p&gt;
+Die Standard-Design-Rules sind so gewählt, dass sie für 
+die meisten Anwendungen passen. Sollte ihre Platine 
+besondere Anforderungen haben, treffen Sie die erforderlichen
+Einstellungen hier und speichern die Design Rules unter 
+einem neuen Namen ab.</description>
+<description language="en">&lt;b&gt;Laen's PCB Order Design Rules&lt;/b&gt;
+&lt;p&gt;
+Please make sure your boards conform to these design rules.</description>
+<param name="layerSetup" value="(1*16)"/>
+<param name="mtCopper" value="0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm"/>
+<param name="mtIsolate" value="1.5011mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm"/>
+<param name="mdWireWire" value="6mil"/>
+<param name="mdWirePad" value="6mil"/>
+<param name="mdWireVia" value="6mil"/>
+<param name="mdPadPad" value="6mil"/>
+<param name="mdPadVia" value="6mil"/>
+<param name="mdViaVia" value="6mil"/>
+<param name="mdSmdPad" value="0mil"/>
+<param name="mdSmdVia" value="0mil"/>
+<param name="mdSmdSmd" value="0mil"/>
+<param name="mdViaViaSameLayer" value="8mil"/>
+<param name="mnLayersViaInSmd" value="2"/>
+<param name="mdCopperDimension" value="10mil"/>
+<param name="mdDrill" value="6mil"/>
+<param name="mdSmdStop" value="0mil"/>
+<param name="msWidth" value="8mil"/>
+<param name="msDrill" value="12mil"/>
+<param name="msMicroVia" value="12mil"/>
+<param name="msBlindViaRatio" value="0.5"/>
+<param name="rvPadTop" value="0.25"/>
+<param name="rvPadInner" value="0.25"/>
+<param name="rvPadBottom" value="0.25"/>
+<param name="rvViaOuter" value="0.25"/>
+<param name="rvViaInner" value="0.25"/>
+<param name="rvMicroViaOuter" value="0.25"/>
+<param name="rvMicroViaInner" value="0.25"/>
+<param name="rlMinPadTop" value="7mil"/>
+<param name="rlMaxPadTop" value="20mil"/>
+<param name="rlMinPadInner" value="7mil"/>
+<param name="rlMaxPadInner" value="20mil"/>
+<param name="rlMinPadBottom" value="7mil"/>
+<param name="rlMaxPadBottom" value="20mil"/>
+<param name="rlMinViaOuter" value="7mil"/>
+<param name="rlMaxViaOuter" value="20mil"/>
+<param name="rlMinViaInner" value="7mil"/>
+<param name="rlMaxViaInner" value="20mil"/>
+<param name="rlMinMicroViaOuter" value="4mil"/>
+<param name="rlMaxMicroViaOuter" value="20mil"/>
+<param name="rlMinMicroViaInner" value="4mil"/>
+<param name="rlMaxMicroViaInner" value="20mil"/>
+<param name="psTop" value="-1"/>
+<param name="psBottom" value="-1"/>
+<param name="psFirst" value="-1"/>
+<param name="psElongationLong" value="100"/>
+<param name="psElongationOffset" value="100"/>
+<param name="mvStopFrame" value="1"/>
+<param name="mvCreamFrame" value="0"/>
+<param name="mlMinStopFrame" value="3mil"/>
+<param name="mlMaxStopFrame" value="3mil"/>
+<param name="mlMinCreamFrame" value="0mil"/>
+<param name="mlMaxCreamFrame" value="0mil"/>
+<param name="mlViaStopLimit" value="25mil"/>
+<param name="srRoundness" value="0"/>
+<param name="srMinRoundness" value="0mil"/>
+<param name="srMaxRoundness" value="0mil"/>
+<param name="slThermalIsolate" value="6mil"/>
+<param name="slThermalsForVias" value="0"/>
+<param name="dpMaxLengthDifference" value="10mm"/>
+<param name="dpGapFactor" value="2.5"/>
+<param name="checkGrid" value="0"/>
+<param name="checkAngle" value="0"/>
+<param name="checkFont" value="1"/>
+<param name="checkRestrict" value="1"/>
+<param name="useDiameter" value="13"/>
+<param name="maxErrors" value="50"/>
+</designrules>
+<autorouter>
+<pass name="Default">
+<param name="RoutingGrid" value="50mil"/>
+<param name="AutoGrid" value="1"/>
+<param name="Efforts" value="0"/>
+<param name="TopRouterVariant" value="1"/>
+<param name="tpViaShape" value="round"/>
+<param name="PrefDir.1" value="a"/>
+<param name="PrefDir.2" value="0"/>
+<param name="PrefDir.3" value="0"/>
+<param name="PrefDir.4" value="0"/>
+<param name="PrefDir.5" value="0"/>
+<param name="PrefDir.6" value="0"/>
+<param name="PrefDir.7" value="0"/>
+<param name="PrefDir.8" value="0"/>
+<param name="PrefDir.9" value="0"/>
+<param name="PrefDir.10" value="0"/>
+<param name="PrefDir.11" value="0"/>
+<param name="PrefDir.12" value="0"/>
+<param name="PrefDir.13" value="0"/>
+<param name="PrefDir.14" value="0"/>
+<param name="PrefDir.15" value="0"/>
+<param name="PrefDir.16" value="a"/>
+<param name="cfVia" value="8"/>
+<param name="cfNonPref" value="5"/>
+<param name="cfChangeDir" value="2"/>
+<param name="cfOrthStep" value="2"/>
+<param name="cfDiagStep" value="3"/>
+<param name="cfExtdStep" value="0"/>
+<param name="cfBonusStep" value="1"/>
+<param name="cfMalusStep" value="1"/>
+<param name="cfPadImpact" value="4"/>
+<param name="cfSmdImpact" value="4"/>
+<param name="cfBusImpact" value="0"/>
+<param name="cfHugging" value="3"/>
+<param name="cfAvoid" value="4"/>
+<param name="cfPolygon" value="10"/>
+<param name="cfBase.1" value="0"/>
+<param name="cfBase.2" value="1"/>
+<param name="cfBase.3" value="1"/>
+<param name="cfBase.4" value="1"/>
+<param name="cfBase.5" value="1"/>
+<param name="cfBase.6" value="1"/>
+<param name="cfBase.7" value="1"/>
+<param name="cfBase.8" value="1"/>
+<param name="cfBase.9" value="1"/>
+<param name="cfBase.10" value="1"/>
+<param name="cfBase.11" value="1"/>
+<param name="cfBase.12" value="1"/>
+<param name="cfBase.13" value="1"/>
+<param name="cfBase.14" value="1"/>
+<param name="cfBase.15" value="1"/>
+<param name="cfBase.16" value="0"/>
+<param name="mnVias" value="20"/>
+<param name="mnSegments" value="9999"/>
+<param name="mnExtdSteps" value="9999"/>
+<param name="mnRipupLevel" value="10"/>
+<param name="mnRipupSteps" value="100"/>
+<param name="mnRipupTotal" value="100"/>
+</pass>
+<pass name="Follow-me" refer="Default" active="yes">
+</pass>
+<pass name="Busses" refer="Default" active="yes">
+<param name="cfNonPref" value="4"/>
+<param name="cfBusImpact" value="4"/>
+<param name="cfHugging" value="0"/>
+<param name="mnVias" value="0"/>
+</pass>
+<pass name="Route" refer="Default" active="yes">
+</pass>
+<pass name="Optimize1" refer="Default" active="yes">
+<param name="cfVia" value="99"/>
+<param name="cfExtdStep" value="10"/>
+<param name="cfHugging" value="1"/>
+<param name="mnExtdSteps" value="1"/>
+<param name="mnRipupLevel" value="0"/>
+</pass>
+<pass name="Optimize2" refer="Optimize1" active="yes">
+<param name="cfNonPref" value="0"/>
+<param name="cfChangeDir" value="6"/>
+<param name="cfExtdStep" value="0"/>
+<param name="cfBonusStep" value="2"/>
+<param name="cfMalusStep" value="2"/>
+<param name="cfPadImpact" value="2"/>
+<param name="cfSmdImpact" value="2"/>
+<param name="cfHugging" value="0"/>
+</pass>
+<pass name="Optimize3" refer="Optimize2" active="yes">
+<param name="cfChangeDir" value="8"/>
+<param name="cfPadImpact" value="0"/>
+<param name="cfSmdImpact" value="0"/>
+</pass>
+<pass name="Optimize4" refer="Optimize3" active="yes">
+<param name="cfChangeDir" value="25"/>
+</pass>
+</autorouter>
+<elements>
+<element name="IC2" library="ataradov_mcu" package="SO-14" value="ATSAMD11C" x="9.906" y="6.096" smashed="yes" rot="MR270">
+<attribute name="NAME" x="9.906" y="10.922" size="1.27" layer="26" font="vector" rot="MR0" align="bottom-center"/>
+</element>
+<element name="C1" library="ataradov_rlc" package="SMD0603" value="1uF" x="2.032" y="3.556" rot="MR180"/>
+<element name="C2" library="ataradov_rlc" package="SMD0603" value="1uF" x="4.318" y="5.334" rot="MR90"/>
+<element name="R2" library="ataradov_rlc" package="SMD0603" value="100" x="11.43" y="3.048" rot="R180"/>
+<element name="IC1" library="ataradov_vreg" package="SOT23-5" value="MIC5504-3.3" x="2.032" y="6.096" smashed="yes" rot="MR0">
+<attribute name="NAME" x="2.032" y="8.382" size="1.27" layer="26" font="vector" rot="MR0" align="bottom-center"/>
+</element>
+<element name="R7" library="ataradov_rlc" package="SMD0603" value="470" x="8.382" y="8.382" rot="R270"/>
+<element name="TP1" library="ataradov_misc" package="TP-1.27MM" value="SIO" x="7.366" y="1.27" rot="MR0"/>
+<element name="TP2" library="ataradov_misc" package="TP-1.27MM" value="" x="12.446" y="1.27" rot="MR0"/>
+<element name="TP3" library="ataradov_misc" package="TP-1.27MM" value="" x="9.906" y="1.27" rot="MR0"/>
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+<element name="RN1" library="ataradov_rlc" package="SMD0603-X4" value="100" x="11.43" y="6.604" rot="R90"/>
+</elements>
+<signals>
+<signal name="GND">
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+<signal name="N$1">
+<contactref element="IC2" pad="9"/>
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+<signal name="N$2">
+<contactref element="IC2" pad="10"/>
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+</signal>
+<signal name="V_USB">
+<contactref element="IC1" pad="3"/>
+<contactref element="IC1" pad="1"/>
+<contactref element="C1" pad="2"/>
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+<wire x1="5.118" y1="6.134" x2="4.318" y2="6.134" width="0.254" layer="16"/>
+</signal>
+<signal name="SWDIO">
+<contactref element="IC2" pad="8"/>
+<contactref element="TP1" pad="1"/>
+<wire x1="7.306" y1="2.286" x2="7.366" y2="2.226" width="0.254" layer="16"/>
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+</signal>
+<signal name="PA02">
+<contactref element="IC2" pad="13"/>
+</signal>
+<signal name="PA04">
+<contactref element="IC2" pad="14"/>
+<contactref element="R7" pad="1"/>
+<via x="7.366" y="9.652" extent="1-16" drill="0.3302" diameter="0.254"/>
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+</signal>
+<signal name="SWCLK">
+<contactref element="IC2" pad="7"/>
+<contactref element="TP2" pad="1"/>
+<wire x1="12.506" y1="2.286" x2="12.446" y2="2.226" width="0.254" layer="16"/>
+<wire x1="12.446" y1="2.226" x2="12.446" y2="1.27" width="0.254" layer="16"/>
+</signal>
+<signal name="RESET">
+<contactref element="IC2" pad="6"/>
+<contactref element="TP3" pad="1"/>
+<wire x1="12.506" y1="3.556" x2="11.43" y2="3.556" width="0.254" layer="16"/>
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+</signal>
+<signal name="N$8">
+</signal>
+<signal name="N$5">
+<contactref element="J1" pad="2"/>
+<contactref element="R2" pad="1"/>
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+</signal>
+<signal name="N$9">
+<contactref element="J1" pad="4"/>
+<contactref element="RN1" pad="1"/>
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+<wire x1="13.011" y1="5.404" x2="14.351" y2="4.064" width="0.254" layer="1"/>
+</signal>
+<signal name="N$10">
+<contactref element="J1" pad="6"/>
+<contactref element="RN1" pad="2"/>
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+<signal name="N$11">
+<contactref element="J1" pad="8"/>
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+<signal name="N$12">
+<contactref element="J1" pad="10"/>
+<contactref element="RN1" pad="4"/>
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+<signal name="PA14">
+<contactref element="IC2" pad="4"/>
+<via x="9.652" y="5.08" extent="1-16" drill="0.3302"/>
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+<signal name="PA15">
+<contactref element="IC2" pad="5"/>
+<contactref element="R2" pad="2"/>
+<via x="9.652" y="4.064" extent="1-16" drill="0.3302"/>
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+<signal name="N$3">
+<contactref element="R7" pad="2"/>
+<contactref element="LED1" pad="1"/>
+<wire x1="8.382" y1="7.582" x2="8.382" y2="6.134" width="0.254" layer="1"/>
+</signal>
+<signal name="PA09">
+<contactref element="IC2" pad="3"/>
+<via x="9.652" y="6.096" extent="1-16" drill="0.3302"/>
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+<signal name="PA08">
+<contactref element="IC2" pad="2"/>
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+<signal name="PA05">
+<contactref element="IC2" pad="1"/>
+<via x="9.652" y="8.128" extent="1-16" drill="0.3302"/>
+<contactref element="RN1" pad="5"/>
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+</signal>
+</signals>
+</board>
+</drawing>
+</eagle>

dap_link/lib/free-dap/hardware/d11_micro_usb_std_v2/d11_micro_usb_std_v2.sch

@@ -0,0 +1,1372 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="7.3.0">
+<drawing>
+<settings>
+<setting alwaysvectorfont="no"/>
+<setting verticaltext="up"/>
+</settings>
+<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>
+<layers>
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+<layer number="16" name="Bottom" color="1" fill="1" visible="no" active="no"/>
+<layer number="17" name="Pads" color="2" fill="1" visible="no" active="no"/>
+<layer number="18" name="Vias" color="2" fill="1" visible="no" active="no"/>
+<layer number="19" name="Unrouted" color="6" fill="1" visible="no" active="no"/>
+<layer number="20" name="Dimension" color="15" fill="1" visible="no" active="no"/>
+<layer number="21" name="tPlace" color="7" fill="1" visible="no" active="no"/>
+<layer number="22" name="bPlace" color="7" fill="1" visible="no" active="no"/>
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+<layer number="25" name="tNames" color="7" fill="1" visible="no" active="no"/>
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+<layer number="29" name="tStop" color="7" fill="3" visible="no" active="no"/>
+<layer number="30" name="bStop" color="7" fill="6" visible="no" active="no"/>
+<layer number="31" name="tCream" color="7" fill="4" visible="no" active="no"/>
+<layer number="32" name="bCream" color="7" fill="5" visible="no" active="no"/>
+<layer number="33" name="tFinish" color="6" fill="3" visible="no" active="no"/>
+<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="no"/>
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+<layer number="92" name="Busses" color="1" fill="1" visible="yes" active="yes"/>
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+<layer number="94" name="Symbols" color="4" fill="1" visible="yes" active="yes"/>
+<layer number="95" name="Names" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="96" name="Values" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="97" name="Info" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/>
+</layers>
+<schematic xreflabel="%F%N/%S.%C%R" xrefpart="/%S.%C%R">
+<libraries>
+<library name="ataradov_mcu">
+<description>Alex Taradov Library (MCUs)</description>
+<packages>
+<package name="SO-14">
+<description>SO-14</description>
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+<text x="0" y="-0.635" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
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+</package>
+</packages>
+<symbols>
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+<description>Atmel SAM D09C/D10C/D11C Cortex-M0+ microcontroller</description>
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+<wire x1="-12.7" y1="-10.16" x2="-12.7" y2="10.16" width="0.254" layer="94"/>
+<pin name="PA28/RST" x="-15.24" y="-5.08" length="short"/>
+<pin name="PA8" x="-15.24" y="5.08" length="short"/>
+<pin name="PA9" x="-15.24" y="2.54" length="short"/>
+<pin name="PA14" x="-15.24" y="0" length="short"/>
+<pin name="PA15" x="-15.24" y="-2.54" length="short"/>
+<pin name="PA5" x="-15.24" y="7.62" length="short"/>
+<pin name="PA04" x="15.24" y="7.62" length="short" rot="R180"/>
+<pin name="PA02" x="15.24" y="5.08" length="short" rot="R180"/>
+<text x="0" y="10.922" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-12.192" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+<pin name="PA30/SCK" x="-15.24" y="-7.62" length="short"/>
+<pin name="VDD" x="15.24" y="2.54" length="short" rot="R180"/>
+<pin name="GND" x="15.24" y="0" length="short" rot="R180"/>
+<pin name="PA25" x="15.24" y="-2.54" length="short" rot="R180"/>
+<pin name="PA24" x="15.24" y="-5.08" length="short" rot="R180"/>
+<pin name="PA31/SIO" x="15.24" y="-7.62" length="short" rot="R180"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="ATSAMD11C" prefix="IC">
+<gates>
+<gate name="G$1" symbol="ATSAMDXXC" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="SO-14">
+<connects>
+<connect gate="G$1" pin="GND" pad="11"/>
+<connect gate="G$1" pin="PA02" pad="13"/>
+<connect gate="G$1" pin="PA04" pad="14"/>
+<connect gate="G$1" pin="PA14" pad="4"/>
+<connect gate="G$1" pin="PA15" pad="5"/>
+<connect gate="G$1" pin="PA24" pad="9"/>
+<connect gate="G$1" pin="PA25" pad="10"/>
+<connect gate="G$1" pin="PA28/RST" pad="6"/>
+<connect gate="G$1" pin="PA30/SCK" pad="7"/>
+<connect gate="G$1" pin="PA31/SIO" pad="8"/>
+<connect gate="G$1" pin="PA5" pad="1"/>
+<connect gate="G$1" pin="PA8" pad="2"/>
+<connect gate="G$1" pin="PA9" pad="3"/>
+<connect gate="G$1" pin="VDD" pad="12"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_pwr">
+<description>Alex Taradov Library (Power Symbols)</description>
+<packages>
+</packages>
+<symbols>
+<symbol name="+3V3">
+<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/>
+<text x="0" y="0.762" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+<pin name="+3V3" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/>
+</symbol>
+<symbol name="GND">
+<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/>
+<text x="0" y="-2.032" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+<pin name="GND" x="0" y="2.54" visible="off" length="short" direction="sup" rot="R270"/>
+</symbol>
+<symbol name="V_USB">
+<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/>
+<text x="0" y="0.762" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+<pin name="V_USB" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="+3V3" prefix="P_">
+<gates>
+<gate name="1" symbol="+3V3" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="GND" prefix="P_">
+<gates>
+<gate name="1" symbol="GND" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="V_USB" prefix="P_">
+<gates>
+<gate name="1" symbol="V_USB" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_conn">
+<description>Alex Taradov Library (Connectors)</description>
+<packages>
+<package name="HEADER-5X2-1.27MM">
+<wire x1="-3.81" y1="1.905" x2="3.81" y2="1.905" width="0.127" layer="21"/>
+<wire x1="3.81" y1="1.905" x2="3.81" y2="-1.905" width="0.127" layer="21"/>
+<wire x1="3.81" y1="-1.905" x2="-3.175" y2="-1.905" width="0.127" layer="21"/>
+<wire x1="-3.175" y1="-1.905" x2="-3.81" y2="-1.27" width="0.127" layer="21"/>
+<wire x1="-3.81" y1="-1.27" x2="-3.81" y2="1.905" width="0.127" layer="21"/>
+<pad name="1" x="-2.54" y="-0.635" drill="0.6096" diameter="1.016"/>
+<pad name="2" x="-2.54" y="0.635" drill="0.6096" diameter="1.016"/>
+<pad name="3" x="-1.27" y="-0.635" drill="0.6096" diameter="1.016"/>
+<pad name="4" x="-1.27" y="0.635" drill="0.6096" diameter="1.016"/>
+<pad name="5" x="0" y="-0.635" drill="0.6096" diameter="1.016"/>
+<pad name="6" x="0" y="0.635" drill="0.6096" diameter="1.016"/>
+<pad name="7" x="1.27" y="-0.635" drill="0.6096" diameter="1.016"/>
+<pad name="8" x="1.27" y="0.635" drill="0.6096" diameter="1.016"/>
+<pad name="9" x="2.54" y="-0.635" drill="0.6096" diameter="1.016"/>
+<pad name="10" x="2.54" y="0.635" drill="0.6096" diameter="1.016"/>
+<text x="0" y="2.54" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="HEADER-5X2-2.54MM">
+<wire x1="-6.35" y1="0" x2="-3.81" y2="0" width="0.127" layer="21"/>
+<wire x1="-3.81" y1="0" x2="-3.81" y2="-2.54" width="0.127" layer="21"/>
+<wire x1="-6.35" y1="2.54" x2="6.35" y2="2.54" width="0.127" layer="21"/>
+<wire x1="6.35" y1="2.54" x2="6.35" y2="-2.54" width="0.127" layer="21"/>
+<wire x1="6.35" y1="-2.54" x2="-6.35" y2="-2.54" width="0.127" layer="21"/>
+<wire x1="-6.35" y1="-2.54" x2="-6.35" y2="2.54" width="0.127" layer="21"/>
+<pad name="1" x="-5.08" y="-1.27" drill="1.016" shape="square"/>
+<pad name="2" x="-5.08" y="1.27" drill="1.016"/>
+<pad name="3" x="-2.54" y="-1.27" drill="1.016"/>
+<pad name="4" x="-2.54" y="1.27" drill="1.016"/>
+<pad name="5" x="0" y="-1.27" drill="1.016"/>
+<pad name="6" x="0" y="1.27" drill="1.016"/>
+<pad name="7" x="2.54" y="-1.27" drill="1.016"/>
+<pad name="8" x="2.54" y="1.27" drill="1.016"/>
+<pad name="9" x="5.08" y="-1.27" drill="1.016"/>
+<pad name="10" x="5.08" y="1.27" drill="1.016"/>
+<text x="0" y="3.175" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="USB-B-MICRO-SMT-SHELL-TH">
+<pad name="M1" x="2.15" y="-3.6" drill="1.143"/>
+<pad name="M2" x="2.15" y="3.6" drill="1.143"/>
+<smd name="1" x="4.825" y="1.3" dx="1.35" dy="0.4" layer="1" stop="no"/>
+<smd name="2" x="4.825" y="0.65" dx="1.35" dy="0.4" layer="1" stop="no"/>
+<smd name="3" x="4.825" y="0" dx="1.35" dy="0.4" layer="1" stop="no"/>
+<smd name="4" x="4.825" y="-0.65" dx="1.35" dy="0.4" layer="1" stop="no"/>
+<smd name="5" x="4.825" y="-1.3" dx="1.35" dy="0.4" layer="1" stop="no"/>
+<text x="3.175" y="0" size="1.27" layer="25" font="vector" rot="R90" align="bottom-center">&gt;NAME</text>
+<rectangle x1="4.1" y1="1.05" x2="5.55" y2="1.55" layer="29"/>
+<pad name="M3" x="5.05" y="2.425" drill="0.635" shape="long"/>
+<pad name="M4" x="5.05" y="-2.425" drill="0.635" shape="long"/>
+<rectangle x1="4.1" y1="0.4" x2="5.55" y2="0.9" layer="29"/>
+<rectangle x1="4.1" y1="-0.25" x2="5.55" y2="0.25" layer="29"/>
+<rectangle x1="4.1" y1="-0.9" x2="5.55" y2="-0.4" layer="29"/>
+<rectangle x1="4.1" y1="-1.55" x2="5.55" y2="-1.05" layer="29"/>
+<wire x1="-0.5" y1="4" x2="-0.6" y2="3.8" width="0.1524" layer="21"/>
+<wire x1="-0.6" y1="3.8" x2="0" y2="3.5" width="0.1524" layer="21"/>
+<wire x1="0" y1="3.5" x2="0" y2="3.1" width="0.1524" layer="21"/>
+<wire x1="0" y1="3.1" x2="-0.6" y2="3.1" width="0.1524" layer="21"/>
+<wire x1="-0.6" y1="3.1" x2="-0.6" y2="-3.1" width="0.1524" layer="21"/>
+<wire x1="-0.6" y1="-3.1" x2="0" y2="-3.1" width="0.1524" layer="21"/>
+<wire x1="0" y1="-3.1" x2="0" y2="-3.5" width="0.1524" layer="21"/>
+<wire x1="0" y1="-3.5" x2="-0.6" y2="-3.8" width="0.1524" layer="21"/>
+<wire x1="-0.6" y1="-3.8" x2="-0.5" y2="-4" width="0.1524" layer="21"/>
+<wire x1="-0.5" y1="-4" x2="0" y2="-3.75" width="0.1524" layer="21"/>
+<wire x1="0" y1="-3.75" x2="5" y2="-3.75" width="0.1524" layer="21"/>
+<wire x1="5" y1="-3.75" x2="5" y2="-3.16" width="0.1524" layer="21"/>
+<wire x1="-0.5" y1="4" x2="0" y2="3.75" width="0.1524" layer="21"/>
+<wire x1="0" y1="3.75" x2="5" y2="3.75" width="0.1524" layer="21"/>
+<wire x1="5" y1="3.75" x2="5" y2="3.16" width="0.1524" layer="21"/>
+</package>
+<package name="HEADER-5X2-1.27MM-SHR">
+<wire x1="-6.35" y1="2.794" x2="6.35" y2="2.794" width="0.127" layer="21"/>
+<wire x1="6.35" y1="2.794" x2="6.35" y2="-2.794" width="0.127" layer="21"/>
+<wire x1="6.35" y1="-2.794" x2="-6.35" y2="-2.794" width="0.127" layer="21"/>
+<wire x1="-6.35" y1="-2.794" x2="-6.35" y2="2.794" width="0.127" layer="21"/>
+<pad name="1" x="-2.54" y="-0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="2" x="-2.54" y="0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="3" x="-1.27" y="-0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="4" x="-1.27" y="0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="5" x="0" y="-0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="6" x="0" y="0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="7" x="1.27" y="-0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="8" x="1.27" y="0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="9" x="2.54" y="-0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="10" x="2.54" y="0.635" drill="0.6604" diameter="1.0668"/>
+<text x="0" y="3.302" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<circle x="-5.334" y="-1.778" radius="0.381" width="0.254" layer="21"/>
+</package>
+<package name="HEADER-5X2-2.54MM-SHR-RA">
+<description>10-pin right angle shrouded header</description>
+<wire x1="10.16" y1="2.794" x2="10.16" y2="10.922" width="0.127" layer="21"/>
+<wire x1="10.16" y1="10.922" x2="1.778" y2="10.922" width="0.127" layer="21"/>
+<wire x1="1.778" y1="10.922" x2="1.778" y2="4.572" width="0.127" layer="21"/>
+<wire x1="1.778" y1="4.572" x2="-1.778" y2="4.572" width="0.127" layer="21"/>
+<wire x1="-1.778" y1="4.572" x2="-1.778" y2="10.922" width="0.127" layer="21"/>
+<wire x1="1.778" y1="10.922" x2="-1.778" y2="10.922" width="0.127" layer="21"/>
+<wire x1="-1.778" y1="10.922" x2="-10.16" y2="10.922" width="0.127" layer="21"/>
+<wire x1="-10.16" y1="10.922" x2="-10.16" y2="2.794" width="0.127" layer="21"/>
+<wire x1="10.16" y1="2.794" x2="-10.16" y2="2.794" width="0.127" layer="21"/>
+<pad name="1" x="-5.08" y="-1.27" drill="1" diameter="1.4224" shape="square"/>
+<pad name="2" x="-5.08" y="1.27" drill="1" diameter="1.4224"/>
+<pad name="3" x="-2.54" y="-1.27" drill="1" diameter="1.4224"/>
+<pad name="4" x="-2.54" y="1.27" drill="1" diameter="1.4224"/>
+<pad name="5" x="0" y="-1.27" drill="1" diameter="1.4224"/>
+<pad name="6" x="0" y="1.27" drill="1" diameter="1.4224"/>
+<pad name="7" x="2.54" y="-1.27" drill="1" diameter="1.4224"/>
+<pad name="8" x="2.54" y="1.27" drill="1" diameter="1.4224"/>
+<pad name="9" x="5.08" y="-1.27" drill="1" diameter="1.4224"/>
+<pad name="10" x="5.08" y="1.27" drill="1" diameter="1.4224"/>
+<text x="-8.89" y="-0.508" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<wire x1="-8.89" y1="10.16" x2="-6.35" y2="10.16" width="0.127" layer="21"/>
+<wire x1="-6.35" y1="10.16" x2="-7.62" y2="8.89" width="0.127" layer="21"/>
+<wire x1="-7.62" y1="8.89" x2="-8.89" y2="10.16" width="0.127" layer="21"/>
+</package>
+<package name="HEADER-5X2-2.54MM-SHR-SIDE">
+<wire x1="10.16" y1="0.254" x2="10.16" y2="8.382" width="0.127" layer="21"/>
+<wire x1="10.16" y1="8.382" x2="1.778" y2="8.382" width="0.127" layer="21"/>
+<wire x1="1.778" y1="8.382" x2="1.778" y2="2.032" width="0.127" layer="21"/>
+<wire x1="1.778" y1="2.032" x2="-1.778" y2="2.032" width="0.127" layer="21"/>
+<wire x1="-1.778" y1="2.032" x2="-1.778" y2="8.382" width="0.127" layer="21"/>
+<wire x1="1.778" y1="8.382" x2="-1.778" y2="8.382" width="0.127" layer="21"/>
+<wire x1="-1.778" y1="8.382" x2="-10.16" y2="8.382" width="0.127" layer="21"/>
+<wire x1="-10.16" y1="8.382" x2="-10.16" y2="0.254" width="0.127" layer="21"/>
+<wire x1="10.16" y1="0.254" x2="-10.16" y2="0.254" width="0.127" layer="21"/>
+<text x="8.255" y="-3.175" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<wire x1="-8.89" y1="7.62" x2="-6.35" y2="7.62" width="0.127" layer="21"/>
+<wire x1="-6.35" y1="7.62" x2="-7.62" y2="6.35" width="0.127" layer="21"/>
+<wire x1="-7.62" y1="6.35" x2="-8.89" y2="7.62" width="0.127" layer="21"/>
+<smd name="1" x="-5.08" y="-2.54" dx="1.27" dy="2.54" layer="1"/>
+<smd name="3" x="-2.54" y="-2.54" dx="1.27" dy="2.54" layer="1"/>
+<smd name="5" x="0" y="-2.54" dx="1.27" dy="2.54" layer="1"/>
+<smd name="7" x="2.54" y="-2.54" dx="1.27" dy="2.54" layer="1"/>
+<smd name="9" x="5.08" y="-2.54" dx="1.27" dy="2.54" layer="1"/>
+<wire x1="-6.35" y1="-2.54" x2="-7.112" y2="-2.032" width="0.127" layer="21"/>
+<wire x1="-6.35" y1="-2.54" x2="-7.112" y2="-3.048" width="0.127" layer="21"/>
+<wire x1="-7.112" y1="-3.048" x2="-7.112" y2="-2.032" width="0.127" layer="21"/>
+<smd name="2" x="-5.08" y="-2.54" dx="1.27" dy="2.54" layer="16"/>
+<smd name="4" x="-2.54" y="-2.54" dx="1.27" dy="2.54" layer="16"/>
+<smd name="6" x="0" y="-2.54" dx="1.27" dy="2.54" layer="16"/>
+<smd name="8" x="2.54" y="-2.54" dx="1.27" dy="2.54" layer="16"/>
+<smd name="10" x="5.08" y="-2.54" dx="1.27" dy="2.54" layer="16"/>
+</package>
+</packages>
+<symbols>
+<symbol name="HEADER-5X2">
+<wire x1="-5.08" y1="7.62" x2="-5.08" y2="-7.62" width="0.254" layer="94"/>
+<wire x1="-5.08" y1="-7.62" x2="5.08" y2="-7.62" width="0.254" layer="94"/>
+<wire x1="5.08" y1="-7.62" x2="5.08" y2="7.62" width="0.254" layer="94"/>
+<wire x1="5.08" y1="7.62" x2="-5.08" y2="7.62" width="0.254" layer="94"/>
+<pin name="1" x="-7.62" y="5.08" length="short" direction="pas"/>
+<pin name="2" x="7.62" y="5.08" length="short" direction="pas" rot="R180"/>
+<pin name="3" x="-7.62" y="2.54" length="short" direction="pas"/>
+<pin name="4" x="7.62" y="2.54" length="short" direction="pas" rot="R180"/>
+<pin name="5" x="-7.62" y="0" length="short" direction="pas"/>
+<pin name="6" x="7.62" y="0" length="short" direction="pas" rot="R180"/>
+<pin name="7" x="-7.62" y="-2.54" length="short" direction="pas"/>
+<pin name="8" x="7.62" y="-2.54" length="short" direction="pas" rot="R180"/>
+<pin name="9" x="-7.62" y="-5.08" length="short" direction="pas"/>
+<pin name="10" x="7.62" y="-5.08" length="short" direction="pas" rot="R180"/>
+<text x="0" y="8.382" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+</symbol>
+<symbol name="MICRO-USB-5">
+<wire x1="-5.08" y1="7.62" x2="-5.08" y2="-10.16" width="0.254" layer="94"/>
+<text x="0.762" y="8.382" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<pin name="VBUS" x="-7.62" y="5.08" visible="pin" length="short" direction="pas"/>
+<pin name="DM" x="-7.62" y="2.54" visible="pin" length="short" direction="pas"/>
+<pin name="DP" x="-7.62" y="0" visible="pin" length="short" direction="pas"/>
+<pin name="ID" x="-7.62" y="-2.54" visible="pin" length="short" direction="pas"/>
+<pin name="GND" x="-7.62" y="-5.08" visible="pin" length="short" direction="pas"/>
+<wire x1="7.62" y1="7.62" x2="7.62" y2="-10.16" width="0.254" layer="94"/>
+<wire x1="-5.08" y1="7.62" x2="7.62" y2="7.62" width="0.254" layer="94"/>
+<wire x1="-5.08" y1="-10.16" x2="7.62" y2="-10.16" width="0.254" layer="94"/>
+<pin name="SHIELD" x="-7.62" y="-7.62" visible="pin" length="short" direction="pas"/>
+<text x="0.762" y="-12.192" size="1.27" layer="95" align="bottom-center">&gt;VALUE</text>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="HEADER-5X2" prefix="J">
+<gates>
+<gate name="G$1" symbol="HEADER-5X2" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-TH-1.27" package="HEADER-5X2-1.27MM">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="10" pad="10"/>
+<connect gate="G$1" pin="2" pad="2"/>
+<connect gate="G$1" pin="3" pad="3"/>
+<connect gate="G$1" pin="4" pad="4"/>
+<connect gate="G$1" pin="5" pad="5"/>
+<connect gate="G$1" pin="6" pad="6"/>
+<connect gate="G$1" pin="7" pad="7"/>
+<connect gate="G$1" pin="8" pad="8"/>
+<connect gate="G$1" pin="9" pad="9"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-TH-1.27-SHR" package="HEADER-5X2-1.27MM-SHR">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="10" pad="10"/>
+<connect gate="G$1" pin="2" pad="2"/>
+<connect gate="G$1" pin="3" pad="3"/>
+<connect gate="G$1" pin="4" pad="4"/>
+<connect gate="G$1" pin="5" pad="5"/>
+<connect gate="G$1" pin="6" pad="6"/>
+<connect gate="G$1" pin="7" pad="7"/>
+<connect gate="G$1" pin="8" pad="8"/>
+<connect gate="G$1" pin="9" pad="9"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-TH-2.54-SHR-RA" package="HEADER-5X2-2.54MM-SHR-RA">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="10" pad="10"/>
+<connect gate="G$1" pin="2" pad="2"/>
+<connect gate="G$1" pin="3" pad="3"/>
+<connect gate="G$1" pin="4" pad="4"/>
+<connect gate="G$1" pin="5" pad="5"/>
+<connect gate="G$1" pin="6" pad="6"/>
+<connect gate="G$1" pin="7" pad="7"/>
+<connect gate="G$1" pin="8" pad="8"/>
+<connect gate="G$1" pin="9" pad="9"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-TH-2.54-SHR-SIDE" package="HEADER-5X2-2.54MM-SHR-SIDE">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="10" pad="10"/>
+<connect gate="G$1" pin="2" pad="2"/>
+<connect gate="G$1" pin="3" pad="3"/>
+<connect gate="G$1" pin="4" pad="4"/>
+<connect gate="G$1" pin="5" pad="5"/>
+<connect gate="G$1" pin="6" pad="6"/>
+<connect gate="G$1" pin="7" pad="7"/>
+<connect gate="G$1" pin="8" pad="8"/>
+<connect gate="G$1" pin="9" pad="9"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-TH-2.54" package="HEADER-5X2-2.54MM">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="10" pad="10"/>
+<connect gate="G$1" pin="2" pad="2"/>
+<connect gate="G$1" pin="3" pad="3"/>
+<connect gate="G$1" pin="4" pad="4"/>
+<connect gate="G$1" pin="5" pad="5"/>
+<connect gate="G$1" pin="6" pad="6"/>
+<connect gate="G$1" pin="7" pad="7"/>
+<connect gate="G$1" pin="8" pad="8"/>
+<connect gate="G$1" pin="9" pad="9"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="USB-B-MICRO" prefix="J" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="MICRO-USB-5" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-SMT" package="USB-B-MICRO-SMT-SHELL-TH">
+<connects>
+<connect gate="G$1" pin="DM" pad="2"/>
+<connect gate="G$1" pin="DP" pad="3"/>
+<connect gate="G$1" pin="GND" pad="5"/>
+<connect gate="G$1" pin="ID" pad="4"/>
+<connect gate="G$1" pin="SHIELD" pad="M1 M2 M3 M4" route="any"/>
+<connect gate="G$1" pin="VBUS" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_rlc">
+<description>Alex Taradov Library (R, L and C)</description>
+<packages>
+<package name="SMD0508">
+<wire x1="-1" y1="1.25" x2="1" y2="1.25" width="0.1" layer="21"/>
+<wire x1="1" y1="1.25" x2="1" y2="-1.25" width="0.1" layer="21"/>
+<wire x1="1" y1="-1.25" x2="-1" y2="-1.25" width="0.1" layer="21"/>
+<wire x1="-1" y1="-1.25" x2="-1" y2="1.25" width="0.1" layer="21"/>
+<smd name="1" x="-0.5" y="0" dx="2" dy="0.5" layer="1" rot="R90"/>
+<smd name="2" x="0.5" y="0" dx="2" dy="0.5" layer="1" rot="R90"/>
+<text x="0" y="1.524" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SMD0603">
+<wire x1="-1.5" y1="0.75" x2="1.5" y2="0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="0.75" x2="1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="-0.75" x2="-1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="-1.5" y1="-0.75" x2="-1.5" y2="0.75" width="0.1" layer="21"/>
+<smd name="1" x="-0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<smd name="2" x="0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+<package name="SMD0612">
+<wire x1="-1.8" y1="1.4" x2="1.8" y2="1.4" width="0.1" layer="21"/>
+<wire x1="1.8" y1="1.4" x2="1.8" y2="-1.4" width="0.1" layer="21"/>
+<wire x1="1.8" y1="-1.4" x2="-1.8" y2="-1.4" width="0.1" layer="21"/>
+<wire x1="-1.8" y1="-1.4" x2="-1.8" y2="1.4" width="0.1" layer="21"/>
+<smd name="1" x="0" y="0.8" dx="3.2" dy="0.8" layer="1"/>
+<smd name="2" x="0" y="-0.8" dx="3.2" dy="0.8" layer="1"/>
+<text x="0" y="1.778" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SMD1206">
+<wire x1="-2.5" y1="1.5" x2="2.5" y2="1.5" width="0.1" layer="21"/>
+<wire x1="2.5" y1="1.5" x2="2.5" y2="-1.5" width="0.1" layer="21"/>
+<wire x1="2.5" y1="-1.5" x2="-2.5" y2="-1.5" width="0.1" layer="21"/>
+<wire x1="-2.5" y1="-1.5" x2="-2.5" y2="1.5" width="0.1" layer="21"/>
+<smd name="1" x="-1.4" y="0" dx="1.6" dy="2" layer="1"/>
+<smd name="2" x="1.4" y="0" dx="1.6" dy="2" layer="1"/>
+<text x="0" y="1.778" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SMD2512">
+<wire x1="-5.5" y1="2.5" x2="5.5" y2="2.5" width="0.1" layer="21"/>
+<wire x1="5.5" y1="2.5" x2="5.5" y2="-2.5" width="0.1" layer="21"/>
+<wire x1="5.5" y1="-2.5" x2="-5.5" y2="-2.5" width="0.1" layer="21"/>
+<wire x1="-5.5" y1="-2.5" x2="-5.5" y2="2.5" width="0.1" layer="21"/>
+<smd name="1" x="-3.25" y="0" dx="3.5" dy="3" layer="1" rot="R90"/>
+<smd name="2" x="3.25" y="0" dx="3.5" dy="3" layer="1" rot="R90"/>
+<text x="0" y="2.794" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SMD0402">
+<wire x1="-1" y1="0.5" x2="1" y2="0.5" width="0.1" layer="21"/>
+<wire x1="1" y1="0.5" x2="1" y2="-0.5" width="0.1" layer="21"/>
+<wire x1="1" y1="-0.5" x2="-1" y2="-0.5" width="0.1" layer="21"/>
+<wire x1="-1" y1="-0.5" x2="-1" y2="0.5" width="0.1" layer="21"/>
+<smd name="1" x="-0.5" y="0" dx="0.6" dy="0.6" layer="1"/>
+<smd name="2" x="0.5" y="0" dx="0.6" dy="0.6" layer="1"/>
+<text x="0" y="0.762" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+<package name="SMD0805">
+<wire x1="-2" y1="1" x2="2" y2="1" width="0.1" layer="21"/>
+<wire x1="2" y1="1" x2="2" y2="-1" width="0.1" layer="21"/>
+<wire x1="2" y1="-1" x2="-2" y2="-1" width="0.1" layer="21"/>
+<wire x1="-2" y1="-1" x2="-2" y2="1" width="0.1" layer="21"/>
+<smd name="1" x="-0.95" y="0" dx="1.3" dy="1.5" layer="1"/>
+<smd name="2" x="0.95" y="0" dx="1.3" dy="1.5" layer="1"/>
+<text x="0" y="1.27" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+<package name="SMD0603-X4">
+<smd name="1" x="-1.2" y="-0.752" dx="0.5" dy="0.889" layer="1"/>
+<smd name="2" x="-0.4" y="-0.752" dx="0.5" dy="0.889" layer="1"/>
+<smd name="3" x="0.4" y="-0.752" dx="0.5" dy="0.889" layer="1"/>
+<smd name="4" x="1.2" y="-0.752" dx="0.5" dy="0.889" layer="1"/>
+<smd name="5" x="1.2" y="0.752" dx="0.5" dy="0.889" layer="1"/>
+<smd name="6" x="0.4" y="0.752" dx="0.5" dy="0.889" layer="1"/>
+<smd name="7" x="-0.4" y="0.752" dx="0.5" dy="0.889" layer="1"/>
+<smd name="8" x="-1.2" y="0.752" dx="0.5" dy="0.889" layer="1"/>
+<text x="0" y="1.778" size="1.27" layer="25" font="vector" ratio="10" align="bottom-center">&gt;NAME</text>
+<wire x1="1.778" y1="1.4986" x2="1.778" y2="-1.524" width="0.1016" layer="21"/>
+<wire x1="-1.778" y1="1.4986" x2="-1.778" y2="-1.524" width="0.1016" layer="21"/>
+<wire x1="-1.778" y1="1.4986" x2="1.778" y2="1.4986" width="0.1016" layer="21"/>
+<wire x1="-1.778" y1="-1.524" x2="1.778" y2="-1.524" width="0.1016" layer="21"/>
+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" ratio="10" align="bottom-center">&gt;VALUE</text>
+</package>
+</packages>
+<symbols>
+<symbol name="C">
+<rectangle x1="-1.524" y1="-0.254" x2="2.54" y2="0.254" layer="94" rot="R90"/>
+<rectangle x1="-2.54" y1="-0.254" x2="1.524" y2="0.254" layer="94" rot="R90"/>
+<wire x1="-2.54" y1="0" x2="-0.762" y2="0" width="0.1524" layer="94"/>
+<wire x1="2.54" y1="0" x2="0.762" y2="0" width="0.1524" layer="94"/>
+<pin name="1" x="-2.54" y="0" visible="off" length="point" direction="pas" swaplevel="1"/>
+<pin name="2" x="2.54" y="0" visible="off" length="point" direction="pas" swaplevel="1" rot="R180"/>
+<text x="0" y="2.413" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-3.683" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+</symbol>
+<symbol name="R">
+<wire x1="-2.54" y1="-1.016" x2="-2.54" y2="1.016" width="0.254" layer="94"/>
+<pin name="1" x="-5.08" y="0" visible="off" length="short" direction="pas" swaplevel="1"/>
+<pin name="2" x="5.08" y="0" visible="off" length="short" direction="pas" swaplevel="1" rot="R180"/>
+<text x="0" y="1.524" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<text x="0" y="0" size="1.016" layer="96" align="center">&gt;VALUE</text>
+<wire x1="2.54" y1="-1.016" x2="2.54" y2="1.016" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="1.016" x2="2.54" y2="1.016" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="-1.016" x2="2.54" y2="-1.016" width="0.254" layer="94"/>
+</symbol>
+<symbol name="RN-4">
+<wire x1="-2.54" y1="1.524" x2="-2.54" y2="3.556" width="0.254" layer="94"/>
+<pin name="1" x="-5.08" y="2.54" visible="off" length="short" direction="pas"/>
+<pin name="8" x="5.08" y="2.54" visible="off" length="short" direction="pas" rot="R180"/>
+<text x="0" y="4.572" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<wire x1="2.54" y1="1.524" x2="2.54" y2="3.556" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="3.556" x2="2.54" y2="3.556" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="1.524" x2="2.54" y2="1.524" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="-1.016" x2="-2.54" y2="1.016" width="0.254" layer="94"/>
+<pin name="2" x="-5.08" y="0" visible="off" length="short" direction="pas"/>
+<pin name="7" x="5.08" y="0" visible="off" length="short" direction="pas" rot="R180"/>
+<wire x1="2.54" y1="-1.016" x2="2.54" y2="1.016" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="1.016" x2="2.54" y2="1.016" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="-1.016" x2="2.54" y2="-1.016" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="-3.556" x2="-2.54" y2="-1.524" width="0.254" layer="94"/>
+<pin name="3" x="-5.08" y="-2.54" visible="off" length="short" direction="pas"/>
+<pin name="6" x="5.08" y="-2.54" visible="off" length="short" direction="pas" rot="R180"/>
+<wire x1="2.54" y1="-3.556" x2="2.54" y2="-1.524" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="-1.524" x2="2.54" y2="-1.524" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="-3.556" x2="2.54" y2="-3.556" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="-6.096" x2="-2.54" y2="-4.064" width="0.254" layer="94"/>
+<pin name="4" x="-5.08" y="-5.08" visible="off" length="short" direction="pas"/>
+<pin name="5" x="5.08" y="-5.08" visible="off" length="short" direction="pas" rot="R180"/>
+<text x="0" y="2.54" size="1.016" layer="96" align="center">&gt;VALUE</text>
+<wire x1="2.54" y1="-6.096" x2="2.54" y2="-4.064" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="-4.064" x2="2.54" y2="-4.064" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="-6.096" x2="2.54" y2="-6.096" width="0.254" layer="94"/>
+<wire x1="-3.048" y1="-6.604" x2="-3.048" y2="4.064" width="0.127" layer="94" style="shortdash"/>
+<wire x1="3.048" y1="-6.604" x2="3.048" y2="4.064" width="0.127" layer="94" style="shortdash"/>
+<wire x1="3.048" y1="-6.604" x2="-3.048" y2="-6.604" width="0.127" layer="94" style="shortdash"/>
+<wire x1="3.048" y1="4.064" x2="-3.048" y2="4.064" width="0.127" layer="94" style="shortdash"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="C" prefix="C" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="C" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-0402" package="SMD0402">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0508" package="SMD0508">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0603" package="SMD0603">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0612" package="SMD0612">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0805" package="SMD0805">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-1206" package="SMD1206">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-2512" package="SMD2512">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="R" prefix="R" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="R" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-0402" package="SMD0402">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0508" package="SMD0508">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0603" package="SMD0603">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0612" package="SMD0612">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0805" package="SMD0805">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-1206" package="SMD1206">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-2512" package="SMD2512">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="RN-4" prefix="RN" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="RN-4" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-0603-X4" package="SMD0603-X4">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+<connect gate="G$1" pin="3" pad="3"/>
+<connect gate="G$1" pin="4" pad="4"/>
+<connect gate="G$1" pin="5" pad="5"/>
+<connect gate="G$1" pin="6" pad="6"/>
+<connect gate="G$1" pin="7" pad="7"/>
+<connect gate="G$1" pin="8" pad="8"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_vreg">
+<description>Alex Taradov Library (Voltage Regulators)</description>
+<packages>
+<package name="SOT23-5">
+<description>SOT23-5</description>
+<wire x1="1.422" y1="0.81" x2="1.422" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="1.422" y1="-0.81" x2="-1.422" y2="-0.81" width="0.1524" layer="51"/>
+<wire x1="-1.422" y1="-0.81" x2="-1.422" y2="0.81" width="0.1524" layer="21"/>
+<wire x1="-1.422" y1="0.81" x2="1.422" y2="0.81" width="0.1524" layer="51"/>
+<wire x1="-0.522" y1="0.81" x2="0.522" y2="0.81" width="0.1524" layer="21"/>
+<wire x1="-0.428" y1="-0.81" x2="-0.522" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="0.522" y1="-0.81" x2="0.428" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="-1.328" y1="-0.81" x2="-1.422" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="1.422" y1="-0.81" x2="1.328" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="1.328" y1="0.81" x2="1.422" y2="0.81" width="0.1524" layer="21"/>
+<wire x1="-1.422" y1="0.81" x2="-1.328" y2="0.81" width="0.1524" layer="21"/>
+<smd name="1" x="-0.95" y="-1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="2" x="0" y="-1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="3" x="0.95" y="-1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="4" x="0.95" y="1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="5" x="-0.95" y="1.3" dx="0.55" dy="1.2" layer="1"/>
+<text x="0" y="2.286" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+</packages>
+<symbols>
+<symbol name="VREG-3-EN">
+<wire x1="-7.62" y1="5.08" x2="7.62" y2="5.08" width="0.254" layer="94"/>
+<wire x1="7.62" y1="5.08" x2="7.62" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="7.62" y1="-2.54" x2="-7.62" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="-7.62" y1="-2.54" x2="-7.62" y2="5.08" width="0.254" layer="94"/>
+<text x="0" y="5.842" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-4.572" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+<pin name="IN" x="-10.16" y="2.54" length="short" direction="pas"/>
+<pin name="OUT" x="10.16" y="2.54" length="short" direction="pas" rot="R180"/>
+<pin name="GND" x="10.16" y="0" visible="pin" length="short" direction="pas" rot="R180"/>
+<pin name="EN" x="-10.16" y="0" length="short" direction="pas"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="MIC5504" prefix="IC" uservalue="yes">
+<description>LM1117 voltage regulator</description>
+<gates>
+<gate name="G$1" symbol="VREG-3-EN" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-SOT23-5" package="SOT23-5">
+<connects>
+<connect gate="G$1" pin="EN" pad="3"/>
+<connect gate="G$1" pin="GND" pad="2"/>
+<connect gate="G$1" pin="IN" pad="1"/>
+<connect gate="G$1" pin="OUT" pad="5"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_misc">
+<description>Alex Taradov Library (Miscellaneous stuff)</description>
+<packages>
+<package name="TP-1.27MM">
+<smd name="1" x="0" y="0" dx="1.27" dy="1.27" layer="1" roundness="100" cream="no"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="TP-2.54MM">
+<smd name="1" x="0" y="0" dx="2.54" dy="2.54" layer="1" roundness="100" cream="no"/>
+<text x="0" y="1.778" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="TP-0.635MM">
+<smd name="1" x="0" y="0" dx="0.635" dy="0.635" layer="1" roundness="100" cream="no"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="TP-0.5MM">
+<smd name="1" x="0" y="0" dx="0.5" dy="0.5" layer="1" roundness="100" cream="no"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="TP-1.27MM-TH">
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<pad name="1" x="0" y="0" drill="0.762" diameter="1.27"/>
+</package>
+</packages>
+<symbols>
+<symbol name="TP">
+<text x="4.064" y="-0.508" size="1.27" layer="95">&gt;NAME</text>
+<pin name="1" x="0" y="0" visible="off" length="short" direction="pas"/>
+<circle x="3.048" y="0" radius="0.508" width="0" layer="94"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="TEST-POINT" prefix="TP" uservalue="yes">
+<description>Test Point</description>
+<gates>
+<gate name="G$1" symbol="TP" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-1.27MM" package="TP-1.27MM">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0.635MM" package="TP-0.635MM">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0.5MM" package="TP-0.5MM">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-2.54MM" package="TP-2.54MM">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-1.27MM-TH" package="TP-1.27MM-TH">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_led">
+<description>Alex Taradov Library (LEDs and other indication devices)</description>
+<packages>
+<package name="SMD0603">
+<wire x1="-1.5" y1="0.75" x2="1.5" y2="0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="0.75" x2="1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="-0.75" x2="-1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="-1.5" y1="-0.75" x2="-1.5" y2="0.75" width="0.1" layer="21"/>
+<smd name="1" x="-0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<smd name="2" x="0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+<package name="SMD0805">
+<wire x1="-2" y1="1" x2="2" y2="1" width="0.1" layer="21"/>
+<wire x1="2" y1="1" x2="2" y2="-1" width="0.1" layer="21"/>
+<wire x1="2" y1="-1" x2="-2" y2="-1" width="0.1" layer="21"/>
+<wire x1="-2" y1="-1" x2="-2" y2="1" width="0.1" layer="21"/>
+<smd name="1" x="-0.95" y="0" dx="1.3" dy="1.5" layer="1"/>
+<smd name="2" x="0.95" y="0" dx="1.3" dy="1.5" layer="1"/>
+<text x="0" y="1.27" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+</packages>
+<symbols>
+<symbol name="LED">
+<wire x1="1.27" y1="0" x2="0" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="0" y1="-2.54" x2="-1.27" y2="0" width="0.254" layer="94"/>
+<wire x1="1.27" y1="-2.54" x2="0" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="0" y1="-2.54" x2="-1.27" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="1.27" y1="0" x2="0" y2="0" width="0.254" layer="94"/>
+<wire x1="0" y1="0" x2="-1.27" y2="0" width="0.254" layer="94"/>
+<wire x1="-2.032" y1="-0.762" x2="-3.429" y2="-2.159" width="0.1524" layer="94"/>
+<wire x1="-1.905" y1="-1.905" x2="-3.302" y2="-3.302" width="0.1524" layer="94"/>
+<text x="3.556" y="-2.032" size="1.27" layer="95" rot="R90" align="bottom-center">&gt;NAME</text>
+<text x="5.715" y="-2.032" size="1.27" layer="96" rot="R90" align="bottom-center">&gt;VALUE</text>
+<pin name="C" x="0" y="-5.08" visible="off" length="short" direction="pas" rot="R90"/>
+<pin name="A" x="0" y="2.54" visible="off" length="short" direction="pas" rot="R270"/>
+<polygon width="0.1524" layer="94">
+<vertex x="-3.429" y="-2.159"/>
+<vertex x="-3.048" y="-1.27"/>
+<vertex x="-2.54" y="-1.778"/>
+</polygon>
+<polygon width="0.1524" layer="94">
+<vertex x="-3.302" y="-3.302"/>
+<vertex x="-2.921" y="-2.413"/>
+<vertex x="-2.413" y="-2.921"/>
+</polygon>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="LED_SMD" prefix="LED" uservalue="yes">
+<description>SMD_LED</description>
+<gates>
+<gate name="G$1" symbol="LED" x="0" y="0"/>
+</gates>
+<devices>
+<device name="LED_0603" package="SMD0603">
+<connects>
+<connect gate="G$1" pin="A" pad="1"/>
+<connect gate="G$1" pin="C" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="LED_0805" package="SMD0805">
+<connects>
+<connect gate="G$1" pin="A" pad="1"/>
+<connect gate="G$1" pin="C" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+</libraries>
+<attributes>
+</attributes>
+<variantdefs>
+</variantdefs>
+<classes>
+<class number="0" name="default" width="0" drill="0">
+</class>
+</classes>
+<parts>
+<part name="IC2" library="ataradov_mcu" deviceset="ATSAMD11C" device=""/>
+<part name="P_9" library="ataradov_pwr" deviceset="+3V3" device=""/>
+<part name="P_7" library="ataradov_pwr" deviceset="+3V3" device=""/>
+<part name="P_17" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_8" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_16" library="ataradov_pwr" deviceset="V_USB" device=""/>
+<part name="P_3" library="ataradov_pwr" deviceset="V_USB" device=""/>
+<part name="C1" library="ataradov_rlc" deviceset="C" device="-0603" value="1uF"/>
+<part name="C2" library="ataradov_rlc" deviceset="C" device="-0603" value="1uF"/>
+<part name="R2" library="ataradov_rlc" deviceset="R" device="-0603" value="100"/>
+<part name="IC1" library="ataradov_vreg" deviceset="MIC5504" device="-SOT23-5" value="MIC5504-3.3"/>
+<part name="P_4" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_6" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_1" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_2" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="R7" library="ataradov_rlc" deviceset="R" device="-0603" value="470"/>
+<part name="TP1" library="ataradov_misc" deviceset="TEST-POINT" device="-1.27MM" value="SIO"/>
+<part name="TP2" library="ataradov_misc" deviceset="TEST-POINT" device="-1.27MM"/>
+<part name="TP3" library="ataradov_misc" deviceset="TEST-POINT" device="-1.27MM"/>
+<part name="TP4" library="ataradov_misc" deviceset="TEST-POINT" device="-1.27MM"/>
+<part name="LED1" library="ataradov_led" deviceset="LED_SMD" device="LED_0603" value="ORANGE"/>
+<part name="J1" library="ataradov_conn" deviceset="HEADER-5X2" device="-TH-1.27"/>
+<part name="P_11" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_5" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="J2" library="ataradov_conn" deviceset="USB-B-MICRO" device="-SMT"/>
+<part name="RN1" library="ataradov_rlc" deviceset="RN-4" device="-0603-X4" value="100"/>
+</parts>
+<sheets>
+<sheet>
+<plain>
+<frame x1="0" y1="0" x2="152.4" y2="119.38" columns="8" rows="5" layer="97"/>
+<text x="35.56" y="106.68" size="1.778" layer="97" align="bottom-center">Program</text>
+<text x="93.98" y="106.68" size="1.778" layer="97" align="bottom-center">Target</text>
+<text x="60.96" y="15.24" size="1.778" layer="97">Copyright (c) 2016-2021, Alex Taradov &lt;alex@taradov.com&gt;
+
+MCU firmware source code is available at https://github.com/ataradov/free-dap</text>
+</plain>
+<instances>
+<instance part="IC2" gate="G$1" x="40.64" y="53.34"/>
+<instance part="P_9" gate="1" x="53.34" y="27.94"/>
+<instance part="P_7" gate="1" x="58.42" y="66.04"/>
+<instance part="P_17" gate="1" x="76.2" y="40.64"/>
+<instance part="P_8" gate="1" x="58.42" y="40.64"/>
+<instance part="P_16" gate="1" x="76.2" y="60.96"/>
+<instance part="P_3" gate="1" x="25.4" y="27.94"/>
+<instance part="C1" gate="G$1" x="20.32" y="20.32" rot="R90"/>
+<instance part="C2" gate="G$1" x="53.34" y="20.32" rot="R90"/>
+<instance part="R2" gate="G$1" x="106.68" y="99.06"/>
+<instance part="IC1" gate="G$1" x="38.1" y="20.32"/>
+<instance part="P_4" gate="1" x="48.26" y="15.24"/>
+<instance part="P_6" gate="1" x="53.34" y="15.24"/>
+<instance part="P_1" gate="1" x="20.32" y="15.24"/>
+<instance part="P_2" gate="1" x="33.02" y="86.36"/>
+<instance part="R7" gate="G$1" x="114.3" y="53.34"/>
+<instance part="TP1" gate="G$1" x="35.56" y="96.52"/>
+<instance part="TP2" gate="G$1" x="35.56" y="93.98"/>
+<instance part="TP3" gate="G$1" x="35.56" y="91.44"/>
+<instance part="TP4" gate="G$1" x="35.56" y="88.9"/>
+<instance part="LED1" gate="G$1" x="124.46" y="53.34" rot="MR270"/>
+<instance part="J1" gate="G$1" x="88.9" y="91.44"/>
+<instance part="P_11" gate="1" x="78.74" y="83.82"/>
+<instance part="P_5" gate="1" x="132.08" y="48.26"/>
+<instance part="J2" gate="G$1" x="86.36" y="50.8"/>
+<instance part="RN1" gate="G$1" x="106.68" y="91.44"/>
+</instances>
+<busses>
+</busses>
+<nets>
+<net name="N$1" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA24"/>
+<wire x1="55.88" y1="48.26" x2="76.2" y2="48.26" width="0.1524" layer="91"/>
+<wire x1="76.2" y1="48.26" x2="76.2" y2="53.34" width="0.1524" layer="91"/>
+<wire x1="76.2" y1="53.34" x2="78.74" y2="53.34" width="0.1524" layer="91"/>
+<pinref part="J2" gate="G$1" pin="DM"/>
+</segment>
+</net>
+<net name="N$2" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA25"/>
+<wire x1="55.88" y1="50.8" x2="78.74" y2="50.8" width="0.1524" layer="91"/>
+<pinref part="J2" gate="G$1" pin="DP"/>
+</segment>
+</net>
+<net name="GND" class="0">
+<segment>
+<pinref part="P_17" gate="1" pin="GND"/>
+<wire x1="76.2" y1="43.18" x2="76.2" y2="45.72" width="0.1524" layer="91"/>
+<wire x1="76.2" y1="45.72" x2="78.74" y2="45.72" width="0.1524" layer="91"/>
+<pinref part="J2" gate="G$1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="IC1" gate="G$1" pin="GND"/>
+<pinref part="P_4" gate="1" pin="GND"/>
+<wire x1="48.26" y1="17.78" x2="48.26" y2="20.32" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="C1" gate="G$1" pin="1"/>
+<pinref part="P_1" gate="1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="C2" gate="G$1" pin="1"/>
+<pinref part="P_6" gate="1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="GND"/>
+<pinref part="P_8" gate="1" pin="GND"/>
+<wire x1="55.88" y1="53.34" x2="58.42" y2="53.34" width="0.1524" layer="91"/>
+<wire x1="58.42" y1="53.34" x2="58.42" y2="43.18" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="P_2" gate="1" pin="GND"/>
+<wire x1="33.02" y1="88.9" x2="35.56" y2="88.9" width="0.1524" layer="91"/>
+<pinref part="TP4" gate="G$1" pin="1"/>
+</segment>
+<segment>
+<pinref part="J1" gate="G$1" pin="3"/>
+<wire x1="81.28" y1="93.98" x2="78.74" y2="93.98" width="0.1524" layer="91"/>
+<pinref part="P_11" gate="1" pin="GND"/>
+<wire x1="78.74" y1="93.98" x2="78.74" y2="91.44" width="0.1524" layer="91"/>
+<pinref part="J1" gate="G$1" pin="5"/>
+<wire x1="78.74" y1="91.44" x2="78.74" y2="86.36" width="0.1524" layer="91"/>
+<wire x1="81.28" y1="91.44" x2="78.74" y2="91.44" width="0.1524" layer="91"/>
+<junction x="78.74" y="91.44"/>
+</segment>
+<segment>
+<pinref part="P_5" gate="1" pin="GND"/>
+<wire x1="132.08" y1="50.8" x2="132.08" y2="53.34" width="0.1524" layer="91"/>
+<wire x1="132.08" y1="53.34" x2="129.54" y2="53.34" width="0.1524" layer="91"/>
+<pinref part="LED1" gate="G$1" pin="C"/>
+</segment>
+</net>
+<net name="V_USB" class="0">
+<segment>
+<pinref part="P_16" gate="1" pin="V_USB"/>
+<wire x1="76.2" y1="58.42" x2="76.2" y2="55.88" width="0.1524" layer="91"/>
+<wire x1="76.2" y1="55.88" x2="78.74" y2="55.88" width="0.1524" layer="91"/>
+<pinref part="J2" gate="G$1" pin="VBUS"/>
+</segment>
+<segment>
+<pinref part="IC1" gate="G$1" pin="EN"/>
+<pinref part="P_3" gate="1" pin="V_USB"/>
+<wire x1="27.94" y1="20.32" x2="25.4" y2="20.32" width="0.1524" layer="91"/>
+<wire x1="25.4" y1="20.32" x2="25.4" y2="22.86" width="0.1524" layer="91"/>
+<pinref part="IC1" gate="G$1" pin="IN"/>
+<wire x1="25.4" y1="22.86" x2="25.4" y2="25.4" width="0.1524" layer="91"/>
+<wire x1="27.94" y1="22.86" x2="25.4" y2="22.86" width="0.1524" layer="91"/>
+<junction x="25.4" y="22.86"/>
+<pinref part="C1" gate="G$1" pin="2"/>
+<wire x1="25.4" y1="22.86" x2="20.32" y2="22.86" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="+3V3" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="OUT"/>
+<wire x1="48.26" y1="22.86" x2="53.34" y2="22.86" width="0.1524" layer="91"/>
+<pinref part="C2" gate="G$1" pin="2"/>
+<junction x="53.34" y="22.86"/>
+<pinref part="P_9" gate="1" pin="+3V3"/>
+<wire x1="53.34" y1="25.4" x2="53.34" y2="22.86" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="VDD"/>
+<pinref part="P_7" gate="1" pin="+3V3"/>
+<wire x1="55.88" y1="55.88" x2="58.42" y2="55.88" width="0.1524" layer="91"/>
+<wire x1="58.42" y1="55.88" x2="58.42" y2="63.5" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="SWDIO" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA31/SIO"/>
+<wire x1="55.88" y1="45.72" x2="60.96" y2="45.72" width="0.1524" layer="91"/>
+<label x="60.96" y="45.72" size="1.27" layer="95"/>
+</segment>
+<segment>
+<wire x1="35.56" y1="96.52" x2="33.02" y2="96.52" width="0.1524" layer="91"/>
+<label x="33.02" y="96.52" size="1.27" layer="95" rot="MR0"/>
+<pinref part="TP1" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="PA02" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA02"/>
+<wire x1="55.88" y1="58.42" x2="60.96" y2="58.42" width="0.1524" layer="91"/>
+<label x="60.96" y="58.42" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="PA04" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA04"/>
+<wire x1="55.88" y1="60.96" x2="60.96" y2="60.96" width="0.1524" layer="91"/>
+<label x="60.96" y="60.96" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="R7" gate="G$1" pin="1"/>
+<wire x1="109.22" y1="53.34" x2="106.68" y2="53.34" width="0.1524" layer="91"/>
+<label x="106.68" y="53.34" size="1.27" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="SWCLK" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA30/SCK"/>
+<wire x1="25.4" y1="45.72" x2="22.86" y2="45.72" width="0.1524" layer="91"/>
+<label x="22.86" y="45.72" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<label x="33.02" y="93.98" size="1.27" layer="95" rot="MR0"/>
+<wire x1="35.56" y1="93.98" x2="33.02" y2="93.98" width="0.1524" layer="91"/>
+<pinref part="TP2" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="RESET" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA28/RST"/>
+<wire x1="25.4" y1="48.26" x2="22.86" y2="48.26" width="0.1524" layer="91"/>
+<label x="22.86" y="48.26" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<label x="33.02" y="91.44" size="1.27" layer="95" rot="MR0"/>
+<wire x1="35.56" y1="91.44" x2="33.02" y2="91.44" width="0.1524" layer="91"/>
+<pinref part="TP3" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="N$5" class="0">
+<segment>
+<pinref part="J1" gate="G$1" pin="2"/>
+<pinref part="R2" gate="G$1" pin="1"/>
+<wire x1="96.52" y1="96.52" x2="99.06" y2="96.52" width="0.1524" layer="91"/>
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+<wire x1="99.06" y1="99.06" x2="101.6" y2="99.06" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="N$9" class="0">
+<segment>
+<wire x1="101.6" y1="93.98" x2="96.52" y2="93.98" width="0.1524" layer="91"/>
+<pinref part="J1" gate="G$1" pin="4"/>
+<pinref part="RN1" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="N$10" class="0">
+<segment>
+<pinref part="J1" gate="G$1" pin="6"/>
+<wire x1="96.52" y1="91.44" x2="101.6" y2="91.44" width="0.1524" layer="91"/>
+<pinref part="RN1" gate="G$1" pin="2"/>
+</segment>
+</net>
+<net name="N$11" class="0">
+<segment>
+<wire x1="101.6" y1="88.9" x2="96.52" y2="88.9" width="0.1524" layer="91"/>
+<pinref part="J1" gate="G$1" pin="8"/>
+<pinref part="RN1" gate="G$1" pin="3"/>
+</segment>
+</net>
+<net name="N$12" class="0">
+<segment>
+<pinref part="J1" gate="G$1" pin="10"/>
+<wire x1="96.52" y1="86.36" x2="101.6" y2="86.36" width="0.1524" layer="91"/>
+<pinref part="RN1" gate="G$1" pin="4"/>
+</segment>
+</net>
+<net name="PA14" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA14"/>
+<wire x1="22.86" y1="53.34" x2="25.4" y2="53.34" width="0.1524" layer="91"/>
+<label x="22.86" y="53.34" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<wire x1="114.3" y1="93.98" x2="111.76" y2="93.98" width="0.1524" layer="91"/>
+<label x="114.3" y="93.98" size="1.27" layer="95"/>
+<pinref part="RN1" gate="G$1" pin="8"/>
+</segment>
+</net>
+<net name="PA15" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA15"/>
+<wire x1="25.4" y1="50.8" x2="22.86" y2="50.8" width="0.1524" layer="91"/>
+<label x="22.86" y="50.8" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="R2" gate="G$1" pin="2"/>
+<wire x1="114.3" y1="99.06" x2="111.76" y2="99.06" width="0.1524" layer="91"/>
+<label x="114.3" y="99.06" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="N$3" class="0">
+<segment>
+<pinref part="R7" gate="G$1" pin="2"/>
+<pinref part="LED1" gate="G$1" pin="A"/>
+<wire x1="121.92" y1="53.34" x2="119.38" y2="53.34" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="PA09" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA9"/>
+<wire x1="25.4" y1="55.88" x2="22.86" y2="55.88" width="0.1524" layer="91"/>
+<label x="22.86" y="55.88" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<wire x1="114.3" y1="91.44" x2="111.76" y2="91.44" width="0.1524" layer="91"/>
+<label x="114.3" y="91.44" size="1.27" layer="95"/>
+<pinref part="RN1" gate="G$1" pin="7"/>
+</segment>
+</net>
+<net name="PA08" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA8"/>
+<wire x1="25.4" y1="58.42" x2="22.86" y2="58.42" width="0.1524" layer="91"/>
+<label x="22.86" y="58.42" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<wire x1="111.76" y1="88.9" x2="114.3" y2="88.9" width="0.1524" layer="91"/>
+<label x="114.3" y="88.9" size="1.27" layer="95"/>
+<pinref part="RN1" gate="G$1" pin="6"/>
+</segment>
+</net>
+<net name="PA05" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA5"/>
+<wire x1="25.4" y1="60.96" x2="22.86" y2="60.96" width="0.1524" layer="91"/>
+<label x="22.86" y="60.96" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
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+<label x="114.3" y="86.36" size="1.27" layer="95"/>
+<pinref part="RN1" gate="G$1" pin="5"/>
+</segment>
+</net>
+</nets>
+</sheet>
+</sheets>
+</schematic>
+</drawing>
+<compatibility>
+<note version="6.3" minversion="6.2.2" severity="warning">
+Since Version 6.2.2 text objects can contain more than one line,
+which will not be processed correctly with this version.
+</note>
+</compatibility>
+</eagle>

dap_link/lib/free-dap/hardware/d11_pogo/d11_pogo.brd

@@ -0,0 +1,599 @@
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+<wire x1="25.4" y1="0.762" x2="23.876" y2="0.762" width="0.127" layer="21"/>
+<wire x1="1.524" y1="-0.762" x2="0" y2="-0.762" width="0.127" layer="21"/>
+<wire x1="19.558" y1="-0.762" x2="5.842" y2="-0.762" width="0.127" layer="21"/>
+<wire x1="25.4" y1="-0.762" x2="23.876" y2="-0.762" width="0.127" layer="21"/>
+<wire x1="1.524" y1="0" x2="0" y2="0" width="0.127" layer="21"/>
+<wire x1="25.4" y1="0" x2="23.876" y2="0" width="0.127" layer="21"/>
+<wire x1="7.112" y1="0" x2="5.842" y2="0" width="0.127" layer="21"/>
+<wire x1="9.652" y1="0" x2="8.382" y2="0" width="0.127" layer="21"/>
+<wire x1="17.018" y1="0" x2="15.748" y2="0" width="0.127" layer="21"/>
+<wire x1="19.558" y1="0" x2="18.288" y2="0" width="0.127" layer="21"/>
+</package>
+</packages>
+</library>
+<library name="ataradov_rlc">
+<description>Alex Taradov Library (R, L and C)</description>
+<packages>
+<package name="SMD0603">
+<wire x1="-1.5" y1="0.75" x2="1.5" y2="0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="0.75" x2="1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="-0.75" x2="-1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="-1.5" y1="-0.75" x2="-1.5" y2="0.75" width="0.1" layer="21"/>
+<smd name="1" x="-0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<smd name="2" x="0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+</packages>
+</library>
+<library name="ataradov_vreg">
+<description>Alex Taradov Library (Voltage Regulators)</description>
+<packages>
+<package name="SOT23-5">
+<description>SOT23-5</description>
+<wire x1="1.422" y1="0.81" x2="1.422" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="1.422" y1="-0.81" x2="-1.422" y2="-0.81" width="0.1524" layer="51"/>
+<wire x1="-1.422" y1="-0.81" x2="-1.422" y2="0.81" width="0.1524" layer="21"/>
+<wire x1="-1.422" y1="0.81" x2="1.422" y2="0.81" width="0.1524" layer="51"/>
+<wire x1="-0.522" y1="0.81" x2="0.522" y2="0.81" width="0.1524" layer="21"/>
+<wire x1="-0.428" y1="-0.81" x2="-0.522" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="0.522" y1="-0.81" x2="0.428" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="-1.328" y1="-0.81" x2="-1.422" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="1.422" y1="-0.81" x2="1.328" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="1.328" y1="0.81" x2="1.422" y2="0.81" width="0.1524" layer="21"/>
+<wire x1="-1.422" y1="0.81" x2="-1.328" y2="0.81" width="0.1524" layer="21"/>
+<smd name="1" x="-0.95" y="-1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="2" x="0" y="-1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="3" x="0.95" y="-1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="4" x="0.95" y="1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="5" x="-0.95" y="1.3" dx="0.55" dy="1.2" layer="1"/>
+<text x="0" y="2.286" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-3.556" size="1.27" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+<rectangle x1="-1.2" y1="-1.5" x2="-0.7" y2="-0.85" layer="51"/>
+<rectangle x1="-0.25" y1="-1.5" x2="0.25" y2="-0.85" layer="51"/>
+<rectangle x1="0.7" y1="-1.5" x2="1.2" y2="-0.85" layer="51"/>
+<rectangle x1="0.7" y1="0.85" x2="1.2" y2="1.5" layer="51"/>
+<rectangle x1="-1.2" y1="0.85" x2="-0.7" y2="1.5" layer="51"/>
+</package>
+</packages>
+</library>
+<library name="ataradov_misc">
+<description>Alex Taradov Library (Miscellaneous stuff)</description>
+<packages>
+<package name="TP-1.27MM">
+<smd name="1" x="0" y="0" dx="1.27" dy="1.27" layer="1" roundness="100" cream="no"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+</packages>
+</library>
+<library name="ataradov_led">
+<description>Alex Taradov Library (LEDs and other indication devices)</description>
+<packages>
+<package name="SMD0603">
+<wire x1="-1.5" y1="0.75" x2="1.5" y2="0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="0.75" x2="1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="-0.75" x2="-1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="-1.5" y1="-0.75" x2="-1.5" y2="0.75" width="0.1" layer="21"/>
+<smd name="1" x="-0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<smd name="2" x="0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+</packages>
+</library>
+</libraries>
+<attributes>
+</attributes>
+<variantdefs>
+</variantdefs>
+<classes>
+<class number="0" name="default" width="0" drill="0">
+</class>
+</classes>
+<designrules name="std-tented-new">
+<description language="de">&lt;b&gt;EAGLE Design Rules&lt;/b&gt;
+&lt;p&gt;
+Die Standard-Design-Rules sind so gewählt, dass sie für 
+die meisten Anwendungen passen. Sollte ihre Platine 
+besondere Anforderungen haben, treffen Sie die erforderlichen
+Einstellungen hier und speichern die Design Rules unter 
+einem neuen Namen ab.</description>
+<description language="en">&lt;b&gt;Laen's PCB Order Design Rules&lt;/b&gt;
+&lt;p&gt;
+Please make sure your boards conform to these design rules.</description>
+<param name="layerSetup" value="(1*16)"/>
+<param name="mtCopper" value="0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm"/>
+<param name="mtIsolate" value="1.5011mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm"/>
+<param name="mdWireWire" value="6mil"/>
+<param name="mdWirePad" value="6mil"/>
+<param name="mdWireVia" value="6mil"/>
+<param name="mdPadPad" value="6mil"/>
+<param name="mdPadVia" value="6mil"/>
+<param name="mdViaVia" value="6mil"/>
+<param name="mdSmdPad" value="0mil"/>
+<param name="mdSmdVia" value="0mil"/>
+<param name="mdSmdSmd" value="0mil"/>
+<param name="mdViaViaSameLayer" value="8mil"/>
+<param name="mnLayersViaInSmd" value="2"/>
+<param name="mdCopperDimension" value="10mil"/>
+<param name="mdDrill" value="6mil"/>
+<param name="mdSmdStop" value="0mil"/>
+<param name="msWidth" value="8mil"/>
+<param name="msDrill" value="12mil"/>
+<param name="msMicroVia" value="12mil"/>
+<param name="msBlindViaRatio" value="0.5"/>
+<param name="rvPadTop" value="0.25"/>
+<param name="rvPadInner" value="0.25"/>
+<param name="rvPadBottom" value="0.25"/>
+<param name="rvViaOuter" value="0.25"/>
+<param name="rvViaInner" value="0.25"/>
+<param name="rvMicroViaOuter" value="0.25"/>
+<param name="rvMicroViaInner" value="0.25"/>
+<param name="rlMinPadTop" value="7mil"/>
+<param name="rlMaxPadTop" value="20mil"/>
+<param name="rlMinPadInner" value="7mil"/>
+<param name="rlMaxPadInner" value="20mil"/>
+<param name="rlMinPadBottom" value="7mil"/>
+<param name="rlMaxPadBottom" value="20mil"/>
+<param name="rlMinViaOuter" value="7mil"/>
+<param name="rlMaxViaOuter" value="20mil"/>
+<param name="rlMinViaInner" value="7mil"/>
+<param name="rlMaxViaInner" value="20mil"/>
+<param name="rlMinMicroViaOuter" value="4mil"/>
+<param name="rlMaxMicroViaOuter" value="20mil"/>
+<param name="rlMinMicroViaInner" value="4mil"/>
+<param name="rlMaxMicroViaInner" value="20mil"/>
+<param name="psTop" value="-1"/>
+<param name="psBottom" value="-1"/>
+<param name="psFirst" value="-1"/>
+<param name="psElongationLong" value="100"/>
+<param name="psElongationOffset" value="100"/>
+<param name="mvStopFrame" value="1"/>
+<param name="mvCreamFrame" value="0"/>
+<param name="mlMinStopFrame" value="3mil"/>
+<param name="mlMaxStopFrame" value="3mil"/>
+<param name="mlMinCreamFrame" value="0mil"/>
+<param name="mlMaxCreamFrame" value="0mil"/>
+<param name="mlViaStopLimit" value="25mil"/>
+<param name="srRoundness" value="0"/>
+<param name="srMinRoundness" value="0mil"/>
+<param name="srMaxRoundness" value="0mil"/>
+<param name="slThermalIsolate" value="6mil"/>
+<param name="slThermalsForVias" value="0"/>
+<param name="dpMaxLengthDifference" value="10mm"/>
+<param name="dpGapFactor" value="2.5"/>
+<param name="checkGrid" value="0"/>
+<param name="checkAngle" value="0"/>
+<param name="checkFont" value="1"/>
+<param name="checkRestrict" value="1"/>
+<param name="useDiameter" value="13"/>
+<param name="maxErrors" value="50"/>
+</designrules>
+<autorouter>
+<pass name="Default">
+<param name="RoutingGrid" value="50mil"/>
+<param name="AutoGrid" value="1"/>
+<param name="Efforts" value="0"/>
+<param name="TopRouterVariant" value="1"/>
+<param name="tpViaShape" value="round"/>
+<param name="PrefDir.1" value="a"/>
+<param name="PrefDir.2" value="0"/>
+<param name="PrefDir.3" value="0"/>
+<param name="PrefDir.4" value="0"/>
+<param name="PrefDir.5" value="0"/>
+<param name="PrefDir.6" value="0"/>
+<param name="PrefDir.7" value="0"/>
+<param name="PrefDir.8" value="0"/>
+<param name="PrefDir.9" value="0"/>
+<param name="PrefDir.10" value="0"/>
+<param name="PrefDir.11" value="0"/>
+<param name="PrefDir.12" value="0"/>
+<param name="PrefDir.13" value="0"/>
+<param name="PrefDir.14" value="0"/>
+<param name="PrefDir.15" value="0"/>
+<param name="PrefDir.16" value="a"/>
+<param name="cfVia" value="8"/>
+<param name="cfNonPref" value="5"/>
+<param name="cfChangeDir" value="2"/>
+<param name="cfOrthStep" value="2"/>
+<param name="cfDiagStep" value="3"/>
+<param name="cfExtdStep" value="0"/>
+<param name="cfBonusStep" value="1"/>
+<param name="cfMalusStep" value="1"/>
+<param name="cfPadImpact" value="4"/>
+<param name="cfSmdImpact" value="4"/>
+<param name="cfBusImpact" value="0"/>
+<param name="cfHugging" value="3"/>
+<param name="cfAvoid" value="4"/>
+<param name="cfPolygon" value="10"/>
+<param name="cfBase.1" value="0"/>
+<param name="cfBase.2" value="1"/>
+<param name="cfBase.3" value="1"/>
+<param name="cfBase.4" value="1"/>
+<param name="cfBase.5" value="1"/>
+<param name="cfBase.6" value="1"/>
+<param name="cfBase.7" value="1"/>
+<param name="cfBase.8" value="1"/>
+<param name="cfBase.9" value="1"/>
+<param name="cfBase.10" value="1"/>
+<param name="cfBase.11" value="1"/>
+<param name="cfBase.12" value="1"/>
+<param name="cfBase.13" value="1"/>
+<param name="cfBase.14" value="1"/>
+<param name="cfBase.15" value="1"/>
+<param name="cfBase.16" value="0"/>
+<param name="mnVias" value="20"/>
+<param name="mnSegments" value="9999"/>
+<param name="mnExtdSteps" value="9999"/>
+<param name="mnRipupLevel" value="10"/>
+<param name="mnRipupSteps" value="100"/>
+<param name="mnRipupTotal" value="100"/>
+</pass>
+<pass name="Follow-me" refer="Default" active="yes">
+</pass>
+<pass name="Busses" refer="Default" active="yes">
+<param name="cfNonPref" value="4"/>
+<param name="cfBusImpact" value="4"/>
+<param name="cfHugging" value="0"/>
+<param name="mnVias" value="0"/>
+</pass>
+<pass name="Route" refer="Default" active="yes">
+</pass>
+<pass name="Optimize1" refer="Default" active="yes">
+<param name="cfVia" value="99"/>
+<param name="cfExtdStep" value="10"/>
+<param name="cfHugging" value="1"/>
+<param name="mnExtdSteps" value="1"/>
+<param name="mnRipupLevel" value="0"/>
+</pass>
+<pass name="Optimize2" refer="Optimize1" active="yes">
+<param name="cfNonPref" value="0"/>
+<param name="cfChangeDir" value="6"/>
+<param name="cfExtdStep" value="0"/>
+<param name="cfBonusStep" value="2"/>
+<param name="cfMalusStep" value="2"/>
+<param name="cfPadImpact" value="2"/>
+<param name="cfSmdImpact" value="2"/>
+<param name="cfHugging" value="0"/>
+</pass>
+<pass name="Optimize3" refer="Optimize2" active="yes">
+<param name="cfChangeDir" value="8"/>
+<param name="cfPadImpact" value="0"/>
+<param name="cfSmdImpact" value="0"/>
+</pass>
+<pass name="Optimize4" refer="Optimize3" active="yes">
+<param name="cfChangeDir" value="25"/>
+</pass>
+</autorouter>
+<elements>
+<element name="IC2" library="ataradov_mcu" package="SO-14" value="ATSAMD11C" x="10.922" y="6.35" smashed="yes" rot="MR270">
+<attribute name="NAME" x="10.922" y="11.176" size="1.27" layer="26" font="vector" rot="MR0" align="bottom-center"/>
+</element>
+<element name="C1" library="ataradov_rlc" package="SMD0603" value="1uF" x="2.032" y="3.556" rot="MR180"/>
+<element name="C2" library="ataradov_rlc" package="SMD0603" value="1uF" x="4.318" y="5.588" smashed="yes" rot="MR90">
+<attribute name="NAME" x="5.334" y="5.588" size="1.27" layer="26" font="vector" rot="MR90" align="bottom-center"/>
+</element>
+<element name="IC1" library="ataradov_vreg" package="SOT23-5" value="MIC5504-3.3" x="2.032" y="6.35" smashed="yes" rot="MR0">
+<attribute name="NAME" x="2.032" y="8.636" size="1.27" layer="26" font="vector" rot="MR0" align="bottom-center"/>
+</element>
+<element name="R1" library="ataradov_rlc" package="SMD0603" value="10K" x="4.826" y="10.16" rot="MR0"/>
+<element name="TP3" library="ataradov_misc" package="TP-1.27MM" value="SIO" x="8.382" y="1.524" rot="MR0"/>
+<element name="TP1" library="ataradov_misc" package="TP-1.27MM" value="" x="13.462" y="1.524" rot="MR0"/>
+<element name="TP2" library="ataradov_misc" package="TP-1.27MM" value="" x="10.922" y="1.524" rot="MR0"/>
+<element name="TP4" library="ataradov_misc" package="TP-1.27MM" value="" x="5.842" y="1.524" rot="MR0"/>
+<element name="LED1" library="ataradov_led" package="SMD0603" value="ORANGE" x="4.826" y="10.16"/>
+<element name="J1" library="ataradov_conn" package="USB-B-MICRO-SMT-SHELL-TH" value="" x="0" y="5.588"/>
+<element name="J4" library="ataradov_conn" package="POGO-PIN" value="POGO-PIN-SMD" x="31.75" y="6.858" rot="R180"/>
+<element name="J2" library="ataradov_conn" package="POGO-PIN" value="POGO-PIN-SMD" x="31.75" y="1.778" rot="R180"/>
+<element name="J3" library="ataradov_conn" package="POGO-PIN" value="POGO-PIN-SMD" x="31.75" y="4.318" rot="R180"/>
+<element name="J5" library="ataradov_conn" package="POGO-PIN" value="POGO-PIN-SMD" x="31.75" y="9.398" rot="R180"/>
+</elements>
+<signals>
+<signal name="GND">
+<contactref element="IC1" pad="2"/>
+<contactref element="C1" pad="1"/>
+<contactref element="C2" pad="1"/>
+<contactref element="IC2" pad="11"/>
+<contactref element="TP4" pad="1"/>
+<contactref element="LED1" pad="2"/>
+<contactref element="J1" pad="5"/>
+<polygon width="0.254" layer="16" isolate="0.2032">
+<vertex x="0" y="11.176"/>
+<vertex x="31.75" y="11.176"/>
+<vertex x="31.75" y="0"/>
+<vertex x="0" y="0"/>
+</polygon>
+<polygon width="0.254" layer="1" isolate="0.2032">
+<vertex x="0" y="11.176"/>
+<vertex x="31.75" y="11.176"/>
+<vertex x="31.75" y="0"/>
+<vertex x="0" y="0"/>
+</polygon>
+<via x="6.604" y="8.382" extent="1-16" drill="0.3302" diameter="0.254"/>
+<via x="3.81" y="8.89" extent="1-16" drill="0.3302" diameter="0.254"/>
+<via x="20.574" y="8.128" extent="1-16" drill="0.3302" diameter="0.254"/>
+<via x="25.146" y="8.128" extent="1-16" drill="0.3302" diameter="0.254"/>
+<via x="25.146" y="5.588" extent="1-16" drill="0.3302" diameter="0.254"/>
+<via x="30.734" y="8.128" extent="1-16" drill="0.3302" diameter="0.254"/>
+<via x="30.734" y="5.588" extent="1-16" drill="0.3302" diameter="0.254"/>
+<via x="30.734" y="3.048" extent="1-16" drill="0.3302" diameter="0.254"/>
+<via x="25.146" y="3.048" extent="1-16" drill="0.3302" diameter="0.254"/>
+<via x="20.574" y="3.048" extent="1-16" drill="0.3302" diameter="0.254"/>
+<via x="20.574" y="5.588" extent="1-16" drill="0.3302" diameter="0.254"/>
+<contactref element="J5" pad="2" route="any" routetag="G$1.1"/>
+<contactref element="J5" pad="1" route="any" routetag="G$1.1"/>
+<via x="1.016" y="10.16" extent="1-16" drill="0.3302" diameter="0.254"/>
+<via x="1.016" y="1.016" extent="1-16" drill="0.3302" diameter="0.254"/>
+<via x="2.032" y="6.858" extent="1-16" drill="0.3302" diameter="0.254"/>
+<via x="3.81" y="2.286" extent="1-16" drill="0.3302" diameter="0.254"/>
+<via x="15.24" y="3.556" extent="1-16" drill="0.3302" diameter="0.254"/>
+<via x="15.24" y="8.128" extent="1-16" drill="0.3302" diameter="0.254"/>
+<via x="6.604" y="3.048" extent="1-16" drill="0.3302" diameter="0.254"/>
+</signal>
+<signal name="N$1">
+<contactref element="IC2" pad="9"/>
+<contactref element="J1" pad="2"/>
+<via x="6.096" y="6.35" extent="1-16" drill="0.3302" diameter="0.254"/>
+<wire x1="6.096" y1="6.35" x2="5.984" y2="6.238" width="0.254" layer="1"/>
+<wire x1="5.984" y1="6.238" x2="4.825" y2="6.238" width="0.254" layer="1"/>
+<wire x1="7.112" y1="3.81" x2="8.322" y2="3.81" width="0.254" layer="16"/>
+<wire x1="6.096" y1="6.35" x2="6.096" y2="4.826" width="0.254" layer="16"/>
+<wire x1="6.096" y1="4.826" x2="7.112" y2="3.81" width="0.254" layer="16"/>
+</signal>
+<signal name="N$2">
+<contactref element="IC2" pad="10"/>
+<contactref element="J1" pad="3"/>
+<via x="6.858" y="5.588" extent="1-16" drill="0.3302" diameter="0.254"/>
+<wire x1="4.825" y1="5.588" x2="6.858" y2="5.588" width="0.254" layer="1"/>
+<wire x1="6.858" y1="5.588" x2="6.858" y2="5.334" width="0.254" layer="16"/>
+<wire x1="6.858" y1="5.334" x2="7.112" y2="5.08" width="0.254" layer="16"/>
+<wire x1="7.112" y1="5.08" x2="8.322" y2="5.08" width="0.254" layer="16"/>
+</signal>
+<signal name="V_USB">
+<contactref element="IC1" pad="3"/>
+<contactref element="IC1" pad="1"/>
+<contactref element="C1" pad="2"/>
+<contactref element="J1" pad="1"/>
+<wire x1="4.825" y1="6.888" x2="3.84" y2="6.888" width="0.254" layer="1"/>
+<wire x1="3.84" y1="6.888" x2="3.048" y2="6.096" width="0.254" layer="1"/>
+<via x="3.048" y="6.096" extent="1-16" drill="0.3302"/>
+<wire x1="2.982" y1="6.03" x2="2.982" y2="5.05" width="0.254" layer="16"/>
+<wire x1="3.048" y1="6.096" x2="1.27" y2="6.096" width="0.254" layer="16"/>
+<wire x1="1.27" y1="6.096" x2="1.082" y2="5.908" width="0.254" layer="16"/>
+<wire x1="1.082" y1="5.908" x2="1.082" y2="5.05" width="0.254" layer="16"/>
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+<wire x1="2.982" y1="3.706" x2="2.982" y2="5.05" width="0.254" layer="16"/>
+<wire x1="2.982" y1="6.03" x2="3.048" y2="6.096" width="0.254" layer="16"/>
+</signal>
+<signal name="+3V3">
+<contactref element="IC1" pad="5"/>
+<contactref element="C2" pad="2"/>
+<contactref element="IC2" pad="12"/>
+<wire x1="8.322" y1="7.62" x2="7.112" y2="7.62" width="0.254" layer="16"/>
+<wire x1="7.112" y1="7.62" x2="6.604" y2="7.112" width="0.254" layer="16"/>
+<wire x1="6.604" y1="7.112" x2="4.318" y2="7.112" width="0.254" layer="16"/>
+<wire x1="4.318" y1="7.112" x2="4.064" y2="7.112" width="0.254" layer="16"/>
+<wire x1="4.318" y1="6.388" x2="4.318" y2="7.112" width="0.254" layer="16"/>
+<wire x1="4.064" y1="7.112" x2="3.526" y2="7.65" width="0.254" layer="16"/>
+<wire x1="3.526" y1="7.65" x2="2.982" y2="7.65" width="0.254" layer="16"/>
+</signal>
+<signal name="SWDIO">
+<contactref element="IC2" pad="8"/>
+<contactref element="TP3" pad="1"/>
+<wire x1="8.322" y1="2.54" x2="8.382" y2="2.48" width="0.254" layer="16"/>
+<wire x1="8.382" y1="2.48" x2="8.382" y2="1.524" width="0.254" layer="16"/>
+</signal>
+<signal name="LED">
+<contactref element="IC2" pad="14"/>
+<contactref element="R1" pad="1"/>
+<wire x1="8.322" y1="10.16" x2="5.626" y2="10.16" width="0.254" layer="16"/>
+</signal>
+<signal name="SWCLK">
+<contactref element="IC2" pad="7"/>
+<contactref element="TP1" pad="1"/>
+<wire x1="13.522" y1="2.54" x2="13.462" y2="2.48" width="0.254" layer="16"/>
+<wire x1="13.462" y1="2.48" x2="13.462" y2="1.524" width="0.254" layer="16"/>
+</signal>
+<signal name="RESET">
+<contactref element="IC2" pad="6"/>
+<contactref element="TP2" pad="1"/>
+<wire x1="13.522" y1="3.81" x2="12.192" y2="3.81" width="0.254" layer="16"/>
+<wire x1="12.192" y1="3.81" x2="10.922" y2="2.54" width="0.254" layer="16"/>
+<wire x1="10.922" y1="2.54" x2="10.922" y2="1.524" width="0.254" layer="16"/>
+</signal>
+<signal name="N$8">
+</signal>
+<signal name="T_SWCLK">
+<contactref element="IC2" pad="4"/>
+<contactref element="J2" pad="2" route="any" routetag="G$1.1"/>
+<contactref element="J2" pad="1" route="any" routetag="G$1.1"/>
+<via x="16.256" y="3.048" extent="1-16" drill="0.3302"/>
+<wire x1="15.494" y1="6.35" x2="13.522" y2="6.35" width="0.254" layer="16"/>
+<wire x1="10.033" y1="1.778" x2="14.986" y2="1.778" width="0.254" layer="1"/>
+<wire x1="14.986" y1="1.778" x2="16.256" y2="3.048" width="0.254" layer="1"/>
+<wire x1="15.494" y1="6.35" x2="16.256" y2="5.588" width="0.254" layer="16"/>
+<wire x1="16.256" y1="5.588" x2="16.256" y2="3.048" width="0.254" layer="16"/>
+</signal>
+<signal name="T_SWDIO">
+<contactref element="IC2" pad="5"/>
+<contactref element="J4" pad="2" route="any" routetag="G$1.1"/>
+<contactref element="J4" pad="1" route="any" routetag="G$1.1"/>
+<via x="14.986" y="5.588" extent="1-16" drill="0.3302"/>
+<wire x1="10.033" y1="6.858" x2="13.97" y2="6.858" width="0.254" layer="1"/>
+<wire x1="13.97" y1="6.858" x2="14.986" y2="5.588" width="0.254" layer="1"/>
+<wire x1="13.522" y1="5.08" x2="14.732" y2="5.08" width="0.254" layer="16"/>
+<wire x1="14.732" y1="5.08" x2="14.986" y2="5.334" width="0.254" layer="16"/>
+<wire x1="14.986" y1="5.334" x2="14.986" y2="5.588" width="0.254" layer="16"/>
+</signal>
+<signal name="N$3">
+<contactref element="R1" pad="2"/>
+<contactref element="LED1" pad="1"/>
+<via x="3.048" y="10.414" extent="1-16" drill="0.3302"/>
+<wire x1="4.026" y1="10.16" x2="3.302" y2="10.16" width="0.254" layer="16"/>
+<wire x1="3.302" y1="10.16" x2="3.048" y2="10.414" width="0.254" layer="16"/>
+<wire x1="3.048" y1="10.414" x2="3.302" y2="10.16" width="0.254" layer="1"/>
+<wire x1="3.302" y1="10.16" x2="4.026" y2="10.16" width="0.254" layer="1"/>
+</signal>
+<signal name="T_RESET">
+<contactref element="IC2" pad="1"/>
+<contactref element="J3" pad="2" route="any" routetag="G$1.1"/>
+<contactref element="J3" pad="1" route="any" routetag="G$1.1"/>
+<via x="16.256" y="9.144" extent="1-16" drill="0.3302"/>
+<wire x1="15.24" y1="10.16" x2="13.522" y2="10.16" width="0.254" layer="16"/>
+<wire x1="10.033" y1="4.318" x2="15.494" y2="4.318" width="0.254" layer="1"/>
+<wire x1="15.494" y1="4.318" x2="16.256" y2="5.08" width="0.254" layer="1"/>
+<wire x1="16.256" y1="5.08" x2="16.256" y2="9.144" width="0.254" layer="1"/>
+<wire x1="15.24" y1="10.16" x2="16.256" y2="9.144" width="0.254" layer="16"/>
+</signal>
+</signals>
+</board>
+</drawing>
+</eagle>

dap_link/lib/free-dap/hardware/d11_pogo/d11_pogo.sch

@@ -0,0 +1,1064 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="7.3.0">
+<drawing>
+<settings>
+<setting alwaysvectorfont="no"/>
+<setting verticaltext="up"/>
+</settings>
+<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>
+<layers>
+<layer number="1" name="Top" color="4" fill="1" visible="no" active="no"/>
+<layer number="16" name="Bottom" color="1" fill="1" visible="no" active="no"/>
+<layer number="17" name="Pads" color="2" fill="1" visible="no" active="no"/>
+<layer number="18" name="Vias" color="2" fill="1" visible="no" active="no"/>
+<layer number="19" name="Unrouted" color="6" fill="1" visible="no" active="no"/>
+<layer number="20" name="Dimension" color="15" fill="1" visible="no" active="no"/>
+<layer number="21" name="tPlace" color="7" fill="1" visible="no" active="no"/>
+<layer number="22" name="bPlace" color="7" fill="1" visible="no" active="no"/>
+<layer number="23" name="tOrigins" color="15" fill="1" visible="no" active="no"/>
+<layer number="24" name="bOrigins" color="15" fill="1" visible="no" active="no"/>
+<layer number="25" name="tNames" color="7" fill="1" visible="no" active="no"/>
+<layer number="26" name="bNames" color="7" fill="1" visible="no" active="no"/>
+<layer number="27" name="tValues" color="7" fill="1" visible="no" active="no"/>
+<layer number="28" name="bValues" color="7" fill="1" visible="no" active="no"/>
+<layer number="29" name="tStop" color="7" fill="3" visible="no" active="no"/>
+<layer number="30" name="bStop" color="7" fill="6" visible="no" active="no"/>
+<layer number="31" name="tCream" color="7" fill="4" visible="no" active="no"/>
+<layer number="32" name="bCream" color="7" fill="5" visible="no" active="no"/>
+<layer number="33" name="tFinish" color="6" fill="3" visible="no" active="no"/>
+<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="no"/>
+<layer number="35" name="tGlue" color="7" fill="4" visible="no" active="no"/>
+<layer number="36" name="bGlue" color="7" fill="5" visible="no" active="no"/>
+<layer number="37" name="tTest" color="7" fill="1" visible="no" active="no"/>
+<layer number="38" name="bTest" color="7" fill="1" visible="no" active="no"/>
+<layer number="39" name="tKeepout" color="4" fill="11" visible="no" active="no"/>
+<layer number="40" name="bKeepout" color="1" fill="11" visible="no" active="no"/>
+<layer number="41" name="tRestrict" color="4" fill="10" visible="no" active="no"/>
+<layer number="42" name="bRestrict" color="1" fill="10" visible="no" active="no"/>
+<layer number="43" name="vRestrict" color="2" fill="10" visible="no" active="no"/>
+<layer number="44" name="Drills" color="7" fill="1" visible="no" active="no"/>
+<layer number="45" name="Holes" color="7" fill="1" visible="no" active="no"/>
+<layer number="46" name="Milling" color="3" fill="1" visible="no" active="no"/>
+<layer number="47" name="Measures" color="7" fill="1" visible="no" active="no"/>
+<layer number="48" name="Document" color="7" fill="1" visible="no" active="no"/>
+<layer number="49" name="Reference" color="7" fill="1" visible="no" active="no"/>
+<layer number="51" name="tDocu" color="6" fill="1" visible="no" active="no"/>
+<layer number="52" name="bDocu" color="7" fill="1" visible="no" active="no"/>
+<layer number="90" name="Modules" color="5" fill="1" visible="yes" active="yes"/>
+<layer number="91" name="Nets" color="2" fill="1" visible="yes" active="yes"/>
+<layer number="92" name="Busses" color="1" fill="1" visible="yes" active="yes"/>
+<layer number="93" name="Pins" color="2" fill="1" visible="no" active="yes"/>
+<layer number="94" name="Symbols" color="4" fill="1" visible="yes" active="yes"/>
+<layer number="95" name="Names" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="96" name="Values" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="97" name="Info" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/>
+</layers>
+<schematic xreflabel="%F%N/%S.%C%R" xrefpart="/%S.%C%R">
+<libraries>
+<library name="ataradov_mcu">
+<description>Alex Taradov Library (MCUs)</description>
+<packages>
+<package name="SO-14">
+<description>SO-14</description>
+<wire x1="4.318" y1="-1.143" x2="-3.175" y2="-1.143" width="0.127" layer="21"/>
+<wire x1="-3.175" y1="-1.143" x2="-4.318" y2="-1.143" width="0.127" layer="21"/>
+<wire x1="-4.318" y1="-1.143" x2="-4.318" y2="0" width="0.127" layer="21"/>
+<wire x1="-4.318" y1="0" x2="-4.318" y2="1.143" width="0.127" layer="21"/>
+<wire x1="4.318" y1="1.143" x2="4.318" y2="-1.143" width="0.127" layer="21"/>
+<wire x1="-4.318" y1="1.143" x2="4.318" y2="1.143" width="0.127" layer="21"/>
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+<smd name="1" x="-3.81" y="-2.6" dx="0.6" dy="2.2" layer="1"/>
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+<smd name="8" x="3.81" y="2.6" dx="0.6" dy="2.2" layer="1"/>
+<text x="0" y="-0.635" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<wire x1="-4.318" y1="0" x2="-3.175" y2="-1.143" width="0.127" layer="21"/>
+<circle x="-4.699" y="-1.524" radius="0.127" width="0.254" layer="21"/>
+</package>
+</packages>
+<symbols>
+<symbol name="ATSAMDXXC">
+<description>Atmel SAM D09C/D10C/D11C Cortex-M0+ microcontroller</description>
+<wire x1="-12.7" y1="10.16" x2="12.7" y2="10.16" width="0.254" layer="94"/>
+<wire x1="12.7" y1="10.16" x2="12.7" y2="-10.16" width="0.254" layer="94"/>
+<wire x1="12.7" y1="-10.16" x2="-12.7" y2="-10.16" width="0.254" layer="94"/>
+<wire x1="-12.7" y1="-10.16" x2="-12.7" y2="10.16" width="0.254" layer="94"/>
+<pin name="PA28/RST" x="-17.78" y="-5.08" length="middle"/>
+<pin name="PA8" x="-17.78" y="5.08" length="middle"/>
+<pin name="PA9" x="-17.78" y="2.54" length="middle"/>
+<pin name="PA14" x="-17.78" y="0" length="middle"/>
+<pin name="PA15" x="-17.78" y="-2.54" length="middle"/>
+<pin name="PA5" x="-17.78" y="7.62" length="middle"/>
+<pin name="PA04" x="17.78" y="7.62" length="middle" rot="R180"/>
+<pin name="PA02" x="17.78" y="5.08" length="middle" rot="R180"/>
+<text x="0" y="10.922" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-12.192" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+<pin name="PA30/SCK" x="-17.78" y="-7.62" length="middle"/>
+<pin name="VDD" x="17.78" y="2.54" length="middle" rot="R180"/>
+<pin name="GND" x="17.78" y="0" length="middle" rot="R180"/>
+<pin name="PA25" x="17.78" y="-2.54" length="middle" rot="R180"/>
+<pin name="PA24" x="17.78" y="-5.08" length="middle" rot="R180"/>
+<pin name="PA31/SIO" x="17.78" y="-7.62" length="middle" rot="R180"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="ATSAMD11C" prefix="IC">
+<gates>
+<gate name="G$1" symbol="ATSAMDXXC" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="SO-14">
+<connects>
+<connect gate="G$1" pin="GND" pad="11"/>
+<connect gate="G$1" pin="PA02" pad="13"/>
+<connect gate="G$1" pin="PA04" pad="14"/>
+<connect gate="G$1" pin="PA14" pad="4"/>
+<connect gate="G$1" pin="PA15" pad="5"/>
+<connect gate="G$1" pin="PA24" pad="9"/>
+<connect gate="G$1" pin="PA25" pad="10"/>
+<connect gate="G$1" pin="PA28/RST" pad="6"/>
+<connect gate="G$1" pin="PA30/SCK" pad="7"/>
+<connect gate="G$1" pin="PA31/SIO" pad="8"/>
+<connect gate="G$1" pin="PA5" pad="1"/>
+<connect gate="G$1" pin="PA8" pad="2"/>
+<connect gate="G$1" pin="PA9" pad="3"/>
+<connect gate="G$1" pin="VDD" pad="12"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_pwr">
+<description>Alex Taradov Library (Power Symbols)</description>
+<packages>
+</packages>
+<symbols>
+<symbol name="+3V3">
+<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/>
+<text x="0" y="0.762" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+<pin name="+3V3" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/>
+</symbol>
+<symbol name="GND">
+<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/>
+<text x="0" y="-2.032" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+<pin name="GND" x="0" y="2.54" visible="off" length="short" direction="sup" rot="R270"/>
+</symbol>
+<symbol name="V_USB">
+<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/>
+<text x="0" y="0.762" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+<pin name="V_USB" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="+3V3" prefix="P_">
+<gates>
+<gate name="1" symbol="+3V3" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="GND" prefix="P_">
+<gates>
+<gate name="1" symbol="GND" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="V_USB" prefix="P_">
+<gates>
+<gate name="1" symbol="V_USB" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_conn">
+<description>Alex Taradov Library (Connectors)</description>
+<packages>
+<package name="USB-B-MICRO-SMT-SHELL-TH">
+<pad name="M1" x="2.15" y="-3.6" drill="1.143"/>
+<pad name="M2" x="2.15" y="3.6" drill="1.143"/>
+<smd name="1" x="4.825" y="1.3" dx="1.35" dy="0.4" layer="1" stop="no"/>
+<smd name="2" x="4.825" y="0.65" dx="1.35" dy="0.4" layer="1" stop="no"/>
+<smd name="3" x="4.825" y="0" dx="1.35" dy="0.4" layer="1" stop="no"/>
+<smd name="4" x="4.825" y="-0.65" dx="1.35" dy="0.4" layer="1" stop="no"/>
+<smd name="5" x="4.825" y="-1.3" dx="1.35" dy="0.4" layer="1" stop="no"/>
+<text x="3.175" y="0" size="1.27" layer="25" font="vector" rot="R90" align="bottom-center">&gt;NAME</text>
+<rectangle x1="4.1" y1="1.05" x2="5.55" y2="1.55" layer="29"/>
+<pad name="M3" x="5.05" y="2.425" drill="0.635" shape="long"/>
+<pad name="M4" x="5.05" y="-2.425" drill="0.635" shape="long"/>
+<rectangle x1="4.1" y1="0.4" x2="5.55" y2="0.9" layer="29"/>
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+<wire x1="-0.5" y1="4" x2="0" y2="3.75" width="0.1524" layer="21"/>
+<wire x1="0" y1="3.75" x2="5" y2="3.75" width="0.1524" layer="21"/>
+<wire x1="5" y1="3.75" x2="5" y2="3.16" width="0.1524" layer="21"/>
+</package>
+<package name="POGO-PIN">
+<text x="12.7" y="-0.635" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<wire x1="25.4" y1="0.762" x2="25.4" y2="0" width="0.127" layer="21"/>
+<wire x1="25.4" y1="0" x2="25.4" y2="-0.762" width="0.127" layer="21"/>
+<smd name="2" x="21.717" y="0" dx="3.81" dy="2.032" layer="1"/>
+<smd name="1" x="3.683" y="0" dx="3.81" dy="2.032" layer="1"/>
+<wire x1="0" y1="-0.762" x2="0" y2="0" width="0.127" layer="21"/>
+<wire x1="0" y1="0" x2="0" y2="0.762" width="0.127" layer="21"/>
+<wire x1="19.558" y1="0.762" x2="5.842" y2="0.762" width="0.127" layer="21"/>
+<wire x1="1.524" y1="0.762" x2="0" y2="0.762" width="0.127" layer="21"/>
+<wire x1="25.4" y1="0.762" x2="23.876" y2="0.762" width="0.127" layer="21"/>
+<wire x1="1.524" y1="-0.762" x2="0" y2="-0.762" width="0.127" layer="21"/>
+<wire x1="19.558" y1="-0.762" x2="5.842" y2="-0.762" width="0.127" layer="21"/>
+<wire x1="25.4" y1="-0.762" x2="23.876" y2="-0.762" width="0.127" layer="21"/>
+<wire x1="1.524" y1="0" x2="0" y2="0" width="0.127" layer="21"/>
+<wire x1="25.4" y1="0" x2="23.876" y2="0" width="0.127" layer="21"/>
+<wire x1="7.112" y1="0" x2="5.842" y2="0" width="0.127" layer="21"/>
+<wire x1="9.652" y1="0" x2="8.382" y2="0" width="0.127" layer="21"/>
+<wire x1="17.018" y1="0" x2="15.748" y2="0" width="0.127" layer="21"/>
+<wire x1="19.558" y1="0" x2="18.288" y2="0" width="0.127" layer="21"/>
+</package>
+</packages>
+<symbols>
+<symbol name="MICRO-USB-5">
+<wire x1="-5.08" y1="7.62" x2="-5.08" y2="-10.16" width="0.254" layer="94"/>
+<text x="0.762" y="8.382" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<pin name="VBUS" x="-7.62" y="5.08" visible="pin" length="short" direction="pas"/>
+<pin name="DM" x="-7.62" y="2.54" visible="pin" length="short" direction="pas"/>
+<pin name="DP" x="-7.62" y="0" visible="pin" length="short" direction="pas"/>
+<pin name="ID" x="-7.62" y="-2.54" visible="pin" length="short" direction="pas"/>
+<pin name="GND" x="-7.62" y="-5.08" visible="pin" length="short" direction="pas"/>
+<wire x1="7.62" y1="7.62" x2="7.62" y2="-10.16" width="0.254" layer="94"/>
+<wire x1="-5.08" y1="7.62" x2="7.62" y2="7.62" width="0.254" layer="94"/>
+<wire x1="-5.08" y1="-10.16" x2="7.62" y2="-10.16" width="0.254" layer="94"/>
+<pin name="SHIELD" x="-7.62" y="-7.62" visible="pin" length="short" direction="pas"/>
+<text x="0.762" y="-12.192" size="1.27" layer="95" align="bottom-center">&gt;VALUE</text>
+</symbol>
+<symbol name="POGO-PIN">
+<wire x1="0" y1="0.254" x2="4.064" y2="0.254" width="0.254" layer="94"/>
+<wire x1="4.064" y1="0.254" x2="4.318" y2="0" width="0.254" layer="94"/>
+<pin name="1" x="-2.54" y="0" visible="off" length="short" direction="pas" swaplevel="1"/>
+<text x="6.096" y="-0.508" size="1.27" layer="95">&gt;NAME</text>
+<wire x1="4.318" y1="0" x2="4.064" y2="-0.254" width="0.254" layer="94"/>
+<wire x1="0" y1="-0.254" x2="4.064" y2="-0.254" width="0.254" layer="94"/>
+<wire x1="0" y1="0.254" x2="0" y2="-0.254" width="0.254" layer="94"/>
+<wire x1="4.318" y1="0" x2="5.588" y2="0" width="0.254" layer="94"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="USB-B-MICRO" prefix="J" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="MICRO-USB-5" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-SMT" package="USB-B-MICRO-SMT-SHELL-TH">
+<connects>
+<connect gate="G$1" pin="DM" pad="2"/>
+<connect gate="G$1" pin="DP" pad="3"/>
+<connect gate="G$1" pin="GND" pad="5"/>
+<connect gate="G$1" pin="ID" pad="4"/>
+<connect gate="G$1" pin="SHIELD" pad="M1 M2 M3 M4" route="any"/>
+<connect gate="G$1" pin="VBUS" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="POGO-PIN" prefix="J">
+<gates>
+<gate name="G$1" symbol="POGO-PIN" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-SMD" package="POGO-PIN">
+<connects>
+<connect gate="G$1" pin="1" pad="1 2" route="any"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_rlc">
+<description>Alex Taradov Library (R, L and C)</description>
+<packages>
+<package name="SMD0508">
+<wire x1="-1" y1="1.25" x2="1" y2="1.25" width="0.1" layer="21"/>
+<wire x1="1" y1="1.25" x2="1" y2="-1.25" width="0.1" layer="21"/>
+<wire x1="1" y1="-1.25" x2="-1" y2="-1.25" width="0.1" layer="21"/>
+<wire x1="-1" y1="-1.25" x2="-1" y2="1.25" width="0.1" layer="21"/>
+<smd name="1" x="-0.5" y="0" dx="2" dy="0.5" layer="1" rot="R90"/>
+<smd name="2" x="0.5" y="0" dx="2" dy="0.5" layer="1" rot="R90"/>
+<text x="0" y="1.524" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SMD0603">
+<wire x1="-1.5" y1="0.75" x2="1.5" y2="0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="0.75" x2="1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="-0.75" x2="-1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="-1.5" y1="-0.75" x2="-1.5" y2="0.75" width="0.1" layer="21"/>
+<smd name="1" x="-0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<smd name="2" x="0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+<package name="SMD0612">
+<wire x1="-1.8" y1="1.4" x2="1.8" y2="1.4" width="0.1" layer="21"/>
+<wire x1="1.8" y1="1.4" x2="1.8" y2="-1.4" width="0.1" layer="21"/>
+<wire x1="1.8" y1="-1.4" x2="-1.8" y2="-1.4" width="0.1" layer="21"/>
+<wire x1="-1.8" y1="-1.4" x2="-1.8" y2="1.4" width="0.1" layer="21"/>
+<smd name="1" x="0" y="0.8" dx="3.2" dy="0.8" layer="1"/>
+<smd name="2" x="0" y="-0.8" dx="3.2" dy="0.8" layer="1"/>
+<text x="0" y="1.778" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SMD1206">
+<wire x1="-2.5" y1="1.5" x2="2.5" y2="1.5" width="0.1" layer="21"/>
+<wire x1="2.5" y1="1.5" x2="2.5" y2="-1.5" width="0.1" layer="21"/>
+<wire x1="2.5" y1="-1.5" x2="-2.5" y2="-1.5" width="0.1" layer="21"/>
+<wire x1="-2.5" y1="-1.5" x2="-2.5" y2="1.5" width="0.1" layer="21"/>
+<smd name="1" x="-1.4" y="0" dx="1.6" dy="2" layer="1"/>
+<smd name="2" x="1.4" y="0" dx="1.6" dy="2" layer="1"/>
+<text x="0" y="1.778" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SMD2512">
+<wire x1="-5.5" y1="2.5" x2="5.5" y2="2.5" width="0.1" layer="21"/>
+<wire x1="5.5" y1="2.5" x2="5.5" y2="-2.5" width="0.1" layer="21"/>
+<wire x1="5.5" y1="-2.5" x2="-5.5" y2="-2.5" width="0.1" layer="21"/>
+<wire x1="-5.5" y1="-2.5" x2="-5.5" y2="2.5" width="0.1" layer="21"/>
+<smd name="1" x="-3.25" y="0" dx="3.5" dy="3" layer="1" rot="R90"/>
+<smd name="2" x="3.25" y="0" dx="3.5" dy="3" layer="1" rot="R90"/>
+<text x="0" y="2.794" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SMD0402">
+<wire x1="-1" y1="0.5" x2="1" y2="0.5" width="0.1" layer="21"/>
+<wire x1="1" y1="0.5" x2="1" y2="-0.5" width="0.1" layer="21"/>
+<wire x1="1" y1="-0.5" x2="-1" y2="-0.5" width="0.1" layer="21"/>
+<wire x1="-1" y1="-0.5" x2="-1" y2="0.5" width="0.1" layer="21"/>
+<smd name="1" x="-0.5" y="0" dx="0.6" dy="0.6" layer="1"/>
+<smd name="2" x="0.5" y="0" dx="0.6" dy="0.6" layer="1"/>
+<text x="0" y="0.762" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+<package name="SMD0805">
+<wire x1="-2" y1="1" x2="2" y2="1" width="0.1" layer="21"/>
+<wire x1="2" y1="1" x2="2" y2="-1" width="0.1" layer="21"/>
+<wire x1="2" y1="-1" x2="-2" y2="-1" width="0.1" layer="21"/>
+<wire x1="-2" y1="-1" x2="-2" y2="1" width="0.1" layer="21"/>
+<smd name="1" x="-0.95" y="0" dx="1.3" dy="1.5" layer="1"/>
+<smd name="2" x="0.95" y="0" dx="1.3" dy="1.5" layer="1"/>
+<text x="0" y="1.27" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+</packages>
+<symbols>
+<symbol name="C">
+<rectangle x1="-1.524" y1="-0.254" x2="2.54" y2="0.254" layer="94" rot="R90"/>
+<rectangle x1="-2.54" y1="-0.254" x2="1.524" y2="0.254" layer="94" rot="R90"/>
+<wire x1="-2.54" y1="0" x2="-0.762" y2="0" width="0.1524" layer="94"/>
+<wire x1="2.54" y1="0" x2="0.762" y2="0" width="0.1524" layer="94"/>
+<pin name="1" x="-2.54" y="0" visible="off" length="point" direction="pas" swaplevel="1"/>
+<pin name="2" x="2.54" y="0" visible="off" length="point" direction="pas" swaplevel="1" rot="R180"/>
+<text x="0" y="2.413" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-3.683" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+</symbol>
+<symbol name="R">
+<wire x1="-2.54" y1="-1.016" x2="-2.54" y2="1.016" width="0.254" layer="94"/>
+<pin name="1" x="-5.08" y="0" visible="off" length="short" direction="pas" swaplevel="1"/>
+<pin name="2" x="5.08" y="0" visible="off" length="short" direction="pas" swaplevel="1" rot="R180"/>
+<text x="0" y="1.524" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<text x="0" y="0" size="1.016" layer="96" align="center">&gt;VALUE</text>
+<wire x1="2.54" y1="-1.016" x2="2.54" y2="1.016" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="1.016" x2="2.54" y2="1.016" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="-1.016" x2="2.54" y2="-1.016" width="0.254" layer="94"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="C" prefix="C" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="C" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-0402" package="SMD0402">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0508" package="SMD0508">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0603" package="SMD0603">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0612" package="SMD0612">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0805" package="SMD0805">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-1206" package="SMD1206">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-2512" package="SMD2512">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="R" prefix="R" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="R" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-0402" package="SMD0402">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0508" package="SMD0508">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0603" package="SMD0603">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0612" package="SMD0612">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0805" package="SMD0805">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-1206" package="SMD1206">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-2512" package="SMD2512">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_vreg">
+<description>Alex Taradov Library (Voltage Regulators)</description>
+<packages>
+<package name="SOT23-5">
+<description>SOT23-5</description>
+<wire x1="1.422" y1="0.81" x2="1.422" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="1.422" y1="-0.81" x2="-1.422" y2="-0.81" width="0.1524" layer="51"/>
+<wire x1="-1.422" y1="-0.81" x2="-1.422" y2="0.81" width="0.1524" layer="21"/>
+<wire x1="-1.422" y1="0.81" x2="1.422" y2="0.81" width="0.1524" layer="51"/>
+<wire x1="-0.522" y1="0.81" x2="0.522" y2="0.81" width="0.1524" layer="21"/>
+<wire x1="-0.428" y1="-0.81" x2="-0.522" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="0.522" y1="-0.81" x2="0.428" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="-1.328" y1="-0.81" x2="-1.422" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="1.422" y1="-0.81" x2="1.328" y2="-0.81" width="0.1524" layer="21"/>
+<wire x1="1.328" y1="0.81" x2="1.422" y2="0.81" width="0.1524" layer="21"/>
+<wire x1="-1.422" y1="0.81" x2="-1.328" y2="0.81" width="0.1524" layer="21"/>
+<smd name="1" x="-0.95" y="-1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="2" x="0" y="-1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="3" x="0.95" y="-1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="4" x="0.95" y="1.3" dx="0.55" dy="1.2" layer="1"/>
+<smd name="5" x="-0.95" y="1.3" dx="0.55" dy="1.2" layer="1"/>
+<text x="0" y="2.286" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-3.556" size="1.27" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+<rectangle x1="-1.2" y1="-1.5" x2="-0.7" y2="-0.85" layer="51"/>
+<rectangle x1="-0.25" y1="-1.5" x2="0.25" y2="-0.85" layer="51"/>
+<rectangle x1="0.7" y1="-1.5" x2="1.2" y2="-0.85" layer="51"/>
+<rectangle x1="0.7" y1="0.85" x2="1.2" y2="1.5" layer="51"/>
+<rectangle x1="-1.2" y1="0.85" x2="-0.7" y2="1.5" layer="51"/>
+</package>
+</packages>
+<symbols>
+<symbol name="VREG-3-EN">
+<wire x1="-7.62" y1="5.08" x2="7.62" y2="5.08" width="0.254" layer="94"/>
+<wire x1="7.62" y1="5.08" x2="7.62" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="7.62" y1="-2.54" x2="-7.62" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="-7.62" y1="-2.54" x2="-7.62" y2="5.08" width="0.254" layer="94"/>
+<text x="-2.032" y="-1.524" size="1.524" layer="95">GND</text>
+<text x="0" y="5.842" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<text x="1.524" y="-4.318" size="1.27" layer="96">&gt;VALUE</text>
+<pin name="IN" x="-10.16" y="2.54" length="short" direction="sup"/>
+<pin name="OUT" x="10.16" y="2.54" length="short" direction="sup" rot="R180"/>
+<pin name="GND" x="0" y="-5.08" visible="pad" length="short" direction="pwr" rot="R90"/>
+<pin name="EN" x="-10.16" y="0" length="short" direction="in"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="MIC5504" prefix="IC" uservalue="yes">
+<description>LM1117 voltage regulator</description>
+<gates>
+<gate name="G$1" symbol="VREG-3-EN" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-SOT23-5" package="SOT23-5">
+<connects>
+<connect gate="G$1" pin="EN" pad="3"/>
+<connect gate="G$1" pin="GND" pad="2"/>
+<connect gate="G$1" pin="IN" pad="1"/>
+<connect gate="G$1" pin="OUT" pad="5"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_misc">
+<description>Alex Taradov Library (Miscellaneous stuff)</description>
+<packages>
+<package name="TP-1.27MM">
+<smd name="1" x="0" y="0" dx="1.27" dy="1.27" layer="1" roundness="100" cream="no"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="TP-2.54MM">
+<smd name="1" x="0" y="0" dx="2.54" dy="2.54" layer="1" roundness="100" cream="no"/>
+<text x="0" y="1.778" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="TP-0.635MM">
+<smd name="1" x="0" y="0" dx="0.635" dy="0.635" layer="1" roundness="100" cream="no"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="TP-0.5MM">
+<smd name="1" x="0" y="0" dx="0.5" dy="0.5" layer="1" roundness="100" cream="no"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="TP-1.27MM-TH">
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<pad name="1" x="0" y="0" drill="0.762" diameter="1.27"/>
+</package>
+</packages>
+<symbols>
+<symbol name="TP">
+<text x="4.064" y="-0.508" size="1.27" layer="95">&gt;NAME</text>
+<pin name="1" x="0" y="0" visible="off" length="short" direction="pas"/>
+<circle x="3.048" y="0" radius="0.508" width="0" layer="94"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="TEST-POINT" prefix="TP" uservalue="yes">
+<description>Test Point</description>
+<gates>
+<gate name="G$1" symbol="TP" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-1.27MM" package="TP-1.27MM">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0.635MM" package="TP-0.635MM">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0.5MM" package="TP-0.5MM">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-2.54MM" package="TP-2.54MM">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-1.27MM-TH" package="TP-1.27MM-TH">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_led">
+<description>Alex Taradov Library (LEDs and other indication devices)</description>
+<packages>
+<package name="SMD0603">
+<wire x1="-1.5" y1="0.75" x2="1.5" y2="0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="0.75" x2="1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="-0.75" x2="-1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="-1.5" y1="-0.75" x2="-1.5" y2="0.75" width="0.1" layer="21"/>
+<smd name="1" x="-0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<smd name="2" x="0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+<package name="SMD0805">
+<wire x1="-2" y1="1" x2="2" y2="1" width="0.1" layer="21"/>
+<wire x1="2" y1="1" x2="2" y2="-1" width="0.1" layer="21"/>
+<wire x1="2" y1="-1" x2="-2" y2="-1" width="0.1" layer="21"/>
+<wire x1="-2" y1="-1" x2="-2" y2="1" width="0.1" layer="21"/>
+<smd name="1" x="-0.95" y="0" dx="1.3" dy="1.5" layer="1"/>
+<smd name="2" x="0.95" y="0" dx="1.3" dy="1.5" layer="1"/>
+<text x="0" y="1.27" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-0.254" size="0.508" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+</packages>
+<symbols>
+<symbol name="LED">
+<wire x1="1.27" y1="0" x2="0" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="0" y1="-2.54" x2="-1.27" y2="0" width="0.254" layer="94"/>
+<wire x1="1.27" y1="-2.54" x2="0" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="0" y1="-2.54" x2="-1.27" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="1.27" y1="0" x2="0" y2="0" width="0.254" layer="94"/>
+<wire x1="0" y1="0" x2="-1.27" y2="0" width="0.254" layer="94"/>
+<wire x1="-2.032" y1="-0.762" x2="-3.429" y2="-2.159" width="0.1524" layer="94"/>
+<wire x1="-1.905" y1="-1.905" x2="-3.302" y2="-3.302" width="0.1524" layer="94"/>
+<text x="3.556" y="-2.032" size="1.27" layer="95" rot="R90" align="bottom-center">&gt;NAME</text>
+<text x="5.715" y="-2.032" size="1.27" layer="96" rot="R90" align="bottom-center">&gt;VALUE</text>
+<pin name="C" x="0" y="-5.08" visible="off" length="short" direction="pas" rot="R90"/>
+<pin name="A" x="0" y="2.54" visible="off" length="short" direction="pas" rot="R270"/>
+<polygon width="0.1524" layer="94">
+<vertex x="-3.429" y="-2.159"/>
+<vertex x="-3.048" y="-1.27"/>
+<vertex x="-2.54" y="-1.778"/>
+</polygon>
+<polygon width="0.1524" layer="94">
+<vertex x="-3.302" y="-3.302"/>
+<vertex x="-2.921" y="-2.413"/>
+<vertex x="-2.413" y="-2.921"/>
+</polygon>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="LED_SMD" prefix="LED" uservalue="yes">
+<description>SMD_LED</description>
+<gates>
+<gate name="G$1" symbol="LED" x="0" y="0"/>
+</gates>
+<devices>
+<device name="LED_0603" package="SMD0603">
+<connects>
+<connect gate="G$1" pin="A" pad="1"/>
+<connect gate="G$1" pin="C" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="LED_0805" package="SMD0805">
+<connects>
+<connect gate="G$1" pin="A" pad="1"/>
+<connect gate="G$1" pin="C" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+</libraries>
+<attributes>
+</attributes>
+<variantdefs>
+</variantdefs>
+<classes>
+<class number="0" name="default" width="0" drill="0">
+</class>
+</classes>
+<parts>
+<part name="IC2" library="ataradov_mcu" deviceset="ATSAMD11C" device=""/>
+<part name="P_4" library="ataradov_pwr" deviceset="+3V3" device=""/>
+<part name="P_6" library="ataradov_pwr" deviceset="+3V3" device=""/>
+<part name="P_9" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_7" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_8" library="ataradov_pwr" deviceset="V_USB" device=""/>
+<part name="P_1" library="ataradov_pwr" deviceset="V_USB" device=""/>
+<part name="C1" library="ataradov_rlc" deviceset="C" device="-0603" value="1uF"/>
+<part name="C2" library="ataradov_rlc" deviceset="C" device="-0603" value="1uF"/>
+<part name="IC1" library="ataradov_vreg" deviceset="MIC5504" device="-SOT23-5" value="MIC5504-3.3"/>
+<part name="P_3" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_5" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_2" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_11" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="R1" library="ataradov_rlc" deviceset="R" device="-0603" value="10K"/>
+<part name="TP3" library="ataradov_misc" deviceset="TEST-POINT" device="-1.27MM" value="SIO"/>
+<part name="TP1" library="ataradov_misc" deviceset="TEST-POINT" device="-1.27MM"/>
+<part name="TP2" library="ataradov_misc" deviceset="TEST-POINT" device="-1.27MM"/>
+<part name="TP4" library="ataradov_misc" deviceset="TEST-POINT" device="-1.27MM"/>
+<part name="LED1" library="ataradov_led" deviceset="LED_SMD" device="LED_0603" value="ORANGE"/>
+<part name="P_10" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="J1" library="ataradov_conn" deviceset="USB-B-MICRO" device="-SMT"/>
+<part name="J4" library="ataradov_conn" deviceset="POGO-PIN" device="-SMD"/>
+<part name="J2" library="ataradov_conn" deviceset="POGO-PIN" device="-SMD"/>
+<part name="J3" library="ataradov_conn" deviceset="POGO-PIN" device="-SMD"/>
+<part name="J5" library="ataradov_conn" deviceset="POGO-PIN" device="-SMD"/>
+<part name="P_12" library="ataradov_pwr" deviceset="GND" device=""/>
+</parts>
+<sheets>
+<sheet>
+<plain>
+<frame x1="0" y1="0" x2="127" y2="101.6" columns="8" rows="5" layer="97"/>
+<text x="111.76" y="83.82" size="1.778" layer="97" align="bottom-center">Program</text>
+<text x="111.76" y="60.96" size="1.778" layer="97" align="bottom-center">Target</text>
+<text x="22.86" y="7.62" size="1.778" layer="97">Copyright (c) 2021, Alex Taradov &lt;alex@taradov.com&gt;
+
+MCU firmware source code is available at https://github.com/ataradov/free-dap</text>
+</plain>
+<instances>
+<instance part="IC2" gate="G$1" x="38.1" y="71.12"/>
+<instance part="P_4" gate="1" x="43.18" y="38.1"/>
+<instance part="P_6" gate="1" x="58.42" y="83.82"/>
+<instance part="P_9" gate="1" x="71.12" y="58.42"/>
+<instance part="P_7" gate="1" x="58.42" y="58.42"/>
+<instance part="P_8" gate="1" x="71.12" y="78.74"/>
+<instance part="P_1" gate="1" x="15.24" y="38.1"/>
+<instance part="C1" gate="G$1" x="15.24" y="27.94" rot="R90"/>
+<instance part="C2" gate="G$1" x="43.18" y="27.94" rot="R90"/>
+<instance part="IC1" gate="G$1" x="27.94" y="30.48"/>
+<instance part="P_3" gate="1" x="27.94" y="22.86"/>
+<instance part="P_5" gate="1" x="43.18" y="22.86"/>
+<instance part="P_2" gate="1" x="15.24" y="22.86"/>
+<instance part="P_11" gate="1" x="109.22" y="71.12"/>
+<instance part="R1" gate="G$1" x="73.66" y="30.48"/>
+<instance part="TP3" gate="G$1" x="109.22" y="76.2"/>
+<instance part="TP1" gate="G$1" x="109.22" y="81.28"/>
+<instance part="TP2" gate="G$1" x="109.22" y="78.74"/>
+<instance part="TP4" gate="G$1" x="109.22" y="73.66"/>
+<instance part="LED1" gate="G$1" x="83.82" y="30.48" rot="MR270"/>
+<instance part="P_10" gate="1" x="91.44" y="27.94"/>
+<instance part="J1" gate="G$1" x="81.28" y="68.58"/>
+<instance part="J4" gate="G$1" x="111.76" y="53.34"/>
+<instance part="J2" gate="G$1" x="111.76" y="58.42"/>
+<instance part="J3" gate="G$1" x="111.76" y="55.88"/>
+<instance part="J5" gate="G$1" x="111.76" y="50.8"/>
+<instance part="P_12" gate="1" x="109.22" y="48.26"/>
+</instances>
+<busses>
+</busses>
+<nets>
+<net name="N$1" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA24"/>
+<wire x1="55.88" y1="66.04" x2="71.12" y2="66.04" width="0.1524" layer="91"/>
+<wire x1="71.12" y1="66.04" x2="71.12" y2="71.12" width="0.1524" layer="91"/>
+<wire x1="71.12" y1="71.12" x2="73.66" y2="71.12" width="0.1524" layer="91"/>
+<pinref part="J1" gate="G$1" pin="DM"/>
+</segment>
+</net>
+<net name="N$2" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA25"/>
+<wire x1="55.88" y1="68.58" x2="73.66" y2="68.58" width="0.1524" layer="91"/>
+<pinref part="J1" gate="G$1" pin="DP"/>
+</segment>
+</net>
+<net name="GND" class="0">
+<segment>
+<pinref part="P_9" gate="1" pin="GND"/>
+<wire x1="71.12" y1="60.96" x2="71.12" y2="63.5" width="0.1524" layer="91"/>
+<wire x1="71.12" y1="63.5" x2="73.66" y2="63.5" width="0.1524" layer="91"/>
+<pinref part="J1" gate="G$1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="IC1" gate="G$1" pin="GND"/>
+<pinref part="P_3" gate="1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="C1" gate="G$1" pin="1"/>
+<pinref part="P_2" gate="1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="C2" gate="G$1" pin="1"/>
+<pinref part="P_5" gate="1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="GND"/>
+<pinref part="P_7" gate="1" pin="GND"/>
+<wire x1="55.88" y1="71.12" x2="58.42" y2="71.12" width="0.1524" layer="91"/>
+<wire x1="58.42" y1="71.12" x2="58.42" y2="60.96" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="P_11" gate="1" pin="GND"/>
+<pinref part="TP4" gate="G$1" pin="1"/>
+</segment>
+<segment>
+<pinref part="P_10" gate="1" pin="GND"/>
+<wire x1="91.44" y1="30.48" x2="88.9" y2="30.48" width="0.1524" layer="91"/>
+<pinref part="LED1" gate="G$1" pin="C"/>
+</segment>
+<segment>
+<pinref part="J5" gate="G$1" pin="1"/>
+<pinref part="P_12" gate="1" pin="GND"/>
+</segment>
+</net>
+<net name="V_USB" class="0">
+<segment>
+<pinref part="P_8" gate="1" pin="V_USB"/>
+<wire x1="71.12" y1="76.2" x2="71.12" y2="73.66" width="0.1524" layer="91"/>
+<wire x1="71.12" y1="73.66" x2="73.66" y2="73.66" width="0.1524" layer="91"/>
+<pinref part="J1" gate="G$1" pin="VBUS"/>
+</segment>
+<segment>
+<pinref part="IC1" gate="G$1" pin="EN"/>
+<pinref part="P_1" gate="1" pin="V_USB"/>
+<wire x1="17.78" y1="30.48" x2="15.24" y2="30.48" width="0.1524" layer="91"/>
+<pinref part="IC1" gate="G$1" pin="IN"/>
+<wire x1="15.24" y1="33.02" x2="15.24" y2="35.56" width="0.1524" layer="91"/>
+<wire x1="17.78" y1="33.02" x2="15.24" y2="33.02" width="0.1524" layer="91"/>
+<junction x="15.24" y="33.02"/>
+<pinref part="C1" gate="G$1" pin="2"/>
+<wire x1="15.24" y1="33.02" x2="15.24" y2="30.48" width="0.1524" layer="91"/>
+<junction x="15.24" y="30.48"/>
+</segment>
+</net>
+<net name="+3V3" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="OUT"/>
+<wire x1="38.1" y1="33.02" x2="43.18" y2="33.02" width="0.1524" layer="91"/>
+<pinref part="C2" gate="G$1" pin="2"/>
+<wire x1="43.18" y1="30.48" x2="43.18" y2="33.02" width="0.1524" layer="91"/>
+<junction x="43.18" y="33.02"/>
+<pinref part="P_4" gate="1" pin="+3V3"/>
+<wire x1="43.18" y1="35.56" x2="43.18" y2="33.02" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="VDD"/>
+<pinref part="P_6" gate="1" pin="+3V3"/>
+<wire x1="55.88" y1="73.66" x2="58.42" y2="73.66" width="0.1524" layer="91"/>
+<wire x1="58.42" y1="73.66" x2="58.42" y2="81.28" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="SWDIO" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA31/SIO"/>
+<wire x1="55.88" y1="63.5" x2="60.96" y2="63.5" width="0.1524" layer="91"/>
+<label x="60.96" y="63.5" size="1.27" layer="95"/>
+</segment>
+<segment>
+<wire x1="109.22" y1="76.2" x2="106.68" y2="76.2" width="0.1524" layer="91"/>
+<label x="106.68" y="76.2" size="1.27" layer="95" rot="MR0"/>
+<pinref part="TP3" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="LED" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA04"/>
+<wire x1="55.88" y1="78.74" x2="60.96" y2="78.74" width="0.1524" layer="91"/>
+<label x="60.96" y="78.74" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="R1" gate="G$1" pin="1"/>
+<wire x1="68.58" y1="30.48" x2="66.04" y2="30.48" width="0.1524" layer="91"/>
+<label x="66.04" y="30.48" size="1.27" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="SWCLK" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA30/SCK"/>
+<wire x1="20.32" y1="63.5" x2="17.78" y2="63.5" width="0.1524" layer="91"/>
+<label x="17.78" y="63.5" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<label x="106.68" y="81.28" size="1.27" layer="95" rot="MR0"/>
+<wire x1="109.22" y1="81.28" x2="106.68" y2="81.28" width="0.1524" layer="91"/>
+<pinref part="TP1" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="RESET" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA28/RST"/>
+<wire x1="20.32" y1="66.04" x2="17.78" y2="66.04" width="0.1524" layer="91"/>
+<label x="17.78" y="66.04" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<label x="106.68" y="78.74" size="1.27" layer="95" rot="MR0"/>
+<wire x1="109.22" y1="78.74" x2="106.68" y2="78.74" width="0.1524" layer="91"/>
+<pinref part="TP2" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="T_SWCLK" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA14"/>
+<wire x1="17.78" y1="71.12" x2="20.32" y2="71.12" width="0.1524" layer="91"/>
+<label x="17.78" y="71.12" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<wire x1="106.68" y1="58.42" x2="109.22" y2="58.42" width="0.1524" layer="91"/>
+<label x="106.68" y="58.42" size="1.27" layer="95" rot="MR0"/>
+<pinref part="J2" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="T_SWDIO" class="0">
+<segment>
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dap_link/lib/free-dap/hardware/d11_usb_mini/d11_usb_mini.brd

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+<wire x1="0.8304" y1="2.0246" x2="0.5709" y2="1.7651" width="0.1016" layer="21" curve="89.955858"/>
+<wire x1="1.5573" y1="-2.0246" x2="3.4261" y2="-2.0246" width="0.1016" layer="21"/>
+<wire x1="3.0627" y1="-1.9726" x2="3.0627" y2="1.9727" width="0.1016" layer="51"/>
+<wire x1="-4.5684" y1="1.2459" x2="-0.5192" y2="1.0383" width="0.1016" layer="21"/>
+<wire x1="-0.5192" y1="1.0383" x2="-0.3116" y2="0.8306" width="0.1016" layer="21" curve="-83.771817"/>
+<wire x1="-4.5685" y1="1.2459" x2="-4.7761" y2="1.0383" width="0.1016" layer="21" curve="90"/>
+<wire x1="-4.7761" y1="1.0383" x2="-4.7761" y2="1.0382" width="0.1016" layer="21"/>
+<wire x1="-4.7761" y1="1.0382" x2="-4.5685" y2="0.8306" width="0.1016" layer="21" curve="90"/>
+<wire x1="-4.5685" y1="0.8306" x2="-1.1422" y2="0.623" width="0.1016" layer="21"/>
+<wire x1="-5.9182" y1="-3.8414" x2="-3.6879" y2="-3.8414" width="0.1016" layer="51"/>
+<wire x1="-3.6879" y1="-3.8414" x2="-3.6879" y2="-4.8797" width="0.1016" layer="51"/>
+<wire x1="-3.6879" y1="-4.8797" x2="-3.3245" y2="-4.8797" width="0.1016" layer="51"/>
+<wire x1="-3.3245" y1="-4.8797" x2="-3.3245" y2="-4.4644" width="0.1016" layer="51"/>
+<wire x1="-3.3245" y1="-4.4644" x2="-2.7015" y2="-4.4644" width="0.1016" layer="51"/>
+<wire x1="-2.7015" y1="-4.4644" x2="-2.7015" y2="-4.8797" width="0.1016" layer="51"/>
+<wire x1="-2.7015" y1="-4.8797" x2="-2.3093" y2="-4.8797" width="0.1016" layer="51"/>
+<wire x1="-2.3093" y1="-4.8797" x2="-2.3093" y2="-3.8414" width="0.1016" layer="51"/>
+<wire x1="-2.3093" y1="-3.8414" x2="2.8032" y2="-3.8414" width="0.1016" layer="51"/>
+<wire x1="0.7266" y1="-3.8414" x2="0.519" y2="-4.049" width="0.1016" layer="21" curve="90"/>
+<wire x1="0.519" y1="-4.049" x2="0.519" y2="-4.2048" width="0.1016" layer="21"/>
+<wire x1="0.519" y1="-4.2048" x2="2.907" y2="-4.2048" width="0.1016" layer="51"/>
+<wire x1="2.907" y1="-4.2048" x2="3.4781" y2="-3.6337" width="0.1016" layer="51" curve="90.020069"/>
+<wire x1="-1.8171" y1="-2.9589" x2="-4.5685" y2="-2.7512" width="0.1016" layer="21"/>
+<wire x1="-4.5685" y1="-2.7512" x2="-4.828" y2="-2.5436" width="0.1016" layer="21" curve="-68.629849"/>
+<wire x1="-4.828" y1="-2.5436" x2="-4.828" y2="-1.9725" width="0.1016" layer="21" curve="-34.099487"/>
+<wire x1="-4.828" y1="-1.9725" x2="-4.5685" y2="-1.7649" width="0.1016" layer="21" curve="-68.629849"/>
+<wire x1="-4.5685" y1="-1.7649" x2="-1.8171" y2="-1.5053" width="0.1016" layer="21"/>
+<wire x1="-1.8171" y1="-1.5053" x2="-1.8171" y2="-1.713" width="0.1016" layer="21"/>
+<wire x1="-1.8171" y1="-1.713" x2="-4.2051" y2="-1.9725" width="0.1016" layer="21"/>
+<wire x1="-4.2051" y1="-1.9725" x2="-4.2051" y2="-2.4917" width="0.1016" layer="21"/>
+<wire x1="-4.2051" y1="-2.4917" x2="-1.8171" y2="-2.7512" width="0.1016" layer="21"/>
+<wire x1="-1.8171" y1="-2.7512" x2="-1.8171" y2="-2.9589" width="0.1016" layer="21"/>
+<wire x1="2.8032" y1="-3.8414" x2="3.0627" y2="-3.5819" width="0.1016" layer="51" curve="90.044176"/>
+<wire x1="3.0627" y1="-3.5819" x2="3.0627" y2="-3.0108" width="0.1016" layer="51"/>
+<wire x1="3.0627" y1="-3.0108" x2="3.4261" y2="-3.0108" width="0.1016" layer="21"/>
+<wire x1="1.713" y1="-4.2567" x2="1.713" y2="-4.8797" width="0.1016" layer="51"/>
+<wire x1="1.713" y1="-4.8797" x2="2.1283" y2="-4.8797" width="0.1016" layer="51"/>
+<wire x1="2.1283" y1="-4.8797" x2="2.1283" y2="-4.4644" width="0.1016" layer="51"/>
+<wire x1="2.1283" y1="-4.4644" x2="2.6474" y2="-4.4644" width="0.1016" layer="51"/>
+<wire x1="2.6474" y1="-4.4644" x2="2.6474" y2="-4.8797" width="0.1016" layer="51"/>
+<wire x1="2.6474" y1="-4.8797" x2="3.0627" y2="-4.8797" width="0.1016" layer="51"/>
+<wire x1="3.0627" y1="-4.8797" x2="3.0627" y2="-4.2567" width="0.1016" layer="51"/>
+<wire x1="1.0381" y1="-1.8168" x2="0.8305" y2="-2.0244" width="0.1016" layer="21" curve="-90.055225"/>
+<wire x1="0.8304" y1="-2.0244" x2="0.5709" y2="-1.7649" width="0.1016" layer="21" curve="-89.867677"/>
+<wire x1="1.5573" y1="-1.9725" x2="1.5573" y2="2.0248" width="0.1016" layer="51"/>
+<wire x1="1.5573" y1="2.0248" x2="3.4261" y2="2.0248" width="0.1016" layer="21"/>
+<wire x1="-4.5684" y1="-1.2457" x2="-0.5192" y2="-1.0381" width="0.1016" layer="21"/>
+<wire x1="-0.5192" y1="-1.0381" x2="-0.3116" y2="-0.8304" width="0.1016" layer="21" curve="83.722654"/>
+<wire x1="-0.3116" y1="-0.8304" x2="-0.3116" y2="0.8307" width="0.1016" layer="21"/>
+<wire x1="-4.5685" y1="-1.2457" x2="-4.7761" y2="-1.0381" width="0.1016" layer="21" curve="-90"/>
+<wire x1="-4.7761" y1="-1.038" x2="-4.5685" y2="-0.8304" width="0.1016" layer="21" curve="-90"/>
+<wire x1="-4.5685" y1="-0.8304" x2="-1.1422" y2="-0.6228" width="0.1016" layer="21"/>
+<wire x1="-1.1422" y1="-0.6228" x2="-1.1422" y2="0.6232" width="0.1016" layer="21"/>
+<wire x1="-1.5826" y1="-3.8414" x2="0.7267" y2="-3.8415" width="0.1016" layer="21"/>
+<wire x1="-5.9182" y1="-3.8414" x2="-4.4146" y2="-3.8414" width="0.1016" layer="21"/>
+<wire x1="-5.9182" y1="3.8416" x2="-4.4147" y2="3.8415" width="0.1016" layer="21"/>
+<wire x1="-2.3093" y1="3.8416" x2="0.7265" y2="3.8415" width="0.1016" layer="51"/>
+<wire x1="3.4781" y1="-2.0245" x2="3.4781" y2="-3.0109" width="0.1016" layer="21"/>
+<wire x1="3.4781" y1="3.634" x2="3.478" y2="-3.0109" width="0.1016" layer="51"/>
+<wire x1="3.4782" y1="3.011" x2="3.4782" y2="2.0246" width="0.1016" layer="21"/>
+<smd name="M1" x="-3" y="-4.45" dx="2.5" dy="2" layer="1"/>
+<smd name="M2" x="-3" y="4.45" dx="2.5" dy="2" layer="1"/>
+<smd name="M4" x="2.9" y="-4.45" dx="3.3" dy="2" layer="1"/>
+<smd name="M3" x="2.9" y="4.45" dx="3.3" dy="2" layer="1"/>
+<smd name="1" x="3" y="1.6" dx="3.1" dy="0.5" layer="1"/>
+<smd name="2" x="3" y="0.8" dx="3.1" dy="0.5" layer="1"/>
+<smd name="3" x="3" y="0" dx="3.1" dy="0.5" layer="1"/>
+<smd name="4" x="3" y="-0.8" dx="3.1" dy="0.5" layer="1"/>
+<smd name="5" x="3" y="-1.6" dx="3.1" dy="0.5" layer="1"/>
+<text x="-4.445" y="5.715" size="1.27" layer="25">&gt;NAME</text>
+<text x="-4.445" y="-6.985" size="1.27" layer="27">&gt;VALUE</text>
+<hole x="0" y="2.2" drill="0.9"/>
+<hole x="0" y="-2.2" drill="0.9"/>
+</package>
+</packages>
+</library>
+<library name="ataradov_misc">
+<description>Alex Taradov Library (Miscellaneous stuff)</description>
+<packages>
+<package name="TP-1.27MM">
+<smd name="1" x="0" y="0" dx="1.27" dy="1.27" layer="1" roundness="100" cream="no"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+</packages>
+</library>
+<library name="ataradov_led">
+<description>Alex Taradov Library (LEDs and other indication devices)</description>
+<packages>
+<package name="SMD0603">
+<wire x1="-1.5" y1="0.75" x2="1.5" y2="0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="0.75" x2="1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="-0.75" x2="-1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="-1.5" y1="-0.75" x2="-1.5" y2="0.75" width="0.1" layer="21"/>
+<smd name="1" x="-0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<smd name="2" x="0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+</packages>
+</library>
+</libraries>
+<attributes>
+</attributes>
+<variantdefs>
+</variantdefs>
+<classes>
+<class number="0" name="default" width="0" drill="0">
+</class>
+</classes>
+<designrules name="OSHPark">
+<description language="de">&lt;b&gt;EAGLE Design Rules&lt;/b&gt;
+&lt;p&gt;
+Die Standard-Design-Rules sind so gewählt, dass sie für 
+die meisten Anwendungen passen. Sollte ihre Platine 
+besondere Anforderungen haben, treffen Sie die erforderlichen
+Einstellungen hier und speichern die Design Rules unter 
+einem neuen Namen ab.</description>
+<description language="en">&lt;b&gt;Laen's PCB Order Design Rules&lt;/b&gt;
+&lt;p&gt;
+Please make sure your boards conform to these design rules.</description>
+<param name="layerSetup" value="(1*16)"/>
+<param name="mtCopper" value="0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm"/>
+<param name="mtIsolate" value="1.5011mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm"/>
+<param name="mdWireWire" value="6mil"/>
+<param name="mdWirePad" value="6mil"/>
+<param name="mdWireVia" value="6mil"/>
+<param name="mdPadPad" value="6mil"/>
+<param name="mdPadVia" value="6mil"/>
+<param name="mdViaVia" value="6mil"/>
+<param name="mdSmdPad" value="6mil"/>
+<param name="mdSmdVia" value="6mil"/>
+<param name="mdSmdSmd" value="6mil"/>
+<param name="mdViaViaSameLayer" value="8mil"/>
+<param name="mnLayersViaInSmd" value="2"/>
+<param name="mdCopperDimension" value="15mil"/>
+<param name="mdDrill" value="6mil"/>
+<param name="mdSmdStop" value="0mil"/>
+<param name="msWidth" value="6mil"/>
+<param name="msDrill" value="13mil"/>
+<param name="msMicroVia" value="13mil"/>
+<param name="msBlindViaRatio" value="0.5"/>
+<param name="rvPadTop" value="0.25"/>
+<param name="rvPadInner" value="0.25"/>
+<param name="rvPadBottom" value="0.25"/>
+<param name="rvViaOuter" value="0.25"/>
+<param name="rvViaInner" value="0.25"/>
+<param name="rvMicroViaOuter" value="0.25"/>
+<param name="rvMicroViaInner" value="0.25"/>
+<param name="rlMinPadTop" value="7mil"/>
+<param name="rlMaxPadTop" value="20mil"/>
+<param name="rlMinPadInner" value="7mil"/>
+<param name="rlMaxPadInner" value="20mil"/>
+<param name="rlMinPadBottom" value="7mil"/>
+<param name="rlMaxPadBottom" value="20mil"/>
+<param name="rlMinViaOuter" value="7mil"/>
+<param name="rlMaxViaOuter" value="20mil"/>
+<param name="rlMinViaInner" value="7mil"/>
+<param name="rlMaxViaInner" value="20mil"/>
+<param name="rlMinMicroViaOuter" value="4mil"/>
+<param name="rlMaxMicroViaOuter" value="20mil"/>
+<param name="rlMinMicroViaInner" value="4mil"/>
+<param name="rlMaxMicroViaInner" value="20mil"/>
+<param name="psTop" value="-1"/>
+<param name="psBottom" value="-1"/>
+<param name="psFirst" value="-1"/>
+<param name="psElongationLong" value="100"/>
+<param name="psElongationOffset" value="100"/>
+<param name="mvStopFrame" value="1"/>
+<param name="mvCreamFrame" value="0"/>
+<param name="mlMinStopFrame" value="3mil"/>
+<param name="mlMaxStopFrame" value="3mil"/>
+<param name="mlMinCreamFrame" value="0mil"/>
+<param name="mlMaxCreamFrame" value="0mil"/>
+<param name="mlViaStopLimit" value="0mil"/>
+<param name="srRoundness" value="0"/>
+<param name="srMinRoundness" value="0mil"/>
+<param name="srMaxRoundness" value="0mil"/>
+<param name="slThermalIsolate" value="10mil"/>
+<param name="slThermalsForVias" value="0"/>
+<param name="dpMaxLengthDifference" value="10mm"/>
+<param name="dpGapFactor" value="2.5"/>
+<param name="checkGrid" value="0"/>
+<param name="checkAngle" value="0"/>
+<param name="checkFont" value="1"/>
+<param name="checkRestrict" value="1"/>
+<param name="useDiameter" value="13"/>
+<param name="maxErrors" value="50"/>
+</designrules>
+<autorouter>
+<pass name="Default">
+<param name="RoutingGrid" value="50mil"/>
+<param name="AutoGrid" value="1"/>
+<param name="Efforts" value="0"/>
+<param name="TopRouterVariant" value="1"/>
+<param name="tpViaShape" value="round"/>
+<param name="PrefDir.1" value="a"/>
+<param name="PrefDir.2" value="0"/>
+<param name="PrefDir.3" value="0"/>
+<param name="PrefDir.4" value="0"/>
+<param name="PrefDir.5" value="0"/>
+<param name="PrefDir.6" value="0"/>
+<param name="PrefDir.7" value="0"/>
+<param name="PrefDir.8" value="0"/>
+<param name="PrefDir.9" value="0"/>
+<param name="PrefDir.10" value="0"/>
+<param name="PrefDir.11" value="0"/>
+<param name="PrefDir.12" value="0"/>
+<param name="PrefDir.13" value="0"/>
+<param name="PrefDir.14" value="0"/>
+<param name="PrefDir.15" value="0"/>
+<param name="PrefDir.16" value="a"/>
+<param name="cfVia" value="8"/>
+<param name="cfNonPref" value="5"/>
+<param name="cfChangeDir" value="2"/>
+<param name="cfOrthStep" value="2"/>
+<param name="cfDiagStep" value="3"/>
+<param name="cfExtdStep" value="0"/>
+<param name="cfBonusStep" value="1"/>
+<param name="cfMalusStep" value="1"/>
+<param name="cfPadImpact" value="4"/>
+<param name="cfSmdImpact" value="4"/>
+<param name="cfBusImpact" value="0"/>
+<param name="cfHugging" value="3"/>
+<param name="cfAvoid" value="4"/>
+<param name="cfPolygon" value="10"/>
+<param name="cfBase.1" value="0"/>
+<param name="cfBase.2" value="1"/>
+<param name="cfBase.3" value="1"/>
+<param name="cfBase.4" value="1"/>
+<param name="cfBase.5" value="1"/>
+<param name="cfBase.6" value="1"/>
+<param name="cfBase.7" value="1"/>
+<param name="cfBase.8" value="1"/>
+<param name="cfBase.9" value="1"/>
+<param name="cfBase.10" value="1"/>
+<param name="cfBase.11" value="1"/>
+<param name="cfBase.12" value="1"/>
+<param name="cfBase.13" value="1"/>
+<param name="cfBase.14" value="1"/>
+<param name="cfBase.15" value="1"/>
+<param name="cfBase.16" value="0"/>
+<param name="mnVias" value="20"/>
+<param name="mnSegments" value="9999"/>
+<param name="mnExtdSteps" value="9999"/>
+<param name="mnRipupLevel" value="10"/>
+<param name="mnRipupSteps" value="100"/>
+<param name="mnRipupTotal" value="100"/>
+</pass>
+<pass name="Follow-me" refer="Default" active="yes">
+</pass>
+<pass name="Busses" refer="Default" active="yes">
+<param name="cfNonPref" value="4"/>
+<param name="cfBusImpact" value="4"/>
+<param name="cfHugging" value="0"/>
+<param name="mnVias" value="0"/>
+</pass>
+<pass name="Route" refer="Default" active="yes">
+</pass>
+<pass name="Optimize1" refer="Default" active="yes">
+<param name="cfVia" value="99"/>
+<param name="cfExtdStep" value="10"/>
+<param name="cfHugging" value="1"/>
+<param name="mnExtdSteps" value="1"/>
+<param name="mnRipupLevel" value="0"/>
+</pass>
+<pass name="Optimize2" refer="Optimize1" active="yes">
+<param name="cfNonPref" value="0"/>
+<param name="cfChangeDir" value="6"/>
+<param name="cfExtdStep" value="0"/>
+<param name="cfBonusStep" value="2"/>
+<param name="cfMalusStep" value="2"/>
+<param name="cfPadImpact" value="2"/>
+<param name="cfSmdImpact" value="2"/>
+<param name="cfHugging" value="0"/>
+</pass>
+<pass name="Optimize3" refer="Optimize2" active="yes">
+<param name="cfChangeDir" value="8"/>
+<param name="cfPadImpact" value="0"/>
+<param name="cfSmdImpact" value="0"/>
+</pass>
+<pass name="Optimize4" refer="Optimize3" active="yes">
+<param name="cfChangeDir" value="25"/>
+</pass>
+</autorouter>
+<elements>
+<element name="IC2" library="ataradov_mcu" package="SO-14" value="ATSAMD11C" x="4.826" y="7.366" smashed="yes" rot="MR270">
+<attribute name="NAME" x="4.826" y="12.192" size="1.27" layer="26" font="vector" rot="MR0" align="bottom-center"/>
+</element>
+<element name="J5" library="ataradov_conn" package="PIN-TH" value="SIO" x="15.748" y="9.906" smashed="yes">
+<attribute name="NAME" x="15.748" y="11.43" size="1.27" layer="25" font="vector" align="bottom-center"/>
+<attribute name="VALUE" x="14.224" y="9.906" size="0.762" layer="27" font="vector" rot="R90" align="bottom-center"/>
+</element>
+<element name="J6" library="ataradov_conn" package="PIN-TH" value="SCK" x="15.748" y="7.366" smashed="yes">
+<attribute name="NAME" x="15.748" y="8.89" size="1.27" layer="25" font="vector" align="bottom-center"/>
+<attribute name="VALUE" x="14.224" y="7.366" size="0.762" layer="27" font="vector" rot="R90" align="bottom-center"/>
+</element>
+<element name="J7" library="ataradov_conn" package="PIN-TH" value="RST" x="15.748" y="4.826" smashed="yes">
+<attribute name="NAME" x="15.748" y="6.35" size="1.27" layer="25" font="vector" align="bottom-center"/>
+<attribute name="VALUE" x="14.224" y="4.826" size="0.762" layer="27" font="vector" rot="R90" align="bottom-center"/>
+</element>
+<element name="J8" library="ataradov_conn" package="PIN-TH" value="GND" x="15.748" y="2.286" smashed="yes">
+<attribute name="NAME" x="15.748" y="3.81" size="1.27" layer="25" font="vector" align="bottom-center"/>
+<attribute name="VALUE" x="14.224" y="2.286" size="0.762" layer="27" font="vector" rot="R90" align="bottom-center"/>
+</element>
+<element name="C1" library="ataradov_rlc" package="SMD0603" value="1uF" x="11.43" y="10.922" rot="R180"/>
+<element name="C2" library="ataradov_rlc" package="SMD0603" value="1uF" x="11.43" y="4.826" smashed="yes">
+<attribute name="NAME" x="11.43" y="5.842" size="1.27" layer="25" font="vector" align="bottom-center"/>
+</element>
+<element name="R2" library="ataradov_rlc" package="SMD0603" value="330" x="11.43" y="10.922" rot="MR180"/>
+<element name="R3" library="ataradov_rlc" package="SMD0603" value="330" x="11.43" y="9.398" rot="MR180"/>
+<element name="R4" library="ataradov_rlc" package="SMD0603" value="330" x="11.43" y="7.874" rot="MR180"/>
+<element name="IC1" library="ataradov_vreg" package="SOT23-5" value="MIC5504-3.3" x="11.43" y="7.874" smashed="yes" rot="R180">
+<attribute name="NAME" x="11.43" y="5.588" size="1.27" layer="25" font="vector" rot="R180" align="bottom-center"/>
+</element>
+<element name="R5" library="ataradov_rlc" package="SMD0603" value="100K" x="11.43" y="4.826" rot="MR180"/>
+<element name="R6" library="ataradov_rlc" package="SMD0603" value="100K" x="11.43" y="3.302" rot="MR180"/>
+<element name="X1" library="con-cypressindustries" package="32005-201" value="MINI-USB-32005-201" x="4.826" y="6.096" smashed="yes">
+<attribute name="MF" value="" x="4.826" y="6.096" size="1.778" layer="27" display="off"/>
+<attribute name="MPN" value="" x="4.826" y="6.096" size="1.778" layer="27" display="off"/>
+<attribute name="OC_FARNELL" value="unknown" x="4.826" y="6.096" size="1.778" layer="27" display="off"/>
+<attribute name="OC_NEWARK" value="unknown" x="4.826" y="6.096" size="1.778" layer="27" display="off"/>
+<attribute name="NAME" x="0.381" y="11.811" size="1.27" layer="25"/>
+</element>
+<element name="R7" library="ataradov_rlc" package="SMD0603" value="330" x="11.43" y="6.35" rot="MR180"/>
+<element name="TP1" library="ataradov_misc" package="TP-1.27MM" value="SIO" x="4.318" y="1.524" rot="MR0"/>
+<element name="TP2" library="ataradov_misc" package="TP-1.27MM" value="" x="9.398" y="1.524" rot="MR0"/>
+<element name="TP3" library="ataradov_misc" package="TP-1.27MM" value="" x="6.858" y="1.524" rot="MR0"/>
+<element name="TP4" library="ataradov_misc" package="TP-1.27MM" value="" x="1.778" y="1.524" rot="MR0"/>
+<element name="LED1" library="ataradov_led" package="SMD0603" value="" x="11.43" y="3.302"/>
+</elements>
+<signals>
+<signal name="GND">
+<contactref element="IC1" pad="2"/>
+<contactref element="C1" pad="1"/>
+<contactref element="C2" pad="1"/>
+<contactref element="IC2" pad="11"/>
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+</signal>
+<signal name="N$1">
+<contactref element="IC2" pad="9"/>
+<contactref element="X1" pad="2"/>
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+</signal>
+<signal name="N$2">
+<contactref element="IC2" pad="10"/>
+<contactref element="X1" pad="3"/>
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+<wire x1="4.826" y1="6.096" x2="2.226" y2="6.096" width="0.254" layer="16"/>
+</signal>
+<signal name="V_USB">
+<contactref element="IC1" pad="3"/>
+<contactref element="IC1" pad="1"/>
+<contactref element="C1" pad="2"/>
+<contactref element="X1" pad="1"/>
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+<signal name="+3V3">
+<contactref element="IC1" pad="5"/>
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+<contactref element="R6" pad="2"/>
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+<signal name="SWDIO">
+<contactref element="IC2" pad="8"/>
+<contactref element="TP1" pad="1"/>
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+</signal>
+<signal name="PA02">
+<contactref element="IC2" pad="13"/>
+</signal>
+<signal name="PA04">
+<contactref element="IC2" pad="14"/>
+</signal>
+<signal name="SWCLK">
+<contactref element="IC2" pad="7"/>
+<contactref element="R6" pad="1"/>
+<contactref element="TP2" pad="1"/>
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+<wire x1="9.398" y1="1.524" x2="9.398" y2="3.302" width="0.254" layer="16"/>
+</signal>
+<signal name="RESET">
+<contactref element="IC2" pad="6"/>
+<contactref element="R5" pad="1"/>
+<contactref element="TP3" pad="1"/>
+<wire x1="7.426" y1="4.826" x2="6.096" y2="4.826" width="0.254" layer="16"/>
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+</signal>
+<signal name="PA15">
+<contactref element="IC2" pad="5"/>
+</signal>
+<signal name="PA14">
+<contactref element="IC2" pad="4"/>
+<contactref element="R7" pad="1"/>
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+</signal>
+<signal name="PA09">
+<contactref element="IC2" pad="3"/>
+<contactref element="R4" pad="1"/>
+<wire x1="7.426" y1="8.636" x2="9.144" y2="8.636" width="0.254" layer="16"/>
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+</signal>
+<signal name="PA08">
+<contactref element="IC2" pad="2"/>
+<contactref element="R3" pad="1"/>
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+</signal>
+<signal name="PA05">
+<contactref element="IC2" pad="1"/>
+<contactref element="R2" pad="1"/>
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+<wire x1="9.398" y1="10.922" x2="10.63" y2="10.922" width="0.254" layer="16"/>
+</signal>
+<signal name="N$3">
+<contactref element="R2" pad="2"/>
+<contactref element="J5" pad="1"/>
+<wire x1="12.23" y1="10.922" x2="14.732" y2="10.922" width="0.254" layer="16"/>
+<wire x1="14.732" y1="10.922" x2="15.748" y2="9.906" width="0.254" layer="16"/>
+</signal>
+<signal name="N$4">
+<contactref element="R3" pad="2"/>
+<contactref element="J6" pad="1"/>
+<wire x1="12.23" y1="9.398" x2="13.716" y2="9.398" width="0.254" layer="16"/>
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+</signal>
+<signal name="N$5">
+<contactref element="R4" pad="2"/>
+<contactref element="J7" pad="1"/>
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+</signal>
+<signal name="N$8">
+</signal>
+<signal name="N$6">
+<contactref element="R7" pad="2"/>
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+<via x="12.7" y="2.032" extent="1-16" drill="0.508" diameter="0.8636"/>
+<contactref element="LED1" pad="2"/>
+<wire x1="12.23" y1="3.302" x2="12.23" y2="2.502" width="0.254" layer="1"/>
+<wire x1="12.23" y1="2.502" x2="12.7" y2="2.032" width="0.254" layer="1"/>
+</signal>
+</signals>
+</board>
+</drawing>
+</eagle>

dap_link/lib/free-dap/hardware/d11_usb_mini/d11_usb_mini.sch

@@ -0,0 +1,1341 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="7.3.0">
+<drawing>
+<settings>
+<setting alwaysvectorfont="no"/>
+<setting verticaltext="up"/>
+</settings>
+<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>
+<layers>
+<layer number="1" name="Top" color="4" fill="1" visible="no" active="no"/>
+<layer number="16" name="Bottom" color="1" fill="1" visible="no" active="no"/>
+<layer number="17" name="Pads" color="2" fill="1" visible="no" active="no"/>
+<layer number="18" name="Vias" color="2" fill="1" visible="no" active="no"/>
+<layer number="19" name="Unrouted" color="6" fill="1" visible="no" active="no"/>
+<layer number="20" name="Dimension" color="15" fill="1" visible="no" active="no"/>
+<layer number="21" name="tPlace" color="7" fill="1" visible="no" active="no"/>
+<layer number="22" name="bPlace" color="7" fill="1" visible="no" active="no"/>
+<layer number="23" name="tOrigins" color="15" fill="1" visible="no" active="no"/>
+<layer number="24" name="bOrigins" color="15" fill="1" visible="no" active="no"/>
+<layer number="25" name="tNames" color="7" fill="1" visible="no" active="no"/>
+<layer number="26" name="bNames" color="7" fill="1" visible="no" active="no"/>
+<layer number="27" name="tValues" color="7" fill="1" visible="no" active="no"/>
+<layer number="28" name="bValues" color="7" fill="1" visible="no" active="no"/>
+<layer number="29" name="tStop" color="7" fill="3" visible="no" active="no"/>
+<layer number="30" name="bStop" color="7" fill="6" visible="no" active="no"/>
+<layer number="31" name="tCream" color="7" fill="4" visible="no" active="no"/>
+<layer number="32" name="bCream" color="7" fill="5" visible="no" active="no"/>
+<layer number="33" name="tFinish" color="6" fill="3" visible="no" active="no"/>
+<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="no"/>
+<layer number="35" name="tGlue" color="7" fill="4" visible="no" active="no"/>
+<layer number="36" name="bGlue" color="7" fill="5" visible="no" active="no"/>
+<layer number="37" name="tTest" color="7" fill="1" visible="no" active="no"/>
+<layer number="38" name="bTest" color="7" fill="1" visible="no" active="no"/>
+<layer number="39" name="tKeepout" color="4" fill="11" visible="no" active="no"/>
+<layer number="40" name="bKeepout" color="1" fill="11" visible="no" active="no"/>
+<layer number="41" name="tRestrict" color="4" fill="10" visible="no" active="no"/>
+<layer number="42" name="bRestrict" color="1" fill="10" visible="no" active="no"/>
+<layer number="43" name="vRestrict" color="2" fill="10" visible="no" active="no"/>
+<layer number="44" name="Drills" color="7" fill="1" visible="no" active="no"/>
+<layer number="45" name="Holes" color="7" fill="1" visible="no" active="no"/>
+<layer number="46" name="Milling" color="3" fill="1" visible="no" active="no"/>
+<layer number="47" name="Measures" color="7" fill="1" visible="no" active="no"/>
+<layer number="48" name="Document" color="7" fill="1" visible="no" active="no"/>
+<layer number="49" name="Reference" color="7" fill="1" visible="no" active="no"/>
+<layer number="51" name="tDocu" color="6" fill="1" visible="no" active="no"/>
+<layer number="52" name="bDocu" color="7" fill="1" visible="no" active="no"/>
+<layer number="90" name="Modules" color="5" fill="1" visible="yes" active="yes"/>
+<layer number="91" name="Nets" color="2" fill="1" visible="yes" active="yes"/>
+<layer number="92" name="Busses" color="1" fill="1" visible="yes" active="yes"/>
+<layer number="93" name="Pins" color="2" fill="1" visible="no" active="yes"/>
+<layer number="94" name="Symbols" color="4" fill="1" visible="yes" active="yes"/>
+<layer number="95" name="Names" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="96" name="Values" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="97" name="Info" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/>
+</layers>
+<schematic xreflabel="%F%N/%S.%C%R" xrefpart="/%S.%C%R">
+<libraries>
+<library name="ataradov_mcu">
+<description>Alex Taradov Library (MCUs)</description>
+<packages>
+<package name="SO-14">
+<description>SO-14</description>
+<wire x1="4.305" y1="-1.9" x2="-4.305" y2="-1.9" width="0.2032" layer="51"/>
+<wire x1="-4.305" y1="-1.9" x2="-4.305" y2="-1.4" width="0.2032" layer="51"/>
+<wire x1="-4.305" y1="-1.4" x2="-4.305" y2="1.9" width="0.2032" layer="51"/>
+<wire x1="4.305" y1="-1.4" x2="-4.305" y2="-1.4" width="0.2032" layer="51"/>
+<wire x1="4.305" y1="1.9" x2="4.305" y2="-1.4" width="0.2032" layer="51"/>
+<wire x1="4.305" y1="-1.4" x2="4.305" y2="-1.9" width="0.2032" layer="51"/>
+<wire x1="-4.305" y1="1.9" x2="4.305" y2="1.9" width="0.2032" layer="51"/>
+<smd name="2" x="-2.54" y="-2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="13" x="-2.54" y="2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="1" x="-3.81" y="-2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="3" x="-1.27" y="-2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="4" x="0" y="-2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="14" x="-3.81" y="2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="12" x="-1.27" y="2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="11" x="0" y="2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="6" x="2.54" y="-2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="9" x="2.54" y="2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="5" x="1.27" y="-2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="7" x="3.81" y="-2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="10" x="1.27" y="2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="8" x="3.81" y="2.6" dx="0.6" dy="2.2" layer="1"/>
+<text x="-4.826" y="0" size="1.27" layer="25" font="vector" rot="R90" align="bottom-center">&gt;NAME</text>
+<text x="6.096" y="0" size="1.27" layer="27" font="vector" rot="R90" align="bottom-center">&gt;VALUE</text>
+<rectangle x1="-4.0551" y1="-3.1001" x2="-3.5649" y2="-2" layer="51"/>
+<rectangle x1="-2.7851" y1="-3.1001" x2="-2.2949" y2="-2" layer="51"/>
+<rectangle x1="-1.5151" y1="-3.1001" x2="-1.0249" y2="-2" layer="51"/>
+<rectangle x1="-0.2451" y1="-3.1001" x2="0.2451" y2="-2" layer="51"/>
+<rectangle x1="-0.2451" y1="2" x2="0.2451" y2="3.1001" layer="51"/>
+<rectangle x1="-1.5151" y1="2" x2="-1.0249" y2="3.1001" layer="51"/>
+<rectangle x1="-2.7851" y1="2" x2="-2.2949" y2="3.1001" layer="51"/>
+<rectangle x1="-4.0551" y1="2" x2="-3.5649" y2="3.1001" layer="51"/>
+<rectangle x1="1.0249" y1="-3.1001" x2="1.5151" y2="-2" layer="51"/>
+<rectangle x1="2.2949" y1="-3.1001" x2="2.7851" y2="-2" layer="51"/>
+<rectangle x1="3.5649" y1="-3.1001" x2="4.0551" y2="-2" layer="51"/>
+<rectangle x1="3.5649" y1="2" x2="4.0551" y2="3.1001" layer="51"/>
+<rectangle x1="2.2949" y1="2" x2="2.7851" y2="3.1001" layer="51"/>
+<rectangle x1="1.0249" y1="2" x2="1.5151" y2="3.1001" layer="51"/>
+</package>
+</packages>
+<symbols>
+<symbol name="ATSAMDXXC">
+<description>Atmel SAM D09C/D10C/D11C Cortex-M0+ microcontroller</description>
+<wire x1="-12.7" y1="10.16" x2="12.7" y2="10.16" width="0.254" layer="94"/>
+<wire x1="12.7" y1="10.16" x2="12.7" y2="-10.16" width="0.254" layer="94"/>
+<wire x1="12.7" y1="-10.16" x2="-12.7" y2="-10.16" width="0.254" layer="94"/>
+<wire x1="-12.7" y1="-10.16" x2="-12.7" y2="10.16" width="0.254" layer="94"/>
+<pin name="PA28/RST" x="-17.78" y="-5.08" length="middle"/>
+<pin name="PA8" x="-17.78" y="5.08" length="middle"/>
+<pin name="PA9" x="-17.78" y="2.54" length="middle"/>
+<pin name="PA14" x="-17.78" y="0" length="middle"/>
+<pin name="PA15" x="-17.78" y="-2.54" length="middle"/>
+<pin name="PA5" x="-17.78" y="7.62" length="middle"/>
+<pin name="PA04" x="17.78" y="7.62" length="middle" rot="R180"/>
+<pin name="PA02" x="17.78" y="5.08" length="middle" rot="R180"/>
+<text x="0" y="10.922" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-12.192" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+<pin name="PA30/SCK" x="-17.78" y="-7.62" length="middle"/>
+<pin name="VDD" x="17.78" y="2.54" length="middle" rot="R180"/>
+<pin name="GND" x="17.78" y="0" length="middle" rot="R180"/>
+<pin name="PA25" x="17.78" y="-2.54" length="middle" rot="R180"/>
+<pin name="PA24" x="17.78" y="-5.08" length="middle" rot="R180"/>
+<pin name="PA31/SIO" x="17.78" y="-7.62" length="middle" rot="R180"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="ATSAMD11C" prefix="IC">
+<gates>
+<gate name="G$1" symbol="ATSAMDXXC" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="SO-14">
+<connects>
+<connect gate="G$1" pin="GND" pad="11"/>
+<connect gate="G$1" pin="PA02" pad="13"/>
+<connect gate="G$1" pin="PA04" pad="14"/>
+<connect gate="G$1" pin="PA14" pad="4"/>
+<connect gate="G$1" pin="PA15" pad="5"/>
+<connect gate="G$1" pin="PA24" pad="9"/>
+<connect gate="G$1" pin="PA25" pad="10"/>
+<connect gate="G$1" pin="PA28/RST" pad="6"/>
+<connect gate="G$1" pin="PA30/SCK" pad="7"/>
+<connect gate="G$1" pin="PA31/SIO" pad="8"/>
+<connect gate="G$1" pin="PA5" pad="1"/>
+<connect gate="G$1" pin="PA8" pad="2"/>
+<connect gate="G$1" pin="PA9" pad="3"/>
+<connect gate="G$1" pin="VDD" pad="12"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_pwr">
+<description>Alex Taradov Library (Power Symbols)</description>
+<packages>
+</packages>
+<symbols>
+<symbol name="+3V3">
+<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/>
+<text x="0" y="0.762" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+<pin name="+3V3" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/>
+</symbol>
+<symbol name="GND">
+<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/>
+<text x="0" y="-2.032" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+<pin name="GND" x="0" y="2.54" visible="off" length="short" direction="sup" rot="R270"/>
+</symbol>
+<symbol name="V_USB">
+<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/>
+<text x="0" y="0.762" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+<pin name="V_USB" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="+3V3" prefix="P_">
+<gates>
+<gate name="1" symbol="+3V3" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="GND" prefix="P_">
+<gates>
+<gate name="1" symbol="GND" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="V_USB" prefix="P_">
+<gates>
+<gate name="1" symbol="V_USB" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_conn">
+<description>Alex Taradov Library (Connectors)</description>
+<packages>
+<package name="PIN-TH">
+<wire x1="-0.635" y1="1.27" x2="0.635" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="0.635" y1="1.27" x2="1.27" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="1.27" y1="0.635" x2="1.27" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="1.27" y1="-0.635" x2="0.635" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-1.27" y1="0.635" x2="-1.27" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-0.635" y1="1.27" x2="-1.27" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-1.27" y1="-0.635" x2="-0.635" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="0.635" y1="-1.27" x2="-0.635" y2="-1.27" width="0.1524" layer="21"/>
+<rectangle x1="-0.254" y1="-0.254" x2="0.254" y2="0.254" layer="51"/>
+<pad name="1" x="0" y="0" drill="1.016" shape="octagon"/>
+<text x="0" y="1.524" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-2.794" size="1.27" layer="27" font="vector" align="bottom-center">&gt;VALUE</text>
+</package>
+</packages>
+<symbols>
+<symbol name="CONN-SINGLE">
+<wire x1="-2.54" y1="0.762" x2="0.127" y2="0" width="0.254" layer="94"/>
+<wire x1="0.127" y1="0" x2="-2.4765" y2="-0.762" width="0.254" layer="94"/>
+<pin name="1" x="-2.54" y="0" visible="off" length="short" direction="pas" swaplevel="1"/>
+<text x="1.27" y="-0.508" size="1.27" layer="95">&gt;NAME</text>
+<text x="6.096" y="-0.508" size="1.27" layer="96">&gt;VALUE</text>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="CONN-SINGLE" prefix="J" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="CONN-SINGLE" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-TH" package="PIN-TH">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_rlc">
+<description>Alex Taradov Library (R, L and C)</description>
+<packages>
+<package name="SMD0402">
+<wire x1="-1" y1="0.5" x2="1" y2="0.5" width="0.1" layer="21"/>
+<wire x1="1" y1="0.5" x2="1" y2="-0.5" width="0.1" layer="21"/>
+<wire x1="1" y1="-0.5" x2="-1" y2="-0.5" width="0.1" layer="21"/>
+<wire x1="-1" y1="-0.5" x2="-1" y2="0.5" width="0.1" layer="21"/>
+<smd name="1" x="-0.5" y="0" dx="0.6" dy="0.6" layer="1"/>
+<smd name="2" x="0.5" y="0" dx="0.6" dy="0.6" layer="1"/>
+<text x="0" y="0.762" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SMD0508">
+<wire x1="-1" y1="1.25" x2="1" y2="1.25" width="0.1" layer="21"/>
+<wire x1="1" y1="1.25" x2="1" y2="-1.25" width="0.1" layer="21"/>
+<wire x1="1" y1="-1.25" x2="-1" y2="-1.25" width="0.1" layer="21"/>
+<wire x1="-1" y1="-1.25" x2="-1" y2="1.25" width="0.1" layer="21"/>
+<smd name="1" x="-0.5" y="0" dx="2" dy="0.5" layer="1" rot="R90"/>
+<smd name="2" x="0.5" y="0" dx="2" dy="0.5" layer="1" rot="R90"/>
+<text x="0" y="1.524" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SMD0603">
+<wire x1="-1.5" y1="0.75" x2="1.5" y2="0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="0.75" x2="1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="-0.75" x2="-1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="-1.5" y1="-0.75" x2="-1.5" y2="0.75" width="0.1" layer="21"/>
+<smd name="1" x="-0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<smd name="2" x="0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SMD0612">
+<wire x1="-1.8" y1="1.4" x2="1.8" y2="1.4" width="0.1" layer="21"/>
+<wire x1="1.8" y1="1.4" x2="1.8" y2="-1.4" width="0.1" layer="21"/>
+<wire x1="1.8" y1="-1.4" x2="-1.8" y2="-1.4" width="0.1" layer="21"/>
+<wire x1="-1.8" y1="-1.4" x2="-1.8" y2="1.4" width="0.1" layer="21"/>
+<smd name="1" x="0" y="0.8" dx="3.2" dy="0.8" layer="1"/>
+<smd name="2" x="0" y="-0.8" dx="3.2" dy="0.8" layer="1"/>
+<text x="0" y="1.778" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SMD0805">
+<wire x1="-2" y1="1" x2="2" y2="1" width="0.1" layer="21"/>
+<wire x1="2" y1="1" x2="2" y2="-1" width="0.1" layer="21"/>
+<wire x1="2" y1="-1" x2="-2" y2="-1" width="0.1" layer="21"/>
+<wire x1="-2" y1="-1" x2="-2" y2="1" width="0.1" layer="21"/>
+<smd name="1" x="-0.95" y="0" dx="1.3" dy="1.5" layer="1"/>
+<smd name="2" x="0.95" y="0" dx="1.3" dy="1.5" layer="1"/>
+<text x="0" y="1.27" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SMD1206">
+<wire x1="-2.5" y1="1.5" x2="2.5" y2="1.5" width="0.1" layer="21"/>
+<wire x1="2.5" y1="1.5" x2="2.5" y2="-1.5" width="0.1" layer="21"/>
+<wire x1="2.5" y1="-1.5" x2="-2.5" y2="-1.5" width="0.1" layer="21"/>
+<wire x1="-2.5" y1="-1.5" x2="-2.5" y2="1.5" width="0.1" layer="21"/>
+<smd name="1" x="-1.4" y="0" dx="1.6" dy="2" layer="1"/>
+<smd name="2" x="1.4" y="0" dx="1.6" dy="2" layer="1"/>
+<text x="0" y="1.778" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SMD2512">
+<wire x1="-5.5" y1="2.5" x2="5.5" y2="2.5" width="0.1" layer="21"/>
+<wire x1="5.5" y1="2.5" x2="5.5" y2="-2.5" width="0.1" layer="21"/>
+<wire x1="5.5" y1="-2.5" x2="-5.5" y2="-2.5" width="0.1" layer="21"/>
+<wire x1="-5.5" y1="-2.5" x2="-5.5" y2="2.5" width="0.1" layer="21"/>
+<smd name="1" x="-3.25" y="0" dx="3.5" dy="3" layer="1" rot="R90"/>
+<smd name="2" x="3.25" y="0" dx="3.5" dy="3" layer="1" rot="R90"/>
+<text x="0" y="2.794" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+</packages>
+<symbols>
+<symbol name="C">
+<rectangle x1="-1.524" y1="-0.254" x2="2.54" y2="0.254" layer="94" rot="R90"/>
+<rectangle x1="-2.54" y1="-0.254" x2="1.524" y2="0.254" layer="94" rot="R90"/>
+<wire x1="-2.54" y1="0" x2="-0.762" y2="0" width="0.1524" layer="94"/>
+<wire x1="2.54" y1="0" x2="0.762" y2="0" width="0.1524" layer="94"/>
+<pin name="1" x="-2.54" y="0" visible="off" length="point" direction="pas" swaplevel="1"/>
+<pin name="2" x="2.54" y="0" visible="off" length="point" direction="pas" swaplevel="1" rot="R180"/>
+<text x="0" y="2.413" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-3.683" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+</symbol>
+<symbol name="R">
+<wire x1="-2.54" y1="-1.016" x2="-2.54" y2="1.016" width="0.254" layer="94"/>
+<pin name="1" x="-5.08" y="0" visible="off" length="short" direction="pas" swaplevel="1"/>
+<pin name="2" x="5.08" y="0" visible="off" length="short" direction="pas" swaplevel="1" rot="R180"/>
+<text x="0" y="1.524" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<text x="0" y="0" size="1.016" layer="96" align="center">&gt;VALUE</text>
+<wire x1="2.54" y1="-1.016" x2="2.54" y2="1.016" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="1.016" x2="2.54" y2="1.016" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="-1.016" x2="2.54" y2="-1.016" width="0.254" layer="94"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="C" prefix="C" uservalue="yes">
+<gates>
+<gate name="G$1" symbol="C" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-0402" package="SMD0402">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0508" package="SMD0508">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0603" package="SMD0603">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0612" package="SMD0612">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-0805" package="SMD0805">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-1206" package="SMD1206">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-2512" package="SMD2512">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
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+</technologies>
+</device>
+<device name="LED_0805" package="SMD0805">
+<connects>
+<connect gate="G$1" pin="A" pad="1"/>
+<connect gate="G$1" pin="C" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+</libraries>
+<attributes>
+</attributes>
+<variantdefs>
+</variantdefs>
+<classes>
+<class number="0" name="default" width="0" drill="0">
+</class>
+</classes>
+<parts>
+<part name="IC2" library="ataradov_mcu" deviceset="ATSAMD11C" device=""/>
+<part name="P_9" library="ataradov_pwr" deviceset="+3V3" device=""/>
+<part name="P_7" library="ataradov_pwr" deviceset="+3V3" device=""/>
+<part name="P_17" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_8" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_16" library="ataradov_pwr" deviceset="V_USB" device=""/>
+<part name="P_3" library="ataradov_pwr" deviceset="V_USB" device=""/>
+<part name="J5" library="ataradov_conn" deviceset="CONN-SINGLE" device="-TH" value="SIO"/>
+<part name="J6" library="ataradov_conn" deviceset="CONN-SINGLE" device="-TH" value="SCK"/>
+<part name="J7" library="ataradov_conn" deviceset="CONN-SINGLE" device="-TH" value="RST"/>
+<part name="J8" library="ataradov_conn" deviceset="CONN-SINGLE" device="-TH" value="GND"/>
+<part name="C1" library="ataradov_rlc" deviceset="C" device="-0603" value="1uF"/>
+<part name="C2" library="ataradov_rlc" deviceset="C" device="-0603" value="1uF"/>
+<part name="R2" library="ataradov_rlc" deviceset="R" device="-0603" value="330"/>
+<part name="R3" library="ataradov_rlc" deviceset="R" device="-0603" value="330"/>
+<part name="R4" library="ataradov_rlc" deviceset="R" device="-0603" value="330"/>
+<part name="IC1" library="ataradov_vreg" deviceset="MIC5504" device="-SOT23-5" value="MIC5504-3.3"/>
+<part name="P_4" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_6" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_1" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_2" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_11" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="R5" library="ataradov_rlc" deviceset="R" device="-0603" value="100K"/>
+<part name="R6" library="ataradov_rlc" deviceset="R" device="-0603" value="100K"/>
+<part name="P_18" library="ataradov_pwr" deviceset="+3V3" device=""/>
+<part name="P_19" library="ataradov_pwr" deviceset="+3V3" device=""/>
+<part name="X1" library="con-cypressindustries" deviceset="MINI-USB-" device="32005-201"/>
+<part name="R7" library="ataradov_rlc" deviceset="R" device="-0603" value="330"/>
+<part name="TP1" library="ataradov_misc" deviceset="TEST-POINT" device="-1.27MM" value="SIO"/>
+<part name="TP2" library="ataradov_misc" deviceset="TEST-POINT" device="-1.27MM"/>
+<part name="TP3" library="ataradov_misc" deviceset="TEST-POINT" device="-1.27MM"/>
+<part name="TP4" library="ataradov_misc" deviceset="TEST-POINT" device="-1.27MM"/>
+<part name="P_5" library="ataradov_pwr" deviceset="+3V3" device=""/>
+<part name="LED1" library="ataradov_led" deviceset="LED_SMD" device="LED_0603"/>
+</parts>
+<sheets>
+<sheet>
+<plain>
+<frame x1="0" y1="0" x2="152.4" y2="119.38" columns="8" rows="5" layer="97"/>
+<text x="35.56" y="106.68" size="1.778" layer="97" align="bottom-center">Program</text>
+<text x="78.74" y="106.68" size="1.778" layer="97" align="bottom-center">Target</text>
+<text x="60.96" y="15.24" size="1.778" layer="97">Copyright (c) 2016-2017, Alex Taradov &lt;alex@taradov.com&gt;
+
+MCU firmware source code is available at https://github.com/ataradov/free-dap</text>
+</plain>
+<instances>
+<instance part="IC2" gate="G$1" x="40.64" y="53.34"/>
+<instance part="P_9" gate="1" x="53.34" y="27.94"/>
+<instance part="P_7" gate="1" x="60.96" y="66.04"/>
+<instance part="P_17" gate="1" x="76.2" y="40.64"/>
+<instance part="P_8" gate="1" x="60.96" y="40.64"/>
+<instance part="P_16" gate="1" x="76.2" y="60.96"/>
+<instance part="P_3" gate="1" x="25.4" y="27.94"/>
+<instance part="J5" gate="G$1" x="91.44" y="101.6"/>
+<instance part="J6" gate="G$1" x="91.44" y="99.06"/>
+<instance part="J7" gate="G$1" x="91.44" y="96.52"/>
+<instance part="J8" gate="G$1" x="91.44" y="93.98"/>
+<instance part="C1" gate="G$1" x="20.32" y="17.78" rot="R90"/>
+<instance part="C2" gate="G$1" x="53.34" y="17.78" rot="R90"/>
+<instance part="R2" gate="G$1" x="71.12" y="101.6"/>
+<instance part="R3" gate="G$1" x="71.12" y="96.52"/>
+<instance part="R4" gate="G$1" x="71.12" y="91.44"/>
+<instance part="IC1" gate="G$1" x="38.1" y="20.32"/>
+<instance part="P_4" gate="1" x="38.1" y="12.7"/>
+<instance part="P_6" gate="1" x="53.34" y="12.7"/>
+<instance part="P_1" gate="1" x="20.32" y="12.7"/>
+<instance part="P_2" gate="1" x="38.1" y="76.2"/>
+<instance part="P_11" gate="1" x="86.36" y="91.44"/>
+<instance part="R5" gate="G$1" x="38.1" y="93.98" rot="R90"/>
+<instance part="R6" gate="G$1" x="33.02" y="93.98" rot="R90"/>
+<instance part="P_18" gate="1" x="33.02" y="101.6"/>
+<instance part="P_19" gate="1" x="38.1" y="101.6"/>
+<instance part="X1" gate="G$1" x="83.82" y="50.8" smashed="yes">
+<attribute name="NAME" x="81.28" y="62.23" size="1.778" layer="95"/>
+</instance>
+<instance part="R7" gate="G$1" x="73.66" y="78.74"/>
+<instance part="TP1" gate="G$1" x="40.64" y="86.36"/>
+<instance part="TP2" gate="G$1" x="40.64" y="83.82"/>
+<instance part="TP3" gate="G$1" x="40.64" y="81.28"/>
+<instance part="TP4" gate="G$1" x="40.64" y="78.74"/>
+<instance part="P_5" gate="1" x="91.44" y="83.82"/>
+<instance part="LED1" gate="G$1" x="86.36" y="78.74" rot="R270"/>
+</instances>
+<busses>
+</busses>
+<nets>
+<net name="N$1" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA24"/>
+<wire x1="58.42" y1="48.26" x2="76.2" y2="48.26" width="0.1524" layer="91"/>
+<wire x1="76.2" y1="48.26" x2="76.2" y2="53.34" width="0.1524" layer="91"/>
+<wire x1="76.2" y1="53.34" x2="78.74" y2="53.34" width="0.1524" layer="91"/>
+<pinref part="X1" gate="G$1" pin="2"/>
+</segment>
+</net>
+<net name="N$2" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA25"/>
+<wire x1="58.42" y1="50.8" x2="78.74" y2="50.8" width="0.1524" layer="91"/>
+<pinref part="X1" gate="G$1" pin="3"/>
+</segment>
+</net>
+<net name="GND" class="0">
+<segment>
+<pinref part="P_17" gate="1" pin="GND"/>
+<wire x1="76.2" y1="43.18" x2="76.2" y2="45.72" width="0.1524" layer="91"/>
+<wire x1="76.2" y1="45.72" x2="78.74" y2="45.72" width="0.1524" layer="91"/>
+<pinref part="X1" gate="G$1" pin="5"/>
+</segment>
+<segment>
+<pinref part="IC1" gate="G$1" pin="GND"/>
+<pinref part="P_4" gate="1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="C1" gate="G$1" pin="1"/>
+<pinref part="P_1" gate="1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="C2" gate="G$1" pin="1"/>
+<pinref part="P_6" gate="1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="GND"/>
+<pinref part="P_8" gate="1" pin="GND"/>
+<wire x1="58.42" y1="53.34" x2="60.96" y2="53.34" width="0.1524" layer="91"/>
+<wire x1="60.96" y1="53.34" x2="60.96" y2="43.18" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="P_2" gate="1" pin="GND"/>
+<wire x1="38.1" y1="78.74" x2="40.64" y2="78.74" width="0.1524" layer="91"/>
+<pinref part="TP4" gate="G$1" pin="1"/>
+</segment>
+<segment>
+<pinref part="P_11" gate="1" pin="GND"/>
+<pinref part="J8" gate="G$1" pin="1"/>
+<wire x1="86.36" y1="93.98" x2="88.9" y2="93.98" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="V_USB" class="0">
+<segment>
+<pinref part="P_16" gate="1" pin="V_USB"/>
+<wire x1="76.2" y1="58.42" x2="76.2" y2="55.88" width="0.1524" layer="91"/>
+<wire x1="76.2" y1="55.88" x2="78.74" y2="55.88" width="0.1524" layer="91"/>
+<pinref part="X1" gate="G$1" pin="1"/>
+</segment>
+<segment>
+<pinref part="IC1" gate="G$1" pin="EN"/>
+<pinref part="P_3" gate="1" pin="V_USB"/>
+<wire x1="27.94" y1="20.32" x2="25.4" y2="20.32" width="0.1524" layer="91"/>
+<wire x1="25.4" y1="20.32" x2="25.4" y2="22.86" width="0.1524" layer="91"/>
+<pinref part="IC1" gate="G$1" pin="IN"/>
+<wire x1="25.4" y1="22.86" x2="25.4" y2="25.4" width="0.1524" layer="91"/>
+<wire x1="27.94" y1="22.86" x2="25.4" y2="22.86" width="0.1524" layer="91"/>
+<junction x="25.4" y="22.86"/>
+<pinref part="C1" gate="G$1" pin="2"/>
+<wire x1="25.4" y1="22.86" x2="20.32" y2="22.86" width="0.1524" layer="91"/>
+<wire x1="20.32" y1="22.86" x2="20.32" y2="20.32" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="+3V3" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="OUT"/>
+<wire x1="48.26" y1="22.86" x2="53.34" y2="22.86" width="0.1524" layer="91"/>
+<pinref part="C2" gate="G$1" pin="2"/>
+<wire x1="53.34" y1="20.32" x2="53.34" y2="22.86" width="0.1524" layer="91"/>
+<junction x="53.34" y="22.86"/>
+<pinref part="P_9" gate="1" pin="+3V3"/>
+<wire x1="53.34" y1="25.4" x2="53.34" y2="22.86" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="VDD"/>
+<pinref part="P_7" gate="1" pin="+3V3"/>
+<wire x1="58.42" y1="55.88" x2="60.96" y2="55.88" width="0.1524" layer="91"/>
+<wire x1="60.96" y1="55.88" x2="60.96" y2="63.5" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="R6" gate="G$1" pin="2"/>
+<pinref part="P_18" gate="1" pin="+3V3"/>
+</segment>
+<segment>
+<pinref part="R5" gate="G$1" pin="2"/>
+<pinref part="P_19" gate="1" pin="+3V3"/>
+</segment>
+<segment>
+<wire x1="88.9" y1="78.74" x2="91.44" y2="78.74" width="0.1524" layer="91"/>
+<pinref part="P_5" gate="1" pin="+3V3"/>
+<wire x1="91.44" y1="81.28" x2="91.44" y2="78.74" width="0.1524" layer="91"/>
+<pinref part="LED1" gate="G$1" pin="A"/>
+</segment>
+</net>
+<net name="SWDIO" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA31/SIO"/>
+<wire x1="58.42" y1="45.72" x2="63.5" y2="45.72" width="0.1524" layer="91"/>
+<label x="63.5" y="45.72" size="1.27" layer="95"/>
+</segment>
+<segment>
+<wire x1="40.64" y1="86.36" x2="22.86" y2="86.36" width="0.1524" layer="91"/>
+<label x="22.86" y="86.36" size="1.27" layer="95" rot="MR0"/>
+<pinref part="TP1" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="PA02" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA02"/>
+<wire x1="58.42" y1="58.42" x2="63.5" y2="58.42" width="0.1524" layer="91"/>
+<label x="63.5" y="58.42" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="PA04" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA04"/>
+<wire x1="58.42" y1="60.96" x2="63.5" y2="60.96" width="0.1524" layer="91"/>
+<label x="63.5" y="60.96" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="SWCLK" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA30/SCK"/>
+<wire x1="22.86" y1="45.72" x2="20.32" y2="45.72" width="0.1524" layer="91"/>
+<label x="20.32" y="45.72" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<wire x1="40.64" y1="83.82" x2="33.02" y2="83.82" width="0.1524" layer="91"/>
+<label x="22.86" y="83.82" size="1.27" layer="95" rot="MR0"/>
+<pinref part="R6" gate="G$1" pin="1"/>
+<wire x1="33.02" y1="83.82" x2="22.86" y2="83.82" width="0.1524" layer="91"/>
+<wire x1="33.02" y1="88.9" x2="33.02" y2="83.82" width="0.1524" layer="91"/>
+<junction x="33.02" y="83.82"/>
+<pinref part="TP2" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="RESET" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA28/RST"/>
+<wire x1="22.86" y1="48.26" x2="20.32" y2="48.26" width="0.1524" layer="91"/>
+<label x="20.32" y="48.26" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<wire x1="40.64" y1="81.28" x2="38.1" y2="81.28" width="0.1524" layer="91"/>
+<label x="22.86" y="81.28" size="1.27" layer="95" rot="MR0"/>
+<pinref part="R5" gate="G$1" pin="1"/>
+<wire x1="38.1" y1="81.28" x2="22.86" y2="81.28" width="0.1524" layer="91"/>
+<wire x1="38.1" y1="88.9" x2="38.1" y2="81.28" width="0.1524" layer="91"/>
+<junction x="38.1" y="81.28"/>
+<pinref part="TP3" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="PA15" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA15"/>
+<wire x1="22.86" y1="50.8" x2="20.32" y2="50.8" width="0.1524" layer="91"/>
+<label x="20.32" y="50.8" size="1.27" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="PA14" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA14"/>
+<wire x1="22.86" y1="53.34" x2="20.32" y2="53.34" width="0.1524" layer="91"/>
+<label x="20.32" y="53.34" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<wire x1="68.58" y1="78.74" x2="66.04" y2="78.74" width="0.1524" layer="91"/>
+<label x="66.04" y="78.74" size="1.27" layer="95" rot="MR0"/>
+<pinref part="R7" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="PA09" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA9"/>
+<wire x1="22.86" y1="55.88" x2="20.32" y2="55.88" width="0.1524" layer="91"/>
+<label x="20.32" y="55.88" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="R4" gate="G$1" pin="1"/>
+<wire x1="66.04" y1="91.44" x2="63.5" y2="91.44" width="0.1524" layer="91"/>
+<label x="63.5" y="91.44" size="1.27" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="PA08" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA8"/>
+<wire x1="22.86" y1="58.42" x2="20.32" y2="58.42" width="0.1524" layer="91"/>
+<label x="20.32" y="58.42" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="R3" gate="G$1" pin="1"/>
+<wire x1="66.04" y1="96.52" x2="63.5" y2="96.52" width="0.1524" layer="91"/>
+<label x="63.5" y="96.52" size="1.27" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="PA05" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA5"/>
+<wire x1="22.86" y1="60.96" x2="20.32" y2="60.96" width="0.1524" layer="91"/>
+<label x="20.32" y="60.96" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="R2" gate="G$1" pin="1"/>
+<wire x1="66.04" y1="101.6" x2="63.5" y2="101.6" width="0.1524" layer="91"/>
+<label x="63.5" y="101.6" size="1.27" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="N$3" class="0">
+<segment>
+<pinref part="R2" gate="G$1" pin="2"/>
+<pinref part="J5" gate="G$1" pin="1"/>
+<wire x1="76.2" y1="101.6" x2="88.9" y2="101.6" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="N$4" class="0">
+<segment>
+<pinref part="R3" gate="G$1" pin="2"/>
+<wire x1="76.2" y1="96.52" x2="78.74" y2="96.52" width="0.1524" layer="91"/>
+<wire x1="78.74" y1="96.52" x2="78.74" y2="99.06" width="0.1524" layer="91"/>
+<pinref part="J6" gate="G$1" pin="1"/>
+<wire x1="78.74" y1="99.06" x2="88.9" y2="99.06" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="N$5" class="0">
+<segment>
+<pinref part="R4" gate="G$1" pin="2"/>
+<wire x1="76.2" y1="91.44" x2="81.28" y2="91.44" width="0.1524" layer="91"/>
+<wire x1="81.28" y1="91.44" x2="81.28" y2="96.52" width="0.1524" layer="91"/>
+<pinref part="J7" gate="G$1" pin="1"/>
+<wire x1="81.28" y1="96.52" x2="88.9" y2="96.52" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="N$6" class="0">
+<segment>
+<pinref part="R7" gate="G$1" pin="2"/>
+<wire x1="78.74" y1="78.74" x2="81.28" y2="78.74" width="0.1524" layer="91"/>
+<pinref part="LED1" gate="G$1" pin="C"/>
+</segment>
+</net>
+</nets>
+</sheet>
+</sheets>
+</schematic>
+</drawing>
+<compatibility>
+<note version="6.3" minversion="6.2.2" severity="warning">
+Since Version 6.2.2 text objects can contain more than one line,
+which will not be processed correctly with this version.
+</note>
+</compatibility>
+</eagle>

dap_link/lib/free-dap/hardware/d11_usb_std/d11_usb_std.brd

@@ -0,0 +1,807 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="7.3.0">
+<drawing>
+<settings>
+<setting alwaysvectorfont="no"/>
+<setting verticaltext="up"/>
+</settings>
+<grid distance="0.01" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.025" altunitdist="inch" altunit="inch"/>
+<layers>
+<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>
+<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="yes"/>
+<layer number="17" name="Pads" color="2" fill="1" visible="yes" active="yes"/>
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+<wire x1="0.7266" y1="-3.8414" x2="0.519" y2="-4.049" width="0.1016" layer="21" curve="90"/>
+<wire x1="0.519" y1="-4.049" x2="0.519" y2="-4.2048" width="0.1016" layer="21"/>
+<wire x1="0.519" y1="-4.2048" x2="2.907" y2="-4.2048" width="0.1016" layer="51"/>
+<wire x1="2.907" y1="-4.2048" x2="3.4781" y2="-3.6337" width="0.1016" layer="51" curve="90.020069"/>
+<wire x1="-1.8171" y1="-2.9589" x2="-4.5685" y2="-2.7512" width="0.1016" layer="21"/>
+<wire x1="-4.5685" y1="-2.7512" x2="-4.828" y2="-2.5436" width="0.1016" layer="21" curve="-68.629849"/>
+<wire x1="-4.828" y1="-2.5436" x2="-4.828" y2="-1.9725" width="0.1016" layer="21" curve="-34.099487"/>
+<wire x1="-4.828" y1="-1.9725" x2="-4.5685" y2="-1.7649" width="0.1016" layer="21" curve="-68.629849"/>
+<wire x1="-4.5685" y1="-1.7649" x2="-1.8171" y2="-1.5053" width="0.1016" layer="21"/>
+<wire x1="-1.8171" y1="-1.5053" x2="-1.8171" y2="-1.713" width="0.1016" layer="21"/>
+<wire x1="-1.8171" y1="-1.713" x2="-4.2051" y2="-1.9725" width="0.1016" layer="21"/>
+<wire x1="-4.2051" y1="-1.9725" x2="-4.2051" y2="-2.4917" width="0.1016" layer="21"/>
+<wire x1="-4.2051" y1="-2.4917" x2="-1.8171" y2="-2.7512" width="0.1016" layer="21"/>
+<wire x1="-1.8171" y1="-2.7512" x2="-1.8171" y2="-2.9589" width="0.1016" layer="21"/>
+<wire x1="2.8032" y1="-3.8414" x2="3.0627" y2="-3.5819" width="0.1016" layer="51" curve="90.044176"/>
+<wire x1="3.0627" y1="-3.5819" x2="3.0627" y2="-3.0108" width="0.1016" layer="51"/>
+<wire x1="3.0627" y1="-3.0108" x2="3.4261" y2="-3.0108" width="0.1016" layer="21"/>
+<wire x1="1.713" y1="-4.2567" x2="1.713" y2="-4.8797" width="0.1016" layer="51"/>
+<wire x1="1.713" y1="-4.8797" x2="2.1283" y2="-4.8797" width="0.1016" layer="51"/>
+<wire x1="2.1283" y1="-4.8797" x2="2.1283" y2="-4.4644" width="0.1016" layer="51"/>
+<wire x1="2.1283" y1="-4.4644" x2="2.6474" y2="-4.4644" width="0.1016" layer="51"/>
+<wire x1="2.6474" y1="-4.4644" x2="2.6474" y2="-4.8797" width="0.1016" layer="51"/>
+<wire x1="2.6474" y1="-4.8797" x2="3.0627" y2="-4.8797" width="0.1016" layer="51"/>
+<wire x1="3.0627" y1="-4.8797" x2="3.0627" y2="-4.2567" width="0.1016" layer="51"/>
+<wire x1="1.0381" y1="-1.8168" x2="0.8305" y2="-2.0244" width="0.1016" layer="21" curve="-90.055225"/>
+<wire x1="0.8304" y1="-2.0244" x2="0.5709" y2="-1.7649" width="0.1016" layer="21" curve="-89.867677"/>
+<wire x1="1.5573" y1="-1.9725" x2="1.5573" y2="2.0248" width="0.1016" layer="51"/>
+<wire x1="1.5573" y1="2.0248" x2="3.4261" y2="2.0248" width="0.1016" layer="21"/>
+<wire x1="-4.5684" y1="-1.2457" x2="-0.5192" y2="-1.0381" width="0.1016" layer="21"/>
+<wire x1="-0.5192" y1="-1.0381" x2="-0.3116" y2="-0.8304" width="0.1016" layer="21" curve="83.722654"/>
+<wire x1="-0.3116" y1="-0.8304" x2="-0.3116" y2="0.8307" width="0.1016" layer="21"/>
+<wire x1="-4.5685" y1="-1.2457" x2="-4.7761" y2="-1.0381" width="0.1016" layer="21" curve="-90"/>
+<wire x1="-4.7761" y1="-1.038" x2="-4.5685" y2="-0.8304" width="0.1016" layer="21" curve="-90"/>
+<wire x1="-4.5685" y1="-0.8304" x2="-1.1422" y2="-0.6228" width="0.1016" layer="21"/>
+<wire x1="-1.1422" y1="-0.6228" x2="-1.1422" y2="0.6232" width="0.1016" layer="21"/>
+<wire x1="-1.5826" y1="-3.8414" x2="0.7267" y2="-3.8415" width="0.1016" layer="21"/>
+<wire x1="-5.9182" y1="-3.8414" x2="-4.4146" y2="-3.8414" width="0.1016" layer="21"/>
+<wire x1="-5.9182" y1="3.8416" x2="-4.4147" y2="3.8415" width="0.1016" layer="21"/>
+<wire x1="-2.3093" y1="3.8416" x2="0.7265" y2="3.8415" width="0.1016" layer="51"/>
+<wire x1="3.4781" y1="-2.0245" x2="3.4781" y2="-3.0109" width="0.1016" layer="21"/>
+<wire x1="3.4781" y1="3.634" x2="3.478" y2="-3.0109" width="0.1016" layer="51"/>
+<wire x1="3.4782" y1="3.011" x2="3.4782" y2="2.0246" width="0.1016" layer="21"/>
+<smd name="M1" x="-3" y="-4.45" dx="2.5" dy="2" layer="1"/>
+<smd name="M2" x="-3" y="4.45" dx="2.5" dy="2" layer="1"/>
+<smd name="M4" x="2.9" y="-4.45" dx="3.3" dy="2" layer="1"/>
+<smd name="M3" x="2.9" y="4.45" dx="3.3" dy="2" layer="1"/>
+<smd name="1" x="3" y="1.6" dx="3.1" dy="0.5" layer="1"/>
+<smd name="2" x="3" y="0.8" dx="3.1" dy="0.5" layer="1"/>
+<smd name="3" x="3" y="0" dx="3.1" dy="0.5" layer="1"/>
+<smd name="4" x="3" y="-0.8" dx="3.1" dy="0.5" layer="1"/>
+<smd name="5" x="3" y="-1.6" dx="3.1" dy="0.5" layer="1"/>
+<text x="-4.445" y="5.715" size="1.27" layer="25">&gt;NAME</text>
+<text x="-4.445" y="-6.985" size="1.27" layer="27">&gt;VALUE</text>
+<hole x="0" y="2.2" drill="0.9"/>
+<hole x="0" y="-2.2" drill="0.9"/>
+</package>
+</packages>
+</library>
+<library name="ataradov_misc">
+<description>Alex Taradov Library (Miscellaneous stuff)</description>
+<packages>
+<package name="TP-1.27MM">
+<smd name="1" x="0" y="0" dx="1.27" dy="1.27" layer="1" roundness="100" cream="no"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+</packages>
+</library>
+<library name="ataradov_led">
+<description>Alex Taradov Library (LEDs and other indication devices)</description>
+<packages>
+<package name="SMD0603">
+<wire x1="-1.5" y1="0.75" x2="1.5" y2="0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="0.75" x2="1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="-0.75" x2="-1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="-1.5" y1="-0.75" x2="-1.5" y2="0.75" width="0.1" layer="21"/>
+<smd name="1" x="-0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<smd name="2" x="0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+</packages>
+</library>
+</libraries>
+<attributes>
+</attributes>
+<variantdefs>
+</variantdefs>
+<classes>
+<class number="0" name="default" width="0" drill="0">
+</class>
+</classes>
+<designrules name="OSHPark">
+<description language="de">&lt;b&gt;EAGLE Design Rules&lt;/b&gt;
+&lt;p&gt;
+Die Standard-Design-Rules sind so gewählt, dass sie für 
+die meisten Anwendungen passen. Sollte ihre Platine 
+besondere Anforderungen haben, treffen Sie die erforderlichen
+Einstellungen hier und speichern die Design Rules unter 
+einem neuen Namen ab.</description>
+<description language="en">&lt;b&gt;Laen's PCB Order Design Rules&lt;/b&gt;
+&lt;p&gt;
+Please make sure your boards conform to these design rules.</description>
+<param name="layerSetup" value="(1*16)"/>
+<param name="mtCopper" value="0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm"/>
+<param name="mtIsolate" value="1.5011mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm"/>
+<param name="mdWireWire" value="6mil"/>
+<param name="mdWirePad" value="6mil"/>
+<param name="mdWireVia" value="6mil"/>
+<param name="mdPadPad" value="6mil"/>
+<param name="mdPadVia" value="6mil"/>
+<param name="mdViaVia" value="6mil"/>
+<param name="mdSmdPad" value="6mil"/>
+<param name="mdSmdVia" value="6mil"/>
+<param name="mdSmdSmd" value="6mil"/>
+<param name="mdViaViaSameLayer" value="8mil"/>
+<param name="mnLayersViaInSmd" value="2"/>
+<param name="mdCopperDimension" value="15mil"/>
+<param name="mdDrill" value="6mil"/>
+<param name="mdSmdStop" value="0mil"/>
+<param name="msWidth" value="6mil"/>
+<param name="msDrill" value="13mil"/>
+<param name="msMicroVia" value="13mil"/>
+<param name="msBlindViaRatio" value="0.5"/>
+<param name="rvPadTop" value="0.25"/>
+<param name="rvPadInner" value="0.25"/>
+<param name="rvPadBottom" value="0.25"/>
+<param name="rvViaOuter" value="0.25"/>
+<param name="rvViaInner" value="0.25"/>
+<param name="rvMicroViaOuter" value="0.25"/>
+<param name="rvMicroViaInner" value="0.25"/>
+<param name="rlMinPadTop" value="7mil"/>
+<param name="rlMaxPadTop" value="20mil"/>
+<param name="rlMinPadInner" value="7mil"/>
+<param name="rlMaxPadInner" value="20mil"/>
+<param name="rlMinPadBottom" value="7mil"/>
+<param name="rlMaxPadBottom" value="20mil"/>
+<param name="rlMinViaOuter" value="7mil"/>
+<param name="rlMaxViaOuter" value="20mil"/>
+<param name="rlMinViaInner" value="7mil"/>
+<param name="rlMaxViaInner" value="20mil"/>
+<param name="rlMinMicroViaOuter" value="4mil"/>
+<param name="rlMaxMicroViaOuter" value="20mil"/>
+<param name="rlMinMicroViaInner" value="4mil"/>
+<param name="rlMaxMicroViaInner" value="20mil"/>
+<param name="psTop" value="-1"/>
+<param name="psBottom" value="-1"/>
+<param name="psFirst" value="-1"/>
+<param name="psElongationLong" value="100"/>
+<param name="psElongationOffset" value="100"/>
+<param name="mvStopFrame" value="1"/>
+<param name="mvCreamFrame" value="0"/>
+<param name="mlMinStopFrame" value="3mil"/>
+<param name="mlMaxStopFrame" value="3mil"/>
+<param name="mlMinCreamFrame" value="0mil"/>
+<param name="mlMaxCreamFrame" value="0mil"/>
+<param name="mlViaStopLimit" value="0mil"/>
+<param name="srRoundness" value="0"/>
+<param name="srMinRoundness" value="0mil"/>
+<param name="srMaxRoundness" value="0mil"/>
+<param name="slThermalIsolate" value="10mil"/>
+<param name="slThermalsForVias" value="0"/>
+<param name="dpMaxLengthDifference" value="10mm"/>
+<param name="dpGapFactor" value="2.5"/>
+<param name="checkGrid" value="0"/>
+<param name="checkAngle" value="0"/>
+<param name="checkFont" value="1"/>
+<param name="checkRestrict" value="1"/>
+<param name="useDiameter" value="13"/>
+<param name="maxErrors" value="50"/>
+</designrules>
+<autorouter>
+<pass name="Default">
+<param name="RoutingGrid" value="50mil"/>
+<param name="AutoGrid" value="1"/>
+<param name="Efforts" value="0"/>
+<param name="TopRouterVariant" value="1"/>
+<param name="tpViaShape" value="round"/>
+<param name="PrefDir.1" value="a"/>
+<param name="PrefDir.2" value="0"/>
+<param name="PrefDir.3" value="0"/>
+<param name="PrefDir.4" value="0"/>
+<param name="PrefDir.5" value="0"/>
+<param name="PrefDir.6" value="0"/>
+<param name="PrefDir.7" value="0"/>
+<param name="PrefDir.8" value="0"/>
+<param name="PrefDir.9" value="0"/>
+<param name="PrefDir.10" value="0"/>
+<param name="PrefDir.11" value="0"/>
+<param name="PrefDir.12" value="0"/>
+<param name="PrefDir.13" value="0"/>
+<param name="PrefDir.14" value="0"/>
+<param name="PrefDir.15" value="0"/>
+<param name="PrefDir.16" value="a"/>
+<param name="cfVia" value="8"/>
+<param name="cfNonPref" value="5"/>
+<param name="cfChangeDir" value="2"/>
+<param name="cfOrthStep" value="2"/>
+<param name="cfDiagStep" value="3"/>
+<param name="cfExtdStep" value="0"/>
+<param name="cfBonusStep" value="1"/>
+<param name="cfMalusStep" value="1"/>
+<param name="cfPadImpact" value="4"/>
+<param name="cfSmdImpact" value="4"/>
+<param name="cfBusImpact" value="0"/>
+<param name="cfHugging" value="3"/>
+<param name="cfAvoid" value="4"/>
+<param name="cfPolygon" value="10"/>
+<param name="cfBase.1" value="0"/>
+<param name="cfBase.2" value="1"/>
+<param name="cfBase.3" value="1"/>
+<param name="cfBase.4" value="1"/>
+<param name="cfBase.5" value="1"/>
+<param name="cfBase.6" value="1"/>
+<param name="cfBase.7" value="1"/>
+<param name="cfBase.8" value="1"/>
+<param name="cfBase.9" value="1"/>
+<param name="cfBase.10" value="1"/>
+<param name="cfBase.11" value="1"/>
+<param name="cfBase.12" value="1"/>
+<param name="cfBase.13" value="1"/>
+<param name="cfBase.14" value="1"/>
+<param name="cfBase.15" value="1"/>
+<param name="cfBase.16" value="0"/>
+<param name="mnVias" value="20"/>
+<param name="mnSegments" value="9999"/>
+<param name="mnExtdSteps" value="9999"/>
+<param name="mnRipupLevel" value="10"/>
+<param name="mnRipupSteps" value="100"/>
+<param name="mnRipupTotal" value="100"/>
+</pass>
+<pass name="Follow-me" refer="Default" active="yes">
+</pass>
+<pass name="Busses" refer="Default" active="yes">
+<param name="cfNonPref" value="4"/>
+<param name="cfBusImpact" value="4"/>
+<param name="cfHugging" value="0"/>
+<param name="mnVias" value="0"/>
+</pass>
+<pass name="Route" refer="Default" active="yes">
+</pass>
+<pass name="Optimize1" refer="Default" active="yes">
+<param name="cfVia" value="99"/>
+<param name="cfExtdStep" value="10"/>
+<param name="cfHugging" value="1"/>
+<param name="mnExtdSteps" value="1"/>
+<param name="mnRipupLevel" value="0"/>
+</pass>
+<pass name="Optimize2" refer="Optimize1" active="yes">
+<param name="cfNonPref" value="0"/>
+<param name="cfChangeDir" value="6"/>
+<param name="cfExtdStep" value="0"/>
+<param name="cfBonusStep" value="2"/>
+<param name="cfMalusStep" value="2"/>
+<param name="cfPadImpact" value="2"/>
+<param name="cfSmdImpact" value="2"/>
+<param name="cfHugging" value="0"/>
+</pass>
+<pass name="Optimize3" refer="Optimize2" active="yes">
+<param name="cfChangeDir" value="8"/>
+<param name="cfPadImpact" value="0"/>
+<param name="cfSmdImpact" value="0"/>
+</pass>
+<pass name="Optimize4" refer="Optimize3" active="yes">
+<param name="cfChangeDir" value="25"/>
+</pass>
+</autorouter>
+<elements>
+<element name="IC2" library="ataradov_mcu" package="SO-14" value="ATSAMD11C" x="4.826" y="7.366" smashed="yes" rot="MR270">
+<attribute name="NAME" x="4.826" y="12.192" size="1.27" layer="26" font="vector" rot="MR0" align="bottom-center"/>
+</element>
+<element name="C1" library="ataradov_rlc" package="SMD0603" value="1uF" x="11.684" y="8.382" rot="R180"/>
+<element name="C2" library="ataradov_rlc" package="SMD0603" value="1uF" x="11.684" y="2.54" smashed="yes">
+<attribute name="NAME" x="11.684" y="3.556" size="1.27" layer="25" font="vector" align="bottom-center"/>
+</element>
+<element name="R2" library="ataradov_rlc" package="SMD0603" value="330" x="11.684" y="4.826" rot="MR0"/>
+<element name="R3" library="ataradov_rlc" package="SMD0603" value="330" x="11.684" y="6.35" rot="MR0"/>
+<element name="R4" library="ataradov_rlc" package="SMD0603" value="330" x="11.684" y="7.874" rot="MR0"/>
+<element name="IC1" library="ataradov_vreg" package="SOT23-5" value="MIC5504-3.3" x="11.684" y="5.334" smashed="yes" rot="R180">
+<attribute name="NAME" x="11.684" y="3.048" size="1.27" layer="25" font="vector" rot="R180" align="bottom-center"/>
+</element>
+<element name="R5" library="ataradov_rlc" package="SMD0603" value="100K" x="11.684" y="3.302" rot="MR180"/>
+<element name="R6" library="ataradov_rlc" package="SMD0603" value="100K" x="11.684" y="1.778" rot="MR180"/>
+<element name="X1" library="con-cypressindustries" package="32005-201" value="MINI-USB-32005-201" x="4.826" y="6.096" smashed="yes">
+<attribute name="MF" value="" x="4.826" y="6.096" size="1.778" layer="27" display="off"/>
+<attribute name="MPN" value="" x="4.826" y="6.096" size="1.778" layer="27" display="off"/>
+<attribute name="OC_FARNELL" value="unknown" x="4.826" y="6.096" size="1.778" layer="27" display="off"/>
+<attribute name="OC_NEWARK" value="unknown" x="4.826" y="6.096" size="1.778" layer="27" display="off"/>
+<attribute name="NAME" x="0.381" y="11.811" size="1.27" layer="25"/>
+</element>
+<element name="R7" library="ataradov_rlc" package="SMD0603" value="330" x="11.684" y="10.922"/>
+<element name="TP1" library="ataradov_misc" package="TP-1.27MM" value="SIO" x="4.318" y="1.524" rot="MR0"/>
+<element name="TP2" library="ataradov_misc" package="TP-1.27MM" value="" x="9.398" y="1.524" rot="MR0"/>
+<element name="TP3" library="ataradov_misc" package="TP-1.27MM" value="" x="6.858" y="1.524" rot="MR0"/>
+<element name="TP4" library="ataradov_misc" package="TP-1.27MM" value="" x="1.778" y="1.524" rot="MR0"/>
+<element name="LED1" library="ataradov_led" package="SMD0603" value="" x="11.684" y="9.652" rot="R180"/>
+<element name="J1" library="ataradov_conn" package="HEADER-5X2-1.27MM" value="HEADER-5X2-TH-1.27" x="15.494" y="6.096" rot="R90"/>
+<element name="R1" library="ataradov_rlc" package="SMD0603" value="330" x="11.684" y="9.398" rot="MR0"/>
+<element name="R8" library="ataradov_rlc" package="SMD0603" value="330" x="11.684" y="10.922" rot="MR0"/>
+</elements>
+<signals>
+<signal name="GND">
+<contactref element="IC1" pad="2"/>
+<contactref element="C1" pad="1"/>
+<contactref element="C2" pad="1"/>
+<contactref element="IC2" pad="11"/>
+<contactref element="X1" pad="5"/>
+<contactref element="TP4" pad="1"/>
+<contactref element="J1" pad="3"/>
+<contactref element="J1" pad="5"/>
+<wire x1="2.226" y1="7.366" x2="1.016" y2="7.366" width="0.254" layer="16"/>
+<wire x1="1.016" y1="7.366" x2="0.762" y2="7.112" width="0.254" layer="16"/>
+<wire x1="0.762" y1="7.112" x2="0.762" y2="2.032" width="0.254" layer="16"/>
+<wire x1="0.762" y1="2.032" x2="1.27" y2="1.524" width="0.254" layer="16"/>
+<wire x1="1.27" y1="1.524" x2="1.778" y2="1.524" width="0.254" layer="16"/>
+<wire x1="7.826" y1="4.496" x2="7.75" y2="4.572" width="0.254" layer="1"/>
+<wire x1="7.75" y1="4.572" x2="5.842" y2="4.572" width="0.254" layer="1"/>
+<wire x1="5.842" y1="4.572" x2="5.334" y2="5.08" width="0.254" layer="1"/>
+<wire x1="5.334" y1="5.08" x2="4.826" y2="5.08" width="0.254" layer="1"/>
+<wire x1="4.826" y1="5.08" x2="4.572" y2="4.826" width="0.254" layer="1"/>
+<wire x1="4.572" y1="4.826" x2="3.556" y2="4.826" width="0.254" layer="1"/>
+<wire x1="3.556" y1="4.826" x2="3.048" y2="5.334" width="0.254" layer="1"/>
+<wire x1="3.048" y1="5.334" x2="3.048" y2="6.604" width="0.254" layer="1"/>
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+<contactref element="IC2" pad="6"/>
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+<signal name="N$8">
+</signal>
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+<contactref element="J1" pad="2"/>
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+<signal name="PA05">
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+</signals>
+</board>
+</drawing>
+</eagle>

dap_link/lib/free-dap/hardware/d11_usb_std/d11_usb_std.sch

@@ -0,0 +1,1430 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="7.3.0">
+<drawing>
+<settings>
+<setting alwaysvectorfont="no"/>
+<setting verticaltext="up"/>
+</settings>
+<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>
+<layers>
+<layer number="1" name="Top" color="4" fill="1" visible="no" active="no"/>
+<layer number="16" name="Bottom" color="1" fill="1" visible="no" active="no"/>
+<layer number="17" name="Pads" color="2" fill="1" visible="no" active="no"/>
+<layer number="18" name="Vias" color="2" fill="1" visible="no" active="no"/>
+<layer number="19" name="Unrouted" color="6" fill="1" visible="no" active="no"/>
+<layer number="20" name="Dimension" color="15" fill="1" visible="no" active="no"/>
+<layer number="21" name="tPlace" color="7" fill="1" visible="no" active="no"/>
+<layer number="22" name="bPlace" color="7" fill="1" visible="no" active="no"/>
+<layer number="23" name="tOrigins" color="15" fill="1" visible="no" active="no"/>
+<layer number="24" name="bOrigins" color="15" fill="1" visible="no" active="no"/>
+<layer number="25" name="tNames" color="7" fill="1" visible="no" active="no"/>
+<layer number="26" name="bNames" color="7" fill="1" visible="no" active="no"/>
+<layer number="27" name="tValues" color="7" fill="1" visible="no" active="no"/>
+<layer number="28" name="bValues" color="7" fill="1" visible="no" active="no"/>
+<layer number="29" name="tStop" color="7" fill="3" visible="no" active="no"/>
+<layer number="30" name="bStop" color="7" fill="6" visible="no" active="no"/>
+<layer number="31" name="tCream" color="7" fill="4" visible="no" active="no"/>
+<layer number="32" name="bCream" color="7" fill="5" visible="no" active="no"/>
+<layer number="33" name="tFinish" color="6" fill="3" visible="no" active="no"/>
+<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="no"/>
+<layer number="35" name="tGlue" color="7" fill="4" visible="no" active="no"/>
+<layer number="36" name="bGlue" color="7" fill="5" visible="no" active="no"/>
+<layer number="37" name="tTest" color="7" fill="1" visible="no" active="no"/>
+<layer number="38" name="bTest" color="7" fill="1" visible="no" active="no"/>
+<layer number="39" name="tKeepout" color="4" fill="11" visible="no" active="no"/>
+<layer number="40" name="bKeepout" color="1" fill="11" visible="no" active="no"/>
+<layer number="41" name="tRestrict" color="4" fill="10" visible="no" active="no"/>
+<layer number="42" name="bRestrict" color="1" fill="10" visible="no" active="no"/>
+<layer number="43" name="vRestrict" color="2" fill="10" visible="no" active="no"/>
+<layer number="44" name="Drills" color="7" fill="1" visible="no" active="no"/>
+<layer number="45" name="Holes" color="7" fill="1" visible="no" active="no"/>
+<layer number="46" name="Milling" color="3" fill="1" visible="no" active="no"/>
+<layer number="47" name="Measures" color="7" fill="1" visible="no" active="no"/>
+<layer number="48" name="Document" color="7" fill="1" visible="no" active="no"/>
+<layer number="49" name="Reference" color="7" fill="1" visible="no" active="no"/>
+<layer number="51" name="tDocu" color="6" fill="1" visible="no" active="no"/>
+<layer number="52" name="bDocu" color="7" fill="1" visible="no" active="no"/>
+<layer number="90" name="Modules" color="5" fill="1" visible="yes" active="yes"/>
+<layer number="91" name="Nets" color="2" fill="1" visible="yes" active="yes"/>
+<layer number="92" name="Busses" color="1" fill="1" visible="yes" active="yes"/>
+<layer number="93" name="Pins" color="2" fill="1" visible="no" active="yes"/>
+<layer number="94" name="Symbols" color="4" fill="1" visible="yes" active="yes"/>
+<layer number="95" name="Names" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="96" name="Values" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="97" name="Info" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/>
+</layers>
+<schematic xreflabel="%F%N/%S.%C%R" xrefpart="/%S.%C%R">
+<libraries>
+<library name="ataradov_mcu">
+<description>Alex Taradov Library (MCUs)</description>
+<packages>
+<package name="SO-14">
+<description>SO-14</description>
+<wire x1="4.305" y1="-1.9" x2="-4.305" y2="-1.9" width="0.2032" layer="51"/>
+<wire x1="-4.305" y1="-1.9" x2="-4.305" y2="-1.4" width="0.2032" layer="51"/>
+<wire x1="-4.305" y1="-1.4" x2="-4.305" y2="1.9" width="0.2032" layer="51"/>
+<wire x1="4.305" y1="-1.4" x2="-4.305" y2="-1.4" width="0.2032" layer="51"/>
+<wire x1="4.305" y1="1.9" x2="4.305" y2="-1.4" width="0.2032" layer="51"/>
+<wire x1="4.305" y1="-1.4" x2="4.305" y2="-1.9" width="0.2032" layer="51"/>
+<wire x1="-4.305" y1="1.9" x2="4.305" y2="1.9" width="0.2032" layer="51"/>
+<smd name="2" x="-2.54" y="-2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="13" x="-2.54" y="2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="1" x="-3.81" y="-2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="3" x="-1.27" y="-2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="4" x="0" y="-2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="14" x="-3.81" y="2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="12" x="-1.27" y="2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="11" x="0" y="2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="6" x="2.54" y="-2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="9" x="2.54" y="2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="5" x="1.27" y="-2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="7" x="3.81" y="-2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="10" x="1.27" y="2.6" dx="0.6" dy="2.2" layer="1"/>
+<smd name="8" x="3.81" y="2.6" dx="0.6" dy="2.2" layer="1"/>
+<text x="-4.826" y="0" size="1.27" layer="25" font="vector" rot="R90" align="bottom-center">&gt;NAME</text>
+<text x="6.096" y="0" size="1.27" layer="27" font="vector" rot="R90" align="bottom-center">&gt;VALUE</text>
+<rectangle x1="-4.0551" y1="-3.1001" x2="-3.5649" y2="-2" layer="51"/>
+<rectangle x1="-2.7851" y1="-3.1001" x2="-2.2949" y2="-2" layer="51"/>
+<rectangle x1="-1.5151" y1="-3.1001" x2="-1.0249" y2="-2" layer="51"/>
+<rectangle x1="-0.2451" y1="-3.1001" x2="0.2451" y2="-2" layer="51"/>
+<rectangle x1="-0.2451" y1="2" x2="0.2451" y2="3.1001" layer="51"/>
+<rectangle x1="-1.5151" y1="2" x2="-1.0249" y2="3.1001" layer="51"/>
+<rectangle x1="-2.7851" y1="2" x2="-2.2949" y2="3.1001" layer="51"/>
+<rectangle x1="-4.0551" y1="2" x2="-3.5649" y2="3.1001" layer="51"/>
+<rectangle x1="1.0249" y1="-3.1001" x2="1.5151" y2="-2" layer="51"/>
+<rectangle x1="2.2949" y1="-3.1001" x2="2.7851" y2="-2" layer="51"/>
+<rectangle x1="3.5649" y1="-3.1001" x2="4.0551" y2="-2" layer="51"/>
+<rectangle x1="3.5649" y1="2" x2="4.0551" y2="3.1001" layer="51"/>
+<rectangle x1="2.2949" y1="2" x2="2.7851" y2="3.1001" layer="51"/>
+<rectangle x1="1.0249" y1="2" x2="1.5151" y2="3.1001" layer="51"/>
+</package>
+</packages>
+<symbols>
+<symbol name="ATSAMDXXC">
+<description>Atmel SAM D09C/D10C/D11C Cortex-M0+ microcontroller</description>
+<wire x1="-12.7" y1="10.16" x2="12.7" y2="10.16" width="0.254" layer="94"/>
+<wire x1="12.7" y1="10.16" x2="12.7" y2="-10.16" width="0.254" layer="94"/>
+<wire x1="12.7" y1="-10.16" x2="-12.7" y2="-10.16" width="0.254" layer="94"/>
+<wire x1="-12.7" y1="-10.16" x2="-12.7" y2="10.16" width="0.254" layer="94"/>
+<pin name="PA28/RST" x="-17.78" y="-5.08" length="middle"/>
+<pin name="PA8" x="-17.78" y="5.08" length="middle"/>
+<pin name="PA9" x="-17.78" y="2.54" length="middle"/>
+<pin name="PA14" x="-17.78" y="0" length="middle"/>
+<pin name="PA15" x="-17.78" y="-2.54" length="middle"/>
+<pin name="PA5" x="-17.78" y="7.62" length="middle"/>
+<pin name="PA04" x="17.78" y="7.62" length="middle" rot="R180"/>
+<pin name="PA02" x="17.78" y="5.08" length="middle" rot="R180"/>
+<text x="0" y="10.922" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+<text x="0" y="-12.192" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+<pin name="PA30/SCK" x="-17.78" y="-7.62" length="middle"/>
+<pin name="VDD" x="17.78" y="2.54" length="middle" rot="R180"/>
+<pin name="GND" x="17.78" y="0" length="middle" rot="R180"/>
+<pin name="PA25" x="17.78" y="-2.54" length="middle" rot="R180"/>
+<pin name="PA24" x="17.78" y="-5.08" length="middle" rot="R180"/>
+<pin name="PA31/SIO" x="17.78" y="-7.62" length="middle" rot="R180"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="ATSAMD11C" prefix="IC">
+<gates>
+<gate name="G$1" symbol="ATSAMDXXC" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="SO-14">
+<connects>
+<connect gate="G$1" pin="GND" pad="11"/>
+<connect gate="G$1" pin="PA02" pad="13"/>
+<connect gate="G$1" pin="PA04" pad="14"/>
+<connect gate="G$1" pin="PA14" pad="4"/>
+<connect gate="G$1" pin="PA15" pad="5"/>
+<connect gate="G$1" pin="PA24" pad="9"/>
+<connect gate="G$1" pin="PA25" pad="10"/>
+<connect gate="G$1" pin="PA28/RST" pad="6"/>
+<connect gate="G$1" pin="PA30/SCK" pad="7"/>
+<connect gate="G$1" pin="PA31/SIO" pad="8"/>
+<connect gate="G$1" pin="PA5" pad="1"/>
+<connect gate="G$1" pin="PA8" pad="2"/>
+<connect gate="G$1" pin="PA9" pad="3"/>
+<connect gate="G$1" pin="VDD" pad="12"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_pwr">
+<description>Alex Taradov Library (Power Symbols)</description>
+<packages>
+</packages>
+<symbols>
+<symbol name="+3V3">
+<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/>
+<text x="0" y="0.762" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+<pin name="+3V3" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/>
+</symbol>
+<symbol name="GND">
+<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/>
+<text x="0" y="-2.032" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+<pin name="GND" x="0" y="2.54" visible="off" length="short" direction="sup" rot="R270"/>
+</symbol>
+<symbol name="V_USB">
+<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/>
+<text x="0" y="0.762" size="1.27" layer="96" align="bottom-center">&gt;VALUE</text>
+<pin name="V_USB" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="+3V3" prefix="P_">
+<gates>
+<gate name="1" symbol="+3V3" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="GND" prefix="P_">
+<gates>
+<gate name="1" symbol="GND" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="V_USB" prefix="P_">
+<gates>
+<gate name="1" symbol="V_USB" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_conn">
+<description>Alex Taradov Library (Connectors)</description>
+<packages>
+<package name="HEADER-5X2-1.27MM">
+<wire x1="-3.81" y1="1.905" x2="3.81" y2="1.905" width="0.127" layer="21"/>
+<wire x1="3.81" y1="1.905" x2="3.81" y2="-1.905" width="0.127" layer="21"/>
+<wire x1="3.81" y1="-1.905" x2="-3.175" y2="-1.905" width="0.127" layer="21"/>
+<wire x1="-3.175" y1="-1.905" x2="-3.81" y2="-1.27" width="0.127" layer="21"/>
+<wire x1="-3.81" y1="-1.27" x2="-3.81" y2="1.905" width="0.127" layer="21"/>
+<pad name="1" x="-2.54" y="-0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="2" x="-2.54" y="0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="3" x="-1.27" y="-0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="4" x="-1.27" y="0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="5" x="0" y="-0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="6" x="0" y="0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="7" x="1.27" y="-0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="8" x="1.27" y="0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="9" x="2.54" y="-0.635" drill="0.6604" diameter="1.0668"/>
+<pad name="10" x="2.54" y="0.635" drill="0.6604" diameter="1.0668"/>
+<text x="0" y="2.54" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="HEADER-5X2-2.54MM">
+<wire x1="-6.35" y1="0" x2="-3.81" y2="0" width="0.127" layer="21"/>
+<wire x1="-3.81" y1="0" x2="-3.81" y2="-2.54" width="0.127" layer="21"/>
+<wire x1="-6.35" y1="2.54" x2="6.35" y2="2.54" width="0.127" layer="21"/>
+<wire x1="6.35" y1="2.54" x2="6.35" y2="-2.54" width="0.127" layer="21"/>
+<wire x1="6.35" y1="-2.54" x2="-6.35" y2="-2.54" width="0.127" layer="21"/>
+<wire x1="-6.35" y1="-2.54" x2="-6.35" y2="2.54" width="0.127" layer="21"/>
+<pad name="1" x="-5.08" y="-1.27" drill="1.016" shape="square"/>
+<pad name="2" x="-5.08" y="1.27" drill="1.016"/>
+<pad name="3" x="-2.54" y="-1.27" drill="1.016"/>
+<pad name="4" x="-2.54" y="1.27" drill="1.016"/>
+<pad name="5" x="0" y="-1.27" drill="1.016"/>
+<pad name="6" x="0" y="1.27" drill="1.016"/>
+<pad name="7" x="2.54" y="-1.27" drill="1.016"/>
+<pad name="8" x="2.54" y="1.27" drill="1.016"/>
+<pad name="9" x="5.08" y="-1.27" drill="1.016"/>
+<pad name="10" x="5.08" y="1.27" drill="1.016"/>
+<text x="0" y="3.175" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+</packages>
+<symbols>
+<symbol name="HEADER-5X2">
+<wire x1="-5.08" y1="7.62" x2="-5.08" y2="-7.62" width="0.254" layer="94"/>
+<wire x1="-5.08" y1="-7.62" x2="5.08" y2="-7.62" width="0.254" layer="94"/>
+<wire x1="5.08" y1="-7.62" x2="5.08" y2="7.62" width="0.254" layer="94"/>
+<wire x1="5.08" y1="7.62" x2="-5.08" y2="7.62" width="0.254" layer="94"/>
+<pin name="1" x="-7.62" y="5.08" length="short" direction="pas"/>
+<pin name="2" x="7.62" y="5.08" length="short" direction="pas" rot="R180"/>
+<pin name="3" x="-7.62" y="2.54" length="short" direction="pas"/>
+<pin name="4" x="7.62" y="2.54" length="short" direction="pas" rot="R180"/>
+<pin name="5" x="-7.62" y="0" length="short" direction="pas"/>
+<pin name="6" x="7.62" y="0" length="short" direction="pas" rot="R180"/>
+<pin name="7" x="-7.62" y="-2.54" length="short" direction="pas"/>
+<pin name="8" x="7.62" y="-2.54" length="short" direction="pas" rot="R180"/>
+<pin name="9" x="-7.62" y="-5.08" length="short" direction="pas"/>
+<pin name="10" x="7.62" y="-5.08" length="short" direction="pas" rot="R180"/>
+<text x="0" y="8.382" size="1.27" layer="95" align="bottom-center">&gt;NAME</text>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="HEADER-5X2" prefix="J">
+<gates>
+<gate name="G$1" symbol="HEADER-5X2" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-TH-1.27" package="HEADER-5X2-1.27MM">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="10" pad="10"/>
+<connect gate="G$1" pin="2" pad="2"/>
+<connect gate="G$1" pin="3" pad="3"/>
+<connect gate="G$1" pin="4" pad="4"/>
+<connect gate="G$1" pin="5" pad="5"/>
+<connect gate="G$1" pin="6" pad="6"/>
+<connect gate="G$1" pin="7" pad="7"/>
+<connect gate="G$1" pin="8" pad="8"/>
+<connect gate="G$1" pin="9" pad="9"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-TH-2.54" package="HEADER-5X2-2.54MM">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="10" pad="10"/>
+<connect gate="G$1" pin="2" pad="2"/>
+<connect gate="G$1" pin="3" pad="3"/>
+<connect gate="G$1" pin="4" pad="4"/>
+<connect gate="G$1" pin="5" pad="5"/>
+<connect gate="G$1" pin="6" pad="6"/>
+<connect gate="G$1" pin="7" pad="7"/>
+<connect gate="G$1" pin="8" pad="8"/>
+<connect gate="G$1" pin="9" pad="9"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_rlc">
+<description>Alex Taradov Library (R, L and C)</description>
+<packages>
+<package name="SMD0402">
+<wire x1="-1" y1="0.5" x2="1" y2="0.5" width="0.1" layer="21"/>
+<wire x1="1" y1="0.5" x2="1" y2="-0.5" width="0.1" layer="21"/>
+<wire x1="1" y1="-0.5" x2="-1" y2="-0.5" width="0.1" layer="21"/>
+<wire x1="-1" y1="-0.5" x2="-1" y2="0.5" width="0.1" layer="21"/>
+<smd name="1" x="-0.5" y="0" dx="0.6" dy="0.6" layer="1"/>
+<smd name="2" x="0.5" y="0" dx="0.6" dy="0.6" layer="1"/>
+<text x="0" y="0.762" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SMD0508">
+<wire x1="-1" y1="1.25" x2="1" y2="1.25" width="0.1" layer="21"/>
+<wire x1="1" y1="1.25" x2="1" y2="-1.25" width="0.1" layer="21"/>
+<wire x1="1" y1="-1.25" x2="-1" y2="-1.25" width="0.1" layer="21"/>
+<wire x1="-1" y1="-1.25" x2="-1" y2="1.25" width="0.1" layer="21"/>
+<smd name="1" x="-0.5" y="0" dx="2" dy="0.5" layer="1" rot="R90"/>
+<smd name="2" x="0.5" y="0" dx="2" dy="0.5" layer="1" rot="R90"/>
+<text x="0" y="1.524" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SMD0603">
+<wire x1="-1.5" y1="0.75" x2="1.5" y2="0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="0.75" x2="1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="-0.75" x2="-1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="-1.5" y1="-0.75" x2="-1.5" y2="0.75" width="0.1" layer="21"/>
+<smd name="1" x="-0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<smd name="2" x="0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SMD0612">
+<wire x1="-1.8" y1="1.4" x2="1.8" y2="1.4" width="0.1" layer="21"/>
+<wire x1="1.8" y1="1.4" x2="1.8" y2="-1.4" width="0.1" layer="21"/>
+<wire x1="1.8" y1="-1.4" x2="-1.8" y2="-1.4" width="0.1" layer="21"/>
+<wire x1="-1.8" y1="-1.4" x2="-1.8" y2="1.4" width="0.1" layer="21"/>
+<smd name="1" x="0" y="0.8" dx="3.2" dy="0.8" layer="1"/>
+<smd name="2" x="0" y="-0.8" dx="3.2" dy="0.8" layer="1"/>
+<text x="0" y="1.778" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SMD0805">
+<wire x1="-2" y1="1" x2="2" y2="1" width="0.1" layer="21"/>
+<wire x1="2" y1="1" x2="2" y2="-1" width="0.1" layer="21"/>
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+<library name="con-cypressindustries">
+<description>&lt;b&gt;Connectors from Cypress Industries&lt;/b&gt;&lt;p&gt;
+www.cypressindustries.com&lt;br&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
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+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_misc">
+<description>Alex Taradov Library (Miscellaneous stuff)</description>
+<packages>
+<package name="TP-1.27MM">
+<smd name="1" x="0" y="0" dx="1.27" dy="1.27" layer="1" roundness="100" cream="no"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="TP-2.54MM">
+<smd name="1" x="0" y="0" dx="2.54" dy="2.54" layer="1" roundness="100" cream="no"/>
+<text x="0" y="1.778" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+</packages>
+<symbols>
+<symbol name="TP">
+<text x="4.064" y="-0.508" size="1.27" layer="95">&gt;NAME</text>
+<pin name="1" x="0" y="0" visible="off" length="short" direction="pas"/>
+<circle x="3.048" y="0" radius="0.508" width="0" layer="94"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="TEST-POINT" prefix="TP" uservalue="yes">
+<description>Test Point</description>
+<gates>
+<gate name="G$1" symbol="TP" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-1.27MM" package="TP-1.27MM">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-2.54MM" package="TP-2.54MM">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="ataradov_led">
+<description>Alex Taradov Library (LEDs and other indication devices)</description>
+<packages>
+<package name="SMD0603">
+<wire x1="-1.5" y1="0.75" x2="1.5" y2="0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="0.75" x2="1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="1.5" y1="-0.75" x2="-1.5" y2="-0.75" width="0.1" layer="21"/>
+<wire x1="-1.5" y1="-0.75" x2="-1.5" y2="0.75" width="0.1" layer="21"/>
+<smd name="1" x="-0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<smd name="2" x="0.8" y="0" dx="0.9" dy="0.9" layer="1"/>
+<text x="0" y="1.016" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+<package name="SMD0805">
+<wire x1="-2" y1="1" x2="2" y2="1" width="0.1" layer="21"/>
+<wire x1="2" y1="1" x2="2" y2="-1" width="0.1" layer="21"/>
+<wire x1="2" y1="-1" x2="-2" y2="-1" width="0.1" layer="21"/>
+<wire x1="-2" y1="-1" x2="-2" y2="1" width="0.1" layer="21"/>
+<smd name="1" x="-0.95" y="0" dx="1.3" dy="1.5" layer="1"/>
+<smd name="2" x="0.95" y="0" dx="1.3" dy="1.5" layer="1"/>
+<text x="0" y="1.27" size="1.27" layer="25" font="vector" align="bottom-center">&gt;NAME</text>
+</package>
+</packages>
+<symbols>
+<symbol name="LED">
+<wire x1="1.27" y1="0" x2="0" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="0" y1="-2.54" x2="-1.27" y2="0" width="0.254" layer="94"/>
+<wire x1="1.27" y1="-2.54" x2="0" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="0" y1="-2.54" x2="-1.27" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="1.27" y1="0" x2="0" y2="0" width="0.254" layer="94"/>
+<wire x1="0" y1="0" x2="-1.27" y2="0" width="0.254" layer="94"/>
+<wire x1="-2.032" y1="-0.762" x2="-3.429" y2="-2.159" width="0.1524" layer="94"/>
+<wire x1="-1.905" y1="-1.905" x2="-3.302" y2="-3.302" width="0.1524" layer="94"/>
+<text x="3.556" y="-2.032" size="1.27" layer="95" rot="R90" align="bottom-center">&gt;NAME</text>
+<text x="5.715" y="-2.032" size="1.27" layer="96" rot="R90" align="bottom-center">&gt;VALUE</text>
+<pin name="C" x="0" y="-5.08" visible="off" length="short" direction="pas" rot="R90"/>
+<pin name="A" x="0" y="2.54" visible="off" length="short" direction="pas" rot="R270"/>
+<polygon width="0.1524" layer="94">
+<vertex x="-3.429" y="-2.159"/>
+<vertex x="-3.048" y="-1.27"/>
+<vertex x="-2.54" y="-1.778"/>
+</polygon>
+<polygon width="0.1524" layer="94">
+<vertex x="-3.302" y="-3.302"/>
+<vertex x="-2.921" y="-2.413"/>
+<vertex x="-2.413" y="-2.921"/>
+</polygon>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="LED_SMD" prefix="LED" uservalue="yes">
+<description>SMD_LED</description>
+<gates>
+<gate name="G$1" symbol="LED" x="0" y="0"/>
+</gates>
+<devices>
+<device name="LED_0603" package="SMD0603">
+<connects>
+<connect gate="G$1" pin="A" pad="1"/>
+<connect gate="G$1" pin="C" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="LED_0805" package="SMD0805">
+<connects>
+<connect gate="G$1" pin="A" pad="1"/>
+<connect gate="G$1" pin="C" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+</libraries>
+<attributes>
+</attributes>
+<variantdefs>
+</variantdefs>
+<classes>
+<class number="0" name="default" width="0" drill="0">
+</class>
+</classes>
+<parts>
+<part name="IC2" library="ataradov_mcu" deviceset="ATSAMD11C" device=""/>
+<part name="P_9" library="ataradov_pwr" deviceset="+3V3" device=""/>
+<part name="P_7" library="ataradov_pwr" deviceset="+3V3" device=""/>
+<part name="P_17" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_8" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_16" library="ataradov_pwr" deviceset="V_USB" device=""/>
+<part name="P_3" library="ataradov_pwr" deviceset="V_USB" device=""/>
+<part name="C1" library="ataradov_rlc" deviceset="C" device="-0603" value="1uF"/>
+<part name="C2" library="ataradov_rlc" deviceset="C" device="-0603" value="1uF"/>
+<part name="R2" library="ataradov_rlc" deviceset="R" device="-0603" value="330"/>
+<part name="R3" library="ataradov_rlc" deviceset="R" device="-0603" value="330"/>
+<part name="R4" library="ataradov_rlc" deviceset="R" device="-0603" value="330"/>
+<part name="IC1" library="ataradov_vreg" deviceset="MIC5504" device="-SOT23-5" value="MIC5504-3.3"/>
+<part name="P_4" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_6" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_1" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="P_2" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="R5" library="ataradov_rlc" deviceset="R" device="-0603" value="100K"/>
+<part name="R6" library="ataradov_rlc" deviceset="R" device="-0603" value="100K"/>
+<part name="P_18" library="ataradov_pwr" deviceset="+3V3" device=""/>
+<part name="P_19" library="ataradov_pwr" deviceset="+3V3" device=""/>
+<part name="X1" library="con-cypressindustries" deviceset="MINI-USB-" device="32005-201"/>
+<part name="R7" library="ataradov_rlc" deviceset="R" device="-0603" value="330"/>
+<part name="TP1" library="ataradov_misc" deviceset="TEST-POINT" device="-1.27MM" value="SIO"/>
+<part name="TP2" library="ataradov_misc" deviceset="TEST-POINT" device="-1.27MM"/>
+<part name="TP3" library="ataradov_misc" deviceset="TEST-POINT" device="-1.27MM"/>
+<part name="TP4" library="ataradov_misc" deviceset="TEST-POINT" device="-1.27MM"/>
+<part name="LED1" library="ataradov_led" deviceset="LED_SMD" device="LED_0603"/>
+<part name="J1" library="ataradov_conn" deviceset="HEADER-5X2" device="-TH-1.27"/>
+<part name="P_11" library="ataradov_pwr" deviceset="GND" device=""/>
+<part name="R1" library="ataradov_rlc" deviceset="R" device="-0603" value="330"/>
+<part name="R8" library="ataradov_rlc" deviceset="R" device="-0603" value="330"/>
+<part name="P_5" library="ataradov_pwr" deviceset="GND" device=""/>
+</parts>
+<sheets>
+<sheet>
+<plain>
+<frame x1="0" y1="0" x2="152.4" y2="119.38" columns="8" rows="5" layer="97"/>
+<text x="35.56" y="106.68" size="1.778" layer="97" align="bottom-center">Program</text>
+<text x="93.98" y="106.68" size="1.778" layer="97" align="bottom-center">Target</text>
+<text x="60.96" y="15.24" size="1.778" layer="97">Copyright (c) 2016-2017, Alex Taradov &lt;alex@taradov.com&gt;
+
+MCU firmware source code is available at https://github.com/ataradov/free-dap</text>
+</plain>
+<instances>
+<instance part="IC2" gate="G$1" x="40.64" y="53.34"/>
+<instance part="P_9" gate="1" x="53.34" y="27.94"/>
+<instance part="P_7" gate="1" x="60.96" y="66.04"/>
+<instance part="P_17" gate="1" x="76.2" y="40.64"/>
+<instance part="P_8" gate="1" x="60.96" y="40.64"/>
+<instance part="P_16" gate="1" x="76.2" y="60.96"/>
+<instance part="P_3" gate="1" x="25.4" y="27.94"/>
+<instance part="C1" gate="G$1" x="20.32" y="17.78" rot="R90"/>
+<instance part="C2" gate="G$1" x="53.34" y="17.78" rot="R90"/>
+<instance part="R2" gate="G$1" x="111.76" y="96.52"/>
+<instance part="R3" gate="G$1" x="111.76" y="91.44"/>
+<instance part="R4" gate="G$1" x="111.76" y="86.36"/>
+<instance part="IC1" gate="G$1" x="38.1" y="20.32"/>
+<instance part="P_4" gate="1" x="38.1" y="12.7"/>
+<instance part="P_6" gate="1" x="53.34" y="12.7"/>
+<instance part="P_1" gate="1" x="20.32" y="12.7"/>
+<instance part="P_2" gate="1" x="38.1" y="76.2"/>
+<instance part="R5" gate="G$1" x="38.1" y="93.98" rot="R90"/>
+<instance part="R6" gate="G$1" x="33.02" y="93.98" rot="R90"/>
+<instance part="P_18" gate="1" x="33.02" y="101.6"/>
+<instance part="P_19" gate="1" x="38.1" y="101.6"/>
+<instance part="X1" gate="G$1" x="83.82" y="50.8" smashed="yes">
+<attribute name="NAME" x="81.28" y="62.23" size="1.778" layer="95"/>
+</instance>
+<instance part="R7" gate="G$1" x="114.3" y="53.34"/>
+<instance part="TP1" gate="G$1" x="40.64" y="86.36"/>
+<instance part="TP2" gate="G$1" x="40.64" y="83.82"/>
+<instance part="TP3" gate="G$1" x="40.64" y="81.28"/>
+<instance part="TP4" gate="G$1" x="40.64" y="78.74"/>
+<instance part="LED1" gate="G$1" x="124.46" y="53.34" rot="MR270"/>
+<instance part="J1" gate="G$1" x="88.9" y="91.44"/>
+<instance part="P_11" gate="1" x="78.74" y="81.28"/>
+<instance part="R1" gate="G$1" x="111.76" y="81.28"/>
+<instance part="R8" gate="G$1" x="111.76" y="76.2"/>
+<instance part="P_5" gate="1" x="132.08" y="48.26"/>
+</instances>
+<busses>
+</busses>
+<nets>
+<net name="N$1" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA24"/>
+<wire x1="58.42" y1="48.26" x2="76.2" y2="48.26" width="0.1524" layer="91"/>
+<wire x1="76.2" y1="48.26" x2="76.2" y2="53.34" width="0.1524" layer="91"/>
+<wire x1="76.2" y1="53.34" x2="78.74" y2="53.34" width="0.1524" layer="91"/>
+<pinref part="X1" gate="G$1" pin="2"/>
+</segment>
+</net>
+<net name="N$2" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA25"/>
+<wire x1="58.42" y1="50.8" x2="78.74" y2="50.8" width="0.1524" layer="91"/>
+<pinref part="X1" gate="G$1" pin="3"/>
+</segment>
+</net>
+<net name="GND" class="0">
+<segment>
+<pinref part="P_17" gate="1" pin="GND"/>
+<wire x1="76.2" y1="43.18" x2="76.2" y2="45.72" width="0.1524" layer="91"/>
+<wire x1="76.2" y1="45.72" x2="78.74" y2="45.72" width="0.1524" layer="91"/>
+<pinref part="X1" gate="G$1" pin="5"/>
+</segment>
+<segment>
+<pinref part="IC1" gate="G$1" pin="GND"/>
+<pinref part="P_4" gate="1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="C1" gate="G$1" pin="1"/>
+<pinref part="P_1" gate="1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="C2" gate="G$1" pin="1"/>
+<pinref part="P_6" gate="1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="GND"/>
+<pinref part="P_8" gate="1" pin="GND"/>
+<wire x1="58.42" y1="53.34" x2="60.96" y2="53.34" width="0.1524" layer="91"/>
+<wire x1="60.96" y1="53.34" x2="60.96" y2="43.18" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="P_2" gate="1" pin="GND"/>
+<wire x1="38.1" y1="78.74" x2="40.64" y2="78.74" width="0.1524" layer="91"/>
+<pinref part="TP4" gate="G$1" pin="1"/>
+</segment>
+<segment>
+<pinref part="J1" gate="G$1" pin="3"/>
+<wire x1="81.28" y1="93.98" x2="78.74" y2="93.98" width="0.1524" layer="91"/>
+<pinref part="P_11" gate="1" pin="GND"/>
+<wire x1="78.74" y1="93.98" x2="78.74" y2="91.44" width="0.1524" layer="91"/>
+<pinref part="J1" gate="G$1" pin="5"/>
+<wire x1="78.74" y1="91.44" x2="78.74" y2="83.82" width="0.1524" layer="91"/>
+<wire x1="81.28" y1="91.44" x2="78.74" y2="91.44" width="0.1524" layer="91"/>
+<junction x="78.74" y="91.44"/>
+</segment>
+<segment>
+<pinref part="P_5" gate="1" pin="GND"/>
+<wire x1="132.08" y1="50.8" x2="132.08" y2="53.34" width="0.1524" layer="91"/>
+<wire x1="132.08" y1="53.34" x2="129.54" y2="53.34" width="0.1524" layer="91"/>
+<pinref part="LED1" gate="G$1" pin="C"/>
+</segment>
+</net>
+<net name="V_USB" class="0">
+<segment>
+<pinref part="P_16" gate="1" pin="V_USB"/>
+<wire x1="76.2" y1="58.42" x2="76.2" y2="55.88" width="0.1524" layer="91"/>
+<wire x1="76.2" y1="55.88" x2="78.74" y2="55.88" width="0.1524" layer="91"/>
+<pinref part="X1" gate="G$1" pin="1"/>
+</segment>
+<segment>
+<pinref part="IC1" gate="G$1" pin="EN"/>
+<pinref part="P_3" gate="1" pin="V_USB"/>
+<wire x1="27.94" y1="20.32" x2="25.4" y2="20.32" width="0.1524" layer="91"/>
+<wire x1="25.4" y1="20.32" x2="25.4" y2="22.86" width="0.1524" layer="91"/>
+<pinref part="IC1" gate="G$1" pin="IN"/>
+<wire x1="25.4" y1="22.86" x2="25.4" y2="25.4" width="0.1524" layer="91"/>
+<wire x1="27.94" y1="22.86" x2="25.4" y2="22.86" width="0.1524" layer="91"/>
+<junction x="25.4" y="22.86"/>
+<pinref part="C1" gate="G$1" pin="2"/>
+<wire x1="25.4" y1="22.86" x2="20.32" y2="22.86" width="0.1524" layer="91"/>
+<wire x1="20.32" y1="22.86" x2="20.32" y2="20.32" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="+3V3" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="OUT"/>
+<wire x1="48.26" y1="22.86" x2="53.34" y2="22.86" width="0.1524" layer="91"/>
+<pinref part="C2" gate="G$1" pin="2"/>
+<wire x1="53.34" y1="20.32" x2="53.34" y2="22.86" width="0.1524" layer="91"/>
+<junction x="53.34" y="22.86"/>
+<pinref part="P_9" gate="1" pin="+3V3"/>
+<wire x1="53.34" y1="25.4" x2="53.34" y2="22.86" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="VDD"/>
+<pinref part="P_7" gate="1" pin="+3V3"/>
+<wire x1="58.42" y1="55.88" x2="60.96" y2="55.88" width="0.1524" layer="91"/>
+<wire x1="60.96" y1="55.88" x2="60.96" y2="63.5" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="R6" gate="G$1" pin="2"/>
+<pinref part="P_18" gate="1" pin="+3V3"/>
+</segment>
+<segment>
+<pinref part="R5" gate="G$1" pin="2"/>
+<pinref part="P_19" gate="1" pin="+3V3"/>
+</segment>
+</net>
+<net name="SWDIO" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA31/SIO"/>
+<wire x1="58.42" y1="45.72" x2="63.5" y2="45.72" width="0.1524" layer="91"/>
+<label x="63.5" y="45.72" size="1.27" layer="95"/>
+</segment>
+<segment>
+<wire x1="40.64" y1="86.36" x2="22.86" y2="86.36" width="0.1524" layer="91"/>
+<label x="22.86" y="86.36" size="1.27" layer="95" rot="MR0"/>
+<pinref part="TP1" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="PA02" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA02"/>
+<wire x1="58.42" y1="58.42" x2="63.5" y2="58.42" width="0.1524" layer="91"/>
+<label x="63.5" y="58.42" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="PA04" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA04"/>
+<wire x1="58.42" y1="60.96" x2="63.5" y2="60.96" width="0.1524" layer="91"/>
+<label x="63.5" y="60.96" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="R7" gate="G$1" pin="1"/>
+<wire x1="109.22" y1="53.34" x2="106.68" y2="53.34" width="0.1524" layer="91"/>
+<label x="106.68" y="53.34" size="1.27" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="SWCLK" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA30/SCK"/>
+<wire x1="22.86" y1="45.72" x2="20.32" y2="45.72" width="0.1524" layer="91"/>
+<label x="20.32" y="45.72" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<wire x1="40.64" y1="83.82" x2="33.02" y2="83.82" width="0.1524" layer="91"/>
+<label x="22.86" y="83.82" size="1.27" layer="95" rot="MR0"/>
+<pinref part="R6" gate="G$1" pin="1"/>
+<wire x1="33.02" y1="83.82" x2="22.86" y2="83.82" width="0.1524" layer="91"/>
+<wire x1="33.02" y1="88.9" x2="33.02" y2="83.82" width="0.1524" layer="91"/>
+<junction x="33.02" y="83.82"/>
+<pinref part="TP2" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="RESET" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA28/RST"/>
+<wire x1="22.86" y1="48.26" x2="20.32" y2="48.26" width="0.1524" layer="91"/>
+<label x="20.32" y="48.26" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<wire x1="40.64" y1="81.28" x2="38.1" y2="81.28" width="0.1524" layer="91"/>
+<label x="22.86" y="81.28" size="1.27" layer="95" rot="MR0"/>
+<pinref part="R5" gate="G$1" pin="1"/>
+<wire x1="38.1" y1="81.28" x2="22.86" y2="81.28" width="0.1524" layer="91"/>
+<wire x1="38.1" y1="88.9" x2="38.1" y2="81.28" width="0.1524" layer="91"/>
+<junction x="38.1" y="81.28"/>
+<pinref part="TP3" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="N$5" class="0">
+<segment>
+<pinref part="J1" gate="G$1" pin="2"/>
+<pinref part="R2" gate="G$1" pin="1"/>
+<wire x1="96.52" y1="96.52" x2="106.68" y2="96.52" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="N$9" class="0">
+<segment>
+<pinref part="R3" gate="G$1" pin="1"/>
+<wire x1="106.68" y1="91.44" x2="106.68" y2="93.98" width="0.1524" layer="91"/>
+<pinref part="J1" gate="G$1" pin="4"/>
+<wire x1="106.68" y1="93.98" x2="96.52" y2="93.98" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="N$10" class="0">
+<segment>
+<pinref part="J1" gate="G$1" pin="6"/>
+<wire x1="96.52" y1="91.44" x2="104.14" y2="91.44" width="0.1524" layer="91"/>
+<wire x1="104.14" y1="91.44" x2="104.14" y2="86.36" width="0.1524" layer="91"/>
+<pinref part="R4" gate="G$1" pin="1"/>
+<wire x1="104.14" y1="86.36" x2="106.68" y2="86.36" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="N$11" class="0">
+<segment>
+<pinref part="R1" gate="G$1" pin="1"/>
+<wire x1="106.68" y1="81.28" x2="101.6" y2="81.28" width="0.1524" layer="91"/>
+<wire x1="101.6" y1="81.28" x2="101.6" y2="88.9" width="0.1524" layer="91"/>
+<pinref part="J1" gate="G$1" pin="8"/>
+<wire x1="101.6" y1="88.9" x2="96.52" y2="88.9" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="N$12" class="0">
+<segment>
+<pinref part="J1" gate="G$1" pin="10"/>
+<wire x1="96.52" y1="86.36" x2="99.06" y2="86.36" width="0.1524" layer="91"/>
+<wire x1="99.06" y1="86.36" x2="99.06" y2="76.2" width="0.1524" layer="91"/>
+<pinref part="R8" gate="G$1" pin="1"/>
+<wire x1="99.06" y1="76.2" x2="106.68" y2="76.2" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="PA14" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA14"/>
+<wire x1="20.32" y1="53.34" x2="22.86" y2="53.34" width="0.1524" layer="91"/>
+<label x="20.32" y="53.34" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="R3" gate="G$1" pin="2"/>
+<wire x1="119.38" y1="91.44" x2="116.84" y2="91.44" width="0.1524" layer="91"/>
+<label x="119.38" y="91.44" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="PA15" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA15"/>
+<wire x1="22.86" y1="50.8" x2="20.32" y2="50.8" width="0.1524" layer="91"/>
+<label x="20.32" y="50.8" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="R2" gate="G$1" pin="2"/>
+<wire x1="119.38" y1="96.52" x2="116.84" y2="96.52" width="0.1524" layer="91"/>
+<label x="119.38" y="96.52" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="N$3" class="0">
+<segment>
+<pinref part="R7" gate="G$1" pin="2"/>
+<pinref part="LED1" gate="G$1" pin="A"/>
+<wire x1="121.92" y1="53.34" x2="119.38" y2="53.34" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="PA09" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA9"/>
+<wire x1="22.86" y1="55.88" x2="20.32" y2="55.88" width="0.1524" layer="91"/>
+<label x="20.32" y="55.88" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="R4" gate="G$1" pin="2"/>
+<wire x1="119.38" y1="86.36" x2="116.84" y2="86.36" width="0.1524" layer="91"/>
+<label x="119.38" y="86.36" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="PA08" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA8"/>
+<wire x1="22.86" y1="58.42" x2="20.32" y2="58.42" width="0.1524" layer="91"/>
+<label x="20.32" y="58.42" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="R1" gate="G$1" pin="2"/>
+<wire x1="116.84" y1="81.28" x2="119.38" y2="81.28" width="0.1524" layer="91"/>
+<label x="119.38" y="81.28" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="PA05" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="PA5"/>
+<wire x1="22.86" y1="60.96" x2="20.32" y2="60.96" width="0.1524" layer="91"/>
+<label x="20.32" y="60.96" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="R8" gate="G$1" pin="2"/>
+<wire x1="119.38" y1="76.2" x2="116.84" y2="76.2" width="0.1524" layer="91"/>
+<label x="119.38" y="76.2" size="1.27" layer="95"/>
+</segment>
+</net>
+</nets>
+</sheet>
+</sheets>
+</schematic>
+</drawing>
+<compatibility>
+<note version="6.3" minversion="6.2.2" severity="warning">
+Since Version 6.2.2 text objects can contain more than one line,
+which will not be processed correctly with this version.
+</note>
+</compatibility>
+</eagle>

dap_link/lib/free-dap/hardware/m484-dap/.gitignore

@@ -0,0 +1,5 @@
+output/*
+!output/*.pdf
+!output/*.zip
+fp-info-cache
+

dap_link/lib/free-dap/hardware/m484-dap/m484-dap.kicad_pcb

@@ -0,0 +1,8106 @@
+(kicad_pcb (version 20211014) (generator pcbnew)
+
+  (general
+    (thickness 1.6)
+  )
+
+  (paper "User" 99.9998 99.9998)
+  (layers
+    (0 "F.Cu" signal)
+    (31 "B.Cu" signal)
+    (32 "B.Adhes" user "B.Adhesive")
+    (33 "F.Adhes" user "F.Adhesive")
+    (34 "B.Paste" user)
+    (35 "F.Paste" user)
+    (36 "B.SilkS" user "B.Silkscreen")
+    (37 "F.SilkS" user "F.Silkscreen")
+    (38 "B.Mask" user)
+    (39 "F.Mask" user)
+    (40 "Dwgs.User" user "User.Drawings")
+    (41 "Cmts.User" user "User.Comments")
+    (42 "Eco1.User" user "User.Eco1")
+    (43 "Eco2.User" user "User.Eco2")
+    (44 "Edge.Cuts" user)
+    (45 "Margin" user)
+    (46 "B.CrtYd" user "B.Courtyard")
+    (47 "F.CrtYd" user "F.Courtyard")
+    (48 "B.Fab" user)
+    (49 "F.Fab" user)
+    (50 "User.1" user)
+    (51 "User.2" user)
+    (52 "User.3" user)
+    (53 "User.4" user)
+    (54 "User.5" user)
+    (55 "User.6" user)
+    (56 "User.7" user)
+    (57 "User.8" user)
+    (58 "User.9" user)
+  )
+
+  (setup
+    (stackup
+      (layer "F.SilkS" (type "Top Silk Screen"))
+      (layer "F.Paste" (type "Top Solder Paste"))
+      (layer "F.Mask" (type "Top Solder Mask") (thickness 0.01))
+      (layer "F.Cu" (type "copper") (thickness 0.035))
+      (layer "dielectric 1" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
+      (layer "B.Cu" (type "copper") (thickness 0.035))
+      (layer "B.Mask" (type "Bottom Solder Mask") (thickness 0.01))
+      (layer "B.Paste" (type "Bottom Solder Paste"))
+      (layer "B.SilkS" (type "Bottom Silk Screen"))
+      (copper_finish "None")
+      (dielectric_constraints no)
+    )
+    (pad_to_mask_clearance 0)
+    (pcbplotparams
+      (layerselection 0x00010f0_ffffffff)
+      (disableapertmacros true)
+      (usegerberextensions true)
+      (usegerberattributes false)
+      (usegerberadvancedattributes false)
+      (creategerberjobfile false)
+      (svguseinch false)
+      (svgprecision 6)
+      (excludeedgelayer true)
+      (plotframeref false)
+      (viasonmask false)
+      (mode 1)
+      (useauxorigin false)
+      (hpglpennumber 1)
+      (hpglpenspeed 20)
+      (hpglpendiameter 15.000000)
+      (dxfpolygonmode true)
+      (dxfimperialunits true)
+      (dxfusepcbnewfont true)
+      (psnegative false)
+      (psa4output false)
+      (plotreference true)
+      (plotvalue true)
+      (plotinvisibletext false)
+      (sketchpadsonfab false)
+      (subtractmaskfromsilk true)
+      (outputformat 1)
+      (mirror false)
+      (drillshape 0)
+      (scaleselection 1)
+      (outputdirectory "output/")
+    )
+  )
+
+  (net 0 "")
+  (net 1 "GND")
+  (net 2 "/RESET")
+  (net 3 "/SWCLK")
+  (net 4 "/SWDIO")
+  (net 5 "+3V3")
+  (net 6 "Net-(J1-PadCC1)")
+  (net 7 "Net-(J1-PadCC2)")
+  (net 8 "unconnected-(J2-Pad7)")
+  (net 9 "unconnected-(J1-PadSBU1)")
+  (net 10 "unconnected-(J1-PadSBU2)")
+  (net 11 "VBUS")
+  (net 12 "/USB_DP")
+  (net 13 "/USB_DM")
+  (net 14 "unconnected-(IC2-Pad1)")
+  (net 15 "unconnected-(IC2-Pad3)")
+  (net 16 "unconnected-(IC2-Pad4)")
+  (net 17 "unconnected-(IC2-Pad6)")
+  (net 18 "unconnected-(IC2-Pad7)")
+  (net 19 "unconnected-(IC2-Pad12)")
+  (net 20 "unconnected-(IC2-Pad15)")
+  (net 21 "unconnected-(IC2-Pad17)")
+  (net 22 "unconnected-(IC2-Pad18)")
+  (net 23 "unconnected-(IC2-Pad19)")
+  (net 24 "unconnected-(IC2-Pad20)")
+  (net 25 "unconnected-(IC2-Pad21)")
+  (net 26 "unconnected-(IC2-Pad25)")
+  (net 27 "unconnected-(IC2-Pad26)")
+  (net 28 "unconnected-(IC2-Pad27)")
+  (net 29 "unconnected-(IC2-Pad28)")
+  (net 30 "unconnected-(IC2-Pad29)")
+  (net 31 "unconnected-(IC2-Pad30)")
+  (net 32 "unconnected-(IC2-Pad36)")
+  (net 33 "unconnected-(IC2-Pad37)")
+  (net 34 "unconnected-(IC2-Pad38)")
+  (net 35 "unconnected-(IC2-Pad39)")
+  (net 36 "unconnected-(IC2-Pad40)")
+  (net 37 "unconnected-(IC2-Pad48)")
+  (net 38 "unconnected-(IC2-Pad53)")
+  (net 39 "unconnected-(IC2-Pad54)")
+  (net 40 "unconnected-(IC2-Pad55)")
+  (net 41 "unconnected-(IC2-Pad56)")
+  (net 42 "unconnected-(IC2-Pad60)")
+  (net 43 "unconnected-(IC2-Pad61)")
+  (net 44 "unconnected-(IC2-Pad62)")
+  (net 45 "unconnected-(IC2-Pad63)")
+  (net 46 "Net-(IC2-Pad41)")
+  (net 47 "/12MHz")
+  (net 48 "/T_SWDIO_TMS")
+  (net 49 "/T_SWCLK_TCK")
+  (net 50 "/T_TDO")
+  (net 51 "/T_TDI")
+  (net 52 "/T_RESET")
+  (net 53 "/STATUS_LED")
+  (net 54 "Net-(LED1-Pad2)")
+  (net 55 "Net-(C6-Pad2)")
+  (net 56 "unconnected-(IC2-Pad35)")
+  (net 57 "unconnected-(IC2-Pad52)")
+  (net 58 "unconnected-(J2-Pad1)")
+  (net 59 "Net-(C3-Pad2)")
+  (net 60 "Net-(C4-Pad1)")
+  (net 61 "Net-(C5-Pad2)")
+  (net 62 "unconnected-(IC2-Pad10)")
+  (net 63 "unconnected-(IC2-Pad9)")
+  (net 64 "Net-(C3-Pad1)")
+
+  (footprint "ataradov_ic:TQFP-64-0.4mm" (layer "F.Cu")
+    (tedit 61AC865A) (tstamp 0e33928e-78cb-4df8-a938-7a768ad7b43e)
+    (at 47.117 51.308 180)
+    (property "Sheetfile" "m484-dap.kicad_sch")
+    (property "Sheetname" "")
+    (path "/b4eec5a6-4c00-4bb4-8bd1-32e5eedceb3a")
+    (attr smd)
+    (fp_text reference "IC2" (at 1.143 -6.604) (layer "F.SilkS")
+      (effects (font (size 1 1) (thickness 0.127)))
+      (tstamp d15a517d-2a01-4d49-b25d-1c2a7d7c8eb3)
+    )
+    (fp_text value "M48XSIDAE" (at 0 0) (layer "F.Fab")
+      (effects (font (size 0.5 0.5) (thickness 0.1)))
+      (tstamp f04af639-df13-4a4a-a75e-5e007f6dc1aa)
+    )
+    (fp_line (start -2.794 -2.032) (end -2.032 -2.794) (layer "F.SilkS") (width 0.127) (tstamp 05381d6c-466c-4919-8f34-878cc7c5a0e9))
+    (fp_line (start 2.794 2.794) (end -2.794 2.794) (layer "F.SilkS") (width 0.127) (tstamp 85166307-32a0-49b8-9ea6-a33732b6f036))
+    (fp_line (start -2.032 -2.794) (end 2.794 -2.794) (layer "F.SilkS") (width 0.127) (tstamp 96c40b68-dc82-40a4-a990-6c01c1d6b84c))
+    (fp_line (start -2.794 2.794) (end -2.794 -2.032) (layer "F.SilkS") (width 0.127) (tstamp b7dade1c-e591-4d20-a88a-ae4c690e9423))
+    (fp_line (start 2.794 -2.794) (end 2.794 2.794) (layer "F.SilkS") (width 0.127) (tstamp cec6e3f0-51c9-4237-aa39-aa66300ebd11))
+    (fp_poly (pts
+        (xy -5.334 -3.048)
+        (xy -5.588 -2.794)
+        (xy -5.588 -3.302)
+      ) (layer "F.SilkS") (width 0.127) (fill solid) (tstamp 051d1faf-d923-4304-b89e-5f9953e8c7df))
+    (pad "1" smd rect (at -4.1 -3 180) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
+      (net 14 "unconnected-(IC2-Pad1)") (pinfunction "PB6") (pintype "bidirectional") (tstamp 19753934-7479-4176-bb62-39892acc9249))
+    (pad "2" smd rect (at -4.1 -2.6 180) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
+      (net 48 "/T_SWDIO_TMS") (pinfunction "PB5") (pintype "bidirectional") (tstamp d276781f-6cdb-4291-b62a-ce392c4e57c7))
+    (pad "3" smd rect (at -4.1 -2.2 180) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
+      (net 15 "unconnected-(IC2-Pad3)") (pinfunction "PB4") (pintype "bidirectional") (tstamp b6fbbf88-c81b-4226-8191-e2a236e01e59))
+    (pad "4" smd rect (at -4.1 -1.8 180) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
+      (net 16 "unconnected-(IC2-Pad4)") (pinfunction "PB3") (pintype "bidirectional") (tstamp dc5e3cd5-52e8-462e-aeef-4edae2b75279))
+    (pad "5" smd rect (at -4.1 -1.4 180) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
+      (net 49 "/T_SWCLK_TCK") (pinfunction "PB2") (pintype "bidirectional") (tstamp 96265898-eb13-44e9-8ddc-737710cb5173))
+    (pad "6" smd rect (at -4.1 -1 180) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
+      (net 17 "unconnected-(IC2-Pad6)") (pinfunction "PB1") (pintype "bidirectional") (tstamp 0379ce99-99bb-4a80-85d0-c20af6d1cd08))
+    (pad "7" smd rect (at -4.1 -0.6 180) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
+      (net 18 "unconnected-(IC2-Pad7)") (pinfunction "PB0") (pintype "bidirectional") (tstamp 3d6f9efe-07c7-4092-aaeb-eb159afdc6ae))
+    (pad "8" smd rect (at -4.1 -0.2 180) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
+      (net 50 "/T_TDO") (pinfunction "PA11") (pintype "bidirectional") (tstamp f1a4e564-9843-4030-b5e0-09c4feb42d40))
+    (pad "9" smd rect (at -4.1 0.2 180) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
+      (net 63 "unconnected-(IC2-Pad9)") (pinfunction "PA10") (pintype "bidirectional") (tstamp 4ebbdaf2-f5db-4784-8a7b-c2281017a5ea))
+    (pad "10" smd rect (at -4.1 0.6 180) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
+      (net 62 "unconnected-(IC2-Pad10)") (pinfunction "PA9") (pintype "bidirectional") (tstamp aaae2fc4-c833-4900-b46f-28f86341a30b))
+    (pad "11" smd rect (at -4.1 1 180) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
+      (net 51 "/T_TDI") (pinfunction "PA8") (pintype "bidirectional") (tstamp 8a883818-5d4d-48ca-b222-ff753eabf7b8))
+    (pad "12" smd rect (at -4.1 1.4 180) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
+      (net 19 "unconnected-(IC2-Pad12)") (pinfunction "PF6") (pintype "bidirectional") (tstamp ba9e4017-9a85-4125-bd7d-23eb9ba0ee08))
+    (pad "13" smd rect (at -4.1 1.8 180) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
+      (net 5 "+3V3") (pinfunction "VDD*3") (pintype "power_in") (tstamp 7b051f52-37cd-4547-95b3-796616dea57e))
+    (pad "14" smd rect (at -4.1 2.2 180) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
+      (net 52 "/T_RESET") (pinfunction "PF5/X32_IN") (pintype "bidirectional") (tstamp 700f8d93-56a9-4373-bdd4-53cb47348a80))
+    (pad "15" smd rect (at -4.1 2.6 180) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
+      (net 20 "unconnected-(IC2-Pad15)") (pinfunction "PF4/X32_OUT") (pintype "bidirectional") (tstamp 28abf64f-e00b-4105-9187-92af39cb1425))
+    (pad "16" smd rect (at -4.1 3 180) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
+      (net 47 "/12MHz") (pinfunction "PF3/XT1_IN") (pintype "bidirectional") (tstamp 3db671b9-07cd-4bcd-ae91-676a74ee0605))
+    (pad "17" smd rect (at -3 4.1 270) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
+      (net 21 "unconnected-(IC2-Pad17)") (pinfunction "PF2/XT1_OUT") (pintype "bidirectional") (tstamp 7c05a9c7-a6fc-4a5a-948e-0a889226b688))
+    (pad "18" smd rect (at -2.6 4.1 270) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
+      (net 22 "unconnected-(IC2-Pad18)") (pinfunction "PC7") (pintype "bidirectional") (tstamp 28d182bf-05ff-432a-9c64-50b2fa0bbe26))
+    (pad "19" smd rect (at -2.2 4.1 270) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
+      (net 23 "unconnected-(IC2-Pad19)") (pinfunction "PC6") (pintype "bidirectional") (tstamp f5bb33f1-8c48-4bfc-8219-a76bc7336f95))
+    (pad "20" smd rect (at -1.8 4.1 270) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
+      (net 24 "unconnected-(IC2-Pad20)") (pinfunction "PA7") (pintype "bidirectional") (tstamp c28f768b-be68-4415-8540-681fd0b54d31))
+    (pad "21" smd rect (at -1.4 4.1 270) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
+      (net 25 "unconnected-(IC2-Pad21)") (pinfunction "PA6") (pintype "bidirectional") (tstamp ca275af3-1eb8-4c8c-ae26-7ad48fb0b768))
+    (pad "22" smd rect (at -1 4.1 270) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
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+    (pad "24" smd rect (at -0.2 4.1 270) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
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+    (pad "25" smd rect (at 0.2 4.1 270) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
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+      (net 27 "unconnected-(IC2-Pad26)") (pinfunction "PA4") (pintype "bidirectional") (tstamp 0f90ce12-43f0-4b64-80b1-926d98d22540))
+    (pad "27" smd rect (at 1 4.1 270) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
+      (net 28 "unconnected-(IC2-Pad27)") (pinfunction "PA3") (pintype "bidirectional") (tstamp bd6bda2b-98fc-412b-b36a-620bf182c2c7))
+    (pad "28" smd rect (at 1.4 4.1 270) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
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+    (pad "29" smd rect (at 1.8 4.1 270) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
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+    (pad "30" smd rect (at 2.2 4.1 270) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
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+    (pad "32" smd rect (at 3 4.1 270) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
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+    (pad "35" smd rect (at 4.1 2.2 180) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
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+    (pad "38" smd rect (at 4.1 1 180) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
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+    (pad "39" smd rect (at 4.1 0.6 180) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
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+    (pad "42" smd rect (at 4.1 -0.6 180) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
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+    (pad "43" smd rect (at 4.1 -1 180) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
+      (net 11 "VBUS") (pinfunction "USBHS_VBUS") (pintype "input") (tstamp 595ab957-eafe-4e6a-a364-ea9219e6c0fd))
+    (pad "44" smd rect (at 4.1 -1.4 180) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
+      (net 13 "/USB_DM") (pinfunction "USBHS_DM") (pintype "bidirectional") (tstamp 4b3710f3-db6e-43f0-acce-17622d7f47e2))
+    (pad "45" smd rect (at 4.1 -1.8 180) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
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+    (pad "46" smd rect (at 4.1 -2.2 180) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
+      (net 12 "/USB_DP") (pinfunction "USBHS_DP") (pintype "bidirectional") (tstamp 722a1570-cda8-4fa3-89bb-55e80aeb319c))
+    (pad "47" smd rect (at 4.1 -2.6 180) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
+      (net 60 "Net-(C4-Pad1)") (pinfunction "USBHS_CAP") (pintype "passive") (tstamp 26e67825-5355-464d-9b18-a150d06e0d10))
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+      (net 37 "unconnected-(IC2-Pad48)") (pinfunction "USBHS_ID") (pintype "bidirectional") (tstamp ee9f893e-340c-4328-b178-ab002c62cde5))
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+    (pad "50" smd rect (at 2.6 -4.1 270) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
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+    (pad "53" smd rect (at 1.4 -4.1 270) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
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+      (net 45 "unconnected-(IC2-Pad63)") (pinfunction "PB8") (pintype "bidirectional") (tstamp c3ced161-58dd-4ee8-9210-4b997962855f))
+    (pad "64" smd rect (at -3 -4.1 270) (size 1.5 0.22) (layers "F.Cu" "F.Paste" "F.Mask")
+      (net 53 "/STATUS_LED") (pinfunction "PB7") (pintype "bidirectional") (tstamp 4a757d2e-b667-45ed-a7b7-a02cfaf8bf9c))
+  )
+
+  (footprint "ataradov_misc:Logo-Small" (layer "F.Cu")
+    (tedit 61C6C194) (tstamp 217a6ab0-8c75-4e09-8113-c7b7b906da43)
+    (at 35.179 52.578 90)
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+    (property "Sheetname" "")
+    (path "/c5ac15a6-7a3d-42a9-adb0-f88cb8f1134d")
+    (attr smd)
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+      (tstamp fe2b320a-ede0-4599-8996-e6b57dc8879f)
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+  )
+
+  (footprint "ataradov_conn:Header-5x2-1.27mm" (layer "F.Cu")
+    (tedit 61AE8C8C) (tstamp 7b130b4c-2bbe-4733-89ba-ff3bf576cf72)
+    (at 54.483 51.308 90)
+    (property "Sheetfile" "m484-dap.kicad_sch")
+    (property "Sheetname" "")
+    (path "/0220b3c5-3933-430c-9a95-3250361c369c")
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+      (net 49 "/T_SWCLK_TCK") (pinfunction "4") (pintype "passive") (tstamp c9018a4a-c0e2-4081-aa9c-0a48251b47ae))
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+    (pad "6" thru_hole circle (at 0 -0.635 90) (size 1.016 1.016) (drill 0.6096) (layers *.Cu *.Mask)
+      (net 50 "/T_TDO") (pinfunction "6") (pintype "passive") (tstamp bf80f3ba-8587-4765-bf89-9a899d7fc779))
+    (pad "7" thru_hole circle (at 1.27 0.635 90) (size 1.016 1.016) (drill 0.6096) (layers *.Cu *.Mask)
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+    (pad "8" thru_hole circle (at 1.27 -0.643 90) (size 1.016 1.016) (drill 0.6096) (layers *.Cu *.Mask)
+      (net 51 "/T_TDI") (pinfunction "8") (pintype "passive") (tstamp 9780afc7-57f1-43b4-a16b-bebfc03a5630))
+    (pad "9" thru_hole circle (at 2.54 0.635 90) (size 1.016 1.016) (drill 0.6096) (layers *.Cu *.Mask)
+      (net 1 "GND") (pinfunction "9") (pintype "passive") (tstamp 119f5b63-0013-43ed-8803-48cb481bfce8))
+    (pad "10" thru_hole circle (at 2.54 -0.635 90) (size 1.016 1.016) (drill 0.6096) (layers *.Cu *.Mask)
+      (net 52 "/T_RESET") (pinfunction "10") (pintype "passive") (tstamp 4968683f-60d5-4e86-a307-0e72de4a99a2))
+  )
+
+  (footprint "ataradov_misc:TestPoint-1.27mm-Small" (layer "F.Cu")
+    (tedit 619EF054) (tstamp 8c94943c-0078-4487-91c2-55b1516633d4)
+    (at 48.641 53.848)
+    (property "Sheetfile" "m484-dap.kicad_sch")
+    (property "Sheetname" "")
+    (path "/2fdf4489-bc00-4109-aa4e-8518129c5f65")
+    (attr through_hole)
+    (fp_text reference "TP3" (at 0 1.778) (layer "F.SilkS") hide
+      (effects (font (size 1 1) (thickness 0.127)))
+      (tstamp 9a2cdc2c-1f16-40f2-8109-9a08bae734a8)
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+      (effects (font (size 1 1) (thickness 0.127)))
+      (tstamp 735ab9a8-dcec-4005-90d9-f926f9c50dca)
+    )
+    (pad "1" thru_hole circle (at 0 0) (size 1.016 1.016) (drill 0.6096) (layers *.Cu *.Mask)
+      (net 1 "GND") (pinfunction "1") (pintype "passive") (tstamp 7a9fc7fd-2b25-4f31-9717-21f57b93935a))
+  )
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dap_link/lib/free-dap/hardware/m484-dap/m484-dap.kicad_prl

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dap_link/lib/free-dap/hardware/m484-dap/m484-dap.kicad_pro

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+      "pin_to_pin": "error",
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+      "similar_labels": "warning",
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+      "unit_value_mismatch": "error",
+      "unresolved_variable": "error",
+      "wire_dangling": "error"
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+  },
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+    "pinned_footprint_libs": [],
+    "pinned_symbol_libs": []
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+      "idf": "",
+      "netlist": "",
+      "specctra_dsn": "",
+      "step": "",
+      "vrml": ""
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+    "legacy_lib_list": [],
+    "meta": {
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+    },
+    "net_format_name": "",
+    "ngspice": {
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+      "fix_passive_vals": false,
+      "meta": {
+        "version": 0
+      },
+      "model_mode": 0,
+      "workbook_filename": ""
+    },
+    "page_layout_descr_file": "sch.kicad_wks",
+    "plot_directory": "output/",
+    "spice_adjust_passive_values": false,
+    "spice_external_command": "spice \"%I\"",
+    "subpart_first_id": 65,
+    "subpart_id_separator": 0
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+  "sheets": [
+    [
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+}

dap_link/lib/free-dap/hardware/m484-dap/m484-dap.kicad_sch

@@ -0,0 +1,2956 @@
+(kicad_sch (version 20211123) (generator eeschema)
+
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+
+  (paper "USLetter")
+
+  (title_block
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+    (rev "1")
+  )
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+      (reference "L2") (unit 1) (value "BLM15BD471SN1D") (footprint "ataradov_smd:0402")
+    )
+    (path "/6bc6f722-72ae-42d6-be95-2b8bf65cd61e"
+      (reference "LED1") (unit 1) (value "Orange") (footprint "ataradov_smd:0603")
+    )
+    (path "/c5ac15a6-7a3d-42a9-adb0-f88cb8f1134d"
+      (reference "Logo1") (unit 1) (value "Logo") (footprint "ataradov_misc:Logo-Small")
+    )
+    (path "/9ccf3359-ba11-46a6-9a0c-9b63f86fe90d"
+      (reference "R1") (unit 1) (value "5.1K") (footprint "ataradov_smd:0603")
+    )
+    (path "/c2ea3529-b16a-465b-b793-cd4bcdfbeef6"
+      (reference "R2") (unit 1) (value "5.1K") (footprint "ataradov_smd:0603")
+    )
+    (path "/d7ddab23-d82d-4b1f-bb60-867ca3aacbad"
+      (reference "R3") (unit 1) (value "200") (footprint "ataradov_smd:0402")
+    )
+    (path "/cba72152-8d99-4bd5-8244-e2df9f952f40"
+      (reference "R4") (unit 1) (value "10K") (footprint "ataradov_smd:0603")
+    )
+    (path "/539cec94-91a0-4ec0-99cc-490e4a898fee"
+      (reference "R5") (unit 1) (value "10K") (footprint "ataradov_smd:0603")
+    )
+    (path "/5b90fd4b-899a-4541-8472-8fc45aa265a6"
+      (reference "R6") (unit 1) (value "10K") (footprint "ataradov_smd:0603")
+    )
+    (path "/c594dcf2-f562-4ebf-9380-711463f31929"
+      (reference "R7") (unit 1) (value "10K") (footprint "ataradov_smd:0603")
+    )
+    (path "/cfdc7c2b-eeb6-41c8-a335-12ee514fb84a"
+      (reference "TP1") (unit 1) (value "SWCLK") (footprint "ataradov_misc:TestPoint-1.27mm-Small")
+    )
+    (path "/6235414f-a7d9-4f2a-85bb-4ac75e44c66e"
+      (reference "TP2") (unit 1) (value "SWDIO") (footprint "ataradov_misc:TestPoint-1.27mm-Small")
+    )
+    (path "/2fdf4489-bc00-4109-aa4e-8518129c5f65"
+      (reference "TP3") (unit 1) (value "GND") (footprint "ataradov_misc:TestPoint-1.27mm-Small")
+    )
+  )
+)

dap_link/lib/free-dap/hardware/m484-dap/pcb.kicad_wks

@@ -0,0 +1,5 @@
+(kicad_wks (version 20210606) (generator pl_editor)
+  (setup (textsize 1.5 1.5)(linewidth 0.15)(textlinewidth 0.15)
+  (left_margin 10)(right_margin 10)(top_margin 10)(bottom_margin 10))
+  (line (name "segm1:Line") (start 0 0) (end 0 0))
+)

dap_link/lib/free-dap/hardware/m484-dap/sch.kicad_wks

@@ -0,0 +1,15 @@
+(kicad_wks (version 20210606) (generator pl_editor)
+  (setup (textsize 1.5 1.5)(linewidth 0.15)(textlinewidth 0.15)
+  (left_margin 10)(right_margin 10)(top_margin 10)(bottom_margin 10))
+  (rect (name "") (start 0 0 ltcorner) (end 0 0) (repeat 2) (incrx 2) (incry 2))
+  (line (name "") (start 50 2 ltcorner) (end 50 0 ltcorner) (repeat 30) (incrx 50))
+  (tbtext "1" (name "") (pos 25 1 ltcorner) (font (size 1.3 1.3)) (repeat 100) (incrx 50))
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+  (tbtext "A" (name "") (pos 1 25 ltcorner) (font (size 1.3 1.3)) (justify center) (repeat 100) (incry 50))
+  (line (name "") (start 0 50 rtcorner) (end 2 50 rtcorner) (repeat 30) (incry 50))
+  (tbtext "A" (name "") (pos 1 25 rtcorner) (font (size 1.3 1.3)) (justify center) (repeat 100) (incry 50))
+  (tbtext "${TITLE}${SHEETNAME} ${FILENAME}, rev ${REVISION} (${ISSUE_DATE}), page ${#} of ${##}" (name "") (pos 3 4) (justify right) (comment "Sheet id")
+)
+)

dap_link/lib/free-dap/platform/m484/dap_config.h

@@ -0,0 +1,239 @@
+// SPDX-License-Identifier: BSD-3-Clause
+// Copyright (c) 2022, Alex Taradov <alex@taradov.com>. All rights reserved.
+
+#ifndef _DAP_CONFIG_H_
+#define _DAP_CONFIG_H_
+
+/*- Includes ----------------------------------------------------------------*/
+#include "M480.h"
+#include "hal_config.h"
+
+/*- Definitions -------------------------------------------------------------*/
+#define DAP_CONFIG_ENABLE_JTAG
+
+#define DAP_CONFIG_DEFAULT_PORT        DAP_PORT_SWD
+#define DAP_CONFIG_DEFAULT_CLOCK       1000000 // Hz
+
+#define DAP_CONFIG_PACKET_SIZE         512
+#define DAP_CONFIG_PACKET_COUNT        1
+
+#define DAP_CONFIG_JTAG_DEV_COUNT      8
+
+// DAP_CONFIG_PRODUCT_STR must contain "CMSIS-DAP" to be compatible with the standard
+#define DAP_CONFIG_VENDOR_STR          "Alex Taradov"
+#define DAP_CONFIG_PRODUCT_STR         "Generic CMSIS-DAP Adapter"
+#define DAP_CONFIG_SER_NUM_STR         usb_serial_number
+#define DAP_CONFIG_CMSIS_DAP_VER_STR   "2.0.0"
+
+//#define DAP_CONFIG_RESET_TARGET_FN     target_specific_reset_function
+//#define DAP_CONFIG_VENDOR_FN           vendor_command_handler_function
+
+// Attribute to use for performance-critical functions
+#define DAP_CONFIG_PERFORMANCE_ATTR
+
+// A value at which dap_clock_test() produces 1 kHz output on the SWCLK pin
+#define DAP_CONFIG_DELAY_CONSTANT      19000
+
+// A threshold for switching to fast clock (no added delays)
+// This is the frequency produced by dap_clock_test(1) on the SWCLK pin
+#define DAP_CONFIG_FAST_CLOCK          8550000
+
+/*- Prototypes --------------------------------------------------------------*/
+extern char usb_serial_number[16];
+
+/*- Implementations ---------------------------------------------------------*/
+
+//-----------------------------------------------------------------------------
+static inline void DAP_CONFIG_SWCLK_TCK_write(int value)
+{
+  HAL_GPIO_SWCLK_TCK_write(value);
+}
+
+//-----------------------------------------------------------------------------
+static inline void DAP_CONFIG_SWDIO_TMS_write(int value)
+{
+  HAL_GPIO_SWDIO_TMS_write(value);
+}
+
+//-----------------------------------------------------------------------------
+static inline void DAP_CONFIG_TDI_write(int value)
+{
+#ifdef DAP_CONFIG_ENABLE_JTAG
+  HAL_GPIO_TDI_write(value);
+#else
+  (void)value;
+#endif
+}
+
+//-----------------------------------------------------------------------------
+static inline void DAP_CONFIG_TDO_write(int value)
+{
+#ifdef DAP_CONFIG_ENABLE_JTAG
+  HAL_GPIO_TDO_write(value);
+#else
+  (void)value;
+#endif
+}
+
+//-----------------------------------------------------------------------------
+static inline void DAP_CONFIG_nTRST_write(int value)
+{
+  (void)value;
+}
+
+//-----------------------------------------------------------------------------
+static inline void DAP_CONFIG_nRESET_write(int value)
+{
+  HAL_GPIO_nRESET_write(value);
+}
+
+//-----------------------------------------------------------------------------
+static inline int DAP_CONFIG_SWCLK_TCK_read(void)
+{
+  return HAL_GPIO_SWCLK_TCK_read();
+}
+
+//-----------------------------------------------------------------------------
+static inline int DAP_CONFIG_SWDIO_TMS_read(void)
+{
+  return HAL_GPIO_SWDIO_TMS_read();
+}
+
+//-----------------------------------------------------------------------------
+static inline int DAP_CONFIG_TDO_read(void)
+{
+#ifdef DAP_CONFIG_ENABLE_JTAG
+  return HAL_GPIO_TDO_read();
+#else
+  return 0;
+#endif
+}
+
+//-----------------------------------------------------------------------------
+static inline int DAP_CONFIG_TDI_read(void)
+{
+#ifdef DAP_CONFIG_ENABLE_JTAG
+  return HAL_GPIO_TDI_read();
+#else
+  return 0;
+#endif
+}
+
+//-----------------------------------------------------------------------------
+static inline int DAP_CONFIG_nTRST_read(void)
+{
+  return 0;
+}
+
+//-----------------------------------------------------------------------------
+static inline int DAP_CONFIG_nRESET_read(void)
+{
+  return HAL_GPIO_nRESET_read();
+}
+
+//-----------------------------------------------------------------------------
+static inline void DAP_CONFIG_SWCLK_TCK_set(void)
+{
+  HAL_GPIO_SWCLK_TCK_set();
+}
+
+//-----------------------------------------------------------------------------
+static inline void DAP_CONFIG_SWCLK_TCK_clr(void)
+{
+  HAL_GPIO_SWCLK_TCK_clr();
+}
+
+//-----------------------------------------------------------------------------
+static inline void DAP_CONFIG_SWDIO_TMS_in(void)
+{
+  HAL_GPIO_SWDIO_TMS_in();
+}
+
+//-----------------------------------------------------------------------------
+static inline void DAP_CONFIG_SWDIO_TMS_out(void)
+{
+  HAL_GPIO_SWDIO_TMS_out();
+}
+
+//-----------------------------------------------------------------------------
+static inline void DAP_CONFIG_SETUP(void)
+{
+  HAL_GPIO_SWCLK_TCK_in();
+  HAL_GPIO_SWDIO_TMS_in();
+  HAL_GPIO_nRESET_in();
+#ifdef DAP_CONFIG_ENABLE_JTAG
+  HAL_GPIO_TDO_in();
+  HAL_GPIO_TDI_in();
+#endif
+}
+
+//-----------------------------------------------------------------------------
+static inline void DAP_CONFIG_DISCONNECT(void)
+{
+  HAL_GPIO_SWCLK_TCK_in();
+  HAL_GPIO_SWDIO_TMS_in();
+  HAL_GPIO_nRESET_in();
+#ifdef DAP_CONFIG_ENABLE_JTAG
+  HAL_GPIO_TDO_in();
+  HAL_GPIO_TDI_in();
+#endif
+}
+
+//-----------------------------------------------------------------------------
+static inline void DAP_CONFIG_CONNECT_SWD(void)
+{
+  HAL_GPIO_SWDIO_TMS_out();
+  HAL_GPIO_SWDIO_TMS_set();
+
+  HAL_GPIO_SWCLK_TCK_out();
+  HAL_GPIO_SWCLK_TCK_set();
+
+  HAL_GPIO_nRESET_out();
+  HAL_GPIO_nRESET_set();
+
+#ifdef DAP_CONFIG_ENABLE_JTAG
+  HAL_GPIO_TDO_in();
+  HAL_GPIO_TDI_in();
+#endif
+}
+
+//-----------------------------------------------------------------------------
+static inline void DAP_CONFIG_CONNECT_JTAG(void)
+{
+  HAL_GPIO_SWDIO_TMS_out();
+  HAL_GPIO_SWDIO_TMS_set();
+
+  HAL_GPIO_SWCLK_TCK_out();
+  HAL_GPIO_SWCLK_TCK_set();
+
+  HAL_GPIO_nRESET_out();
+  HAL_GPIO_nRESET_set();
+
+#ifdef DAP_CONFIG_ENABLE_JTAG
+  HAL_GPIO_TDO_in();
+
+  HAL_GPIO_TDI_out();
+  HAL_GPIO_TDI_set();
+#endif
+}
+
+//-----------------------------------------------------------------------------
+static inline void DAP_CONFIG_LED(int index, int state)
+{
+  (void)index;
+  (void)state;
+}
+
+//-----------------------------------------------------------------------------
+__attribute__((always_inline))
+static inline void DAP_CONFIG_DELAY(uint32_t cycles)
+{
+  asm volatile (
+    "1: subs %[cycles], %[cycles], #1 \n"
+    "   bne 1b \n"
+    : [cycles] "+l"(cycles)
+  );
+}
+
+#endif // _DAP_CONFIG_H_
+

dap_link/lib/free-dap/platform/m484/hal_config.h

@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: BSD-3-Clause
+// Copyright (c) 2022, Alex Taradov <alex@taradov.com>. All rights reserved.
+
+#ifndef _HAL_CONFIG_H_
+#define _HAL_CONFIG_H_
+
+/*- Includes ----------------------------------------------------------------*/
+#include "M480.h"
+#include "hal_gpio.h"
+
+/*- Definitions -------------------------------------------------------------*/
+//#define HAL_BOARD_GENERIC
+#define HAL_BOARD_M484_DAP
+
+#if defined(HAL_BOARD_GENERIC)
+  #define HAL_CONFIG_ENABLE_VCP
+
+  HAL_GPIO_PIN(SWCLK_TCK,      B, 0)
+  HAL_GPIO_PIN(SWDIO_TMS,      B, 1)
+  HAL_GPIO_PIN(TDI,            B, 2)
+  HAL_GPIO_PIN(TDO,            B, 3)
+  HAL_GPIO_PIN(nRESET,         B, 4)
+
+  HAL_GPIO_PIN(VCP_STATUS,     A, 5);
+  HAL_GPIO_PIN(DAP_STATUS,     C, 14);
+
+  HAL_GPIO_PIN(BOOT_ENTER,     A, 7);
+
+  HAL_GPIO_PIN(UART_RX,        A, 0)
+  HAL_GPIO_PIN(UART_TX,        A, 1)
+
+  #define UART_PER             UART0
+  #define UART_RX_MPF          7
+  #define UART_TX_MPF          7
+  #define UART_APBCLK_EN       CLK_APBCLK0_UART0CKEN_Msk
+  #define UART_CLKSEL_REG      CLKSEL1
+  #define UART_CLKSEL_POS      CLK_CLKSEL1_UART0SEL_Pos
+  #define UART_CLKSEL_MSK      CLK_CLKSEL1_UART0SEL_Msk
+  #define UART_IRQ_INDEX       UART0_IRQn
+  #define UART_IRQ_HANDLER     irq_handler_uart0
+  #define UART_CLOCK           192000000
+
+#elif defined(HAL_BOARD_M484_DAP)
+  HAL_GPIO_PIN(SWCLK_TCK,      B, 2)
+  HAL_GPIO_PIN(SWDIO_TMS,      B, 5)
+  HAL_GPIO_PIN(TDI,            A, 8)
+  HAL_GPIO_PIN(TDO,            A, 11)
+  HAL_GPIO_PIN(nRESET,         F, 5)
+
+  HAL_GPIO_PIN(DAP_STATUS,     B, 7);
+
+  HAL_GPIO_PIN(BOOT_ENTER,     A, 6);
+
+#else
+  #error No board defined
+#endif
+
+#endif // _HAL_CONFIG_H_
+

dap_link/lib/free-dap/platform/m484/hal_gpio.h

@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) 2021, Alex Taradov <alex@taradov.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _HAL_GPIO_H_
+#define _HAL_GPIO_H_
+
+/*- Definitions -------------------------------------------------------------*/
+#define HAL_GPIO_PIN(name, port, pin)						\
+  static inline void HAL_GPIO_##name##_set(void)				\
+  {										\
+    P##port->PDIO[pin] = 1;							\
+    (void)HAL_GPIO_##name##_set;						\
+  }										\
+										\
+  static inline void HAL_GPIO_##name##_clr(void)				\
+  {										\
+    P##port->PDIO[pin] = 0;							\
+    (void)HAL_GPIO_##name##_clr;						\
+  }										\
+										\
+  static inline void HAL_GPIO_##name##_toggle(void)				\
+  {										\
+    P##port->DOUT ^= GPIO_DOUT_DOUT##pin##_Msk;					\
+    (void)HAL_GPIO_##name##_toggle;						\
+  }										\
+										\
+  static inline void HAL_GPIO_##name##_write(int value)				\
+  {										\
+    P##port->PDIO[pin] = (value > 0);						\
+    (void)HAL_GPIO_##name##_write;						\
+  }										\
+										\
+  static inline void HAL_GPIO_##name##_in(void)					\
+  {										\
+    P##port->MODE = (P##port->MODE & ~GPIO_MODE_MODE##pin##_Msk);		\
+    (void)HAL_GPIO_##name##_in;							\
+  }										\
+										\
+  static inline void HAL_GPIO_##name##_out(void)				\
+  {										\
+    P##port->MODE = (P##port->MODE & ~GPIO_MODE_MODE##pin##_Msk) | 		\
+        (1 << GPIO_MODE_MODE##pin##_Pos);					\
+    (void)HAL_GPIO_##name##_out;						\
+  }										\
+										\
+  static inline void HAL_GPIO_##name##_odrain(void)				\
+  {										\
+    P##port->MODE = (P##port->MODE & ~GPIO_MODE_MODE##pin##_Msk) | 		\
+        (2 << GPIO_MODE_MODE##pin##_Pos);					\
+    (void)HAL_GPIO_##name##_odrain;						\
+  }										\
+										\
+  static inline void HAL_GPIO_##name##_pullup(void)				\
+  {										\
+    P##port->PUSEL = (P##port->PUSEL & ~GPIO_PUSEL_PUSEL##pin##_Msk) | 		\
+        (1 << GPIO_PUSEL_PUSEL##pin##_Pos);					\
+    (void)HAL_GPIO_##name##_pullup;						\
+  }										\
+										\
+  static inline void HAL_GPIO_##name##_pulldown(void)				\
+  {										\
+    P##port->PUSEL = (P##port->PUSEL & ~GPIO_PUSEL_PUSEL##pin##_Msk) | 		\
+        (2 << GPIO_PUSEL_PUSEL##pin##_Pos);					\
+    (void)HAL_GPIO_##name##_pulldown;						\
+  }										\
+										\
+  static inline void HAL_GPIO_##name##_pulldis(void)				\
+  {										\
+    P##port->PUSEL = (P##port->PUSEL & ~GPIO_PUSEL_PUSEL##pin##_Msk); 		\
+    (void)HAL_GPIO_##name##_pulldis;						\
+  }										\
+										\
+  static inline int HAL_GPIO_##name##_read(void)				\
+  {										\
+    return P##port->PDIO[pin];							\
+    (void)HAL_GPIO_##name##_read;						\
+  }										\
+										\
+  static inline void HAL_GPIO_##name##_mfp(int value)				\
+  {										\
+    uint32_t mfp = (pin < 8) ? SYS->GP##port##_MFPL : SYS->GP##port##_MFPH;	\
+    uint32_t offs = ((pin < 8) ? pin : (pin-8)) * 4;				\
+    mfp = (mfp & ~(0xf << offs)) | (value << offs);				\
+    if (pin < 8)								\
+      SYS->GP##port##_MFPL = mfp;						\
+    else									\
+      SYS->GP##port##_MFPH = mfp;						\
+    (void)HAL_GPIO_##name##_mfp;						\
+  }										\
+										\
+  static inline void HAL_GPIO_##name##_mfos(int value)				\
+  {										\
+    if (value)									\
+      SYS->GP##port##_MFOS |= SYS_GPA_MFOS_MFOS##pin##_Msk;			\
+    else									\
+      SYS->GP##port##_MFOS &= ~SYS_GPA_MFOS_MFOS##pin##_Msk;			\
+    (void)HAL_GPIO_##name##_mfos;						\
+  }										\
+										\
+  static inline void HAL_GPIO_##name##_smten(int value)				\
+  {										\
+    if (value)									\
+      P##port->SMTEN |= GPIO_SMTEN_SMTEN##pin##_Msk;				\
+    else									\
+      P##port->SMTEN &= ~GPIO_SMTEN_SMTEN##pin##_Msk;				\
+    (void)HAL_GPIO_##name##_smten;						\
+  }										\
+										\
+  static inline void HAL_GPIO_##name##_dinoff(int value)			\
+  {										\
+    if (value)									\
+      P##port->DINOFF |= GPIO_DINOFF_DINOFF##pin##_Msk;				\
+    else									\
+      P##port->DINOFF &= ~GPIO_DINOFF_DINOFF##pin##_Msk;			\
+    (void)HAL_GPIO_##name##_dinoff;						\
+  }										\
+										\
+  static inline void HAL_GPIO_##name##_dben(int value)				\
+  {										\
+    if (value)									\
+      P##port->DBEN |= GPIO_DBEN_DBEN##pin##_Msk;				\
+    else									\
+      P##port->DBEN &= ~GPIO_DBEN_DBEN##pin##_Msk;				\
+    (void)HAL_GPIO_##name##_dben;						\
+  }										\
+										\
+  static inline void HAL_GPIO_##name##_slew(int value)				\
+  {										\
+    P##port->SLEWCTL = (P##port->SLEWCTL & ~GPIO_SLEWCTL_HSREN##pin##_Msk) |	\
+        (value << GPIO_SLEWCTL_HSREN##pin##_Pos);				\
+    (void)HAL_GPIO_##name##_slew;						\
+  }										\
+
+#endif // _HAL_GPIO_H_
+
+

dap_link/lib/free-dap/platform/m484/include/M480.h

@@ -0,0 +1,716 @@
+/**************************************************************************//**
+ * @file     M480.h
+ * @version  V1.00
+ * @brief    M480 peripheral access layer header file.
+ *           This file contains all the peripheral register's definitions,
+ *           bits definitions and memory mapping for NuMicro M480 MCU.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+/**
+  \mainpage NuMicro M480 Driver Reference Guide
+  *
+  * <b>Introduction</b>
+  *
+  * This user manual describes the usage of M480 Series MCU device driver
+  *
+  * <b>Disclaimer</b>
+  *
+  * The Software is furnished "AS IS", without warranty as to performance or results, and
+  * the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all
+  * warranties, express, implied or otherwise, with regard to the Software, its use, or
+  * operation, including without limitation any and all warranties of merchantability, fitness
+  * for a particular purpose, and non-infringement of intellectual property rights.
+  *
+  * <b>Important Notice</b>
+  *
+  * Nuvoton Products are neither intended nor warranted for usage in systems or equipment,
+  * any malfunction or failure of which may cause loss of human life, bodily injury or severe
+  * property damage. Such applications are deemed, "Insecure Usage".
+  *
+  * Insecure usage includes, but is not limited to: equipment for surgical implementation,
+  * atomic energy control instruments, airplane or spaceship instruments, the control or
+  * operation of dynamic, brake or safety systems designed for vehicular use, traffic signal
+  * instruments, all types of safety devices, and other applications intended to support or
+  * sustain life.
+  *
+  * All Insecure Usage shall be made at customer's risk, and in the event that third parties
+  * lay claims to Nuvoton as a result of customer's Insecure Usage, customer shall indemnify
+  * the damages and liabilities thus incurred by Nuvoton.
+  *
+  * Please note that all data and specifications are subject to change without notice. All the
+  * trademarks of products and companies mentioned in this datasheet belong to their respective
+  * owners.
+  *
+  * <b>Copyright Notice</b>
+  *
+  * Copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+  */
+#ifndef __M480_H__
+#define __M480_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SET_FIELD(p, r, f, v) p->r = (p->r & ~p##_##r##_##f##_Msk) | ((v) << p##_##r##_##f##_Pos)
+
+/******************************************************************************/
+/*                Processor and Core Peripherals                              */
+/******************************************************************************/
+/** @addtogroup CMSIS_Device Device CMSIS Definitions
+  Configuration of the Cortex-M4 Processor and Core Peripherals
+  @{
+*/
+
+/**
+ * @details  Interrupt Number Definition.
+ */
+typedef enum IRQn
+{
+    /******  Cortex-M4 Processor Exceptions Numbers ***************************************************/
+    NonMaskableInt_IRQn           = -14,      /*!<  2 Non Maskable Interrupt                        */
+    MemoryManagement_IRQn         = -12,      /*!<  4 Memory Management Interrupt                   */
+    BusFault_IRQn                 = -11,      /*!<  5 Bus Fault Interrupt                           */
+    UsageFault_IRQn               = -10,      /*!<  6 Usage Fault Interrupt                         */
+    SVCall_IRQn                   = -5,       /*!< 11 SV Call Interrupt                             */
+    DebugMonitor_IRQn             = -4,       /*!< 12 Debug Monitor Interrupt                       */
+    PendSV_IRQn                   = -2,       /*!< 14 Pend SV Interrupt                             */
+    SysTick_IRQn                  = -1,       /*!< 15 System Tick Interrupt                         */
+
+    /******  M480 Specific Interrupt Numbers ********************************************************/
+
+    BOD_IRQn                      = 0,        /*!< Brown Out detection Interrupt                    */
+    IRC_IRQn                      = 1,        /*!< Internal RC Interrupt                            */
+    PWRWU_IRQn                    = 2,        /*!< Power Down Wake Up Interrupt                     */
+    RAMPE_IRQn                    = 3,        /*!< SRAM parity check failed Interrupt               */
+    CKFAIL_IRQn                   = 4,        /*!< Clock failed Interrupt                           */
+    RTC_IRQn                      = 6,        /*!< Real Time Clock Interrupt                        */
+    TAMPER_IRQn                   = 7,        /*!< Tamper detection Interrupt                       */
+    WDT_IRQn                      = 8,        /*!< Watchdog timer Interrupt                         */
+    WWDT_IRQn                     = 9,        /*!< Window Watchdog timer Interrupt                  */
+    EINT0_IRQn                    = 10,       /*!< External Input 0 Interrupt                       */
+    EINT1_IRQn                    = 11,       /*!< External Input 1 Interrupt                       */
+    EINT2_IRQn                    = 12,       /*!< External Input 2 Interrupt                       */
+    EINT3_IRQn                    = 13,       /*!< External Input 3 Interrupt                       */
+    EINT4_IRQn                    = 14,       /*!< External Input 4 Interrupt                       */
+    EINT5_IRQn                    = 15,       /*!< External Input 5 Interrupt                       */
+    GPA_IRQn                      = 16,       /*!< GPIO Port A Interrupt                            */
+    GPB_IRQn                      = 17,       /*!< GPIO Port B Interrupt                            */
+    GPC_IRQn                      = 18,       /*!< GPIO Port C Interrupt                            */
+    GPD_IRQn                      = 19,       /*!< GPIO Port D Interrupt                            */
+    GPE_IRQn                      = 20,       /*!< GPIO Port E Interrupt                            */
+    GPF_IRQn                      = 21,       /*!< GPIO Port F Interrupt                            */
+    QSPI0_IRQn                    = 22,       /*!< QSPI0 Interrupt                                   */
+    SPI0_IRQn                     = 23,       /*!< SPI0 Interrupt                                   */
+    BRAKE0_IRQn                   = 24,       /*!< BRAKE0 Interrupt                                 */
+    EPWM0P0_IRQn                  = 25,       /*!< EPWM0P0 Interrupt                                */
+    EPWM0P1_IRQn                  = 26,       /*!< EPWM0P1 Interrupt                                */
+    EPWM0P2_IRQn                  = 27,       /*!< EPWM0P2 Interrupt                                */
+    BRAKE1_IRQn                   = 28,       /*!< BRAKE1 Interrupt                                 */
+    EPWM1P0_IRQn                  = 29,       /*!< EPWM1P0 Interrupt                                */
+    EPWM1P1_IRQn                  = 30,       /*!< EPWM1P1 Interrupt                                */
+    EPWM1P2_IRQn                  = 31,       /*!< EPWM1P2 Interrupt                                */
+    TMR0_IRQn                     = 32,       /*!< Timer 0 Interrupt                                */
+    TMR1_IRQn                     = 33,       /*!< Timer 1 Interrupt                                */
+    TMR2_IRQn                     = 34,       /*!< Timer 2 Interrupt                                */
+    TMR3_IRQn                     = 35,       /*!< Timer 3 Interrupt                                */
+    UART0_IRQn                    = 36,       /*!< UART 0 Interrupt                                 */
+    UART1_IRQn                    = 37,       /*!< UART 1 Interrupt                                 */
+    I2C0_IRQn                     = 38,       /*!< I2C 0 Interrupt                                  */
+    I2C1_IRQn                     = 39,       /*!< I2C 1 Interrupt                                  */
+    PDMA_IRQn                     = 40,       /*!< Peripheral DMA Interrupt                         */
+    DAC_IRQn                      = 41,       /*!< DAC Interrupt                                    */
+    EADC00_IRQn                   = 42,       /*!< EADC00 Interrupt                                 */
+    EADC01_IRQn                   = 43,       /*!< EADC01 Interrupt                                 */
+    ACMP01_IRQn                   = 44,       /*!< Analog Comparator 0 and 1 Interrupt              */
+    EADC02_IRQn                   = 46,       /*!< EADC02 Interrupt                                 */
+    EADC03_IRQn                   = 47,       /*!< EADC03 Interrupt                                 */
+    UART2_IRQn                    = 48,       /*!< UART2 Interrupt                                  */
+    UART3_IRQn                    = 49,       /*!< UART3 Interrupt                                  */
+    QSPI1_IRQn                    = 50,       /*!< QSPI1 Interrupt                                   */
+    SPI1_IRQn                     = 51,       /*!< SPI1 Interrupt                                   */
+    SPI2_IRQn                     = 52,       /*!< SPI2 Interrupt                                   */
+    USBD_IRQn                     = 53,       /*!< USB device Interrupt                             */
+    USBH_IRQn                     = 54,       /*!< USB host Interrupt                               */
+    USBOTG_IRQn                   = 55,       /*!< USB OTG Interrupt                                */
+    CAN0_IRQn                     = 56,       /*!< CAN0 Interrupt                                   */
+    CAN1_IRQn                     = 57,       /*!< CAN1 Interrupt                                   */
+    SC0_IRQn                      = 58,       /*!< Smart Card 0 Interrupt                           */
+    SC1_IRQn                      = 59,       /*!< Smart Card 1 Interrupt                           */
+    SC2_IRQn                      = 60,       /*!< Smart Card 2 Interrupt                           */
+    SPI3_IRQn                     = 62,       /*!< SPI3 Interrupt                                   */
+    EMAC_TX_IRQn                  = 66,       /*!< Ethernet MAC TX Interrupt                        */
+    EMAC_RX_IRQn                  = 67,       /*!< Ethernet MAC RX Interrupt                        */
+    SDH0_IRQn                     = 64,       /*!< Secure Digital Host Controller 0 Interrupt       */
+    USBD20_IRQn                   = 65,       /*!< High Speed USB device Interrupt                  */
+    I2S0_IRQn                     = 68,       /*!< I2S0 Interrupt                                   */
+    OPA_IRQn                      = 70,       /*!< OPA Interrupt                                    */
+    CRPT_IRQn                     = 71,       /*!< CRPT Interrupt                                   */
+    GPG_IRQn                      = 72,       /*!< GPIO Port G Interrupt                            */
+    EINT6_IRQn                    = 73,       /*!< External Input 6 Interrupt                       */
+    UART4_IRQn                    = 74,       /*!< UART4 Interrupt                                  */
+    UART5_IRQn                    = 75,       /*!< UART5 Interrupt                                  */
+    USCI0_IRQn                    = 76,       /*!< USCI0 Interrupt                                  */
+    USCI1_IRQn                    = 77,       /*!< USCI1 Interrupt                                  */
+    BPWM0_IRQn                    = 78,       /*!< BPWM0 Interrupt                                  */
+    BPWM1_IRQn                    = 79,       /*!< BPWM1 Interrupt                                  */
+    SPIM_IRQn                     = 80,       /*!< SPIM Interrupt                                   */
+    CCAP_IRQn                     = 81,       /*!< CCAP Interrupt                                   */
+    I2C2_IRQn                     = 82,       /*!< I2C2 Interrupt                                   */
+    QEI0_IRQn                     = 84,       /*!< QEI0 Interrupt                                   */
+    QEI1_IRQn                     = 85,       /*!< QEI1 Interrupt                                   */
+    ECAP0_IRQn                    = 86,       /*!< ECAP0 Interrupt                                  */
+    ECAP1_IRQn                    = 87,       /*!< ECAP1 Interrupt                                  */
+    GPH_IRQn                      = 88,       /*!< GPIO Port H Interrupt                            */
+    EINT7_IRQn                    = 89,       /*!< External Input 7 Interrupt                       */
+    SDH1_IRQn                     = 90,       /*!< Secure Digital Host Controller 1 Interrupt       */
+    HSUSBH_IRQn                   = 92,       /*!< High speed USB host Interrupt                    */
+    USBOTG20_IRQn                 = 93,       /*!< High speed USB OTG Interrupt                     */
+    TRNG_IRQn                     = 101,      /*!< TRNG Interrupt                                   */
+    UART6_IRQn                    = 102,      /*!< UART6 Interrupt                                  */
+    UART7_IRQn                    = 103,      /*!< UART7 Interrupt                                  */
+    EADC10_IRQn                   = 104,      /*!< EADC10 Interrupt                                 */
+    EADC11_IRQn                   = 105,      /*!< EADC11 Interrupt                                 */
+    EADC12_IRQn                   = 106,      /*!< EADC12 Interrupt                                 */
+    EADC13_IRQn                   = 107,      /*!< EADC13 Interrupt                                 */
+    CAN2_IRQn                     = 108,      /*!< CAN2 Interrupt                                   */
+}
+IRQn_Type;
+
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M4 Processor and Core Peripherals */
+#define __CM4_REV                 0x0201UL    /*!< Core Revision r2p1                               */
+#define __NVIC_PRIO_BITS          4UL         /*!< Number of Bits used for Priority Levels          */
+#define __Vendor_SysTickConfig    0UL         /*!< Set to 1 if different SysTick Config is used     */
+#define __MPU_PRESENT             1UL         /*!< MPU present or not                               */
+#ifdef __FPU_PRESENT
+#undef __FPU_PRESENT
+#define __FPU_PRESENT             1UL         /*!< FPU present or not                               */
+#else
+#define __FPU_PRESENT             1UL         /*!< FPU present or not                               */
+#endif
+
+/*@}*/ /* end of group CMSIS_Device */
+
+
+#include "core_cm4.h"               /* Cortex-M4 processor and core peripherals           */
+#include "system_M480.h"            /* System include file                         */
+#include <stdint.h>
+
+
+
+#if defined ( __CC_ARM   )
+#pragma anon_unions
+#endif
+
+/******************************************************************************/
+/*                            Register definitions                            */
+/******************************************************************************/
+
+#include "sys_reg.h"
+#include "clk_reg.h"
+#include "fmc_reg.h"
+#include "gpio_reg.h"
+#include "pdma_reg.h"
+#include "timer_reg.h"
+#include "wdt_reg.h"
+#include "wwdt_reg.h"
+#include "rtc_reg.h"
+#include "epwm_reg.h"
+#include "bpwm_reg.h"
+#include "qei_reg.h"
+#include "ecap_reg.h"
+#include "uart_reg.h"
+#include "emac_reg.h"
+#include "sc_reg.h"
+#include "i2s_reg.h"
+#include "spi_reg.h"
+#include "qspi_reg.h"
+#include "spim_reg.h"
+#include "i2c_reg.h"
+#include "uuart_reg.h"
+#include "uspi_reg.h"
+#include "ui2c_reg.h"
+#include "can_reg.h"
+#include "sdh_reg.h"
+#include "ebi_reg.h"
+#include "usbd_reg.h"
+#include "hsusbd_reg.h"
+#include "usbh_reg.h"
+#include "hsusbh_reg.h"
+#include "otg_reg.h"
+#include "hsotg_reg.h"
+#include "crc_reg.h"
+#include "crypto_reg.h"
+#include "trng_reg.h"
+#include "eadc_reg.h"
+#include "dac_reg.h"
+#include "acmp_reg.h"
+#include "opa_reg.h"
+#include "ccap_reg.h"
+
+
+/** @addtogroup PERIPHERAL_MEM_MAP Peripheral Memory Base
+  Memory Mapped Structure for Peripherals
+  @{
+ */
+/* Peripheral and SRAM base address */
+#define FLASH_BASE           ((uint32_t)0x00000000)      /*!< Flash base address      */
+#define SRAM_BASE            ((uint32_t)0x20000000)      /*!< SRAM Base Address       */
+#define PERIPH_BASE          ((uint32_t)0x40000000)      /*!< Peripheral Base Address */
+#define AHBPERIPH_BASE       PERIPH_BASE                 /*!< AHB Base Address */
+#define APBPERIPH_BASE       (PERIPH_BASE + (uint32_t)0x00040000)  /*!< APB Base Address */
+
+/*!< AHB peripherals */
+#define SYS_BASE               (AHBPERIPH_BASE + 0x00000UL)
+#define CLK_BASE               (AHBPERIPH_BASE + 0x00200UL)
+#define NMI_BASE               (AHBPERIPH_BASE + 0x00300UL)
+#define GPIOA_BASE             (AHBPERIPH_BASE + 0x04000UL)
+#define GPIOB_BASE             (AHBPERIPH_BASE + 0x04040UL)
+#define GPIOC_BASE             (AHBPERIPH_BASE + 0x04080UL)
+#define GPIOD_BASE             (AHBPERIPH_BASE + 0x040C0UL)
+#define GPIOE_BASE             (AHBPERIPH_BASE + 0x04100UL)
+#define GPIOF_BASE             (AHBPERIPH_BASE + 0x04140UL)
+#define GPIOG_BASE             (AHBPERIPH_BASE + 0x04180UL)
+#define GPIOH_BASE             (AHBPERIPH_BASE + 0x041C0UL)
+#define GPIOI_BASE             (AHBPERIPH_BASE + 0x04200UL)
+#define GPIO_DBCTL_BASE        (AHBPERIPH_BASE + 0x04440UL)
+#define GPIO_PIN_DATA_BASE     (AHBPERIPH_BASE + 0x04800UL)
+#define PDMA_BASE              (AHBPERIPH_BASE + 0x08000UL)
+#define USBH_BASE              (AHBPERIPH_BASE + 0x09000UL)
+#define HSUSBH_BASE            (AHBPERIPH_BASE + 0x1A000UL)
+#define EMAC_BASE              (AHBPERIPH_BASE + 0x0B000UL)
+#define FMC_BASE               (AHBPERIPH_BASE + 0x0C000UL)
+#define SDH0_BASE              (AHBPERIPH_BASE + 0x0D000UL)
+#define SDH1_BASE              (AHBPERIPH_BASE + 0x0E000UL)
+#define EBI_BASE               (AHBPERIPH_BASE + 0x10000UL)
+#define HSUSBD_BASE            (AHBPERIPH_BASE + 0x19000UL)
+#define CCAP_BASE              (AHBPERIPH_BASE + 0x30000UL)
+#define CRC_BASE               (AHBPERIPH_BASE + 0x31000UL)
+#define TAMPER_BASE            (AHBPERIPH_BASE + 0xE1000UL)
+
+/*!< APB2 peripherals */
+#define WDT_BASE              (APBPERIPH_BASE + 0x00000UL)
+#define WWDT_BASE             (APBPERIPH_BASE + 0x00100UL)
+#define OPA_BASE              (APBPERIPH_BASE + 0x06000UL)
+#define I2S_BASE              (APBPERIPH_BASE + 0x08000UL)
+#define EADC1_BASE            (APBPERIPH_BASE + 0x0B000UL)
+#define TIMER0_BASE           (APBPERIPH_BASE + 0x10000UL)
+#define TIMER1_BASE           (APBPERIPH_BASE + 0x10100UL)
+#define EPWM0_BASE            (APBPERIPH_BASE + 0x18000UL)
+#define BPWM0_BASE            (APBPERIPH_BASE + 0x1A000UL)
+#define QSPI0_BASE            (APBPERIPH_BASE + 0x20000UL)
+#define SPI1_BASE             (APBPERIPH_BASE + 0x22000UL)
+#define SPI3_BASE             (APBPERIPH_BASE + 0x24000UL)
+#define UART0_BASE            (APBPERIPH_BASE + 0x30000UL)
+#define UART2_BASE            (APBPERIPH_BASE + 0x32000UL)
+#define UART4_BASE            (APBPERIPH_BASE + 0x34000UL)
+#define UART6_BASE            (APBPERIPH_BASE + 0x36000UL)
+#define I2C0_BASE             (APBPERIPH_BASE + 0x40000UL)
+#define I2C2_BASE             (APBPERIPH_BASE + 0x42000UL)
+#define CAN0_BASE             (APBPERIPH_BASE + 0x60000UL)
+#define CAN2_BASE             (APBPERIPH_BASE + 0x62000UL)
+#define QEI0_BASE             (APBPERIPH_BASE + 0x70000UL)
+#define ECAP0_BASE            (APBPERIPH_BASE + 0x74000UL)
+#define USCI0_BASE            (APBPERIPH_BASE + 0x90000UL)
+
+
+/*!< APB1 peripherals */
+#define RTC_BASE              (APBPERIPH_BASE + 0x01000UL)
+#define EADC_BASE             (APBPERIPH_BASE + 0x03000UL)
+#define ACMP01_BASE           (APBPERIPH_BASE + 0x05000UL)
+#define USBD_BASE             (APBPERIPH_BASE + 0x80000UL)
+#define OTG_BASE              (APBPERIPH_BASE + 0x0D000UL)
+#define HSOTG_BASE            (APBPERIPH_BASE + 0x0F000UL)
+#define TIMER2_BASE           (APBPERIPH_BASE + 0x11000UL)
+#define TIMER3_BASE           (APBPERIPH_BASE + 0x11100UL)
+#define EPWM1_BASE            (APBPERIPH_BASE + 0x19000UL)
+#define BPWM1_BASE            (APBPERIPH_BASE + 0x1B000UL)
+#define SPI0_BASE             (APBPERIPH_BASE + 0x21000UL)
+#define SPI2_BASE             (APBPERIPH_BASE + 0x23000UL)
+#define QSPI1_BASE            (APBPERIPH_BASE + 0x29000UL)
+#define UART1_BASE            (APBPERIPH_BASE + 0x31000UL)
+#define UART3_BASE            (APBPERIPH_BASE + 0x33000UL)
+#define UART5_BASE            (APBPERIPH_BASE + 0x35000UL)
+#define UART7_BASE            (APBPERIPH_BASE + 0x37000UL)
+#define I2C1_BASE             (APBPERIPH_BASE + 0x41000UL)
+#define CAN1_BASE             (APBPERIPH_BASE + 0x61000UL)
+#define QEI1_BASE             (APBPERIPH_BASE + 0x71000UL)
+#define ECAP1_BASE            (APBPERIPH_BASE + 0x75000UL)
+#define TRNG_BASE             (APBPERIPH_BASE + 0x79000UL)
+#define USCI1_BASE            (APBPERIPH_BASE + 0x91000UL)
+#define CRPT_BASE             (0x50080000UL)
+#define SPIM_BASE             (0x40007000UL)
+
+#define SC0_BASE             (APBPERIPH_BASE + 0x50000UL)
+#define SC1_BASE             (APBPERIPH_BASE + 0x51000UL)
+#define SC2_BASE             (APBPERIPH_BASE + 0x52000UL)
+#define DAC0_BASE            (APBPERIPH_BASE + 0x07000UL)
+#define DAC1_BASE            (APBPERIPH_BASE + 0x07040UL)
+#define DACDBG_BASE          (APBPERIPH_BASE + 0x07FECUL)
+#define OPA0_BASE            (APBPERIPH_BASE + 0x06000UL)
+
+/*@}*/ /* end of group PERIPHERAL_MEM_MAP */
+
+
+/** @addtogroup PERIPHERAL_DECLARATION Peripheral Pointer
+  The Declaration of Peripherals
+  @{
+ */
+
+#define SYS                  ((SYS_T *)   SYS_BASE)
+#define CLK                  ((CLK_T *)   CLK_BASE)
+#define NMI                  ((NMI_T *)   NMI_BASE)
+#define PA                   ((GPIO_T *)  GPIOA_BASE)
+#define PB                   ((GPIO_T *)  GPIOB_BASE)
+#define PC                   ((GPIO_T *)  GPIOC_BASE)
+#define PD                   ((GPIO_T *)  GPIOD_BASE)
+#define PE                   ((GPIO_T *)  GPIOE_BASE)
+#define PF                   ((GPIO_T *)  GPIOF_BASE)
+#define PG                   ((GPIO_T *)  GPIOG_BASE)
+#define PH                   ((GPIO_T *)  GPIOH_BASE)
+#define GPA                  ((GPIO_T *)  GPIOA_BASE)
+#define GPB                  ((GPIO_T *)  GPIOB_BASE)
+#define GPC                  ((GPIO_T *)  GPIOC_BASE)
+#define GPD                  ((GPIO_T *)  GPIOD_BASE)
+#define GPE                  ((GPIO_T *)  GPIOE_BASE)
+#define GPF                  ((GPIO_T *)  GPIOF_BASE)
+#define GPG                  ((GPIO_T *)  GPIOG_BASE)
+#define GPH                  ((GPIO_T *)  GPIOH_BASE)
+#define GPIO                 ((GPIO_DBCTL_T *) GPIO_DBCTL_BASE)
+#define PDMA                 ((PDMA_T *)  PDMA_BASE)
+#define USBH                 ((USBH_T *)  USBH_BASE)
+#define HSUSBH               ((HSUSBH_T *)  HSUSBH_BASE)
+#define EMAC                 ((EMAC_T *)  EMAC_BASE)
+#define FMC                  ((FMC_T *)   FMC_BASE)
+#define SDH0                 ((SDH_T *)   SDH0_BASE)
+#define SDH1                 ((SDH_T *)   SDH1_BASE)
+#define EBI                  ((EBI_T *)   EBI_BASE)
+#define CRC                  ((CRC_T *)   CRC_BASE)
+#define TAMPER               ((TAMPER_T *) TAMPER_BASE)
+
+#define WDT                  ((WDT_T *)   WDT_BASE)
+#define WWDT                 ((WWDT_T *)  WWDT_BASE)
+#define RTC                  ((RTC_T *)   RTC_BASE)
+#define EADC                 ((EADC_T *)  EADC_BASE)
+#define EADC0                ((EADC_T *)  EADC_BASE)
+#define EADC1                ((EADC_T *)  EADC1_BASE)
+#define ACMP01               ((ACMP_T *)  ACMP01_BASE)
+
+#define I2S0                 ((I2S_T *)   I2S_BASE)
+#define USBD                 ((USBD_T *)  USBD_BASE)
+#define OTG                  ((OTG_T *)   OTG_BASE)
+#define HSUSBD               ((HSUSBD_T *)HSUSBD_BASE)
+#define HSOTG                ((HSOTG_T *) HSOTG_BASE)
+#define TIMER0               ((TIMER_T *) TIMER0_BASE)
+#define TIMER1               ((TIMER_T *) TIMER1_BASE)
+#define TIMER2               ((TIMER_T *) TIMER2_BASE)
+#define TIMER3               ((TIMER_T *) TIMER3_BASE)
+#define EPWM0                ((EPWM_T *)  EPWM0_BASE)
+#define EPWM1                ((EPWM_T *)  EPWM1_BASE)
+#define BPWM0                ((BPWM_T *)  BPWM0_BASE)
+#define BPWM1                ((BPWM_T *)  BPWM1_BASE)
+#define ECAP0                ((ECAP_T *)  ECAP0_BASE)
+#define ECAP1                ((ECAP_T *)  ECAP1_BASE)
+#define QEI0                 ((QEI_T *)   QEI0_BASE)
+#define QEI1                 ((QEI_T *)   QEI1_BASE)
+#define QSPI0                ((QSPI_T *)  QSPI0_BASE)
+#define QSPI1                ((QSPI_T *)  QSPI1_BASE)
+#define SPI0                 ((SPI_T *)   SPI0_BASE)
+#define SPI1                 ((SPI_T *)   SPI1_BASE)
+#define SPI2                 ((SPI_T *)   SPI2_BASE)
+#define SPI3                 ((SPI_T *)   SPI3_BASE)
+#define UART0                ((UART_T *)  UART0_BASE)
+#define UART1                ((UART_T *)  UART1_BASE)
+#define UART2                ((UART_T *)  UART2_BASE)
+#define UART3                ((UART_T *)  UART3_BASE)
+#define UART4                ((UART_T *)  UART4_BASE)
+#define UART5                ((UART_T *)  UART5_BASE)
+#define UART6                ((UART_T *)  UART6_BASE)
+#define UART7                ((UART_T *)  UART7_BASE)
+#define I2C0                 ((I2C_T *)   I2C0_BASE)
+#define I2C1                 ((I2C_T *)   I2C1_BASE)
+#define I2C2                 ((I2C_T *)   I2C2_BASE)
+#define SC0                  ((SC_T *)    SC0_BASE)
+#define SC1                  ((SC_T *)    SC1_BASE)
+#define SC2                  ((SC_T *)    SC2_BASE)
+#define CAN0                 ((CAN_T *)   CAN0_BASE)
+#define CAN1                 ((CAN_T *)   CAN1_BASE)
+#define CAN2                 ((CAN_T *)   CAN2_BASE)
+#define CRPT                 ((CRPT_T *)  CRPT_BASE)
+#define TRNG                 ((TRNG_T *)  TRNG_BASE)
+#define SPIM                 ((volatile SPIM_T *)  SPIM_BASE)
+#define DAC0                 ((DAC_T *)   DAC0_BASE)
+#define DAC1                 ((DAC_T *)   DAC1_BASE)
+#define USPI0                ((USPI_T *) USCI0_BASE)                     /*!< USPI0 Configuration Struct                       */
+#define USPI1                ((USPI_T *) USCI1_BASE)                     /*!< USPI1 Configuration Struct                       */
+#define OPA                  ((OPA_T *) OPA_BASE)
+#define UI2C0                ((UI2C_T *) USCI0_BASE)                     /*!< UI2C0 Configuration Struct                       */
+#define UI2C1                ((UI2C_T *) USCI1_BASE)                     /*!< UI2C1 Configuration Struct                       */
+#define UUART0               ((UUART_T *) USCI0_BASE)                    /*!< UUART0 Configuration Struct                      */
+#define UUART1               ((UUART_T *) USCI1_BASE)                    /*!< UUART1 Configuration Struct                      */
+#define CCAP                 ((CCAP_T *)  CCAP_BASE)
+
+/*@}*/ /* end of group ERIPHERAL_DECLARATION */
+
+/** @addtogroup IO_ROUTINE I/O Routines
+  The Declaration of I/O Routines
+  @{
+ */
+
+typedef volatile unsigned char  vu8;        ///< Define 8-bit unsigned volatile data type
+typedef volatile unsigned short vu16;       ///< Define 16-bit unsigned volatile data type
+typedef volatile unsigned long  vu32;       ///< Define 32-bit unsigned volatile data type
+
+/**
+  * @brief Get a 8-bit unsigned value from specified address
+  * @param[in] addr Address to get 8-bit data from
+  * @return  8-bit unsigned value stored in specified address
+  */
+#define M8(addr)  (*((vu8  *) (addr)))
+
+/**
+  * @brief Get a 16-bit unsigned value from specified address
+  * @param[in] addr Address to get 16-bit data from
+  * @return  16-bit unsigned value stored in specified address
+  * @note The input address must be 16-bit aligned
+  */
+#define M16(addr) (*((vu16 *) (addr)))
+
+/**
+  * @brief Get a 32-bit unsigned value from specified address
+  * @param[in] addr Address to get 32-bit data from
+  * @return  32-bit unsigned value stored in specified address
+  * @note The input address must be 32-bit aligned
+  */
+#define M32(addr) (*((vu32 *) (addr)))
+
+/**
+  * @brief Set a 32-bit unsigned value to specified I/O port
+  * @param[in] port Port address to set 32-bit data
+  * @param[in] value Value to write to I/O port
+  * @return  None
+  * @note The output port must be 32-bit aligned
+  */
+#define outpw(port,value)     *((volatile unsigned int *)(port)) = (value)
+
+/**
+  * @brief Get a 32-bit unsigned value from specified I/O port
+  * @param[in] port Port address to get 32-bit data from
+  * @return  32-bit unsigned value stored in specified I/O port
+  * @note The input port must be 32-bit aligned
+  */
+#define inpw(port)            (*((volatile unsigned int *)(port)))
+
+/**
+  * @brief Set a 16-bit unsigned value to specified I/O port
+  * @param[in] port Port address to set 16-bit data
+  * @param[in] value Value to write to I/O port
+  * @return  None
+  * @note The output port must be 16-bit aligned
+  */
+#define outps(port,value)     *((volatile unsigned short *)(port)) = (value)
+
+/**
+  * @brief Get a 16-bit unsigned value from specified I/O port
+  * @param[in] port Port address to get 16-bit data from
+  * @return  16-bit unsigned value stored in specified I/O port
+  * @note The input port must be 16-bit aligned
+  */
+#define inps(port)            (*((volatile unsigned short *)(port)))
+
+/**
+  * @brief Set a 8-bit unsigned value to specified I/O port
+  * @param[in] port Port address to set 8-bit data
+  * @param[in] value Value to write to I/O port
+  * @return  None
+  */
+#define outpb(port,value)     *((volatile unsigned char *)(port)) = (value)
+
+/**
+  * @brief Get a 8-bit unsigned value from specified I/O port
+  * @param[in] port Port address to get 8-bit data from
+  * @return  8-bit unsigned value stored in specified I/O port
+  */
+#define inpb(port)            (*((volatile unsigned char *)(port)))
+
+/**
+  * @brief Set a 32-bit unsigned value to specified I/O port
+  * @param[in] port Port address to set 32-bit data
+  * @param[in] value Value to write to I/O port
+  * @return  None
+  * @note The output port must be 32-bit aligned
+  */
+#define outp32(port,value)    *((volatile unsigned int *)(port)) = (value)
+
+/**
+  * @brief Get a 32-bit unsigned value from specified I/O port
+  * @param[in] port Port address to get 32-bit data from
+  * @return  32-bit unsigned value stored in specified I/O port
+  * @note The input port must be 32-bit aligned
+  */
+#define inp32(port)           (*((volatile unsigned int *)(port)))
+
+/**
+  * @brief Set a 16-bit unsigned value to specified I/O port
+  * @param[in] port Port address to set 16-bit data
+  * @param[in] value Value to write to I/O port
+  * @return  None
+  * @note The output port must be 16-bit aligned
+  */
+#define outp16(port,value)    *((volatile unsigned short *)(port)) = (value)
+
+/**
+  * @brief Get a 16-bit unsigned value from specified I/O port
+  * @param[in] port Port address to get 16-bit data from
+  * @return  16-bit unsigned value stored in specified I/O port
+  * @note The input port must be 16-bit aligned
+  */
+#define inp16(port)           (*((volatile unsigned short *)(port)))
+
+/**
+  * @brief Set a 8-bit unsigned value to specified I/O port
+  * @param[in] port Port address to set 8-bit data
+  * @param[in] value Value to write to I/O port
+  * @return  None
+  */
+#define outp8(port,value)     *((volatile unsigned char *)(port)) = (value)
+
+/**
+  * @brief Get a 8-bit unsigned value from specified I/O port
+  * @param[in] port Port address to get 8-bit data from
+  * @return  8-bit unsigned value stored in specified I/O port
+  */
+#define inp8(port)            (*((volatile unsigned char *)(port)))
+
+
+/*@}*/ /* end of group IO_ROUTINE */
+
+/******************************************************************************/
+/*                Legacy Constants                                            */
+/******************************************************************************/
+/** @addtogroup Legacy_Constants Legacy Constants
+  Legacy Constants
+  @{
+*/
+
+#ifndef NULL
+#define NULL           (0)      ///< NULL pointer
+#endif
+
+#define TRUE           (1UL)      ///< Boolean true, define to use in API parameters or return value
+#define FALSE          (0UL)      ///< Boolean false, define to use in API parameters or return value
+
+#define ENABLE         (1UL)      ///< Enable, define to use in API parameters
+#define DISABLE        (0UL)      ///< Disable, define to use in API parameters
+
+/* Define one bit mask */
+#define BIT0     (0x00000001UL)       ///< Bit 0 mask of an 32 bit integer
+#define BIT1     (0x00000002UL)       ///< Bit 1 mask of an 32 bit integer
+#define BIT2     (0x00000004UL)       ///< Bit 2 mask of an 32 bit integer
+#define BIT3     (0x00000008UL)       ///< Bit 3 mask of an 32 bit integer
+#define BIT4     (0x00000010UL)       ///< Bit 4 mask of an 32 bit integer
+#define BIT5     (0x00000020UL)       ///< Bit 5 mask of an 32 bit integer
+#define BIT6     (0x00000040UL)       ///< Bit 6 mask of an 32 bit integer
+#define BIT7     (0x00000080UL)       ///< Bit 7 mask of an 32 bit integer
+#define BIT8     (0x00000100UL)       ///< Bit 8 mask of an 32 bit integer
+#define BIT9     (0x00000200UL)       ///< Bit 9 mask of an 32 bit integer
+#define BIT10    (0x00000400UL)       ///< Bit 10 mask of an 32 bit integer
+#define BIT11    (0x00000800UL)       ///< Bit 11 mask of an 32 bit integer
+#define BIT12    (0x00001000UL)       ///< Bit 12 mask of an 32 bit integer
+#define BIT13    (0x00002000UL)       ///< Bit 13 mask of an 32 bit integer
+#define BIT14    (0x00004000UL)       ///< Bit 14 mask of an 32 bit integer
+#define BIT15    (0x00008000UL)       ///< Bit 15 mask of an 32 bit integer
+#define BIT16    (0x00010000UL)       ///< Bit 16 mask of an 32 bit integer
+#define BIT17    (0x00020000UL)       ///< Bit 17 mask of an 32 bit integer
+#define BIT18    (0x00040000UL)       ///< Bit 18 mask of an 32 bit integer
+#define BIT19    (0x00080000UL)       ///< Bit 19 mask of an 32 bit integer
+#define BIT20    (0x00100000UL)       ///< Bit 20 mask of an 32 bit integer
+#define BIT21    (0x00200000UL)       ///< Bit 21 mask of an 32 bit integer
+#define BIT22    (0x00400000UL)       ///< Bit 22 mask of an 32 bit integer
+#define BIT23    (0x00800000UL)       ///< Bit 23 mask of an 32 bit integer
+#define BIT24    (0x01000000UL)       ///< Bit 24 mask of an 32 bit integer
+#define BIT25    (0x02000000UL)       ///< Bit 25 mask of an 32 bit integer
+#define BIT26    (0x04000000UL)       ///< Bit 26 mask of an 32 bit integer
+#define BIT27    (0x08000000UL)       ///< Bit 27 mask of an 32 bit integer
+#define BIT28    (0x10000000UL)       ///< Bit 28 mask of an 32 bit integer
+#define BIT29    (0x20000000UL)       ///< Bit 29 mask of an 32 bit integer
+#define BIT30    (0x40000000UL)       ///< Bit 30 mask of an 32 bit integer
+#define BIT31    (0x80000000UL)       ///< Bit 31 mask of an 32 bit integer
+
+/* Byte Mask Definitions */
+#define BYTE0_Msk              (0x000000FFUL)         ///< Mask to get bit0~bit7 from a 32 bit integer
+#define BYTE1_Msk              (0x0000FF00UL)         ///< Mask to get bit8~bit15 from a 32 bit integer
+#define BYTE2_Msk              (0x00FF0000UL)         ///< Mask to get bit16~bit23 from a 32 bit integer
+#define BYTE3_Msk              (0xFF000000UL)         ///< Mask to get bit24~bit31 from a 32 bit integer
+
+#define GET_BYTE0(u32Param)    (((u32Param) & BYTE0_Msk)      )  /*!< Extract Byte 0 (Bit  0~ 7) from parameter u32Param */
+#define GET_BYTE1(u32Param)    (((u32Param) & BYTE1_Msk) >>  8)  /*!< Extract Byte 1 (Bit  8~15) from parameter u32Param */
+#define GET_BYTE2(u32Param)    (((u32Param) & BYTE2_Msk) >> 16)  /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */
+#define GET_BYTE3(u32Param)    (((u32Param) & BYTE3_Msk) >> 24)  /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */
+
+/*@}*/ /* end of group Legacy_Constants */
+
+
+/******************************************************************************/
+/*                         Peripheral header files                            */
+/******************************************************************************/
+/*
+#include "sys.h"
+#include "clk.h"
+
+#include "acmp.h"
+#include "dac.h"
+#include "emac.h"
+#include "uart.h"
+#include "usci_spi.h"
+#include "gpio.h"
+#include "ccap.h"
+#include "ecap.h"
+#include "qei.h"
+#include "timer.h"
+#include "timer_pwm.h"
+#include "pdma.h"
+#include "crypto.h"
+#include "trng.h"
+#include "fmc.h"
+#include "spim.h"
+#include "i2c.h"
+#include "i2s.h"
+#include "epwm.h"
+#include "eadc.h"
+#include "bpwm.h"
+#include "wdt.h"
+#include "wwdt.h"
+#include "opa.h"
+#include "crc.h"
+#include "ebi.h"
+#include "usci_i2c.h"
+#include "scuart.h"
+#include "sc.h"
+#include "spi.h"
+#include "qspi.h"
+#include "can.h"
+#include "rtc.h"
+#include "usci_uart.h"
+#include "sdh.h"
+#include "usbd.h"
+#include "hsusbd.h"
+#include "otg.h"
+#include "hsotg.h"
+*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __M480_H__ */
+

dap_link/lib/free-dap/platform/m484/include/NuMicro.h

@@ -0,0 +1,16 @@
+/**************************************************************************//**
+ * @file     NuMicro.h
+ * @version  V1.00
+ * @brief    NuMicro peripheral access layer header file.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NUMICRO_H__
+#define __NUMICRO_H__
+
+#include "M480.h"
+
+#endif  /* __NUMICRO_H__ */
+
+

dap_link/lib/free-dap/platform/m484/include/acmp_reg.h

@@ -0,0 +1,240 @@
+/**************************************************************************//**
+ * @file     acmp_reg.h
+ * @version  V1.00
+ * @brief    ACMP register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __ACMP_REG_H__
+#define __ACMP_REG_H__
+
+#if defined ( __CC_ARM   )
+#pragma anon_unions
+#endif
+
+/**
+   @addtogroup REGISTER Control Register
+   @{
+*/
+
+/**
+    @addtogroup ACMP Analog Comparator Controller(ACMP)
+    Memory Mapped Structure for ACMP Controller
+@{ */
+
+typedef struct
+{
+
+
+    /**
+     * @var ACMP_T::CTL
+     * Offset: 0x00~0x04  Analog Comparator 0/1 Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ACMPEN    |Comparator Enable Bit
+     * |        |          |0 = Comparator x Disabled.
+     * |        |          |1 = Comparator x Enabled.
+     * |[1]     |ACMPIE    |Comparator Interrupt Enable Bit
+     * |        |          |0 = Comparator x interrupt Disabled.
+     * |        |          |1 = Comparator x interrupt Enabled
+     * |        |          |If WKEN (ACMP_CTL0[16]) is set to 1, the wake-up interrupt function will be enabled as well.
+     * |[3]     |ACMPOINV  |Comparator Output Inverse
+     * |        |          |0 = Comparator x output inverse Disabled.
+     * |        |          |1 = Comparator x output inverse Enabled.
+     * |[5:4]   |NEGSEL    |Comparator Negative Input Selection
+     * |        |          |00 = ACMPx_N pin.
+     * |        |          |01 = Internal comparator reference voltage (CRV).
+     * |        |          |10 = Band-gap voltage.
+     * |        |          |11 = DAC output.
+     * |[7:6]   |POSSEL    |Comparator Positive Input Selection
+     * |        |          |00 = Input from ACMPx_P0.
+     * |        |          |01 = Input from ACMPx_P1.
+     * |        |          |10 = Input from ACMPx_P2.
+     * |        |          |11 = Input from ACMPx_P3.
+     * |[9:8]   |INTPOL    |Interrupt Condition Polarity Selection
+     * |        |          |ACMPIFx will be set to 1 when comparator output edge condition is detected.
+     * |        |          |00 = Rising edge or falling edge.
+     * |        |          |01 = Rising edge.
+     * |        |          |10 = Falling edge.
+     * |        |          |11 = Reserved.
+     * |[12]    |OUTSEL    |Comparator Output Select
+     * |        |          |0 = Comparator x output to ACMPx_O pin is unfiltered comparator output.
+     * |        |          |1 = Comparator x output to ACMPx_O pin is from filter output.
+     * |[15:13] |FILTSEL   |Comparator Output Filter Count Selection
+     * |        |          |000 = Filter function is Disabled.
+     * |        |          |001 = ACMPx output is sampled 1 consecutive PCLK.
+     * |        |          |010 = ACMPx output is sampled 2 consecutive PCLKs.
+     * |        |          |011 = ACMPx output is sampled 4 consecutive PCLKs.
+     * |        |          |100 = ACMPx output is sampled 8 consecutive PCLKs.
+     * |        |          |101 = ACMPx output is sampled 16 consecutive PCLKs.
+     * |        |          |110 = ACMPx output is sampled 32 consecutive PCLKs.
+     * |        |          |111 = ACMPx output is sampled 64 consecutive PCLKs.
+     * |[16]    |WKEN      |Power-down Wake-up Enable Bit
+     * |        |          |0 = Wake-up function Disabled.
+     * |        |          |1 = Wake-up function Enabled.
+     * |[17]    |WLATEN    |Window Latch Mode Enable Bit
+     * |        |          |0 = Window Latch Mode Disabled.
+     * |        |          |1 = Window Latch Mode Enabled.
+     * |[18]    |WCMPSEL   |Window Compare Mode Selection
+     * |        |          |0 = Window Compare Mode Disabled.
+     * |        |          |1 = Window Compare Mode is Selected.
+     * |[25:24] |HYSSEL    |Hysteresis Mode Selection
+     * |        |          |00 = Hysteresis is 0mV.
+     * |        |          |01 = Hysteresis is 10mV.
+     * |        |          |10 = Hysteresis is 20mV.
+     * |        |          |11 = Hysteresis is 30mV.
+     * |[29:28] |MODESEL   |Propagation Delay Mode Selection
+     * |        |          |00 = Max propagation delay is 4.5uS, operation current is 1.2uA.
+     * |        |          |01 = Max propagation delay is 2uS, operation current is 3uA.
+     * |        |          |10 = Max propagation delay is 600nS, operation current is 10uA.
+     * |        |          |11 = Max propagation delay is 200nS, operation current is 75uA.
+     * @var ACMP_T::STATUS
+     * Offset: 0x08  Analog Comparator Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ACMPIF0   |Comparator 0 Interrupt Flag
+     * |        |          |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8])
+     * |        |          |is detected on comparator 0 output.
+     * |        |          |This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[1]     |ACMPIF1   |Comparator 1 Interrupt Flag
+     * |        |          |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8])
+     * |        |          |is detected on comparator 1 output.
+     * |        |          |This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[4]     |ACMPO0    |Comparator 0 Output
+     * |        |          |Synchronized to the PCLK to allow reading by software
+     * |        |          |Cleared when the comparator 0 is disabled, i.e.
+     * |        |          |ACMPEN (ACMP_CTL0[0]) is cleared to 0.
+     * |[5]     |ACMPO1    |Comparator 1 Output
+     * |        |          |Synchronized to the PCLK to allow reading by software.
+     * |        |          |Cleared when the comparator 1 is disabled, i.e.
+     * |        |          |ACMPEN (ACMP_CTL1[0]) is cleared to 0.
+     * |[8]     |WKIF0     |Comparator 0 Power-down Wake-up Interrupt Flag
+     * |        |          |This bit will be set to 1 when ACMP0 wake-up interrupt event occurs.
+     * |        |          |0 = No power-down wake-up occurred.
+     * |        |          |1 = Power-down wake-up occurred.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[9]     |WKIF1     |Comparator 1 Power-down Wake-up Interrupt Flag
+     * |        |          |This bit will be set to 1 when ACMP1 wake-up interrupt event occurs.
+     * |        |          |0 = No power-down wake-up occurred.
+     * |        |          |1 = Power-down wake-up occurred.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[12]    |ACMPS0    |Comparator 0 Status
+     * |        |          |Synchronized to the PCLK to allow reading by software
+     * |        |          |Cleared when the comparator 0 is disabled, i.e.
+     * |        |          |ACMPEN (ACMP_CTL0[0]) is cleared to 0.
+     * |[13]    |ACMPS1    |Comparator 1 Status
+     * |        |          |Synchronized to the PCLK to allow reading by software
+     * |        |          |Cleared when the comparator 1 is disabled, i.e.
+     * |        |          |ACMPEN (ACMP_CTL1[0]) is cleared to 0.
+     * |[16]    |ACMPWO    |Comparator Window Output
+     * |        |          |This bit shows the output status of window compare mode
+     * |        |          |0 = The positive input voltage is outside the window.
+     * |        |          |1 = The positive input voltage is in the window.
+     * @var ACMP_T::VREF
+     * Offset: 0x0C  Analog Comparator Reference Voltage Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |CRVCTL    |Comparator Reference Voltage Setting
+     * |        |          |CRV = CRV source voltage * (1/6+CRVCTL/24).
+     * |[6]     |CRVSSEL   |CRV Source Voltage Selection
+     * |        |          |0 = VDDA is selected as CRV source voltage.
+     * |        |          |1 = The reference voltage defined by SYS_VREFCTL register is selected as CRV source voltage.
+     */
+    __IO uint32_t CTL[2];                /*!< [0x0000~0x0004] Analog Comparator 0/1 Control Register                    */
+    __IO uint32_t STATUS;                /*!< [0x0008] Analog Comparator Status Register                                */
+    __IO uint32_t VREF;                  /*!< [0x000c] Analog Comparator Reference Voltage Control Register             */
+
+} ACMP_T;
+
+/**
+    @addtogroup ACMP_CONST ACMP Bit Field Definition
+    Constant Definitions for ACMP Controller
+@{ */
+
+#define ACMP_CTL_ACMPEN_Pos              (0)                                               /*!< ACMP_T::CTL: ACMPEN Position           */
+#define ACMP_CTL_ACMPEN_Msk              (0x1ul << ACMP_CTL_ACMPEN_Pos)                    /*!< ACMP_T::CTL: ACMPEN Mask               */
+
+#define ACMP_CTL_ACMPIE_Pos              (1)                                               /*!< ACMP_T::CTL: ACMPIE Position           */
+#define ACMP_CTL_ACMPIE_Msk              (0x1ul << ACMP_CTL_ACMPIE_Pos)                    /*!< ACMP_T::CTL: ACMPIE Mask               */
+
+#define ACMP_CTL_ACMPOINV_Pos            (3)                                               /*!< ACMP_T::CTL: ACMPOINV Position         */
+#define ACMP_CTL_ACMPOINV_Msk            (0x1ul << ACMP_CTL_ACMPOINV_Pos)                  /*!< ACMP_T::CTL: ACMPOINV Mask             */
+
+#define ACMP_CTL_NEGSEL_Pos              (4)                                               /*!< ACMP_T::CTL: NEGSEL Position           */
+#define ACMP_CTL_NEGSEL_Msk              (0x3ul << ACMP_CTL_NEGSEL_Pos)                    /*!< ACMP_T::CTL: NEGSEL Mask               */
+
+#define ACMP_CTL_POSSEL_Pos              (6)                                               /*!< ACMP_T::CTL: POSSEL Position           */
+#define ACMP_CTL_POSSEL_Msk              (0x3ul << ACMP_CTL_POSSEL_Pos)                    /*!< ACMP_T::CTL: POSSEL Mask               */
+
+#define ACMP_CTL_INTPOL_Pos              (8)                                               /*!< ACMP_T::CTL: INTPOL Position           */
+#define ACMP_CTL_INTPOL_Msk              (0x3ul << ACMP_CTL_INTPOL_Pos)                    /*!< ACMP_T::CTL: INTPOL Mask               */
+
+#define ACMP_CTL_OUTSEL_Pos              (12)                                              /*!< ACMP_T::CTL: OUTSEL Position           */
+#define ACMP_CTL_OUTSEL_Msk              (0x1ul << ACMP_CTL_OUTSEL_Pos)                    /*!< ACMP_T::CTL: OUTSEL Mask               */
+
+#define ACMP_CTL_FILTSEL_Pos             (13)                                              /*!< ACMP_T::CTL: FILTSEL Position          */
+#define ACMP_CTL_FILTSEL_Msk             (0x7ul << ACMP_CTL_FILTSEL_Pos)                   /*!< ACMP_T::CTL: FILTSEL Mask              */
+
+#define ACMP_CTL_WKEN_Pos                (16)                                              /*!< ACMP_T::CTL: WKEN Position             */
+#define ACMP_CTL_WKEN_Msk                (0x1ul << ACMP_CTL_WKEN_Pos)                      /*!< ACMP_T::CTL: WKEN Mask                 */
+
+#define ACMP_CTL_WLATEN_Pos              (17)                                              /*!< ACMP_T::CTL: WLATEN Position           */
+#define ACMP_CTL_WLATEN_Msk              (0x1ul << ACMP_CTL_WLATEN_Pos)                    /*!< ACMP_T::CTL: WLATEN Mask               */
+
+#define ACMP_CTL_WCMPSEL_Pos             (18)                                              /*!< ACMP_T::CTL: WCMPSEL Position          */
+#define ACMP_CTL_WCMPSEL_Msk             (0x1ul << ACMP_CTL_WCMPSEL_Pos)                   /*!< ACMP_T::CTL: WCMPSEL Mask              */
+
+#define ACMP_CTL_HYSSEL_Pos              (24)                                              /*!< ACMP_T::CTL: HYSSEL Position           */
+#define ACMP_CTL_HYSSEL_Msk              (0x3ul << ACMP_CTL_HYSSEL_Pos)                    /*!< ACMP_T::CTL: HYSSEL Mask               */
+
+#define ACMP_CTL_MODESEL_Pos             (28)                                              /*!< ACMP_T::CTL: MODESEL Position          */
+#define ACMP_CTL_MODESEL_Msk             (0x3ul << ACMP_CTL_MODESEL_Pos)                   /*!< ACMP_T::CTL: MODESEL Mask              */
+
+#define ACMP_STATUS_ACMPIF0_Pos          (0)                                               /*!< ACMP_T::STATUS: ACMPIF0 Position       */
+#define ACMP_STATUS_ACMPIF0_Msk          (0x1ul << ACMP_STATUS_ACMPIF0_Pos)                /*!< ACMP_T::STATUS: ACMPIF0 Mask           */
+
+#define ACMP_STATUS_ACMPIF1_Pos          (1)                                               /*!< ACMP_T::STATUS: ACMPIF1 Position       */
+#define ACMP_STATUS_ACMPIF1_Msk          (0x1ul << ACMP_STATUS_ACMPIF1_Pos)                /*!< ACMP_T::STATUS: ACMPIF1 Mask           */
+
+#define ACMP_STATUS_ACMPO0_Pos           (4)                                               /*!< ACMP_T::STATUS: ACMPO0 Position        */
+#define ACMP_STATUS_ACMPO0_Msk           (0x1ul << ACMP_STATUS_ACMPO0_Pos)                 /*!< ACMP_T::STATUS: ACMPO0 Mask            */
+
+#define ACMP_STATUS_ACMPO1_Pos           (5)                                               /*!< ACMP_T::STATUS: ACMPO1 Position        */
+#define ACMP_STATUS_ACMPO1_Msk           (0x1ul << ACMP_STATUS_ACMPO1_Pos)                 /*!< ACMP_T::STATUS: ACMPO1 Mask            */
+
+#define ACMP_STATUS_WKIF0_Pos            (8)                                               /*!< ACMP_T::STATUS: WKIF0 Position         */
+#define ACMP_STATUS_WKIF0_Msk            (0x1ul << ACMP_STATUS_WKIF0_Pos)                  /*!< ACMP_T::STATUS: WKIF0 Mask             */
+
+#define ACMP_STATUS_WKIF1_Pos            (9)                                               /*!< ACMP_T::STATUS: WKIF1 Position         */
+#define ACMP_STATUS_WKIF1_Msk            (0x1ul << ACMP_STATUS_WKIF1_Pos)                  /*!< ACMP_T::STATUS: WKIF1 Mask             */
+
+#define ACMP_STATUS_ACMPS0_Pos           (12)                                              /*!< ACMP_T::STATUS: ACMPS0 Position        */
+#define ACMP_STATUS_ACMPS0_Msk           (0x1ul << ACMP_STATUS_ACMPS0_Pos)                 /*!< ACMP_T::STATUS: ACMPS0 Mask            */
+
+#define ACMP_STATUS_ACMPS1_Pos           (13)                                              /*!< ACMP_T::STATUS: ACMPS1 Position        */
+#define ACMP_STATUS_ACMPS1_Msk           (0x1ul << ACMP_STATUS_ACMPS1_Pos)                 /*!< ACMP_T::STATUS: ACMPS1 Mask            */
+
+#define ACMP_STATUS_ACMPWO_Pos           (16)                                              /*!< ACMP_T::STATUS: ACMPWO Position        */
+#define ACMP_STATUS_ACMPWO_Msk           (0x1ul << ACMP_STATUS_ACMPWO_Pos)                 /*!< ACMP_T::STATUS: ACMPWO Mask            */
+
+#define ACMP_VREF_CRVCTL_Pos             (0)                                               /*!< ACMP_T::VREF: CRVCTL Position          */
+#define ACMP_VREF_CRVCTL_Msk             (0xful << ACMP_VREF_CRVCTL_Pos)                   /*!< ACMP_T::VREF: CRVCTL Mask              */
+
+#define ACMP_VREF_CRVSSEL_Pos            (6)                                               /*!< ACMP_T::VREF: CRVSSEL Position         */
+#define ACMP_VREF_CRVSSEL_Msk            (0x1ul << ACMP_VREF_CRVSSEL_Pos)                  /*!< ACMP_T::VREF: CRVSSEL Mask             */
+
+/**@}*/ /* ACMP_CONST */
+/**@}*/ /* end of ACMP register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM   )
+#pragma no_anon_unions
+#endif
+
+#endif /* __ACMP_REG_H__ */

dap_link/lib/free-dap/platform/m484/include/bpwm_reg.h

@@ -0,0 +1,1835 @@
+/**************************************************************************//**
+ * @file     bpwm_reg.h
+ * @version  V1.00
+ * @brief    BPWM register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __BPWM_REG_H__
+#define __BPWM_REG_H__
+
+#if defined ( __CC_ARM   )
+#pragma anon_unions
+#endif
+
+/**
+   @addtogroup REGISTER Control Register
+   @{
+*/
+
+/**
+    @addtogroup BPWM Basic Pulse Width Modulation Controller(BPWM)
+    Memory Mapped Structure for BPWM Controller
+@{ */
+
+typedef struct
+{
+    /**
+     * @var BCAPDAT_T::RCAPDAT
+     * Offset: 0x20C  BPWM Rising Capture Data Register 0~5
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |RCAPDAT   |BPWM Rising Capture Data (Read Only)
+     * |        |          |When rising capture condition happened, the BPWM counter value will be saved in this register.
+     * @var BCAPDAT_T::FCAPDAT
+     * Offset: 0x210  BPWM Falling Capture Data Register 0~5
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |FCAPDAT   |BPWM Falling Capture Data (Read Only)
+     * |        |          |When falling capture condition happened, the BPWM counter value will be saved in this register.
+     */
+    __IO uint32_t RCAPDAT; /*!< [0x20C/0x214/0x21C/0x224/0x22C/0x234] BPWM Rising Capture Data Register 0~5 */
+    __IO uint32_t FCAPDAT; /*!< [0x210/0x218/0x220/0x228/0x230/0x238] BPWM Falling Capture Data Register 0~5 */
+} BCAPDAT_T;
+
+typedef struct
+{
+
+
+    /**
+     * @var BPWM_T::CTL0
+     * Offset: 0x00  BPWM Control Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CTRLD0    |Center Re-load
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |In up-down counter type, PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the center point of a period
+     * |[1]     |CTRLD1    |Center Re-load
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |In up-down counter type, PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the center point of a period
+     * |[2]     |CTRLD2    |Center Re-load
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |In up-down counter type, PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the center point of a period
+     * |[3]     |CTRLD3    |Center Re-load
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |In up-down counter type, PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the center point of a period
+     * |[4]     |CTRLD4    |Center Re-load
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |In up-down counter type, PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the center point of a period
+     * |[5]     |CTRLD5    |Center Re-load
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |In up-down counter type, PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the center point of a period
+     * |[16]    |IMMLDEN0  |Immediately Load Enable Bit(S)
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+     * |        |          |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
+     * |        |          |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
+     * |[17]    |IMMLDEN1  |Immediately Load Enable Bit(S)
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+     * |        |          |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
+     * |        |          |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
+     * |[18]    |IMMLDEN2  |Immediately Load Enable Bit(S)
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+     * |        |          |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
+     * |        |          |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
+     * |[19]    |IMMLDEN3  |Immediately Load Enable Bit(S)
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+     * |        |          |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
+     * |        |          |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
+     * |[20]    |IMMLDEN4  |Immediately Load Enable Bit(S)
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+     * |        |          |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
+     * |        |          |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
+     * |[21]    |IMMLDEN5  |Immediately Load Enable Bit(S)
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+     * |        |          |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
+     * |        |          |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
+     * |[30]    |DBGHALT   |ICE Debug Mode Counter Halt (Write Protect)
+     * |        |          |If counter halt is enabled, BPWM all counters will keep current value until exit ICE debug mode.
+     * |        |          |0 = ICE debug mode counter halt Disabled.
+     * |        |          |1 = ICE debug mode counter halt Enabled.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[31]    |DBGTRIOFF |ICE Debug Mode Acknowledge Disable (Write Protect)
+     * |        |          |0 = ICE debug mode acknowledgement effects BPWM output.
+     * |        |          |BPWM pin will be forced as tri-state while ICE debug mode acknowledged.
+     * |        |          |1 = ICE debug mode acknowledgement Disabled.
+     * |        |          |BPWM pin will keep output no matter ICE debug mode acknowledged or not.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * @var BPWM_T::CTL1
+     * Offset: 0x04  BPWM Control Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |CNTTYPE0  |BPWM Counter Behavior Type 0
+     * |        |          |Each bit n controls corresponding BPWM channel n.
+     * |        |          |00 = Up counter type (supports in capture mode).
+     * |        |          |01 = Down count type (supports in capture mode).
+     * |        |          |10 = Up-down counter type.
+     * |        |          |11 = Reserved.
+     * @var BPWM_T::CLKSRC
+     * Offset: 0x10  BPWM Clock Source Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |ECLKSRC0  |BPWM_CH01 External Clock Source Select
+     * |        |          |000 = BPWMx_CLK, x denotes 0 or 1.
+     * |        |          |001 = TIMER0 overflow.
+     * |        |          |010 = TIMER1 overflow.
+     * |        |          |011 = TIMER2 overflow.
+     * |        |          |100 = TIMER3 overflow.
+     * |        |          |Others = Reserved.
+     * @var BPWM_T::CLKPSC
+     * Offset: 0x14  BPWM Clock Prescale Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[11:0]  |CLKPSC    |BPWM Counter Clock Prescale
+     * |        |          |The clock of BPWM counter is decided by clock prescaler
+     * |        |          |Each BPWM pair share one BPWM counter clock prescaler
+     * |        |          |The clock of BPWM counter is divided by (CLKPSC+ 1)
+     * @var BPWM_T::CNTEN
+     * Offset: 0x20  BPWM Counter Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CNTEN0    |BPWM Counter 0 Enable Bit
+     * |        |          |0 = BPWM Counter and clock prescaler stop running.
+     * |        |          |1 = BPWM Counter and clock prescaler start running.
+     * @var BPWM_T::CNTCLR
+     * Offset: 0x24  BPWM Clear Counter Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CNTCLR0   |Clear BPWM Counter Control Bit 0
+     * |        |          |It is automatically cleared by hardware.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear 16-bit BPWM counter to 0000H.
+     * @var BPWM_T::PERIOD
+     * Offset: 0x30  BPWM Period Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |PERIOD    |BPWM Period Register
+     * |        |          |Up-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, and restarts from 0.
+     * |        |          |Down-Count mode: In this mode, BPWM counter counts from PERIOD to 0, and restarts from PERIOD.
+     * |        |          |BPWM period time = (PERIOD+1) * BPWM_CLK period.
+     * |        |          |Up-Down-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again.
+     * |        |          |BPWM period time = 2 * PERIOD * BPWM_CLK period.
+     * @var BPWM_T::CMPDAT[6]
+     * Offset: 0x50  BPWM Comparator Register 0~5
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |CMPDAT    |BPWM Comparator Register
+     * |        |          |CMPDAT use to compare with CNTR to generate BPWM waveform, interrupt and trigger EADC.
+     * |        |          |In independent mode, CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point.
+     * @var BPWM_T::CNT
+     * Offset: 0x90  BPWM Counter Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |CNT       |BPWM Data Register (Read Only)
+     * |        |          |User can monitor CNTR to know the current value in 16-bit period counter.
+     * |[16]    |DIRF      |BPWM Direction Indicator Flag (Read Only)
+     * |        |          |0 = Counter is Down count.
+     * |        |          |1 = Counter is UP count.
+     * @var BPWM_T::WGCTL0
+     * Offset: 0xB0  BPWM Generation Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |ZPCTL0    |BPWM Zero Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM zero point output Low.
+     * |        |          |10 = BPWM zero point output High.
+     * |        |          |11 = BPWM zero point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter count to zero.
+     * |[3:2]   |ZPCTL1    |BPWM Zero Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM zero point output Low.
+     * |        |          |10 = BPWM zero point output High.
+     * |        |          |11 = BPWM zero point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter count to zero.
+     * |[5:4]   |ZPCTL2    |BPWM Zero Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM zero point output Low.
+     * |        |          |10 = BPWM zero point output High.
+     * |        |          |11 = BPWM zero point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter count to zero.
+     * |[7:6]   |ZPCTL3    |BPWM Zero Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM zero point output Low.
+     * |        |          |10 = BPWM zero point output High.
+     * |        |          |11 = BPWM zero point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter count to zero.
+     * |[9:8]   |ZPCTL4    |BPWM Zero Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM zero point output Low.
+     * |        |          |10 = BPWM zero point output High.
+     * |        |          |11 = BPWM zero point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter count to zero.
+     * |[11:10] |ZPCTL5    |BPWM Zero Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM zero point output Low.
+     * |        |          |10 = BPWM zero point output High.
+     * |        |          |11 = BPWM zero point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter count to zero.
+     * |[17:16] |PRDPCTL0  |BPWM Period (Center) Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM period (center) point output Low.
+     * |        |          |10 = BPWM period (center) point output High.
+     * |        |          |11 = BPWM period (center) point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter count to (PERIOD+1).
+     * |        |          |Note: This bit is center point control when BPWM counter operating in up-down counter type.
+     * |[19:18] |PRDPCTL1  |BPWM Period (Center) Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM period (center) point output Low.
+     * |        |          |10 = BPWM period (center) point output High.
+     * |        |          |11 = BPWM period (center) point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter count to (PERIOD+1).
+     * |        |          |Note: This bit is center point control when BPWM counter operating in up-down counter type.
+     * |[21:20] |PRDPCTL2  |BPWM Period (Center) Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM period (center) point output Low.
+     * |        |          |10 = BPWM period (center) point output High.
+     * |        |          |11 = BPWM period (center) point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter count to (PERIOD+1).
+     * |        |          |Note: This bit is center point control when BPWM counter operating in up-down counter type.
+     * |[23:22] |PRDPCTL3  |BPWM Period (Center) Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM period (center) point output Low.
+     * |        |          |10 = BPWM period (center) point output High.
+     * |        |          |11 = BPWM period (center) point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter count to (PERIOD+1).
+     * |        |          |Note: This bit is center point control when BPWM counter operating in up-down counter type.
+     * |[25:24] |PRDPCTL4  |BPWM Period (Center) Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM period (center) point output Low.
+     * |        |          |10 = BPWM period (center) point output High.
+     * |        |          |11 = BPWM period (center) point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter count to (PERIOD+1).
+     * |        |          |Note: This bit is center point control when BPWM counter operating in up-down counter type.
+     * |[27:26] |PRDPCTL5  |BPWM Period (Center) Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM period (center) point output Low.
+     * |        |          |10 = BPWM period (center) point output High.
+     * |        |          |11 = BPWM period (center) point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter count to (PERIOD+1).
+     * |        |          |Note: This bit is center point control when BPWM counter operating in up-down counter type.
+     * @var BPWM_T::WGCTL1
+     * Offset: 0xB4  BPWM Generation Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |CMPUCTL0  |BPWM Compare Up Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM compare up point output Low.
+     * |        |          |10 = BPWM compare up point output High.
+     * |        |          |11 = BPWM compare up point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter up count to CMPDAT.
+     * |[3:2]   |CMPUCTL1  |BPWM Compare Up Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM compare up point output Low.
+     * |        |          |10 = BPWM compare up point output High.
+     * |        |          |11 = BPWM compare up point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter up count to CMPDAT.
+     * |[5:4]   |CMPUCTL2  |BPWM Compare Up Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM compare up point output Low.
+     * |        |          |10 = BPWM compare up point output High.
+     * |        |          |11 = BPWM compare up point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter up count to CMPDAT.
+     * |[7:6]   |CMPUCTL3  |BPWM Compare Up Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM compare up point output Low.
+     * |        |          |10 = BPWM compare up point output High.
+     * |        |          |11 = BPWM compare up point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter up count to CMPDAT.
+     * |[9:8]   |CMPUCTL4  |BPWM Compare Up Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM compare up point output Low.
+     * |        |          |10 = BPWM compare up point output High.
+     * |        |          |11 = BPWM compare up point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter up count to CMPDAT.
+     * |[11:10] |CMPUCTL5  |BPWM Compare Up Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM compare up point output Low.
+     * |        |          |10 = BPWM compare up point output High.
+     * |        |          |11 = BPWM compare up point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter up count to CMPDAT.
+     * |[17:16] |CMPDCTL0  |BPWM Compare Down Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM compare down point output Low.
+     * |        |          |10 = BPWM compare down point output High.
+     * |        |          |11 = BPWM compare down point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter down count to CMPDAT.
+     * |[19:18] |CMPDCTL1  |BPWM Compare Down Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM compare down point output Low.
+     * |        |          |10 = BPWM compare down point output High.
+     * |        |          |11 = BPWM compare down point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter down count to CMPDAT.
+     * |[21:20] |CMPDCTL2  |BPWM Compare Down Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM compare down point output Low.
+     * |        |          |10 = BPWM compare down point output High.
+     * |        |          |11 = BPWM compare down point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter down count to CMPDAT.
+     * |[23:22] |CMPDCTL3  |BPWM Compare Down Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM compare down point output Low.
+     * |        |          |10 = BPWM compare down point output High.
+     * |        |          |11 = BPWM compare down point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter down count to CMPDAT.
+     * |[25:24] |CMPDCTL4  |BPWM Compare Down Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM compare down point output Low.
+     * |        |          |10 = BPWM compare down point output High.
+     * |        |          |11 = BPWM compare down point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter down count to CMPDAT.
+     * |[27:26] |CMPDCTL5  |BPWM Compare Down Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM compare down point output Low.
+     * |        |          |10 = BPWM compare down point output High.
+     * |        |          |11 = BPWM compare down point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter down count to CMPDAT.
+     * @var BPWM_T::MSKEN
+     * Offset: 0xB8  BPWM Mask Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |MSKEN0    |BPWM Mask Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |The BPWM output signal will be masked when this bit is enabled
+     * |        |          |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
+     * |        |          |0 = BPWM output signal is non-masked.
+     * |        |          |1 = BPWM output signal is masked and output MSKDATn data.
+     * |[1]     |MSKEN1    |BPWM Mask Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |The BPWM output signal will be masked when this bit is enabled
+     * |        |          |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
+     * |        |          |0 = BPWM output signal is non-masked.
+     * |        |          |1 = BPWM output signal is masked and output MSKDATn data.
+     * |[2]     |MSKEN2    |BPWM Mask Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |The BPWM output signal will be masked when this bit is enabled
+     * |        |          |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
+     * |        |          |0 = BPWM output signal is non-masked.
+     * |        |          |1 = BPWM output signal is masked and output MSKDATn data.
+     * |[3]     |MSKEN3    |BPWM Mask Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |The BPWM output signal will be masked when this bit is enabled
+     * |        |          |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
+     * |        |          |0 = BPWM output signal is non-masked.
+     * |        |          |1 = BPWM output signal is masked and output MSKDATn data.
+     * |[4]     |MSKEN4    |BPWM Mask Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |The BPWM output signal will be masked when this bit is enabled
+     * |        |          |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
+     * |        |          |0 = BPWM output signal is non-masked.
+     * |        |          |1 = BPWM output signal is masked and output MSKDATn data.
+     * |[5]     |MSKEN5    |BPWM Mask Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |The BPWM output signal will be masked when this bit is enabled
+     * |        |          |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
+     * |        |          |0 = BPWM output signal is non-masked.
+     * |        |          |1 = BPWM output signal is masked and output MSKDATn data.
+     * @var BPWM_T::MSK
+     * Offset: 0xBC  BPWM Mask Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |MSKDAT0   |BPWM Mask Data Bit
+     * |        |          |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Output logic low to BPWMn.
+     * |        |          |1 = Output logic high to BPWMn.
+     * |[1]     |MSKDAT1   |BPWM Mask Data Bit
+     * |        |          |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Output logic low to BPWMn.
+     * |        |          |1 = Output logic high to BPWMn.
+     * |[2]     |MSKDAT2   |BPWM Mask Data Bit
+     * |        |          |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Output logic low to BPWMn.
+     * |        |          |1 = Output logic high to BPWMn.
+     * |[3]     |MSKDAT3   |BPWM Mask Data Bit
+     * |        |          |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Output logic low to BPWMn.
+     * |        |          |1 = Output logic high to BPWMn.
+     * |[4]     |MSKDAT4   |BPWM Mask Data Bit
+     * |        |          |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Output logic low to BPWMn.
+     * |        |          |1 = Output logic high to BPWMn.
+     * |[5]     |MSKDAT5   |BPWM Mask Data Bit
+     * |        |          |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Output logic low to BPWMn.
+     * |        |          |1 = Output logic high to BPWMn.
+     * @var BPWM_T::POLCTL
+     * Offset: 0xD4  BPWM Pin Polar Inverse Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |PINV0     |BPWM PIN Polar Inverse Control
+     * |        |          |The register controls polarity state of BPWM output
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM output polar inverse Disabled.
+     * |        |          |1 = BPWM output polar inverse Enabled.
+     * |[1]     |PINV1     |BPWM PIN Polar Inverse Control
+     * |        |          |The register controls polarity state of BPWM output
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM output polar inverse Disabled.
+     * |        |          |1 = BPWM output polar inverse Enabled.
+     * |[2]     |PINV2     |BPWM PIN Polar Inverse Control
+     * |        |          |The register controls polarity state of BPWM output
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM output polar inverse Disabled.
+     * |        |          |1 = BPWM output polar inverse Enabled.
+     * |[3]     |PINV3     |BPWM PIN Polar Inverse Control
+     * |        |          |The register controls polarity state of BPWM output
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM output polar inverse Disabled.
+     * |        |          |1 = BPWM output polar inverse Enabled.
+     * |[4]     |PINV4     |BPWM PIN Polar Inverse Control
+     * |        |          |The register controls polarity state of BPWM output
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM output polar inverse Disabled.
+     * |        |          |1 = BPWM output polar inverse Enabled.
+     * |[5]     |PINV5     |BPWM PIN Polar Inverse Control
+     * |        |          |The register controls polarity state of BPWM output
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM output polar inverse Disabled.
+     * |        |          |1 = BPWM output polar inverse Enabled.
+     * @var BPWM_T::POEN
+     * Offset: 0xD8  BPWM Output Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |POEN0     |BPWM Pin Output Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM pin at tri-state.
+     * |        |          |1 = BPWM pin in output mode.
+     * |[1]     |POEN1     |BPWM Pin Output Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM pin at tri-state.
+     * |        |          |1 = BPWM pin in output mode.
+     * |[2]     |POEN2     |BPWM Pin Output Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM pin at tri-state.
+     * |        |          |1 = BPWM pin in output mode.
+     * |[3]     |POEN3     |BPWM Pin Output Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM pin at tri-state.
+     * |        |          |1 = BPWM pin in output mode.
+     * |[4]     |POEN4     |BPWM Pin Output Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM pin at tri-state.
+     * |        |          |1 = BPWM pin in output mode.
+     * |[5]     |POEN5     |BPWM Pin Output Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM pin at tri-state.
+     * |        |          |1 = BPWM pin in output mode.
+     * @var BPWM_T::INTEN
+     * Offset: 0xE0  BPWM Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ZIEN0     |BPWM Zero Point Interrupt 0 Enable Bit
+     * |        |          |0 = Zero point interrupt Disabled.
+     * |        |          |1 = Zero point interrupt Enabled.
+     * |[8]     |PIEN0     |BPWM Period Point Interrupt 0 Enable Bit
+     * |        |          |0 = Period point interrupt Disabled.
+     * |        |          |1 = Period point interrupt Enabled.
+     * |        |          |Note: When up-down counter type period point means center point.
+     * |[16]    |CMPUIEN0  |BPWM Compare Up Count Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Compare up count interrupt Disabled.
+     * |        |          |1 = Compare up count interrupt Enabled.
+     * |[17]    |CMPUIEN1  |BPWM Compare Up Count Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Compare up count interrupt Disabled.
+     * |        |          |1 = Compare up count interrupt Enabled.
+     * |[18]    |CMPUIEN2  |BPWM Compare Up Count Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Compare up count interrupt Disabled.
+     * |        |          |1 = Compare up count interrupt Enabled.
+     * |[19]    |CMPUIEN3  |BPWM Compare Up Count Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Compare up count interrupt Disabled.
+     * |        |          |1 = Compare up count interrupt Enabled.
+     * |[20]    |CMPUIEN4  |BPWM Compare Up Count Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Compare up count interrupt Disabled.
+     * |        |          |1 = Compare up count interrupt Enabled.
+     * |[21]    |CMPUIEN5  |BPWM Compare Up Count Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Compare up count interrupt Disabled.
+     * |        |          |1 = Compare up count interrupt Enabled.
+     * |[24]    |CMPDIEN0  |BPWM Compare Down Count Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Compare down count interrupt Disabled.
+     * |        |          |1 = Compare down count interrupt Enabled.
+     * |[25]    |CMPDIEN1  |BPWM Compare Down Count Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Compare down count interrupt Disabled.
+     * |        |          |1 = Compare down count interrupt Enabled.
+     * |[26]    |CMPDIEN2  |BPWM Compare Down Count Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Compare down count interrupt Disabled.
+     * |        |          |1 = Compare down count interrupt Enabled.
+     * |[27]    |CMPDIEN3  |BPWM Compare Down Count Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Compare down count interrupt Disabled.
+     * |        |          |1 = Compare down count interrupt Enabled.
+     * |[28]    |CMPDIEN4  |BPWM Compare Down Count Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Compare down count interrupt Disabled.
+     * |        |          |1 = Compare down count interrupt Enabled.
+     * |[29]    |CMPDIEN5  |BPWM Compare Down Count Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Compare down count interrupt Disabled.
+     * |        |          |1 = Compare down count interrupt Enabled.
+     * @var BPWM_T::INTSTS
+     * Offset: 0xE8  BPWM Interrupt Flag Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ZIF0      |BPWM Zero Point Interrupt Flag 0
+     * |        |          |This bit is set by hardware when BPWM_CH0 counter reaches zero, software can write 1 to clear this bit to zero.
+     * |[8]     |PIF0      |BPWM Period Point Interrupt Flag 0
+     * |        |          |This bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0, software can write 1 to clear this bit to zero.
+     * |[16]    |CMPUIF0   |BPWM Compare Up Count Interrupt Flag
+     * |        |          |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+     * |[17]    |CMPUIF1   |BPWM Compare Up Count Interrupt Flag
+     * |        |          |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+     * |[18]    |CMPUIF2   |BPWM Compare Up Count Interrupt Flag
+     * |        |          |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+     * |[19]    |CMPUIF3   |BPWM Compare Up Count Interrupt Flag
+     * |        |          |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+     * |[20]    |CMPUIF4   |BPWM Compare Up Count Interrupt Flag
+     * |        |          |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+     * |[21]    |CMPUIF5   |BPWM Compare Up Count Interrupt Flag
+     * |        |          |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+     * |[24]    |CMPDIF0   |BPWM Compare Down Count Interrupt Flag
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
+     * |        |          |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+     * |[25]    |CMPDIF1   |BPWM Compare Down Count Interrupt Flag
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
+     * |        |          |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+     * |[26]    |CMPDIF2   |BPWM Compare Down Count Interrupt Flag
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
+     * |        |          |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+     * |[27]    |CMPDIF3   |BPWM Compare Down Count Interrupt Flag
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
+     * |        |          |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+     * |[28]    |CMPDIF4   |BPWM Compare Down Count Interrupt Flag
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
+     * |        |          |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+     * |[29]    |CMPDIF5   |BPWM Compare Down Count Interrupt Flag
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
+     * |        |          |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+     * @var BPWM_T::EADCTS0
+     * Offset: 0xF8  BPWM Trigger EADC Source Select Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |TRGSEL0   |BPWM_CH0 Trigger EADC Source Select
+     * |        |          |0000 = BPWM_CH0 zero point.
+     * |        |          |0001 = BPWM_CH0 period point.
+     * |        |          |0010 = BPWM_CH0 zero or period point.
+     * |        |          |0011 = BPWM_CH0 up-count CMPDAT point.
+     * |        |          |0100 = BPWM_CH0 down-count CMPDAT point.
+     * |        |          |0101 = Reserved.
+     * |        |          |0110 = Reserved.
+     * |        |          |0111 = Reserved.
+     * |        |          |1000 = BPWM_CH1 up-count CMPDAT point.
+     * |        |          |1001 = BPWM_CH1 down-count CMPDAT point.
+     * |        |          |Others reserved
+     * |[7]     |TRGEN0    |BPWM_CH0 Trigger EADC Enable Bit
+     * |[11:8]  |TRGSEL1   |BPWM_CH1 Trigger EADC Source Select
+     * |        |          |0000 = BPWM_CH0 zero point.
+     * |        |          |0001 = BPWM_CH0 period point.
+     * |        |          |0010 = BPWM_CH0 zero or period point.
+     * |        |          |0011 = BPWM_CH0 up-count CMPDAT point.
+     * |        |          |0100 = BPWM_CH0 down-count CMPDAT point.
+     * |        |          |0101 = Reserved.
+     * |        |          |0110 = Reserved.
+     * |        |          |0111 = Reserved.
+     * |        |          |1000 = BPWM_CH1 up-count CMPDAT point.
+     * |        |          |1001 = BPWM_CH1 down-count CMPDAT point.
+     * |        |          |Others reserved
+     * |[15]    |TRGEN1    |BPWM_CH1 Trigger EADC Enable Bit
+     * |[19:16] |TRGSEL2   |BPWM_CH2 Trigger EADC Source Select
+     * |        |          |0000 = BPWM_CH2 zero point.
+     * |        |          |0001 = BPWM_CH2 period point.
+     * |        |          |0010 = BPWM_CH2 zero or period point.
+     * |        |          |0011 = BPWM_CH2 up-count CMPDAT point.
+     * |        |          |0100 = BPWM_CH2 down-count CMPDAT point.
+     * |        |          |0101 = Reserved.
+     * |        |          |0110 = Reserved.
+     * |        |          |0111 = Reserved.
+     * |        |          |1000 = BPWM_CH3 up-count CMPDAT point.
+     * |        |          |1001 = BPWM_CH3 down-count CMPDAT point.
+     * |        |          |Others reserved
+     * |[23]    |TRGEN2    |BPWM_CH2 Trigger EADC Enable Bit
+     * |[27:24] |TRGSEL3   |BPWM_CH3 Trigger EADC Source Select
+     * |        |          |0000 = BPWM_CH2 zero point.
+     * |        |          |0001 = BPWM_CH2 period point.
+     * |        |          |0010 = BPWM_CH2 zero or period point.
+     * |        |          |0011 = BPWM_CH2 up-count CMPDAT point.
+     * |        |          |0100 = BPWM_CH2 down-count CMPDAT point.
+     * |        |          |0101 = Reserved.
+     * |        |          |0110 = Reserved.
+     * |        |          |0111 = Reserved.
+     * |        |          |1000 = BPWM_CH3 up-count CMPDAT point.
+     * |        |          |1001 = BPWM_CH3 down-count CMPDAT point.
+     * |        |          |Others reserved.
+     * |[31]    |TRGEN3    |BPWM_CH3 Trigger EADC Enable Bit
+     * @var BPWM_T::EADCTS1
+     * Offset: 0xFC  BPWM Trigger EADC Source Select Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |TRGSEL4   |BPWM_CH4 Trigger EADC Source Select
+     * |        |          |0000 = BPWM_CH4 zero point.
+     * |        |          |0001 = BPWM_CH4 period point.
+     * |        |          |0010 = BPWM_CH4 zero or period point.
+     * |        |          |0011 = BPWM_CH4 up-count CMPDAT point.
+     * |        |          |0100 = BPWM_CH4 down-count CMPDAT point.
+     * |        |          |0101 = Reserved.
+     * |        |          |0110 = Reserved.
+     * |        |          |0111 = Reserved.
+     * |        |          |1000 = BPWM_CH5 up-count CMPDAT point.
+     * |        |          |1001 = BPWM_CH5 down-count CMPDAT point.
+     * |        |          |Others reserved
+     * |[7]     |TRGEN4    |BPWM_CH4 Trigger EADC Enable Bit
+     * |[11:8]  |TRGSEL5   |BPWM_CH5 Trigger EADC Source Select
+     * |        |          |0000 = BPWM_CH4 zero point.
+     * |        |          |0001 = BPWM_CH4 period point.
+     * |        |          |0010 = BPWM_CH4 zero or period point.
+     * |        |          |0011 = BPWM_CH4 up-count CMPDAT point.
+     * |        |          |0100 = BPWM_CH4 down-count CMPDAT point.
+     * |        |          |0101 = Reserved.
+     * |        |          |0110 = Reserved.
+     * |        |          |0111 = Reserved.
+     * |        |          |1000 = BPWM_CH5 up-count CMPDAT point.
+     * |        |          |1001 = BPWM_CH5 down-count CMPDAT point.
+     * |        |          |Others reserved
+     * |[15]    |TRGEN5    |BPWM_CH5 Trigger EADC Enable Bit
+     * @var BPWM_T::SSCTL
+     * Offset: 0x110  BPWM Synchronous Start Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SSEN0     |BPWM Synchronous Start Function 0 Enable Bit
+     * |        |          |When synchronous start function is enabled, the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN).
+     * |        |          |0 = BPWM synchronous start function Disabled.
+     * |        |          |1 = BPWM synchronous start function Enabled.
+     * |[9:8]   |SSRC      |BPWM Synchronous Start Source Select
+     * |        |          |00 = Synchronous start source come from PWM0.
+     * |        |          |01 = Synchronous start source come from PWM1.
+     * |        |          |10 = Synchronous start source come from BPWM0.
+     * |        |          |11 = Synchronous start source come from BPWM1.
+     * @var BPWM_T::SSTRG
+     * Offset: 0x114  BPWM Synchronous Start Trigger Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CNTSEN    |BPWM Counter Synchronous Start Enable Bit(Write Only)
+     * |        |          |BPMW counter synchronous enable function is used to make PWM or BPWM channels start counting at the same time.
+     * |        |          |Writing this bit to 1 will also set the counter enable bit if correlated BPWM channel counter synchronous start function is enabled.
+     * @var BPWM_T::STATUS
+     * Offset: 0x120  BPWM Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CNTMAX0   |Time-base Counter 0 Equal to 0xFFFF Latched Status
+     * |        |          |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
+     * |        |          |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
+     * |[16]    |EADCTRG0  |EADC Start of Conversion Status
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Indicates no EADC start of conversion trigger event has occurred.
+     * |        |          |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+     * |[17]    |EADCTRG1  |EADC Start of Conversion Status
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Indicates no EADC start of conversion trigger event has occurred.
+     * |        |          |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+     * |[18]    |EADCTRG2  |EADC Start of Conversion Status
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Indicates no EADC start of conversion trigger event has occurred.
+     * |        |          |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+     * |[19]    |EADCTRG3  |EADC Start of Conversion Status
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Indicates no EADC start of conversion trigger event has occurred.
+     * |        |          |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+     * |[20]    |EADCTRG4  |EADC Start of Conversion Status
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Indicates no EADC start of conversion trigger event has occurred.
+     * |        |          |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+     * |[21]    |EADCTRG5  |EADC Start of Conversion Status
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Indicates no EADC start of conversion trigger event has occurred.
+     * |        |          |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+     * @var BPWM_T::CAPINEN
+     * Offset: 0x200  BPWM Capture Input Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CAPINEN0  |Capture Input Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM Channel capture input path Disabled
+     * |        |          |The input of BPWM channel capture function is always regarded as 0.
+     * |        |          |1 = BPWM Channel capture input path Enabled
+     * |        |          |The input of BPWM channel capture function comes from correlative multifunction pin.
+     * |[1]     |CAPINEN1  |Capture Input Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM Channel capture input path Disabled
+     * |        |          |The input of BPWM channel capture function is always regarded as 0.
+     * |        |          |1 = BPWM Channel capture input path Enabled
+     * |        |          |The input of BPWM channel capture function comes from correlative multifunction pin.
+     * |[2]     |CAPINEN2  |Capture Input Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM Channel capture input path Disabled
+     * |        |          |The input of BPWM channel capture function is always regarded as 0.
+     * |        |          |1 = BPWM Channel capture input path Enabled
+     * |        |          |The input of BPWM channel capture function comes from correlative multifunction pin.
+     * |[3]     |CAPINEN3  |Capture Input Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM Channel capture input path Disabled
+     * |        |          |The input of BPWM channel capture function is always regarded as 0.
+     * |        |          |1 = BPWM Channel capture input path Enabled
+     * |        |          |The input of BPWM channel capture function comes from correlative multifunction pin.
+     * |[4]     |CAPINEN4  |Capture Input Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM Channel capture input path Disabled
+     * |        |          |The input of BPWM channel capture function is always regarded as 0.
+     * |        |          |1 = BPWM Channel capture input path Enabled
+     * |        |          |The input of BPWM channel capture function comes from correlative multifunction pin.
+     * |[5]     |CAPINEN5  |Capture Input Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM Channel capture input path Disabled
+     * |        |          |The input of BPWM channel capture function is always regarded as 0.
+     * |        |          |1 = BPWM Channel capture input path Enabled
+     * |        |          |The input of BPWM channel capture function comes from correlative multifunction pin.
+     * @var BPWM_T::CAPCTL
+     * Offset: 0x204  BPWM Capture Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CAPEN0    |Capture Function Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+     * |        |          |1 = Capture function Enabled
+     * |        |          |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+     * |[1]     |CAPEN1    |Capture Function Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+     * |        |          |1 = Capture function Enabled
+     * |        |          |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+     * |[2]     |CAPEN2    |Capture Function Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+     * |        |          |1 = Capture function Enabled
+     * |        |          |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+     * |[3]     |CAPEN3    |Capture Function Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+     * |        |          |1 = Capture function Enabled
+     * |        |          |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+     * |[4]     |CAPEN4    |Capture Function Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+     * |        |          |1 = Capture function Enabled
+     * |        |          |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+     * |[5]     |CAPEN5    |Capture Function Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+     * |        |          |1 = Capture function Enabled
+     * |        |          |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+     * |[8]     |CAPINV0   |Capture Inverter Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture source inverter Disabled.
+     * |        |          |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+     * |[9]     |CAPINV1   |Capture Inverter Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture source inverter Disabled.
+     * |        |          |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+     * |[10]    |CAPINV2   |Capture Inverter Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture source inverter Disabled.
+     * |        |          |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+     * |[11]    |CAPINV3   |Capture Inverter Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture source inverter Disabled.
+     * |        |          |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+     * |[12]    |CAPINV4   |Capture Inverter Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture source inverter Disabled.
+     * |        |          |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+     * |[13]    |CAPINV5   |Capture Inverter Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture source inverter Disabled.
+     * |        |          |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+     * |[16]    |RCRLDEN0  |Rising Capture Reload Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Rising capture reload counter Disabled.
+     * |        |          |1 = Rising capture reload counter Enabled.
+     * |[17]    |RCRLDEN1  |Rising Capture Reload Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Rising capture reload counter Disabled.
+     * |        |          |1 = Rising capture reload counter Enabled.
+     * |[18]    |RCRLDEN2  |Rising Capture Reload Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Rising capture reload counter Disabled.
+     * |        |          |1 = Rising capture reload counter Enabled.
+     * |[19]    |RCRLDEN3  |Rising Capture Reload Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Rising capture reload counter Disabled.
+     * |        |          |1 = Rising capture reload counter Enabled.
+     * |[20]    |RCRLDEN4  |Rising Capture Reload Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Rising capture reload counter Disabled.
+     * |        |          |1 = Rising capture reload counter Enabled.
+     * |[21]    |RCRLDEN5  |Rising Capture Reload Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Rising capture reload counter Disabled.
+     * |        |          |1 = Rising capture reload counter Enabled.
+     * |[24]    |FCRLDEN0  |Falling Capture Reload Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Falling capture reload counter Disabled.
+     * |        |          |1 = Falling capture reload counter Enabled.
+     * |[25]    |FCRLDEN1  |Falling Capture Reload Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Falling capture reload counter Disabled.
+     * |        |          |1 = Falling capture reload counter Enabled.
+     * |[26]    |FCRLDEN2  |Falling Capture Reload Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Falling capture reload counter Disabled.
+     * |        |          |1 = Falling capture reload counter Enabled.
+     * |[27]    |FCRLDEN3  |Falling Capture Reload Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Falling capture reload counter Disabled.
+     * |        |          |1 = Falling capture reload counter Enabled.
+     * |[28]    |FCRLDEN4  |Falling Capture Reload Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Falling capture reload counter Disabled.
+     * |        |          |1 = Falling capture reload counter Enabled.
+     * |[29]    |FCRLDEN5  |Falling Capture Reload Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Falling capture reload counter Disabled.
+     * |        |          |1 = Falling capture reload counter Enabled.
+     * @var BPWM_T::CAPSTS
+     * Offset: 0x208  BPWM Capture Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CRIFOV0   |Capture Rising Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
+     * |[1]     |CRIFOV1   |Capture Rising Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
+     * |[2]     |CRIFOV2   |Capture Rising Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
+     * |[3]     |CRIFOV3   |Capture Rising Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
+     * |[4]     |CRIFOV4   |Capture Rising Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
+     * |[5]     |CRIFOV5   |Capture Rising Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
+     * |[8]     |CFIFOV0   |Capture Falling Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
+     * |[9]     |CFIFOV1   |Capture Falling Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
+     * |[10]    |CFIFOV2   |Capture Falling Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
+     * |[11]    |CFIFOV3   |Capture Falling Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
+     * |[12]    |CFIFOV4   |Capture Falling Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
+     * |[13]    |CFIFOV5   |Capture Falling Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
+     * @var BPWM_T::CAPIEN
+     * Offset: 0x250  BPWM Capture Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[5:0]   |CAPRIENn  |BPWM Capture Rising Latch Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture rising edge latch interrupt Disabled.
+     * |        |          |1 = Capture rising edge latch interrupt Enabled.
+     * |[13:8]  |CAPFIENn  |BPWM Capture Falling Latch Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture falling edge latch interrupt Disabled.
+     * |        |          |1 = Capture falling edge latch interrupt Enabled.
+     * @var BPWM_T::CAPIF
+     * Offset: 0x254  BPWM Capture Interrupt Flag Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CAPRIF0   |BPWM Capture Rising Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = No capture rising latch condition happened.
+     * |        |          |1 = Capture rising latch condition happened, this flag will be set to high.
+     * |[1]     |CAPRIF1   |BPWM Capture Rising Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = No capture rising latch condition happened.
+     * |        |          |1 = Capture rising latch condition happened, this flag will be set to high.
+     * |[2]     |CAPRIF2   |BPWM Capture Rising Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = No capture rising latch condition happened.
+     * |        |          |1 = Capture rising latch condition happened, this flag will be set to high.
+     * |[3]     |CAPRIF3   |BPWM Capture Rising Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = No capture rising latch condition happened.
+     * |        |          |1 = Capture rising latch condition happened, this flag will be set to high.
+     * |[4]     |CAPRIF4   |BPWM Capture Rising Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = No capture rising latch condition happened.
+     * |        |          |1 = Capture rising latch condition happened, this flag will be set to high.
+     * |[5]     |CAPRIF5   |BPWM Capture Rising Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = No capture rising latch condition happened.
+     * |        |          |1 = Capture rising latch condition happened, this flag will be set to high.
+     * |[8]     |CAPFIF0   |BPWM Capture Falling Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = No capture falling latch condition happened.
+     * |        |          |1 = Capture falling latch condition happened, this flag will be set to high.
+     * |[9]     |CAPFIF1   |BPWM Capture Falling Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = No capture falling latch condition happened.
+     * |        |          |1 = Capture falling latch condition happened, this flag will be set to high.
+     * |[10]    |CAPFIF2   |BPWM Capture Falling Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = No capture falling latch condition happened.
+     * |        |          |1 = Capture falling latch condition happened, this flag will be set to high.
+     * |[11]    |CAPFIF3   |BPWM Capture Falling Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = No capture falling latch condition happened.
+     * |        |          |1 = Capture falling latch condition happened, this flag will be set to high.
+     * |[12]    |CAPFIF4   |BPWM Capture Falling Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = No capture falling latch condition happened.
+     * |        |          |1 = Capture falling latch condition happened, this flag will be set to high.
+     * |[13]    |CAPFIF5   |BPWM Capture Falling Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = No capture falling latch condition happened.
+     * |        |          |1 = Capture falling latch condition happened, this flag will be set to high.
+     * @var BPWM_T::PBUF
+     * Offset: 0x304  BPWM PERIOD Buffer
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |PBUF      |BPWM Period Buffer (Read Only)
+     * |        |          |Used as PERIOD active register.
+     * @var BPWM_T::CMPBUF[6]
+     * Offset: 0x31C  BPWM CMPDAT 0~5 Buffer
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |CMPBUF    |BPWM Comparator Buffer (Read Only)
+     * |        |          |Used as CMP active register.
+     */
+    __IO uint32_t CTL0;                  /*!< [0x0000] BPWM Control Register 0                                          */
+    __IO uint32_t CTL1;                  /*!< [0x0004] BPWM Control Register 1                                          */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE0[2];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t CLKSRC;                /*!< [0x0010] BPWM Clock Source Register                                       */
+    __IO uint32_t CLKPSC;                /*!< [0x0014] BPWM Clock Prescale Register                                     */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE1[2];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t CNTEN;                 /*!< [0x0020] BPWM Counter Enable Register                                     */
+    __IO uint32_t CNTCLR;                /*!< [0x0024] BPWM Clear Counter Register                                      */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE2[2];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t PERIOD;                /*!< [0x0030] BPWM Period Register                                             */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE3[7];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t CMPDAT[6];             /*!< [0x0050] BPWM Comparator Register 0~5                                     */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE4[10];
+    /// @endcond //HIDDEN_SYMBOLS
+    __I  uint32_t CNT;                   /*!< [0x0090] BPWM Counter Register                                            */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE5[7];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t WGCTL0;                /*!< [0x00b0] BPWM Generation Register 0                                       */
+    __IO uint32_t WGCTL1;                /*!< [0x00b4] BPWM Generation Register 1                                       */
+    __IO uint32_t MSKEN;                 /*!< [0x00b8] BPWM Mask Enable Register                                        */
+    __IO uint32_t MSK;                   /*!< [0x00bc] BPWM Mask Data Register                                          */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE6[5];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t POLCTL;                /*!< [0x00d4] BPWM Pin Polar Inverse Register                                  */
+    __IO uint32_t POEN;                  /*!< [0x00d8] BPWM Output Enable Register                                      */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE7[1];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t INTEN;                 /*!< [0x00e0] BPWM Interrupt Enable Register                                   */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE8[1];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t INTSTS;                /*!< [0x00e8] BPWM Interrupt Flag Register                                     */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE9[3];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t EADCTS0;               /*!< [0x00f8] BPWM Trigger EADC Source Select Register 0                       */
+    __IO uint32_t EADCTS1;               /*!< [0x00fc] BPWM Trigger EADC Source Select Register 1                       */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE10[4];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t SSCTL;                 /*!< [0x0110] BPWM Synchronous Start Control Register                          */
+    __O  uint32_t SSTRG;                 /*!< [0x0114] BPWM Synchronous Start Trigger Register                          */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE11[2];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t STATUS;                /*!< [0x0120] BPWM Status Register                                             */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE12[55];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t CAPINEN;               /*!< [0x0200] BPWM Capture Input Enable Register                               */
+    __IO uint32_t CAPCTL;                /*!< [0x0204] BPWM Capture Control Register                                    */
+    __I  uint32_t CAPSTS;                /*!< [0x0208] BPWM Capture Status Register                                     */
+    BCAPDAT_T CAPDAT[6];                  /*!< [0x020C] BPWM Rising and Falling Capture Data Register 0~5                */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE13[5];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t CAPIEN;                /*!< [0x0250] BPWM Capture Interrupt Enable Register                           */
+    __IO uint32_t CAPIF;                 /*!< [0x0254] BPWM Capture Interrupt Flag Register                             */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE14[43];
+    /// @endcond //HIDDEN_SYMBOLS
+    __I  uint32_t PBUF;                  /*!< [0x0304] BPWM PERIOD Buffer                                               */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE15[5];
+    /// @endcond //HIDDEN_SYMBOLS
+    __I  uint32_t CMPBUF[6];             /*!< [0x031c] BPWM CMPDAT 0~5 Buffer                                           */
+
+} BPWM_T;
+
+/**
+    @addtogroup BPWM_CONST BPWM Bit Field Definition
+    Constant Definitions for BPWM Controller
+@{ */
+
+#define BPWM_CTL0_CTRLD0_Pos             (0)                                               /*!< BPWM_T::CTL0: CTRLD0 Position          */
+#define BPWM_CTL0_CTRLD0_Msk             (0x1ul << BPWM_CTL0_CTRLD0_Pos)                   /*!< BPWM_T::CTL0: CTRLD0 Mask              */
+
+#define BPWM_CTL0_CTRLD1_Pos             (1)                                               /*!< BPWM_T::CTL0: CTRLD1 Position          */
+#define BPWM_CTL0_CTRLD1_Msk             (0x1ul << BPWM_CTL0_CTRLD1_Pos)                   /*!< BPWM_T::CTL0: CTRLD1 Mask              */
+
+#define BPWM_CTL0_CTRLD2_Pos             (2)                                               /*!< BPWM_T::CTL0: CTRLD2 Position          */
+#define BPWM_CTL0_CTRLD2_Msk             (0x1ul << BPWM_CTL0_CTRLD2_Pos)                   /*!< BPWM_T::CTL0: CTRLD2 Mask              */
+
+#define BPWM_CTL0_CTRLD3_Pos             (3)                                               /*!< BPWM_T::CTL0: CTRLD3 Position          */
+#define BPWM_CTL0_CTRLD3_Msk             (0x1ul << BPWM_CTL0_CTRLD3_Pos)                   /*!< BPWM_T::CTL0: CTRLD3 Mask              */
+
+#define BPWM_CTL0_CTRLD4_Pos             (4)                                               /*!< BPWM_T::CTL0: CTRLD4 Position          */
+#define BPWM_CTL0_CTRLD4_Msk             (0x1ul << BPWM_CTL0_CTRLD4_Pos)                   /*!< BPWM_T::CTL0: CTRLD4 Mask              */
+
+#define BPWM_CTL0_CTRLD5_Pos             (5)                                               /*!< BPWM_T::CTL0: CTRLD5 Position          */
+#define BPWM_CTL0_CTRLD5_Msk             (0x1ul << BPWM_CTL0_CTRLD5_Pos)                   /*!< BPWM_T::CTL0: CTRLD5 Mask              */
+
+#define BPWM_CTL0_IMMLDEN0_Pos           (16)                                              /*!< BPWM_T::CTL0: IMMLDEN0 Position        */
+#define BPWM_CTL0_IMMLDEN0_Msk           (0x1ul << BPWM_CTL0_IMMLDEN0_Pos)                 /*!< BPWM_T::CTL0: IMMLDEN0 Mask            */
+
+#define BPWM_CTL0_IMMLDEN1_Pos           (17)                                              /*!< BPWM_T::CTL0: IMMLDEN1 Position        */
+#define BPWM_CTL0_IMMLDEN1_Msk           (0x1ul << BPWM_CTL0_IMMLDEN1_Pos)                 /*!< BPWM_T::CTL0: IMMLDEN1 Mask            */
+
+#define BPWM_CTL0_IMMLDEN2_Pos           (18)                                              /*!< BPWM_T::CTL0: IMMLDEN2 Position        */
+#define BPWM_CTL0_IMMLDEN2_Msk           (0x1ul << BPWM_CTL0_IMMLDEN2_Pos)                 /*!< BPWM_T::CTL0: IMMLDEN2 Mask            */
+
+#define BPWM_CTL0_IMMLDEN3_Pos           (19)                                              /*!< BPWM_T::CTL0: IMMLDEN3 Position        */
+#define BPWM_CTL0_IMMLDEN3_Msk           (0x1ul << BPWM_CTL0_IMMLDEN3_Pos)                 /*!< BPWM_T::CTL0: IMMLDEN3 Mask            */
+
+#define BPWM_CTL0_IMMLDEN4_Pos           (20)                                              /*!< BPWM_T::CTL0: IMMLDEN4 Position        */
+#define BPWM_CTL0_IMMLDEN4_Msk           (0x1ul << BPWM_CTL0_IMMLDEN4_Pos)                 /*!< BPWM_T::CTL0: IMMLDEN4 Mask            */
+
+#define BPWM_CTL0_IMMLDEN5_Pos           (21)                                              /*!< BPWM_T::CTL0: IMMLDEN5 Position        */
+#define BPWM_CTL0_IMMLDEN5_Msk           (0x1ul << BPWM_CTL0_IMMLDEN5_Pos)                 /*!< BPWM_T::CTL0: IMMLDEN5 Mask            */
+
+#define BPWM_CTL0_DBGHALT_Pos            (30)                                              /*!< BPWM_T::CTL0: DBGHALT Position         */
+#define BPWM_CTL0_DBGHALT_Msk            (0x1ul << BPWM_CTL0_DBGHALT_Pos)                  /*!< BPWM_T::CTL0: DBGHALT Mask             */
+
+#define BPWM_CTL0_DBGTRIOFF_Pos          (31)                                              /*!< BPWM_T::CTL0: DBGTRIOFF Position       */
+#define BPWM_CTL0_DBGTRIOFF_Msk          (0x1ul << BPWM_CTL0_DBGTRIOFF_Pos)                /*!< BPWM_T::CTL0: DBGTRIOFF Mask           */
+
+#define BPWM_CTL1_CNTTYPE0_Pos           (0)                                               /*!< BPWM_T::CTL1: CNTTYPE0 Position        */
+#define BPWM_CTL1_CNTTYPE0_Msk           (0x3ul << BPWM_CTL1_CNTTYPE0_Pos)                 /*!< BPWM_T::CTL1: CNTTYPE0 Mask            */
+
+#define BPWM_CLKSRC_ECLKSRC0_Pos         (0)                                               /*!< BPWM_T::CLKSRC: ECLKSRC0 Position      */
+#define BPWM_CLKSRC_ECLKSRC0_Msk         (0x7ul << BPWM_CLKSRC_ECLKSRC0_Pos)               /*!< BPWM_T::CLKSRC: ECLKSRC0 Mask          */
+
+#define BPWM_CLKPSC_CLKPSC_Pos           (0)                                               /*!< BPWM_T::CLKPSC: CLKPSC Position        */
+#define BPWM_CLKPSC_CLKPSC_Msk           (0xffful << BPWM_CLKPSC_CLKPSC_Pos)               /*!< BPWM_T::CLKPSC: CLKPSC Mask            */
+
+#define BPWM_CNTEN_CNTEN0_Pos            (0)                                               /*!< BPWM_T::CNTEN: CNTEN0 Position         */
+#define BPWM_CNTEN_CNTEN0_Msk            (0x1ul << BPWM_CNTEN_CNTEN0_Pos)                  /*!< BPWM_T::CNTEN: CNTEN0 Mask             */
+
+#define BPWM_CNTCLR_CNTCLR0_Pos          (0)                                               /*!< BPWM_T::CNTCLR: CNTCLR0 Position       */
+#define BPWM_CNTCLR_CNTCLR0_Msk          (0x1ul << BPWM_CNTCLR_CNTCLR0_Pos)                /*!< BPWM_T::CNTCLR: CNTCLR0 Mask           */
+
+#define BPWM_PERIOD_PERIOD_Pos           (0)                                               /*!< BPWM_T::PERIOD: PERIOD Position        */
+#define BPWM_PERIOD_PERIOD_Msk           (0xfffful << BPWM_PERIOD_PERIOD_Pos)              /*!< BPWM_T::PERIOD: PERIOD Mask            */
+
+#define BPWM_CMPDAT0_CMPDAT_Pos          (0)                                               /*!< BPWM_T::CMPDAT0: CMPDAT Position       */
+#define BPWM_CMPDAT0_CMPDAT_Msk          (0xfffful << BPWM_CMPDAT0_CMPDAT_Pos)             /*!< BPWM_T::CMPDAT0: CMPDAT Mask           */
+
+#define BPWM_CMPDAT1_CMPDAT_Pos          (0)                                               /*!< BPWM_T::CMPDAT1: CMPDAT Position       */
+#define BPWM_CMPDAT1_CMPDAT_Msk          (0xfffful << BPWM_CMPDAT1_CMPDAT_Pos)             /*!< BPWM_T::CMPDAT1: CMPDAT Mask           */
+
+#define BPWM_CMPDAT2_CMPDAT_Pos          (0)                                               /*!< BPWM_T::CMPDAT2: CMPDAT Position       */
+#define BPWM_CMPDAT2_CMPDAT_Msk          (0xfffful << BPWM_CMPDAT2_CMPDAT_Pos)             /*!< BPWM_T::CMPDAT2: CMPDAT Mask           */
+
+#define BPWM_CMPDAT3_CMPDAT_Pos          (0)                                               /*!< BPWM_T::CMPDAT3: CMPDAT Position       */
+#define BPWM_CMPDAT3_CMPDAT_Msk          (0xfffful << BPWM_CMPDAT3_CMPDAT_Pos)             /*!< BPWM_T::CMPDAT3: CMPDAT Mask           */
+
+#define BPWM_CMPDAT4_CMPDAT_Pos          (0)                                               /*!< BPWM_T::CMPDAT4: CMPDAT Position       */
+#define BPWM_CMPDAT4_CMPDAT_Msk          (0xfffful << BPWM_CMPDAT4_CMPDAT_Pos)             /*!< BPWM_T::CMPDAT4: CMPDAT Mask           */
+
+#define BPWM_CMPDAT5_CMPDAT_Pos          (0)                                               /*!< BPWM_T::CMPDAT5: CMPDAT Position       */
+#define BPWM_CMPDAT5_CMPDAT_Msk          (0xfffful << BPWM_CMPDAT5_CMPDAT_Pos)             /*!< BPWM_T::CMPDAT5: CMPDAT Mask           */
+
+#define BPWM_CNT_CNT_Pos                 (0)                                               /*!< BPWM_T::CNT: CNT Position              */
+#define BPWM_CNT_CNT_Msk                 (0xfffful << BPWM_CNT_CNT_Pos)                    /*!< BPWM_T::CNT: CNT Mask                  */
+
+#define BPWM_CNT_DIRF_Pos                (16)                                              /*!< BPWM_T::CNT: DIRF Position             */
+#define BPWM_CNT_DIRF_Msk                (0x1ul << BPWM_CNT_DIRF_Pos)                      /*!< BPWM_T::CNT: DIRF Mask                 */
+
+#define BPWM_WGCTL0_ZPCTL0_Pos           (0)                                               /*!< BPWM_T::WGCTL0: ZPCTL0 Position        */
+#define BPWM_WGCTL0_ZPCTL0_Msk           (0x3ul << BPWM_WGCTL0_ZPCTL0_Pos)                 /*!< BPWM_T::WGCTL0: ZPCTL0 Mask            */
+
+#define BPWM_WGCTL0_ZPCTL1_Pos           (2)                                               /*!< BPWM_T::WGCTL0: ZPCTL1 Position        */
+#define BPWM_WGCTL0_ZPCTL1_Msk           (0x3ul << BPWM_WGCTL0_ZPCTL1_Pos)                 /*!< BPWM_T::WGCTL0: ZPCTL1 Mask            */
+
+#define BPWM_WGCTL0_ZPCTL2_Pos           (4)                                               /*!< BPWM_T::WGCTL0: ZPCTL2 Position        */
+#define BPWM_WGCTL0_ZPCTL2_Msk           (0x3ul << BPWM_WGCTL0_ZPCTL2_Pos)                 /*!< BPWM_T::WGCTL0: ZPCTL2 Mask            */
+
+#define BPWM_WGCTL0_ZPCTL3_Pos           (6)                                               /*!< BPWM_T::WGCTL0: ZPCTL3 Position        */
+#define BPWM_WGCTL0_ZPCTL3_Msk           (0x3ul << BPWM_WGCTL0_ZPCTL3_Pos)                 /*!< BPWM_T::WGCTL0: ZPCTL3 Mask            */
+
+#define BPWM_WGCTL0_ZPCTL4_Pos           (8)                                               /*!< BPWM_T::WGCTL0: ZPCTL4 Position        */
+#define BPWM_WGCTL0_ZPCTL4_Msk           (0x3ul << BPWM_WGCTL0_ZPCTL4_Pos)                 /*!< BPWM_T::WGCTL0: ZPCTL4 Mask            */
+
+#define BPWM_WGCTL0_ZPCTL5_Pos           (10)                                              /*!< BPWM_T::WGCTL0: ZPCTL5 Position        */
+#define BPWM_WGCTL0_ZPCTL5_Msk           (0x3ul << BPWM_WGCTL0_ZPCTL5_Pos)                 /*!< BPWM_T::WGCTL0: ZPCTL5 Mask            */
+
+#define BPWM_WGCTL0_ZPCTLn_Pos           (0)                                               /*!< BPWM_T::WGCTL0: ZPCTLn Position        */
+#define BPWM_WGCTL0_ZPCTLn_Msk           (0xffful << BPWM_WGCTL0_ZPCTLn_Pos)               /*!< BPWM_T::WGCTL0: ZPCTLn Mask            */
+
+#define BPWM_WGCTL0_PRDPCTL0_Pos         (16)                                              /*!< BPWM_T::WGCTL0: PRDPCTL0 Position      */
+#define BPWM_WGCTL0_PRDPCTL0_Msk         (0x3ul << BPWM_WGCTL0_PRDPCTL0_Pos)               /*!< BPWM_T::WGCTL0: PRDPCTL0 Mask          */
+
+#define BPWM_WGCTL0_PRDPCTL1_Pos         (18)                                              /*!< BPWM_T::WGCTL0: PRDPCTL1 Position      */
+#define BPWM_WGCTL0_PRDPCTL1_Msk         (0x3ul << BPWM_WGCTL0_PRDPCTL1_Pos)               /*!< BPWM_T::WGCTL0: PRDPCTL1 Mask          */
+
+#define BPWM_WGCTL0_PRDPCTL2_Pos         (20)                                              /*!< BPWM_T::WGCTL0: PRDPCTL2 Position      */
+#define BPWM_WGCTL0_PRDPCTL2_Msk         (0x3ul << BPWM_WGCTL0_PRDPCTL2_Pos)               /*!< BPWM_T::WGCTL0: PRDPCTL2 Mask          */
+
+#define BPWM_WGCTL0_PRDPCTL3_Pos         (22)                                              /*!< BPWM_T::WGCTL0: PRDPCTL3 Position      */
+#define BPWM_WGCTL0_PRDPCTL3_Msk         (0x3ul << BPWM_WGCTL0_PRDPCTL3_Pos)               /*!< BPWM_T::WGCTL0: PRDPCTL3 Mask          */
+
+#define BPWM_WGCTL0_PRDPCTL4_Pos         (24)                                              /*!< BPWM_T::WGCTL0: PRDPCTL4 Position      */
+#define BPWM_WGCTL0_PRDPCTL4_Msk         (0x3ul << BPWM_WGCTL0_PRDPCTL4_Pos)               /*!< BPWM_T::WGCTL0: PRDPCTL4 Mask          */
+
+#define BPWM_WGCTL0_PRDPCTL5_Pos         (26)                                              /*!< BPWM_T::WGCTL0: PRDPCTL5 Position      */
+#define BPWM_WGCTL0_PRDPCTL5_Msk         (0x3ul << BPWM_WGCTL0_PRDPCTL5_Pos)               /*!< BPWM_T::WGCTL0: PRDPCTL5 Mask          */
+
+#define BPWM_WGCTL0_PRDPCTLn_Pos         (16)                                              /*!< BPWM_T::WGCTL0: PRDPCTLn Position      */
+#define BPWM_WGCTL0_PRDPCTLn_Msk         (0xffful << BPWM_WGCTL0_PRDPCTLn_Pos)             /*!< BPWM_T::WGCTL0: PRDPCTLn Mask          */
+
+#define BPWM_WGCTL1_CMPUCTL0_Pos         (0)                                               /*!< BPWM_T::WGCTL1: CMPUCTL0 Position      */
+#define BPWM_WGCTL1_CMPUCTL0_Msk         (0x3ul << BPWM_WGCTL1_CMPUCTL0_Pos)               /*!< BPWM_T::WGCTL1: CMPUCTL0 Mask          */
+
+#define BPWM_WGCTL1_CMPUCTL1_Pos         (2)                                               /*!< BPWM_T::WGCTL1: CMPUCTL1 Position      */
+#define BPWM_WGCTL1_CMPUCTL1_Msk         (0x3ul << BPWM_WGCTL1_CMPUCTL1_Pos)               /*!< BPWM_T::WGCTL1: CMPUCTL1 Mask          */
+
+#define BPWM_WGCTL1_CMPUCTL2_Pos         (4)                                               /*!< BPWM_T::WGCTL1: CMPUCTL2 Position      */
+#define BPWM_WGCTL1_CMPUCTL2_Msk         (0x3ul << BPWM_WGCTL1_CMPUCTL2_Pos)               /*!< BPWM_T::WGCTL1: CMPUCTL2 Mask          */
+
+#define BPWM_WGCTL1_CMPUCTL3_Pos         (6)                                               /*!< BPWM_T::WGCTL1: CMPUCTL3 Position      */
+#define BPWM_WGCTL1_CMPUCTL3_Msk         (0x3ul << BPWM_WGCTL1_CMPUCTL3_Pos)               /*!< BPWM_T::WGCTL1: CMPUCTL3 Mask          */
+
+#define BPWM_WGCTL1_CMPUCTL4_Pos         (8)                                               /*!< BPWM_T::WGCTL1: CMPUCTL4 Position      */
+#define BPWM_WGCTL1_CMPUCTL4_Msk         (0x3ul << BPWM_WGCTL1_CMPUCTL4_Pos)               /*!< BPWM_T::WGCTL1: CMPUCTL4 Mask          */
+
+#define BPWM_WGCTL1_CMPUCTL5_Pos         (10)                                              /*!< BPWM_T::WGCTL1: CMPUCTL5 Position      */
+#define BPWM_WGCTL1_CMPUCTL5_Msk         (0x3ul << BPWM_WGCTL1_CMPUCTL5_Pos)               /*!< BPWM_T::WGCTL1: CMPUCTL5 Mask          */
+
+#define BPWM_WGCTL1_CMPUCTLn_Pos         (0)                                               /*!< BPWM_T::WGCTL1: CMPUCTLn Position      */
+#define BPWM_WGCTL1_CMPUCTLn_Msk         (0xffful << BPWM_WGCTL1_CMPUCTLn_Pos)             /*!< BPWM_T::WGCTL1: CMPUCTLn Mask          */
+
+#define BPWM_WGCTL1_CMPDCTL0_Pos         (16)                                              /*!< BPWM_T::WGCTL1: CMPDCTL0 Position      */
+#define BPWM_WGCTL1_CMPDCTL0_Msk         (0x3ul << BPWM_WGCTL1_CMPDCTL0_Pos)               /*!< BPWM_T::WGCTL1: CMPDCTL0 Mask          */
+
+#define BPWM_WGCTL1_CMPDCTL1_Pos         (18)                                              /*!< BPWM_T::WGCTL1: CMPDCTL1 Position      */
+#define BPWM_WGCTL1_CMPDCTL1_Msk         (0x3ul << BPWM_WGCTL1_CMPDCTL1_Pos)               /*!< BPWM_T::WGCTL1: CMPDCTL1 Mask          */
+
+#define BPWM_WGCTL1_CMPDCTL2_Pos         (20)                                              /*!< BPWM_T::WGCTL1: CMPDCTL2 Position      */
+#define BPWM_WGCTL1_CMPDCTL2_Msk         (0x3ul << BPWM_WGCTL1_CMPDCTL2_Pos)               /*!< BPWM_T::WGCTL1: CMPDCTL2 Mask          */
+
+#define BPWM_WGCTL1_CMPDCTL3_Pos         (22)                                              /*!< BPWM_T::WGCTL1: CMPDCTL3 Position      */
+#define BPWM_WGCTL1_CMPDCTL3_Msk         (0x3ul << BPWM_WGCTL1_CMPDCTL3_Pos)               /*!< BPWM_T::WGCTL1: CMPDCTL3 Mask          */
+
+#define BPWM_WGCTL1_CMPDCTL4_Pos         (24)                                              /*!< BPWM_T::WGCTL1: CMPDCTL4 Position      */
+#define BPWM_WGCTL1_CMPDCTL4_Msk         (0x3ul << BPWM_WGCTL1_CMPDCTL4_Pos)               /*!< BPWM_T::WGCTL1: CMPDCTL4 Mask          */
+
+#define BPWM_WGCTL1_CMPDCTL5_Pos         (26)                                              /*!< BPWM_T::WGCTL1: CMPDCTL5 Position      */
+#define BPWM_WGCTL1_CMPDCTL5_Msk         (0x3ul << BPWM_WGCTL1_CMPDCTL5_Pos)               /*!< BPWM_T::WGCTL1: CMPDCTL5 Mask          */
+
+#define BPWM_WGCTL1_CMPDCTLn_Pos         (16)                                              /*!< BPWM_T::WGCTL1: CMPDCTLn Position      */
+#define BPWM_WGCTL1_CMPDCTLn_Msk         (0xffful << BPWM_WGCTL1_CMPDCTLn_Pos)             /*!< BPWM_T::WGCTL1: CMPDCTLn Mask          */
+
+#define BPWM_MSKEN_MSKEN0_Pos            (0)                                               /*!< BPWM_T::MSKEN: MSKEN0 Position         */
+#define BPWM_MSKEN_MSKEN0_Msk            (0x1ul << BPWM_MSKEN_MSKEN0_Pos)                  /*!< BPWM_T::MSKEN: MSKEN0 Mask             */
+
+#define BPWM_MSKEN_MSKEN1_Pos            (1)                                               /*!< BPWM_T::MSKEN: MSKEN1 Position         */
+#define BPWM_MSKEN_MSKEN1_Msk            (0x1ul << BPWM_MSKEN_MSKEN1_Pos)                  /*!< BPWM_T::MSKEN: MSKEN1 Mask             */
+
+#define BPWM_MSKEN_MSKEN2_Pos            (2)                                               /*!< BPWM_T::MSKEN: MSKEN2 Position         */
+#define BPWM_MSKEN_MSKEN2_Msk            (0x1ul << BPWM_MSKEN_MSKEN2_Pos)                  /*!< BPWM_T::MSKEN: MSKEN2 Mask             */
+
+#define BPWM_MSKEN_MSKEN3_Pos            (3)                                               /*!< BPWM_T::MSKEN: MSKEN3 Position         */
+#define BPWM_MSKEN_MSKEN3_Msk            (0x1ul << BPWM_MSKEN_MSKEN3_Pos)                  /*!< BPWM_T::MSKEN: MSKEN3 Mask             */
+
+#define BPWM_MSKEN_MSKEN4_Pos            (4)                                               /*!< BPWM_T::MSKEN: MSKEN4 Position         */
+#define BPWM_MSKEN_MSKEN4_Msk            (0x1ul << BPWM_MSKEN_MSKEN4_Pos)                  /*!< BPWM_T::MSKEN: MSKEN4 Mask             */
+
+#define BPWM_MSKEN_MSKEN5_Pos            (5)                                               /*!< BPWM_T::MSKEN: MSKEN5 Position         */
+#define BPWM_MSKEN_MSKEN5_Msk            (0x1ul << BPWM_MSKEN_MSKEN5_Pos)                  /*!< BPWM_T::MSKEN: MSKEN5 Mask             */
+
+#define BPWM_MSKEN_MSKENn_Pos            (0)                                               /*!< BPWM_T::MSKEN: MSKENn Position         */
+#define BPWM_MSKEN_MSKENn_Msk            (0x3ful << BPWM_MSKEN_MSKENn_Pos)                 /*!< BPWM_T::MSKEN: MSKENn Mask             */
+
+#define BPWM_MSK_MSKDAT0_Pos             (0)                                               /*!< BPWM_T::MSK: MSKDAT0 Position          */
+#define BPWM_MSK_MSKDAT0_Msk             (0x1ul << BPWM_MSK_MSKDAT0_Pos)                   /*!< BPWM_T::MSK: MSKDAT0 Mask              */
+
+#define BPWM_MSK_MSKDAT1_Pos             (1)                                               /*!< BPWM_T::MSK: MSKDAT1 Position          */
+#define BPWM_MSK_MSKDAT1_Msk             (0x1ul << BPWM_MSK_MSKDAT1_Pos)                   /*!< BPWM_T::MSK: MSKDAT1 Mask              */
+
+#define BPWM_MSK_MSKDAT2_Pos             (2)                                               /*!< BPWM_T::MSK: MSKDAT2 Position          */
+#define BPWM_MSK_MSKDAT2_Msk             (0x1ul << BPWM_MSK_MSKDAT2_Pos)                   /*!< BPWM_T::MSK: MSKDAT2 Mask              */
+
+#define BPWM_MSK_MSKDAT3_Pos             (3)                                               /*!< BPWM_T::MSK: MSKDAT3 Position          */
+#define BPWM_MSK_MSKDAT3_Msk             (0x1ul << BPWM_MSK_MSKDAT3_Pos)                   /*!< BPWM_T::MSK: MSKDAT3 Mask              */
+
+#define BPWM_MSK_MSKDAT4_Pos             (4)                                               /*!< BPWM_T::MSK: MSKDAT4 Position          */
+#define BPWM_MSK_MSKDAT4_Msk             (0x1ul << BPWM_MSK_MSKDAT4_Pos)                   /*!< BPWM_T::MSK: MSKDAT4 Mask              */
+
+#define BPWM_MSK_MSKDAT5_Pos             (5)                                               /*!< BPWM_T::MSK: MSKDAT5 Position          */
+#define BPWM_MSK_MSKDAT5_Msk             (0x1ul << BPWM_MSK_MSKDAT5_Pos)                   /*!< BPWM_T::MSK: MSKDAT5 Mask              */
+
+#define BPWM_MSK_MSKDATn_Pos             (0)                                               /*!< BPWM_T::MSK: MSKDATn Position          */
+#define BPWM_MSK_MSKDATn_Msk             (0x3ful << BPWM_MSK_MSKDATn_Pos)                  /*!< BPWM_T::MSK: MSKDATn Mask              */
+
+#define BPWM_POLCTL_PINV0_Pos            (0)                                               /*!< BPWM_T::POLCTL: PINV0 Position         */
+#define BPWM_POLCTL_PINV0_Msk            (0x1ul << BPWM_POLCTL_PINV0_Pos)                  /*!< BPWM_T::POLCTL: PINV0 Mask             */
+
+#define BPWM_POLCTL_PINV1_Pos            (1)                                               /*!< BPWM_T::POLCTL: PINV1 Position         */
+#define BPWM_POLCTL_PINV1_Msk            (0x1ul << BPWM_POLCTL_PINV1_Pos)                  /*!< BPWM_T::POLCTL: PINV1 Mask             */
+
+#define BPWM_POLCTL_PINV2_Pos            (2)                                               /*!< BPWM_T::POLCTL: PINV2 Position         */
+#define BPWM_POLCTL_PINV2_Msk            (0x1ul << BPWM_POLCTL_PINV2_Pos)                  /*!< BPWM_T::POLCTL: PINV2 Mask             */
+
+#define BPWM_POLCTL_PINV3_Pos            (3)                                               /*!< BPWM_T::POLCTL: PINV3 Position         */
+#define BPWM_POLCTL_PINV3_Msk            (0x1ul << BPWM_POLCTL_PINV3_Pos)                  /*!< BPWM_T::POLCTL: PINV3 Mask             */
+
+#define BPWM_POLCTL_PINV4_Pos            (4)                                               /*!< BPWM_T::POLCTL: PINV4 Position         */
+#define BPWM_POLCTL_PINV4_Msk            (0x1ul << BPWM_POLCTL_PINV4_Pos)                  /*!< BPWM_T::POLCTL: PINV4 Mask             */
+
+#define BPWM_POLCTL_PINV5_Pos            (5)                                               /*!< BPWM_T::POLCTL: PINV5 Position         */
+#define BPWM_POLCTL_PINV5_Msk            (0x1ul << BPWM_POLCTL_PINV5_Pos)                  /*!< BPWM_T::POLCTL: PINV5 Mask             */
+
+#define BPWM_POLCTL_PINVn_Pos            (0)                                               /*!< BPWM_T::POLCTL: PINVn Position         */
+#define BPWM_POLCTL_PINVn_Msk            (0x3ful << BPWM_POLCTL_PINVn_Pos)                 /*!< BPWM_T::POLCTL: PINVn Mask             */
+
+#define BPWM_POEN_POEN0_Pos              (0)                                               /*!< BPWM_T::POEN: POEN0 Position           */
+#define BPWM_POEN_POEN0_Msk              (0x1ul << BPWM_POEN_POEN0_Pos)                    /*!< BPWM_T::POEN: POEN0 Mask               */
+
+#define BPWM_POEN_POEN1_Pos              (1)                                               /*!< BPWM_T::POEN: POEN1 Position           */
+#define BPWM_POEN_POEN1_Msk              (0x1ul << BPWM_POEN_POEN1_Pos)                    /*!< BPWM_T::POEN: POEN1 Mask               */
+
+#define BPWM_POEN_POEN2_Pos              (2)                                               /*!< BPWM_T::POEN: POEN2 Position           */
+#define BPWM_POEN_POEN2_Msk              (0x1ul << BPWM_POEN_POEN2_Pos)                    /*!< BPWM_T::POEN: POEN2 Mask               */
+
+#define BPWM_POEN_POEN3_Pos              (3)                                               /*!< BPWM_T::POEN: POEN3 Position           */
+#define BPWM_POEN_POEN3_Msk              (0x1ul << BPWM_POEN_POEN3_Pos)                    /*!< BPWM_T::POEN: POEN3 Mask               */
+
+#define BPWM_POEN_POEN4_Pos              (4)                                               /*!< BPWM_T::POEN: POEN4 Position           */
+#define BPWM_POEN_POEN4_Msk              (0x1ul << BPWM_POEN_POEN4_Pos)                    /*!< BPWM_T::POEN: POEN4 Mask               */
+
+#define BPWM_POEN_POEN5_Pos              (5)                                               /*!< BPWM_T::POEN: POEN5 Position           */
+#define BPWM_POEN_POEN5_Msk              (0x1ul << BPWM_POEN_POEN5_Pos)                    /*!< BPWM_T::POEN: POEN5 Mask               */
+
+#define BPWM_POEN_POENn_Pos              (0)                                               /*!< BPWM_T::POEN: POENn Position           */
+#define BPWM_POEN_POENn_Msk              (0x3ful << BPWM_POEN_POENn_Pos)                   /*!< BPWM_T::POEN: POENn Mask               */
+
+#define BPWM_INTEN_ZIEN0_Pos             (0)                                               /*!< BPWM_T::INTEN: ZIEN0 Position          */
+#define BPWM_INTEN_ZIEN0_Msk             (0x1ul << BPWM_INTEN_ZIEN0_Pos)                   /*!< BPWM_T::INTEN: ZIEN0 Mask              */
+
+#define BPWM_INTEN_PIEN0_Pos             (8)                                               /*!< BPWM_T::INTEN: PIEN0 Position          */
+#define BPWM_INTEN_PIEN0_Msk             (0x1ul << BPWM_INTEN_PIEN0_Pos)                   /*!< BPWM_T::INTEN: PIEN0 Mask              */
+
+#define BPWM_INTEN_CMPUIEN0_Pos          (16)                                              /*!< BPWM_T::INTEN: CMPUIEN0 Position       */
+#define BPWM_INTEN_CMPUIEN0_Msk          (0x1ul << BPWM_INTEN_CMPUIEN0_Pos)                /*!< BPWM_T::INTEN: CMPUIEN0 Mask           */
+
+#define BPWM_INTEN_CMPUIEN1_Pos          (17)                                              /*!< BPWM_T::INTEN: CMPUIEN1 Position       */
+#define BPWM_INTEN_CMPUIEN1_Msk          (0x1ul << BPWM_INTEN_CMPUIEN1_Pos)                /*!< BPWM_T::INTEN: CMPUIEN1 Mask           */
+
+#define BPWM_INTEN_CMPUIEN2_Pos          (18)                                              /*!< BPWM_T::INTEN: CMPUIEN2 Position       */
+#define BPWM_INTEN_CMPUIEN2_Msk          (0x1ul << BPWM_INTEN_CMPUIEN2_Pos)                /*!< BPWM_T::INTEN: CMPUIEN2 Mask           */
+
+#define BPWM_INTEN_CMPUIEN3_Pos          (19)                                              /*!< BPWM_T::INTEN: CMPUIEN3 Position       */
+#define BPWM_INTEN_CMPUIEN3_Msk          (0x1ul << BPWM_INTEN_CMPUIEN3_Pos)                /*!< BPWM_T::INTEN: CMPUIEN3 Mask           */
+
+#define BPWM_INTEN_CMPUIEN4_Pos          (20)                                              /*!< BPWM_T::INTEN: CMPUIEN4 Position       */
+#define BPWM_INTEN_CMPUIEN4_Msk          (0x1ul << BPWM_INTEN_CMPUIEN4_Pos)                /*!< BPWM_T::INTEN: CMPUIEN4 Mask           */
+
+#define BPWM_INTEN_CMPUIEN5_Pos          (21)                                              /*!< BPWM_T::INTEN: CMPUIEN5 Position       */
+#define BPWM_INTEN_CMPUIEN5_Msk          (0x1ul << BPWM_INTEN_CMPUIEN5_Pos)                /*!< BPWM_T::INTEN: CMPUIEN5 Mask           */
+
+#define BPWM_INTEN_CMPUIENn_Pos          (16)                                              /*!< BPWM_T::INTEN: CMPUIENn Position       */
+#define BPWM_INTEN_CMPUIENn_Msk          (0x3ful << BPWM_INTEN_CMPUIENn_Pos)               /*!< BPWM_T::INTEN: CMPUIENn Mask           */
+
+#define BPWM_INTEN_CMPDIEN0_Pos          (24)                                              /*!< BPWM_T::INTEN: CMPDIEN0 Position       */
+#define BPWM_INTEN_CMPDIEN0_Msk          (0x1ul << BPWM_INTEN_CMPDIEN0_Pos)                /*!< BPWM_T::INTEN: CMPDIEN0 Mask           */
+
+#define BPWM_INTEN_CMPDIEN1_Pos          (25)                                              /*!< BPWM_T::INTEN: CMPDIEN1 Position       */
+#define BPWM_INTEN_CMPDIEN1_Msk          (0x1ul << BPWM_INTEN_CMPDIEN1_Pos)                /*!< BPWM_T::INTEN: CMPDIEN1 Mask           */
+
+#define BPWM_INTEN_CMPDIEN2_Pos          (26)                                              /*!< BPWM_T::INTEN: CMPDIEN2 Position       */
+#define BPWM_INTEN_CMPDIEN2_Msk          (0x1ul << BPWM_INTEN_CMPDIEN2_Pos)                /*!< BPWM_T::INTEN: CMPDIEN2 Mask           */
+
+#define BPWM_INTEN_CMPDIEN3_Pos          (27)                                              /*!< BPWM_T::INTEN: CMPDIEN3 Position       */
+#define BPWM_INTEN_CMPDIEN3_Msk          (0x1ul << BPWM_INTEN_CMPDIEN3_Pos)                /*!< BPWM_T::INTEN: CMPDIEN3 Mask           */
+
+#define BPWM_INTEN_CMPDIEN4_Pos          (28)                                              /*!< BPWM_T::INTEN: CMPDIEN4 Position       */
+#define BPWM_INTEN_CMPDIEN4_Msk          (0x1ul << BPWM_INTEN_CMPDIEN4_Pos)                /*!< BPWM_T::INTEN: CMPDIEN4 Mask           */
+
+#define BPWM_INTEN_CMPDIEN5_Pos          (29)                                              /*!< BPWM_T::INTEN: CMPDIEN5 Position       */
+#define BPWM_INTEN_CMPDIEN5_Msk          (0x1ul << BPWM_INTEN_CMPDIEN5_Pos)                /*!< BPWM_T::INTEN: CMPDIEN5 Mask           */
+
+#define BPWM_INTEN_CMPDIENn_Pos          (24)                                              /*!< BPWM_T::INTEN: CMPDIENn Position       */
+#define BPWM_INTEN_CMPDIENn_Msk          (0x3ful << BPWM_INTEN_CMPDIENn_Pos)               /*!< BPWM_T::INTEN: CMPDIENn Mask           */
+
+#define BPWM_INTSTS_ZIF0_Pos             (0)                                               /*!< BPWM_T::INTSTS: ZIF0 Position          */
+#define BPWM_INTSTS_ZIF0_Msk             (0x1ul << BPWM_INTSTS_ZIF0_Pos)                   /*!< BPWM_T::INTSTS: ZIF0 Mask              */
+
+#define BPWM_INTSTS_PIF0_Pos             (8)                                               /*!< BPWM_T::INTSTS: PIF0 Position          */
+#define BPWM_INTSTS_PIF0_Msk             (0x1ul << BPWM_INTSTS_PIF0_Pos)                   /*!< BPWM_T::INTSTS: PIF0 Mask              */
+
+#define BPWM_INTSTS_CMPUIF0_Pos          (16)                                              /*!< BPWM_T::INTSTS: CMPUIF0 Position       */
+#define BPWM_INTSTS_CMPUIF0_Msk          (0x1ul << BPWM_INTSTS_CMPUIF0_Pos)                /*!< BPWM_T::INTSTS: CMPUIF0 Mask           */
+
+#define BPWM_INTSTS_CMPUIF1_Pos          (17)                                              /*!< BPWM_T::INTSTS: CMPUIF1 Position       */
+#define BPWM_INTSTS_CMPUIF1_Msk          (0x1ul << BPWM_INTSTS_CMPUIF1_Pos)                /*!< BPWM_T::INTSTS: CMPUIF1 Mask           */
+
+#define BPWM_INTSTS_CMPUIF2_Pos          (18)                                              /*!< BPWM_T::INTSTS: CMPUIF2 Position       */
+#define BPWM_INTSTS_CMPUIF2_Msk          (0x1ul << BPWM_INTSTS_CMPUIF2_Pos)                /*!< BPWM_T::INTSTS: CMPUIF2 Mask           */
+
+#define BPWM_INTSTS_CMPUIF3_Pos          (19)                                              /*!< BPWM_T::INTSTS: CMPUIF3 Position       */
+#define BPWM_INTSTS_CMPUIF3_Msk          (0x1ul << BPWM_INTSTS_CMPUIF3_Pos)                /*!< BPWM_T::INTSTS: CMPUIF3 Mask           */
+
+#define BPWM_INTSTS_CMPUIF4_Pos          (20)                                              /*!< BPWM_T::INTSTS: CMPUIF4 Position       */
+#define BPWM_INTSTS_CMPUIF4_Msk          (0x1ul << BPWM_INTSTS_CMPUIF4_Pos)                /*!< BPWM_T::INTSTS: CMPUIF4 Mask           */
+
+#define BPWM_INTSTS_CMPUIF5_Pos          (21)                                              /*!< BPWM_T::INTSTS: CMPUIF5 Position       */
+#define BPWM_INTSTS_CMPUIF5_Msk          (0x1ul << BPWM_INTSTS_CMPUIF5_Pos)                /*!< BPWM_T::INTSTS: CMPUIF5 Mask           */
+
+#define BPWM_INTSTS_CMPUIFn_Pos          (16)                                              /*!< BPWM_T::INTSTS: CMPUIFn Position       */
+#define BPWM_INTSTS_CMPUIFn_Msk          (0x3ful << BPWM_INTSTS_CMPUIFn_Pos)               /*!< BPWM_T::INTSTS: CMPUIFn Mask           */
+
+#define BPWM_INTSTS_CMPDIF0_Pos          (24)                                              /*!< BPWM_T::INTSTS: CMPDIF0 Position       */
+#define BPWM_INTSTS_CMPDIF0_Msk          (0x1ul << BPWM_INTSTS_CMPDIF0_Pos)                /*!< BPWM_T::INTSTS: CMPDIF0 Mask           */
+
+#define BPWM_INTSTS_CMPDIF1_Pos          (25)                                              /*!< BPWM_T::INTSTS: CMPDIF1 Position       */
+#define BPWM_INTSTS_CMPDIF1_Msk          (0x1ul << BPWM_INTSTS_CMPDIF1_Pos)                /*!< BPWM_T::INTSTS: CMPDIF1 Mask           */
+
+#define BPWM_INTSTS_CMPDIF2_Pos          (26)                                              /*!< BPWM_T::INTSTS: CMPDIF2 Position       */
+#define BPWM_INTSTS_CMPDIF2_Msk          (0x1ul << BPWM_INTSTS_CMPDIF2_Pos)                /*!< BPWM_T::INTSTS: CMPDIF2 Mask           */
+
+#define BPWM_INTSTS_CMPDIF3_Pos          (27)                                              /*!< BPWM_T::INTSTS: CMPDIF3 Position       */
+#define BPWM_INTSTS_CMPDIF3_Msk          (0x1ul << BPWM_INTSTS_CMPDIF3_Pos)                /*!< BPWM_T::INTSTS: CMPDIF3 Mask           */
+
+#define BPWM_INTSTS_CMPDIF4_Pos          (28)                                              /*!< BPWM_T::INTSTS: CMPDIF4 Position       */
+#define BPWM_INTSTS_CMPDIF4_Msk          (0x1ul << BPWM_INTSTS_CMPDIF4_Pos)                /*!< BPWM_T::INTSTS: CMPDIF4 Mask           */
+
+#define BPWM_INTSTS_CMPDIF5_Pos          (29)                                              /*!< BPWM_T::INTSTS: CMPDIF5 Position       */
+#define BPWM_INTSTS_CMPDIF5_Msk          (0x1ul << BPWM_INTSTS_CMPDIF5_Pos)                /*!< BPWM_T::INTSTS: CMPDIF5 Mask           */
+
+#define BPWM_INTSTS_CMPDIFn_Pos          (24)                                              /*!< BPWM_T::INTSTS: CMPDIFn Position       */
+#define BPWM_INTSTS_CMPDIFn_Msk          (0x3ful << BPWM_INTSTS_CMPDIFn_Pos)               /*!< BPWM_T::INTSTS: CMPDIFn Mask           */
+
+#define BPWM_EADCTS0_TRGSEL0_Pos         (0)                                               /*!< BPWM_T::EADCTS0: TRGSEL0 Position      */
+#define BPWM_EADCTS0_TRGSEL0_Msk         (0xful << BPWM_EADCTS0_TRGSEL0_Pos)               /*!< BPWM_T::EADCTS0: TRGSEL0 Mask          */
+
+#define BPWM_EADCTS0_TRGEN0_Pos          (7)                                               /*!< BPWM_T::EADCTS0: TRGEN0 Position       */
+#define BPWM_EADCTS0_TRGEN0_Msk          (0x1ul << BPWM_EADCTS0_TRGEN0_Pos)                /*!< BPWM_T::EADCTS0: TRGEN0 Mask           */
+
+#define BPWM_EADCTS0_TRGSEL1_Pos         (8)                                               /*!< BPWM_T::EADCTS0: TRGSEL1 Position      */
+#define BPWM_EADCTS0_TRGSEL1_Msk         (0xful << BPWM_EADCTS0_TRGSEL1_Pos)               /*!< BPWM_T::EADCTS0: TRGSEL1 Mask          */
+
+#define BPWM_EADCTS0_TRGEN1_Pos          (15)                                              /*!< BPWM_T::EADCTS0: TRGEN1 Position       */
+#define BPWM_EADCTS0_TRGEN1_Msk          (0x1ul << BPWM_EADCTS0_TRGEN1_Pos)                /*!< BPWM_T::EADCTS0: TRGEN1 Mask           */
+
+#define BPWM_EADCTS0_TRGSEL2_Pos         (16)                                              /*!< BPWM_T::EADCTS0: TRGSEL2 Position      */
+#define BPWM_EADCTS0_TRGSEL2_Msk         (0xful << BPWM_EADCTS0_TRGSEL2_Pos)               /*!< BPWM_T::EADCTS0: TRGSEL2 Mask          */
+
+#define BPWM_EADCTS0_TRGEN2_Pos          (23)                                              /*!< BPWM_T::EADCTS0: TRGEN2 Position       */
+#define BPWM_EADCTS0_TRGEN2_Msk          (0x1ul << BPWM_EADCTS0_TRGEN2_Pos)                /*!< BPWM_T::EADCTS0: TRGEN2 Mask           */
+
+#define BPWM_EADCTS0_TRGSEL3_Pos         (24)                                              /*!< BPWM_T::EADCTS0: TRGSEL3 Position      */
+#define BPWM_EADCTS0_TRGSEL3_Msk         (0xful << BPWM_EADCTS0_TRGSEL3_Pos)               /*!< BPWM_T::EADCTS0: TRGSEL3 Mask          */
+
+#define BPWM_EADCTS0_TRGEN3_Pos          (31)                                              /*!< BPWM_T::EADCTS0: TRGEN3 Position       */
+#define BPWM_EADCTS0_TRGEN3_Msk          (0x1ul << BPWM_EADCTS0_TRGEN3_Pos)                /*!< BPWM_T::EADCTS0: TRGEN3 Mask           */
+
+#define BPWM_EADCTS1_TRGSEL4_Pos         (0)                                               /*!< BPWM_T::EADCTS1: TRGSEL4 Position      */
+#define BPWM_EADCTS1_TRGSEL4_Msk         (0xful << BPWM_EADCTS1_TRGSEL4_Pos)               /*!< BPWM_T::EADCTS1: TRGSEL4 Mask          */
+
+#define BPWM_EADCTS1_TRGEN4_Pos          (7)                                               /*!< BPWM_T::EADCTS1: TRGEN4 Position       */
+#define BPWM_EADCTS1_TRGEN4_Msk          (0x1ul << BPWM_EADCTS1_TRGEN4_Pos)                /*!< BPWM_T::EADCTS1: TRGEN4 Mask           */
+
+#define BPWM_EADCTS1_TRGSEL5_Pos         (8)                                               /*!< BPWM_T::EADCTS1: TRGSEL5 Position      */
+#define BPWM_EADCTS1_TRGSEL5_Msk         (0xful << BPWM_EADCTS1_TRGSEL5_Pos)               /*!< BPWM_T::EADCTS1: TRGSEL5 Mask          */
+
+#define BPWM_EADCTS1_TRGEN5_Pos          (15)                                              /*!< BPWM_T::EADCTS1: TRGEN5 Position       */
+#define BPWM_EADCTS1_TRGEN5_Msk          (0x1ul << BPWM_EADCTS1_TRGEN5_Pos)                /*!< BPWM_T::EADCTS1: TRGEN5 Mask           */
+
+#define BPWM_SSCTL_SSEN0_Pos             (0)                                               /*!< BPWM_T::SSCTL: SSEN0 Position          */
+#define BPWM_SSCTL_SSEN0_Msk             (0x1ul << BPWM_SSCTL_SSEN0_Pos)                   /*!< BPWM_T::SSCTL: SSEN0 Mask              */
+
+#define BPWM_SSCTL_SSRC_Pos              (8)                                               /*!< BPWM_T::SSCTL: SSRC Position           */
+#define BPWM_SSCTL_SSRC_Msk              (0x3ul << BPWM_SSCTL_SSRC_Pos)                    /*!< BPWM_T::SSCTL: SSRC Mask               */
+
+#define BPWM_SSTRG_CNTSEN_Pos            (0)                                               /*!< BPWM_T::SSTRG: CNTSEN Position         */
+#define BPWM_SSTRG_CNTSEN_Msk            (0x1ul << BPWM_SSTRG_CNTSEN_Pos)                  /*!< BPWM_T::SSTRG: CNTSEN Mask             */
+
+#define BPWM_STATUS_CNTMAX0_Pos          (0)                                               /*!< BPWM_T::STATUS: CNTMAX0 Position       */
+#define BPWM_STATUS_CNTMAX0_Msk          (0x1ul << BPWM_STATUS_CNTMAX0_Pos)                /*!< BPWM_T::STATUS: CNTMAX0 Mask           */
+
+#define BPWM_STATUS_EADCTRG0_Pos         (16)                                              /*!< BPWM_T::STATUS: EADCTRG0 Position      */
+#define BPWM_STATUS_EADCTRG0_Msk         (0x1ul << BPWM_STATUS_EADCTRG0_Pos)               /*!< BPWM_T::STATUS: EADCTRG0 Mask          */
+
+#define BPWM_STATUS_EADCTRG1_Pos         (17)                                              /*!< BPWM_T::STATUS: EADCTRG1 Position      */
+#define BPWM_STATUS_EADCTRG1_Msk         (0x1ul << BPWM_STATUS_EADCTRG1_Pos)               /*!< BPWM_T::STATUS: EADCTRG1 Mask          */
+
+#define BPWM_STATUS_EADCTRG2_Pos         (18)                                              /*!< BPWM_T::STATUS: EADCTRG2 Position      */
+#define BPWM_STATUS_EADCTRG2_Msk         (0x1ul << BPWM_STATUS_EADCTRG2_Pos)               /*!< BPWM_T::STATUS: EADCTRG2 Mask          */
+
+#define BPWM_STATUS_EADCTRG3_Pos         (19)                                              /*!< BPWM_T::STATUS: EADCTRG3 Position      */
+#define BPWM_STATUS_EADCTRG3_Msk         (0x1ul << BPWM_STATUS_EADCTRG3_Pos)               /*!< BPWM_T::STATUS: EADCTRG3 Mask          */
+
+#define BPWM_STATUS_EADCTRG4_Pos         (20)                                              /*!< BPWM_T::STATUS: EADCTRG4 Position      */
+#define BPWM_STATUS_EADCTRG4_Msk         (0x1ul << BPWM_STATUS_EADCTRG4_Pos)               /*!< BPWM_T::STATUS: EADCTRG4 Mask          */
+
+#define BPWM_STATUS_EADCTRG5_Pos         (21)                                              /*!< BPWM_T::STATUS: EADCTRG5 Position      */
+#define BPWM_STATUS_EADCTRG5_Msk         (0x1ul << BPWM_STATUS_EADCTRG5_Pos)               /*!< BPWM_T::STATUS: EADCTRG5 Mask          */
+
+#define BPWM_STATUS_EADCTRGn_Pos         (16)                                              /*!< BPWM_T::STATUS: EADCTRGn Position       */
+#define BPWM_STATUS_EADCTRGn_Msk         (0x3ful << BPWM_STATUS_EADCTRGn_Pos)               /*!< BPWM_T::STATUS: EADCTRGn Mask           */
+
+#define BPWM_CAPINEN_CAPINEN0_Pos        (0)                                               /*!< BPWM_T::CAPINEN: CAPINEN0 Position     */
+#define BPWM_CAPINEN_CAPINEN0_Msk        (0x1ul << BPWM_CAPINEN_CAPINEN0_Pos)              /*!< BPWM_T::CAPINEN: CAPINEN0 Mask         */
+
+#define BPWM_CAPINEN_CAPINEN1_Pos        (1)                                               /*!< BPWM_T::CAPINEN: CAPINEN1 Position     */
+#define BPWM_CAPINEN_CAPINEN1_Msk        (0x1ul << BPWM_CAPINEN_CAPINEN1_Pos)              /*!< BPWM_T::CAPINEN: CAPINEN1 Mask         */
+
+#define BPWM_CAPINEN_CAPINEN2_Pos        (2)                                               /*!< BPWM_T::CAPINEN: CAPINEN2 Position     */
+#define BPWM_CAPINEN_CAPINEN2_Msk        (0x1ul << BPWM_CAPINEN_CAPINEN2_Pos)              /*!< BPWM_T::CAPINEN: CAPINEN2 Mask         */
+
+#define BPWM_CAPINEN_CAPINEN3_Pos        (3)                                               /*!< BPWM_T::CAPINEN: CAPINEN3 Position     */
+#define BPWM_CAPINEN_CAPINEN3_Msk        (0x1ul << BPWM_CAPINEN_CAPINEN3_Pos)              /*!< BPWM_T::CAPINEN: CAPINEN3 Mask         */
+
+#define BPWM_CAPINEN_CAPINEN4_Pos        (4)                                               /*!< BPWM_T::CAPINEN: CAPINEN4 Position     */
+#define BPWM_CAPINEN_CAPINEN4_Msk        (0x1ul << BPWM_CAPINEN_CAPINEN4_Pos)              /*!< BPWM_T::CAPINEN: CAPINEN4 Mask         */
+
+#define BPWM_CAPINEN_CAPINEN5_Pos        (5)                                               /*!< BPWM_T::CAPINEN: CAPINEN5 Position     */
+#define BPWM_CAPINEN_CAPINEN5_Msk        (0x1ul << BPWM_CAPINEN_CAPINEN5_Pos)              /*!< BPWM_T::CAPINEN: CAPINEN5 Mask         */
+
+#define BPWM_CAPINEN_CAPINENn_Pos        (0)                                               /*!< BPWM_T::CAPINEN: CAPINENn Position     */
+#define BPWM_CAPINEN_CAPINENn_Msk        (0x3ful << BPWM_CAPINEN_CAPINENn_Pos)             /*!< BPWM_T::CAPINEN: CAPINENn Mask         */
+
+#define BPWM_CAPCTL_CAPEN0_Pos           (0)                                               /*!< BPWM_T::CAPCTL: CAPEN0 Position        */
+#define BPWM_CAPCTL_CAPEN0_Msk           (0x1ul << BPWM_CAPCTL_CAPEN0_Pos)                 /*!< BPWM_T::CAPCTL: CAPEN0 Mask            */
+
+#define BPWM_CAPCTL_CAPEN1_Pos           (1)                                               /*!< BPWM_T::CAPCTL: CAPEN1 Position        */
+#define BPWM_CAPCTL_CAPEN1_Msk           (0x1ul << BPWM_CAPCTL_CAPEN1_Pos)                 /*!< BPWM_T::CAPCTL: CAPEN1 Mask            */
+
+#define BPWM_CAPCTL_CAPEN2_Pos           (2)                                               /*!< BPWM_T::CAPCTL: CAPEN2 Position        */
+#define BPWM_CAPCTL_CAPEN2_Msk           (0x1ul << BPWM_CAPCTL_CAPEN2_Pos)                 /*!< BPWM_T::CAPCTL: CAPEN2 Mask            */
+
+#define BPWM_CAPCTL_CAPEN3_Pos           (3)                                               /*!< BPWM_T::CAPCTL: CAPEN3 Position        */
+#define BPWM_CAPCTL_CAPEN3_Msk           (0x1ul << BPWM_CAPCTL_CAPEN3_Pos)                 /*!< BPWM_T::CAPCTL: CAPEN3 Mask            */
+
+#define BPWM_CAPCTL_CAPEN4_Pos           (4)                                               /*!< BPWM_T::CAPCTL: CAPEN4 Position        */
+#define BPWM_CAPCTL_CAPEN4_Msk           (0x1ul << BPWM_CAPCTL_CAPEN4_Pos)                 /*!< BPWM_T::CAPCTL: CAPEN4 Mask            */
+
+#define BPWM_CAPCTL_CAPEN5_Pos           (5)                                               /*!< BPWM_T::CAPCTL: CAPEN5 Position        */
+#define BPWM_CAPCTL_CAPEN5_Msk           (0x1ul << BPWM_CAPCTL_CAPEN5_Pos)                 /*!< BPWM_T::CAPCTL: CAPEN5 Mask            */
+
+#define BPWM_CAPCTL_CAPENn_Pos           (0)                                               /*!< BPWM_T::CAPCTL: CAPENn Position        */
+#define BPWM_CAPCTL_CAPENn_Msk           (0x3ful << BPWM_CAPCTL_CAPENn_Pos)                /*!< BPWM_T::CAPCTL: CAPENn Mask            */
+
+#define BPWM_CAPCTL_CAPINV0_Pos          (8)                                               /*!< BPWM_T::CAPCTL: CAPINV0 Position       */
+#define BPWM_CAPCTL_CAPINV0_Msk          (0x1ul << BPWM_CAPCTL_CAPINV0_Pos)                /*!< BPWM_T::CAPCTL: CAPINV0 Mask           */
+
+#define BPWM_CAPCTL_CAPINV1_Pos          (9)                                               /*!< BPWM_T::CAPCTL: CAPINV1 Position       */
+#define BPWM_CAPCTL_CAPINV1_Msk          (0x1ul << BPWM_CAPCTL_CAPINV1_Pos)                /*!< BPWM_T::CAPCTL: CAPINV1 Mask           */
+
+#define BPWM_CAPCTL_CAPINV2_Pos          (10)                                              /*!< BPWM_T::CAPCTL: CAPINV2 Position       */
+#define BPWM_CAPCTL_CAPINV2_Msk          (0x1ul << BPWM_CAPCTL_CAPINV2_Pos)                /*!< BPWM_T::CAPCTL: CAPINV2 Mask           */
+
+#define BPWM_CAPCTL_CAPINV3_Pos          (11)                                              /*!< BPWM_T::CAPCTL: CAPINV3 Position       */
+#define BPWM_CAPCTL_CAPINV3_Msk          (0x1ul << BPWM_CAPCTL_CAPINV3_Pos)                /*!< BPWM_T::CAPCTL: CAPINV3 Mask           */
+
+#define BPWM_CAPCTL_CAPINV4_Pos          (12)                                              /*!< BPWM_T::CAPCTL: CAPINV4 Position       */
+#define BPWM_CAPCTL_CAPINV4_Msk          (0x1ul << BPWM_CAPCTL_CAPINV4_Pos)                /*!< BPWM_T::CAPCTL: CAPINV4 Mask           */
+
+#define BPWM_CAPCTL_CAPINV5_Pos          (13)                                              /*!< BPWM_T::CAPCTL: CAPINV5 Position       */
+#define BPWM_CAPCTL_CAPINV5_Msk          (0x1ul << BPWM_CAPCTL_CAPINV5_Pos)                /*!< BPWM_T::CAPCTL: CAPINV5 Mask           */
+
+#define BPWM_CAPCTL_CAPINVn_Pos          (8)                                               /*!< BPWM_T::CAPCTL: CAPINVn Position       */
+#define BPWM_CAPCTL_CAPINVn_Msk          (0x3ful << BPWM_CAPCTL_CAPINVn_Pos)               /*!< BPWM_T::CAPCTL: CAPINVn Mask           */
+
+#define BPWM_CAPCTL_RCRLDEN0_Pos         (16)                                              /*!< BPWM_T::CAPCTL: RCRLDEN0 Position      */
+#define BPWM_CAPCTL_RCRLDEN0_Msk         (0x1ul << BPWM_CAPCTL_RCRLDEN0_Pos)               /*!< BPWM_T::CAPCTL: RCRLDEN0 Mask          */
+
+#define BPWM_CAPCTL_RCRLDEN1_Pos         (17)                                              /*!< BPWM_T::CAPCTL: RCRLDEN1 Position      */
+#define BPWM_CAPCTL_RCRLDEN1_Msk         (0x1ul << BPWM_CAPCTL_RCRLDEN1_Pos)               /*!< BPWM_T::CAPCTL: RCRLDEN1 Mask          */
+
+#define BPWM_CAPCTL_RCRLDEN2_Pos         (18)                                              /*!< BPWM_T::CAPCTL: RCRLDEN2 Position      */
+#define BPWM_CAPCTL_RCRLDEN2_Msk         (0x1ul << BPWM_CAPCTL_RCRLDEN2_Pos)               /*!< BPWM_T::CAPCTL: RCRLDEN2 Mask          */
+
+#define BPWM_CAPCTL_RCRLDEN3_Pos         (19)                                              /*!< BPWM_T::CAPCTL: RCRLDEN3 Position      */
+#define BPWM_CAPCTL_RCRLDEN3_Msk         (0x1ul << BPWM_CAPCTL_RCRLDEN3_Pos)               /*!< BPWM_T::CAPCTL: RCRLDEN3 Mask          */
+
+#define BPWM_CAPCTL_RCRLDEN4_Pos         (20)                                              /*!< BPWM_T::CAPCTL: RCRLDEN4 Position      */
+#define BPWM_CAPCTL_RCRLDEN4_Msk         (0x1ul << BPWM_CAPCTL_RCRLDEN4_Pos)               /*!< BPWM_T::CAPCTL: RCRLDEN4 Mask          */
+
+#define BPWM_CAPCTL_RCRLDEN5_Pos         (21)                                              /*!< BPWM_T::CAPCTL: RCRLDEN5 Position      */
+#define BPWM_CAPCTL_RCRLDEN5_Msk         (0x1ul << BPWM_CAPCTL_RCRLDEN5_Pos)               /*!< BPWM_T::CAPCTL: RCRLDEN5 Mask          */
+
+#define BPWM_CAPCTL_RCRLDENn_Pos         (16)                                              /*!< BPWM_T::CAPCTL: RCRLDENn Position      */
+#define BPWM_CAPCTL_RCRLDENn_Msk         (0x3ful << BPWM_CAPCTL_RCRLDENn_Pos)              /*!< BPWM_T::CAPCTL: RCRLDENn Mask          */
+
+#define BPWM_CAPCTL_FCRLDEN0_Pos         (24)                                              /*!< BPWM_T::CAPCTL: FCRLDEN0 Position      */
+#define BPWM_CAPCTL_FCRLDEN0_Msk         (0x1ul << BPWM_CAPCTL_FCRLDEN0_Pos)               /*!< BPWM_T::CAPCTL: FCRLDEN0 Mask          */
+
+#define BPWM_CAPCTL_FCRLDEN1_Pos         (25)                                              /*!< BPWM_T::CAPCTL: FCRLDEN1 Position      */
+#define BPWM_CAPCTL_FCRLDEN1_Msk         (0x1ul << BPWM_CAPCTL_FCRLDEN1_Pos)               /*!< BPWM_T::CAPCTL: FCRLDEN1 Mask          */
+
+#define BPWM_CAPCTL_FCRLDEN2_Pos         (26)                                              /*!< BPWM_T::CAPCTL: FCRLDEN2 Position      */
+#define BPWM_CAPCTL_FCRLDEN2_Msk         (0x1ul << BPWM_CAPCTL_FCRLDEN2_Pos)               /*!< BPWM_T::CAPCTL: FCRLDEN2 Mask          */
+
+#define BPWM_CAPCTL_FCRLDEN3_Pos         (27)                                              /*!< BPWM_T::CAPCTL: FCRLDEN3 Position      */
+#define BPWM_CAPCTL_FCRLDEN3_Msk         (0x1ul << BPWM_CAPCTL_FCRLDEN3_Pos)               /*!< BPWM_T::CAPCTL: FCRLDEN3 Mask          */
+
+#define BPWM_CAPCTL_FCRLDEN4_Pos         (28)                                              /*!< BPWM_T::CAPCTL: FCRLDEN4 Position      */
+#define BPWM_CAPCTL_FCRLDEN4_Msk         (0x1ul << BPWM_CAPCTL_FCRLDEN4_Pos)               /*!< BPWM_T::CAPCTL: FCRLDEN4 Mask          */
+
+#define BPWM_CAPCTL_FCRLDEN5_Pos         (29)                                              /*!< BPWM_T::CAPCTL: FCRLDEN5 Position      */
+#define BPWM_CAPCTL_FCRLDEN5_Msk         (0x1ul << BPWM_CAPCTL_FCRLDEN5_Pos)               /*!< BPWM_T::CAPCTL: FCRLDEN5 Mask          */
+
+#define BPWM_CAPCTL_FCRLDENn_Pos         (24)                                              /*!< BPWM_T::CAPCTL: FCRLDENn Position      */
+#define BPWM_CAPCTL_FCRLDENn_Msk         (0x3ful << BPWM_CAPCTL_FCRLDENn_Pos)              /*!< BPWM_T::CAPCTL: FCRLDENn Mask          */
+
+#define BPWM_CAPSTS_CRIFOV0_Pos          (0)                                               /*!< BPWM_T::CAPSTS: CRIFOV0 Position       */
+#define BPWM_CAPSTS_CRIFOV0_Msk          (0x1ul << BPWM_CAPSTS_CRIFOV0_Pos)                /*!< BPWM_T::CAPSTS: CRIFOV0 Mask           */
+
+#define BPWM_CAPSTS_CRIFOV1_Pos          (1)                                               /*!< BPWM_T::CAPSTS: CRIFOV1 Position       */
+#define BPWM_CAPSTS_CRIFOV1_Msk          (0x1ul << BPWM_CAPSTS_CRIFOV1_Pos)                /*!< BPWM_T::CAPSTS: CRIFOV1 Mask           */
+
+#define BPWM_CAPSTS_CRIFOV2_Pos          (2)                                               /*!< BPWM_T::CAPSTS: CRIFOV2 Position       */
+#define BPWM_CAPSTS_CRIFOV2_Msk          (0x1ul << BPWM_CAPSTS_CRIFOV2_Pos)                /*!< BPWM_T::CAPSTS: CRIFOV2 Mask           */
+
+#define BPWM_CAPSTS_CRIFOV3_Pos          (3)                                               /*!< BPWM_T::CAPSTS: CRIFOV3 Position       */
+#define BPWM_CAPSTS_CRIFOV3_Msk          (0x1ul << BPWM_CAPSTS_CRIFOV3_Pos)                /*!< BPWM_T::CAPSTS: CRIFOV3 Mask           */
+
+#define BPWM_CAPSTS_CRIFOV4_Pos          (4)                                               /*!< BPWM_T::CAPSTS: CRIFOV4 Position       */
+#define BPWM_CAPSTS_CRIFOV4_Msk          (0x1ul << BPWM_CAPSTS_CRIFOV4_Pos)                /*!< BPWM_T::CAPSTS: CRIFOV4 Mask           */
+
+#define BPWM_CAPSTS_CRIFOV5_Pos          (5)                                               /*!< BPWM_T::CAPSTS: CRIFOV5 Position       */
+#define BPWM_CAPSTS_CRIFOV5_Msk          (0x1ul << BPWM_CAPSTS_CRIFOV5_Pos)                /*!< BPWM_T::CAPSTS: CRIFOV5 Mask           */
+
+#define BPWM_CAPSTS_CRIFOVn_Pos          (0)                                               /*!< BPWM_T::CAPSTS: CRIFOVn Position       */
+#define BPWM_CAPSTS_CRIFOVn_Msk          (0x3ful << BPWM_CAPSTS_CRIFOVn_Pos)               /*!< BPWM_T::CAPSTS: CRIFOVn Mask           */
+
+#define BPWM_CAPSTS_CFIFOV0_Pos          (8)                                               /*!< BPWM_T::CAPSTS: CFIFOV0 Position       */
+#define BPWM_CAPSTS_CFIFOV0_Msk          (0x1ul << BPWM_CAPSTS_CFIFOV0_Pos)                /*!< BPWM_T::CAPSTS: CFIFOV0 Mask           */
+
+#define BPWM_CAPSTS_CFIFOV1_Pos          (9)                                               /*!< BPWM_T::CAPSTS: CFIFOV1 Position       */
+#define BPWM_CAPSTS_CFIFOV1_Msk          (0x1ul << BPWM_CAPSTS_CFIFOV1_Pos)                /*!< BPWM_T::CAPSTS: CFIFOV1 Mask           */
+
+#define BPWM_CAPSTS_CFIFOV2_Pos          (10)                                              /*!< BPWM_T::CAPSTS: CFIFOV2 Position       */
+#define BPWM_CAPSTS_CFIFOV2_Msk          (0x1ul << BPWM_CAPSTS_CFIFOV2_Pos)                /*!< BPWM_T::CAPSTS: CFIFOV2 Mask           */
+
+#define BPWM_CAPSTS_CFIFOV3_Pos          (11)                                              /*!< BPWM_T::CAPSTS: CFIFOV3 Position       */
+#define BPWM_CAPSTS_CFIFOV3_Msk          (0x1ul << BPWM_CAPSTS_CFIFOV3_Pos)                /*!< BPWM_T::CAPSTS: CFIFOV3 Mask           */
+
+#define BPWM_CAPSTS_CFIFOV4_Pos          (12)                                              /*!< BPWM_T::CAPSTS: CFIFOV4 Position       */
+#define BPWM_CAPSTS_CFIFOV4_Msk          (0x1ul << BPWM_CAPSTS_CFIFOV4_Pos)                /*!< BPWM_T::CAPSTS: CFIFOV4 Mask           */
+
+#define BPWM_CAPSTS_CFIFOV5_Pos          (13)                                              /*!< BPWM_T::CAPSTS: CFIFOV5 Position       */
+#define BPWM_CAPSTS_CFIFOV5_Msk          (0x1ul << BPWM_CAPSTS_CFIFOV5_Pos)                /*!< BPWM_T::CAPSTS: CFIFOV5 Mask           */
+
+#define BPWM_CAPSTS_CFIFOVn_Pos          (8)                                               /*!< BPWM_T::CAPSTS: CFIFOVn Position       */
+#define BPWM_CAPSTS_CFIFOVn_Msk          (0x3ful << BPWM_CAPSTS_CFIFOVn_Pos)               /*!< BPWM_T::CAPSTS: CFIFOVn Mask           */
+
+#define BPWM_RCAPDAT0_RCAPDAT_Pos        (0)                                               /*!< BPWM_T::RCAPDAT0: RCAPDAT Position     */
+#define BPWM_RCAPDAT0_RCAPDAT_Msk        (0xfffful << BPWM_RCAPDAT0_RCAPDAT_Pos)           /*!< BPWM_T::RCAPDAT0: RCAPDAT Mask         */
+
+#define BPWM_FCAPDAT0_FCAPDAT_Pos        (0)                                               /*!< BPWM_T::FCAPDAT0: FCAPDAT Position     */
+#define BPWM_FCAPDAT0_FCAPDAT_Msk        (0xfffful << BPWM_FCAPDAT0_FCAPDAT_Pos)           /*!< BPWM_T::FCAPDAT0: FCAPDAT Mask         */
+
+#define BPWM_RCAPDAT1_RCAPDAT_Pos        (0)                                               /*!< BPWM_T::RCAPDAT1: RCAPDAT Position     */
+#define BPWM_RCAPDAT1_RCAPDAT_Msk        (0xfffful << BPWM_RCAPDAT1_RCAPDAT_Pos)           /*!< BPWM_T::RCAPDAT1: RCAPDAT Mask         */
+
+#define BPWM_FCAPDAT1_FCAPDAT_Pos        (0)                                               /*!< BPWM_T::FCAPDAT1: FCAPDAT Position     */
+#define BPWM_FCAPDAT1_FCAPDAT_Msk        (0xfffful << BPWM_FCAPDAT1_FCAPDAT_Pos)           /*!< BPWM_T::FCAPDAT1: FCAPDAT Mask         */
+
+#define BPWM_RCAPDAT2_RCAPDAT_Pos        (0)                                               /*!< BPWM_T::RCAPDAT2: RCAPDAT Position     */
+#define BPWM_RCAPDAT2_RCAPDAT_Msk        (0xfffful << BPWM_RCAPDAT2_RCAPDAT_Pos)           /*!< BPWM_T::RCAPDAT2: RCAPDAT Mask         */
+
+#define BPWM_FCAPDAT2_FCAPDAT_Pos        (0)                                               /*!< BPWM_T::FCAPDAT2: FCAPDAT Position     */
+#define BPWM_FCAPDAT2_FCAPDAT_Msk        (0xfffful << BPWM_FCAPDAT2_FCAPDAT_Pos)           /*!< BPWM_T::FCAPDAT2: FCAPDAT Mask         */
+
+#define BPWM_RCAPDAT3_RCAPDAT_Pos        (0)                                               /*!< BPWM_T::RCAPDAT3: RCAPDAT Position     */
+#define BPWM_RCAPDAT3_RCAPDAT_Msk        (0xfffful << BPWM_RCAPDAT3_RCAPDAT_Pos)           /*!< BPWM_T::RCAPDAT3: RCAPDAT Mask         */
+
+#define BPWM_FCAPDAT3_FCAPDAT_Pos        (0)                                               /*!< BPWM_T::FCAPDAT3: FCAPDAT Position     */
+#define BPWM_FCAPDAT3_FCAPDAT_Msk        (0xfffful << BPWM_FCAPDAT3_FCAPDAT_Pos)           /*!< BPWM_T::FCAPDAT3: FCAPDAT Mask         */
+
+#define BPWM_RCAPDAT4_RCAPDAT_Pos        (0)                                               /*!< BPWM_T::RCAPDAT4: RCAPDAT Position     */
+#define BPWM_RCAPDAT4_RCAPDAT_Msk        (0xfffful << BPWM_RCAPDAT4_RCAPDAT_Pos)           /*!< BPWM_T::RCAPDAT4: RCAPDAT Mask         */
+
+#define BPWM_FCAPDAT4_FCAPDAT_Pos        (0)                                               /*!< BPWM_T::FCAPDAT4: FCAPDAT Position     */
+#define BPWM_FCAPDAT4_FCAPDAT_Msk        (0xfffful << BPWM_FCAPDAT4_FCAPDAT_Pos)           /*!< BPWM_T::FCAPDAT4: FCAPDAT Mask         */
+
+#define BPWM_RCAPDAT5_RCAPDAT_Pos        (0)                                               /*!< BPWM_T::RCAPDAT5: RCAPDAT Position     */
+#define BPWM_RCAPDAT5_RCAPDAT_Msk        (0xfffful << BPWM_RCAPDAT5_RCAPDAT_Pos)           /*!< BPWM_T::RCAPDAT5: RCAPDAT Mask         */
+
+#define BPWM_FCAPDAT5_FCAPDAT_Pos        (0)                                               /*!< BPWM_T::FCAPDAT5: FCAPDAT Position     */
+#define BPWM_FCAPDAT5_FCAPDAT_Msk        (0xfffful << BPWM_FCAPDAT5_FCAPDAT_Pos)           /*!< BPWM_T::FCAPDAT5: FCAPDAT Mask         */
+
+#define BPWM_CAPIEN_CAPRIENn_Pos         (0)                                               /*!< BPWM_T::CAPIEN: CAPRIENn Position      */
+#define BPWM_CAPIEN_CAPRIENn_Msk         (0x3ful << BPWM_CAPIEN_CAPRIENn_Pos)              /*!< BPWM_T::CAPIEN: CAPRIENn Mask          */
+
+#define BPWM_CAPIEN_CAPFIENn_Pos         (8)                                               /*!< BPWM_T::CAPIEN: CAPFIENn Position      */
+#define BPWM_CAPIEN_CAPFIENn_Msk         (0x3ful << BPWM_CAPIEN_CAPFIENn_Pos)              /*!< BPWM_T::CAPIEN: CAPFIENn Mask          */
+
+#define BPWM_CAPIF_CAPRIF0_Pos           (0)                                               /*!< BPWM_T::CAPIF: CAPRIF0 Position        */
+#define BPWM_CAPIF_CAPRIF0_Msk           (0x1ul << BPWM_CAPIF_CAPRIF0_Pos)                 /*!< BPWM_T::CAPIF: CAPRIF0 Mask            */
+
+#define BPWM_CAPIF_CAPRIF1_Pos           (1)                                               /*!< BPWM_T::CAPIF: CAPRIF1 Position        */
+#define BPWM_CAPIF_CAPRIF1_Msk           (0x1ul << BPWM_CAPIF_CAPRIF1_Pos)                 /*!< BPWM_T::CAPIF: CAPRIF1 Mask            */
+
+#define BPWM_CAPIF_CAPRIF2_Pos           (2)                                               /*!< BPWM_T::CAPIF: CAPRIF2 Position        */
+#define BPWM_CAPIF_CAPRIF2_Msk           (0x1ul << BPWM_CAPIF_CAPRIF2_Pos)                 /*!< BPWM_T::CAPIF: CAPRIF2 Mask            */
+
+#define BPWM_CAPIF_CAPRIF3_Pos           (3)                                               /*!< BPWM_T::CAPIF: CAPRIF3 Position        */
+#define BPWM_CAPIF_CAPRIF3_Msk           (0x1ul << BPWM_CAPIF_CAPRIF3_Pos)                 /*!< BPWM_T::CAPIF: CAPRIF3 Mask            */
+
+#define BPWM_CAPIF_CAPRIF4_Pos           (4)                                               /*!< BPWM_T::CAPIF: CAPRIF4 Position        */
+#define BPWM_CAPIF_CAPRIF4_Msk           (0x1ul << BPWM_CAPIF_CAPRIF4_Pos)                 /*!< BPWM_T::CAPIF: CAPRIF4 Mask            */
+
+#define BPWM_CAPIF_CAPRIF5_Pos           (5)                                               /*!< BPWM_T::CAPIF: CAPRIF5 Position        */
+#define BPWM_CAPIF_CAPRIF5_Msk           (0x1ul << BPWM_CAPIF_CAPRIF5_Pos)                 /*!< BPWM_T::CAPIF: CAPRIF5 Mask            */
+
+#define BPWM_CAPIF_CAPRIFn_Pos           (0)                                               /*!< BPWM_T::CAPIF: CAPRIFn Position        */
+#define BPWM_CAPIF_CAPRIFn_Msk           (0x3ful << BPWM_CAPIF_CAPRIFn_Pos)                /*!< BPWM_T::CAPIF: CAPRIFn Mask            */
+
+#define BPWM_CAPIF_CAPFIF0_Pos           (8)                                               /*!< BPWM_T::CAPIF: CAPFIF0 Position        */
+#define BPWM_CAPIF_CAPFIF0_Msk           (0x1ul << BPWM_CAPIF_CAPFIF0_Pos)                 /*!< BPWM_T::CAPIF: CAPFIF0 Mask            */
+
+#define BPWM_CAPIF_CAPFIF1_Pos           (9)                                               /*!< BPWM_T::CAPIF: CAPFIF1 Position        */
+#define BPWM_CAPIF_CAPFIF1_Msk           (0x1ul << BPWM_CAPIF_CAPFIF1_Pos)                 /*!< BPWM_T::CAPIF: CAPFIF1 Mask            */
+
+#define BPWM_CAPIF_CAPFIF2_Pos           (10)                                              /*!< BPWM_T::CAPIF: CAPFIF2 Position        */
+#define BPWM_CAPIF_CAPFIF2_Msk           (0x1ul << BPWM_CAPIF_CAPFIF2_Pos)                 /*!< BPWM_T::CAPIF: CAPFIF2 Mask            */
+
+#define BPWM_CAPIF_CAPFIF3_Pos           (11)                                              /*!< BPWM_T::CAPIF: CAPFIF3 Position        */
+#define BPWM_CAPIF_CAPFIF3_Msk           (0x1ul << BPWM_CAPIF_CAPFIF3_Pos)                 /*!< BPWM_T::CAPIF: CAPFIF3 Mask            */
+
+#define BPWM_CAPIF_CAPFIF4_Pos           (12)                                              /*!< BPWM_T::CAPIF: CAPFIF4 Position        */
+#define BPWM_CAPIF_CAPFIF4_Msk           (0x1ul << BPWM_CAPIF_CAPFIF4_Pos)                 /*!< BPWM_T::CAPIF: CAPFIF4 Mask            */
+
+#define BPWM_CAPIF_CAPFIF5_Pos           (13)                                              /*!< BPWM_T::CAPIF: CAPFIF5 Position        */
+#define BPWM_CAPIF_CAPFIF5_Msk           (0x1ul << BPWM_CAPIF_CAPFIF5_Pos)                 /*!< BPWM_T::CAPIF: CAPFIF5 Mask            */
+
+#define BPWM_CAPIF_CAPFIFn_Pos           (8)                                               /*!< BPWM_T::CAPIF: CAPFIFn Position        */
+#define BPWM_CAPIF_CAPFIFn_Msk           (0x3ful << BPWM_CAPIF_CAPFIFn_Pos)                /*!< BPWM_T::CAPIF: CAPFIFn Mask            */
+
+#define BPWM_PBUF_PBUF_Pos               (0)                                               /*!< BPWM_T::PBUF: PBUF Position            */
+#define BPWM_PBUF_PBUF_Msk               (0xfffful << BPWM_PBUF_PBUF_Pos)                  /*!< BPWM_T::PBUF: PBUF Mask                */
+
+#define BPWM_CMPBUF0_CMPBUF_Pos          (0)                                               /*!< BPWM_T::CMPBUF0: CMPBUF Position       */
+#define BPWM_CMPBUF0_CMPBUF_Msk          (0xfffful << BPWM_CMPBUF0_CMPBUF_Pos)             /*!< BPWM_T::CMPBUF0: CMPBUF Mask           */
+
+#define BPWM_CMPBUF1_CMPBUF_Pos          (0)                                               /*!< BPWM_T::CMPBUF1: CMPBUF Position       */
+#define BPWM_CMPBUF1_CMPBUF_Msk          (0xfffful << BPWM_CMPBUF1_CMPBUF_Pos)             /*!< BPWM_T::CMPBUF1: CMPBUF Mask           */
+
+#define BPWM_CMPBUF2_CMPBUF_Pos          (0)                                               /*!< BPWM_T::CMPBUF2: CMPBUF Position       */
+#define BPWM_CMPBUF2_CMPBUF_Msk          (0xfffful << BPWM_CMPBUF2_CMPBUF_Pos)             /*!< BPWM_T::CMPBUF2: CMPBUF Mask           */
+
+#define BPWM_CMPBUF3_CMPBUF_Pos          (0)                                               /*!< BPWM_T::CMPBUF3: CMPBUF Position       */
+#define BPWM_CMPBUF3_CMPBUF_Msk          (0xfffful << BPWM_CMPBUF3_CMPBUF_Pos)             /*!< BPWM_T::CMPBUF3: CMPBUF Mask           */
+
+#define BPWM_CMPBUF4_CMPBUF_Pos          (0)                                               /*!< BPWM_T::CMPBUF4: CMPBUF Position       */
+#define BPWM_CMPBUF4_CMPBUF_Msk          (0xfffful << BPWM_CMPBUF4_CMPBUF_Pos)             /*!< BPWM_T::CMPBUF4: CMPBUF Mask           */
+
+#define BPWM_CMPBUF5_CMPBUF_Pos          (0)                                               /*!< BPWM_T::CMPBUF5: CMPBUF Position       */
+#define BPWM_CMPBUF5_CMPBUF_Msk          (0xfffful << BPWM_CMPBUF5_CMPBUF_Pos)             /*!< BPWM_T::CMPBUF5: CMPBUF Mask           */
+
+/**@}*/ /* BPWM_CONST */
+/**@}*/ /* end of BPWM register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM   )
+#pragma no_anon_unions
+#endif
+
+#endif /* __BPWM_REG_H__ */

dap_link/lib/free-dap/platform/m484/include/can_reg.h

@@ -0,0 +1,759 @@
+/**************************************************************************//**
+ * @file     can_reg.h
+ * @version  V1.00
+ * @brief    CAN register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __CAN_REG_H__
+#define __CAN_REG_H__
+
+#if defined ( __CC_ARM   )
+#pragma anon_unions
+#endif
+
+/**
+   @addtogroup REGISTER Control Register
+   @{
+*/
+
+/**
+    @addtogroup CAN Controller Area Network Controller(CAN)
+    Memory Mapped Structure for CAN Controller
+@{ */
+
+
+typedef struct
+{
+
+    /**
+     * @var CAN_IF_T::CREQ
+     * Offset: 0x20, 0x80  IFn Command Request Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[5:0]   |MessageNumber|Message Number
+     * |        |          |0x01-0x20: Valid Message Number, the Message Object in the Message
+     * |        |          |RAM is selected for data transfer.
+     * |        |          |0x00: Not a valid Message Number, interpreted as 0x20.
+     * |        |          |0x21-0x3F: Not a valid Message Number, interpreted as 0x01-0x1F.
+     * |[15]    |Busy      |Busy Flag
+     * |        |          |0 = Read/write action has finished.
+     * |        |          |1 = Writing to the IFn Command Request Register is in progress
+     * |        |          |This bit can only be read by the software.
+     * @var CAN_IF_T::CMASK
+     * Offset: 0x24, 0x84  IFn Command Mask Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |DAT_B     |Access Data Bytes [7:4]
+     * |        |          |Write Operation:
+     * |        |          |0 = Data Bytes [7:4] unchanged.
+     * |        |          |1 = Transfer Data Bytes [7:4] to Message Object.
+     * |        |          |Read Operation:
+     * |        |          |0 = Data Bytes [7:4] unchanged.
+     * |        |          |1 = Transfer Data Bytes [7:4] to IFn Message Buffer Register.
+     * |[1]     |DAT_A     |Access Data Bytes [3:0]
+     * |        |          |Write Operation:
+     * |        |          |0 = Data Bytes [3:0] unchanged.
+     * |        |          |1 = Transfer Data Bytes [3:0] to Message Object.
+     * |        |          |Read Operation:
+     * |        |          |0 = Data Bytes [3:0] unchanged.
+     * |        |          |1 = Transfer Data Bytes [3:0] to IFn Message Buffer Register.
+     * |[2]     |TxRqst_NewDat|Access Transmission Request Bit When Write Operation
+     * |        |          |0 = TxRqst bit unchanged.
+     * |        |          |1 = Set TxRqst bit.
+     * |        |          |Note: If a transmission is requested by programming bit TxRqst/NewDat in the IFn Command Mask Register, bit TxRqst in the IFn Message Control Register will be ignored.
+     * |        |          |Access New Data Bit when Read Operation.
+     * |        |          |0 = NewDat bit remains unchanged.
+     * |        |          |1 = Clear NewDat bit in the Message Object.
+     * |        |          |Note: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat
+     * |        |          |The values of these bits transferred to the IFn Message Control Register always reflect the status before resetting these bits.
+     * |[3]     |ClrIntPnd |Clear Interrupt Pending Bit
+     * |        |          |Write Operation:
+     * |        |          |When writing to a Message Object, this bit is ignored.
+     * |        |          |Read Operation:
+     * |        |          |0 = IntPnd bit (CAN_IFn_MCON[13]) remains unchanged.
+     * |        |          |1 = Clear IntPnd bit in the Message Object.
+     * |[4]     |Control   |Control Access Control Bits
+     * |        |          |Write Operation:
+     * |        |          |0 = Control Bits unchanged.
+     * |        |          |1 = Transfer Control Bits to Message Object.
+     * |        |          |Read Operation:
+     * |        |          |0 = Control Bits unchanged.
+     * |        |          |1 = Transfer Control Bits to IFn Message Buffer Register.
+     * |[5]     |Arb       |Access Arbitration Bits
+     * |        |          |Write Operation:
+     * |        |          |0 = Arbitration bits unchanged.
+     * |        |          |1 = Transfer Identifier + Dir (CAN_IFn_ARB2[13]) + Xtd (CAN_IFn_ARB2[14]) + MsgVal (CAN_IFn_ARB2[15]) to Message Object.
+     * |        |          |Read Operation:
+     * |        |          |0 = Arbitration bits unchanged.
+     * |        |          |1 = Transfer Identifier + Dir + Xtd + MsgVal to IFn Message Buffer Register.
+     * |[6]     |Mask      |Access Mask Bits
+     * |        |          |Write Operation:
+     * |        |          |0 = Mask bits unchanged.
+     * |        |          |1 = Transfer Identifier Mask + MDir + MXtd to Message Object.
+     * |        |          |Read Operation:
+     * |        |          |0 = Mask bits unchanged.
+     * |        |          |1 = Transfer Identifier Mask + MDir + MXtd to IFn Message Buffer Register.
+     * |[7]     |WR_RD     |Write / Read Mode
+     * |        |          |0 = Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers.
+     * |        |          |1 = Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register.
+     * @var CAN_IF_T::MASK1
+     * Offset: 0x28, 0x88  IFn Mask 1 Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |Msk       |Identifier Mask 15-0
+     * |        |          |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering.
+     * |        |          |1 = The corresponding identifier bit is used for acceptance filtering.
+     * @var CAN_IF_T::MASK2
+     * Offset: 0x2C, 0x8C  IFn Mask 2 Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[12:0]  |Msk       |Identifier Mask 28-16
+     * |        |          |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering.
+     * |        |          |1 = The corresponding identifier bit is used for acceptance filtering.
+     * |[14]    |MDir      |Mask Message Direction
+     * |        |          |0 = The message direction bit (Dir (CAN_IFn_ARB2[13])) has no effect on the acceptance filtering.
+     * |        |          |1 = The message direction bit (Dir) is used for acceptance filtering.
+     * |[15]    |MXtd      |Mask Extended Identifier
+     * |        |          |0 = The extended identifier bit (IDE) has no effect on the acceptance filtering.
+     * |        |          |1 = The extended identifier bit (IDE) is used for acceptance filtering.
+     * |        |          |Note: When 11-bit (standard) Identifiers are used for a Message Object, the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2])
+     * |        |          |For acceptance filtering, only these bits together with mask bits Msk28 to Msk18 (CAN_IFn_MASK2[12:2]) are considered.
+     * @var CAN_IF_T::ARB1
+     * Offset: 0x30, 0x90  IFn Arbitration 1 Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |ID        |Message Identifier 15-0
+     * |        |          |ID28 - ID0, 29-bit Identifier (Extended Frame)
+     * |        |          |ID28 - ID18, 11-bit Identifier (Standard Frame)
+     * @var CAN_IF_T::ARB2
+     * Offset: 0x34, 0x94  IFn Arbitration 2 Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[12:0]  |ID        |Message Identifier 28-16
+     * |        |          |ID28 - ID0, 29-bit Identifier (Extended Frame)
+     * |        |          |ID28 - ID18, 11-bit Identifier (Standard Frame)
+     * |[13]    |Dir       |Message Direction
+     * |        |          |0 = Direction is receive.
+     * |        |          |On TxRqst, a Remote Frame with the identifier of this Message Object is transmitted
+     * |        |          |On reception of a Data Frame with matching identifier, that message is stored in this Message Object.
+     * |        |          |1 = Direction is transmit.
+     * |        |          |On TxRqst, the respective Message Object is transmitted as a Data Frame
+     * |        |          |On reception of a Remote Frame with matching identifier, the TxRqst bit (CAN_IFn_CMASK[2]) of this Message Object is set (if RmtEn (CAN_IFn_MCON[9]) = one).
+     * |[14]    |Xtd       |Extended Identifier
+     * |        |          |0 = The 11-bit (standard) Identifier will be used for this Message Object.
+     * |        |          |1 = The 29-bit (extended) Identifier will be used for this Message Object.
+     * |[15]    |MsgVal    |Message Valid
+     * |        |          |0 = The Message Object is ignored by the Message Handler.
+     * |        |          |1 = The Message Object is configured and should be considered by the Message Handler.
+     * |        |          |Note: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0])
+     * |        |          |This bit must also be reset before the identifier Id28-0 (CAN_IFn_ARB1/2), the control bits Xtd (CAN_IFn_ARB2[14]), Dir (CAN_IFn_ARB2[13]), or the Data Length Code DLC3-0 (CAN_IFn_MCON[3:0]) are modified, or if the Messages Object is no longer required.
+     * @var CAN_IF_T::MCON
+     * Offset: 0x38, 0x98  IFn Message Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |DLC       |Data Length Code
+     * |        |          |0-8: Data Frame has 0-8 data bytes.
+     * |        |          |9-15: Data Frame has 8 data bytes
+     * |        |          |Note: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes
+     * |        |          |When the Message Handler stores a data frame, it will write the DLC to the value given by the received message.
+     * |        |          |Data(0): 1st data byte of a CAN Data Frame
+     * |        |          |Data(1): 2nd data byte of a CAN Data Frame
+     * |        |          |Data(2): 3rd data byte of a CAN Data Frame
+     * |        |          |Data(3): 4th data byte of a CAN Data Frame
+     * |        |          |Data(4): 5th data byte of a CAN Data Frame
+     * |        |          |Data(5): 6th data byte of a CAN Data Frame
+     * |        |          |Data(6): 7th data byte of a CAN Data Frame
+     * |        |          |Data(7): 8th data byte of a CAN Data Frame
+     * |        |          |Note: The Data(0) byte is the first data byte shifted into the shift register of the CAN Core during a reception while the Data(7) byte is the last
+     * |        |          |When the Message Handler stores a Data Frame, it will write all the eight data bytes into a Message Object
+     * |        |          |If the Data Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by unspecified values.
+     * |[7]     |EoB       |End of Buffer
+     * |        |          |0 = Message Object belongs to a FIFO Buffer and is not the last Message Object of that FIFO Buffer.
+     * |        |          |1 = Single Message Object or last Message Object of a FIFO Buffer.
+     * |        |          |Note: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer
+     * |        |          |For single Message Objects (not belonging to a FIFO Buffer), this bit must always be set to one
+     * |[8]     |TxRqst    |Transmit Request
+     * |        |          |0 = This Message Object is not waiting for transmission.
+     * |        |          |1 = The transmission of this Message Object is requested and is not yet done.
+     * |[9]     |RmtEn     |Remote Enable Bit
+     * |        |          |0 = At the reception of a Remote Frame, TxRqst (CAN_IFn_MCON[8]) is left unchanged.
+     * |        |          |1 = At the reception of a Remote Frame, TxRqst is set.
+     * |[10]    |RxIE      |Receive Interrupt Enable Bit
+     * |        |          |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after a successful reception of a frame.
+     * |        |          |1 = IntPnd will be set after a successful reception of a frame.
+     * |[11]    |TxIE      |Transmit Interrupt Enable Bit
+     * |        |          |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after the successful transmission of a frame.
+     * |        |          |1 = IntPnd will be set after a successful transmission of a frame.
+     * |[12]    |UMask     |Use Acceptance Mask
+     * |        |          |0 = Mask ignored.
+     * |        |          |1 = Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering.
+     * |        |          |Note: If the UMask bit is set to one, the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_ARB2[15]) is set to one.
+     * |[13]    |IntPnd    |Interrupt Pending
+     * |        |          |0 = This message object is not the source of an interrupt.
+     * |        |          |1 = This message object is the source of an interrupt
+     * |        |          |The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority.
+     * |[14]    |MsgLst    |Message Lost (only valid for Message Objects with direction = receive).
+     * |        |          |0 = No message lost since last time this bit was reset by the CPU.
+     * |        |          |1 = The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message.
+     * |[15]    |NewDat    |New Data
+     * |        |          |0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the application software.
+     * |        |          |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
+     * @var CAN_IF_T::DAT_A1
+     * Offset: 0x3C, 0x9C  IFn Data A1 Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |Data_0_   |Data Byte 0
+     * |        |          |1st data byte of a CAN Data Frame
+     * |[15:8]  |Data_1_   |Data Byte 1
+     * |        |          |2nd data byte of a CAN Data Frame
+     * @var CAN_IF_T::DAT_A2
+     * Offset: 0x40, 0xA0  IFn Data A2 Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |Data_2_   |Data Byte 2
+     * |        |          |3rd data byte of CAN Data Frame
+     * |[15:8]  |Data_3_   |Data Byte 3
+     * |        |          |4th data byte of CAN Data Frame
+     * @var CAN_IF_T::DAT_B1
+     * Offset: 0x44, 0xA4  IFn Data B1 Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |Data_4_   |Data Byte 4
+     * |        |          |5th data byte of CAN Data Frame
+     * |[15:8]  |Data_5_   |Data Byte 5
+     * |        |          |6th data byte of CAN Data Frame
+     * @var CAN_IF_T::DAT_B2
+     * Offset: 0x48, 0xA8  IFn Data B2 Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |Data_6_   |Data Byte 6
+     * |        |          |7th data byte of CAN Data Frame.
+     * |[15:8]  |Data_7_   |Data Byte 7
+     * |        |          |8th data byte of CAN Data Frame.
+     */
+    __IO uint32_t CREQ;         /*!< [0x0020] IFn Command Request Register                                     */
+    __IO uint32_t CMASK;        /*!< [0x0024] IFn Command Mask Register                                        */
+    __IO uint32_t MASK1;        /*!< [0x0028] IFn Mask 1 Register                                              */
+    __IO uint32_t MASK2;        /*!< [0x002c] IFn Mask 2 Register                                              */
+    __IO uint32_t ARB1;         /*!< [0x0030] IFn Arbitration 1 Register                                       */
+    __IO uint32_t ARB2;         /*!< [0x0034] IFn Arbitration 2 Register                                       */
+    __IO uint32_t MCON;         /*!< [0x0038] IFn Message Control Register                                     */
+    __IO uint32_t DAT_A1;       /*!< [0x003c] IFn Data A1 Register                                             */
+    __IO uint32_t DAT_A2;       /*!< [0x0040] IFn Data A2 Register                                             */
+    __IO uint32_t DAT_B1;       /*!< [0x0044] IFn Data B1 Register                                             */
+    __IO uint32_t DAT_B2;       /*!< [0x0048] IFn Data B2 Register                                             */
+    /// @cond HIDDEN_SYMBOLS
+    __I uint32_t RESERVE0[13];
+    /// @endcond //HIDDEN_SYMBOLS
+} CAN_IF_T;
+
+
+typedef struct
+{
+
+
+    /**
+     * @var CAN_T::CON
+     * Offset: 0x00  Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |Init      |Init Initialization
+     * |        |          |0 = Normal Operation.
+     * |        |          |1 = Initialization is started.
+     * |[1]     |IE        |Module Interrupt Enable Bit
+     * |        |          |0 = Function interrupt is Disabled.
+     * |        |          |1 = Function interrupt is Enabled.
+     * |[2]     |SIE       |Status Change Interrupt Enable Bit
+     * |        |          |0 = Disabled - No Status Change Interrupt will be generated.
+     * |        |          |1 = Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected.
+     * |[3]     |EIE       |Error Interrupt Enable Bit
+     * |        |          |0 = Disabled - No Error Status Interrupt will be generated.
+     * |        |          |1 = Enabled - A change in the bits BOff (CAN_STATUS[7]) or EWarn (CAN_STATUS[6]) in the Status Register will generate an interrupt.
+     * |[5]     |DAR       |Automatic Re-transmission Disable Bit
+     * |        |          |0 = Automatic Retransmission of disturbed messages Enabled.
+     * |        |          |1 = Automatic Retransmission Disabled.
+     * |[6]     |CCE       |Configuration Change Enable Bit
+     * |        |          |0 = No write access to the Bit Timing Register.
+     * |        |          |1 = Write access to the Bit Timing Register (CAN_BTIME) allowed. (while Init bit (CAN_CON[0]) = 1).
+     * |[7]     |Test      |Test Mode Enable Bit
+     * |        |          |0 = Normal Operation.
+     * |        |          |1 = Test Mode.
+     * @var CAN_T::STATUS
+     * Offset: 0x04  Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |LEC       |Last Error Code (Type of the Last Error to Occur on the CAN Bus)
+     * |        |          |The LEC field holds a code, which indicates the type of the last error to occur on the CAN bus
+     * |        |          |This field will be cleared to '0' when a message has been transferred (reception or transmission) without error
+     * |        |          |The unused code '7' may be written by the CPU to check for updates
+     * |        |          |The Error! Reference source not found
+     * |        |          |describes the error code.
+     * |[3]     |TxOK      |Transmitted a Message Successfully
+     * |        |          |0 = Since this bit was reset by the CPU, no message has been successfully transmitted
+     * |        |          |This bit is never reset by the CAN Core.
+     * |        |          |1 = Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted.
+     * |[4]     |RxOK      |Received a Message Successfully
+     * |        |          |0 = No message has been successfully received since this bit was last reset by the CPU
+     * |        |          |This bit is never reset by the CAN Core.
+     * |        |          |1 = A message has been successfully received since this bit was last reset by the CPU (independent of the result of acceptance filtering).
+     * |[5]     |EPass     |Error Passive (Read Only)
+     * |        |          |0 = The CAN Core is error active.
+     * |        |          |1 = The CAN Core is in the error passive state as defined in the CAN Specification.
+     * |[6]     |EWarn     |Error Warning Status (Read Only)
+     * |        |          |0 = Both error counters are below the error warning limit of 96.
+     * |        |          |1 = At least one of the error counters in the EML has reached the error warning limit of 96.
+     * |[7]     |BOff      |Bus-off Status (Read Only)
+     * |        |          |0 = The CAN module is not in bus-off state.
+     * |        |          |1 = The CAN module is in bus-off state.
+     * @var CAN_T::ERR
+     * Offset: 0x08  Error Counter Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |TEC       |Transmit Error Counter
+     * |        |          |Actual state of the Transmit Error Counter. Values between 0 and 255.
+     * |[14:8]  |REC       |Receive Error Counter
+     * |        |          |Actual state of the Receive Error Counter. Values between 0 and 127.
+     * |[15]    |RP        |Receive Error Passive
+     * |        |          |0 = The Receive Error Counter is below the error passive level.
+     * |        |          |1 = The Receive Error Counter has reached the error passive level as defined in the CAN Specification.
+     * @var CAN_T::BTIME
+     * Offset: 0x0C  Bit Timing Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[5:0]   |BRP       |Baud Rate Prescaler
+     * |        |          |0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta
+     * |        |          |The bit time is built up from a multiple of this quanta
+     * |        |          |Valid values for the Baud Rate Prescaler are [0...63]
+     * |        |          |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
+     * |[7:6]   |SJW       |(Re)Synchronization Jump Width
+     * |        |          |0x0-0x3: Valid programmed values are [0...3]
+     * |        |          |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
+     * |[11:8]  |TSeg1     |Time Segment Before the Sample Point Minus Sync_Seg
+     * |        |          |0x01-0x0F: valid values for TSeg1 are [1...15]
+     * |        |          |The actual interpretation by the hardware of this value is such that one more than the value programmed is used.
+     * |[14:12] |TSeg2     |Time Segment After Sample Point
+     * |        |          |0x0-0x7: Valid values for TSeg2 are [0...7]
+     * |        |          |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
+     * @var CAN_T::IIDR
+     * Offset: 0x10  Interrupt Identifier Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |IntId     |Interrupt Identifier (Indicates the Source of the Interrupt)
+     * |        |          |If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order
+     * |        |          |An interrupt remains pending until the application software has cleared it
+     * |        |          |If IntId is different from 0x0000 and IE (CAN_CON[1]) is set, the IRQ interrupt signal to the EIC is active
+     * |        |          |The interrupt remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset.
+     * |        |          |The Status Interrupt has the highest priority
+     * |        |          |Among the message interrupts, the Message Object' s interrupt priority decreases with increasing message number.
+     * |        |          |A message interrupt is cleared by clearing the Message Object's IntPnd bit (CAN_IFn_MCON[13])
+     * |        |          |The Status Interrupt is cleared by reading the Status Register.
+     * @var CAN_T::TEST
+     * Offset: 0x14  Test Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2]     |Basic     |Basic Mode
+     * |        |          |0 = Basic Mode Disabled.
+     * |        |          |1= IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer.
+     * |[3]     |Silent    |Silent Mode
+     * |        |          |0 = Normal operation.
+     * |        |          |1 = The module is in Silent Mode.
+     * |[4]     |LBack     |Loop Back Mode Enable Bit
+     * |        |          |0 = Loop Back Mode is Disabled.
+     * |        |          |1 = Loop Back Mode is Enabled.
+     * |[6:5]   |Tx        |Tx[1:0]: Control of CAN_TX Pin
+     * |        |          |00 = Reset value, CAN_TX pin is controlled by the CAN Core.
+     * |        |          |01 = Sample Point can be monitored at CAN_TX pin.
+     * |        |          |10 = CAN_TX pin drives a dominant ('0') value.
+     * |        |          |11 = CAN_TX pin drives a recessive ('1') value.
+     * |[7]     |Rx        |Monitors the Actual Value of CAN_RX Pin (Read Only) *(1)
+     * |        |          |0 = The CAN bus is dominant (CAN_RX = '0').
+     * |        |          |1 = The CAN bus is recessive (CAN_RX = '1').
+     * @var CAN_T::BRPE
+     * Offset: 0x18  Baud Rate Prescaler Extension Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |BRPE      |BRPE: Baud Rate Prescaler Extension
+     * |        |          |0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to 1023
+     * |        |          |The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BTIME (LSBs) is used.
+     * @var CAN_T::TXREQ1
+     * Offset: 0x100  Transmission Request Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |TxRqst16_1|Transmission Request Bits 16-1 (of All Message Objects)
+     * |        |          |0 = This Message Object is not waiting for transmission.
+     * |        |          |1 = The transmission of this Message Object is requested and is not yet done.
+     * |        |          |These bits are read only.
+     * @var CAN_T::TXREQ2
+     * Offset: 0x104  Transmission Request Register 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |TxRqst32_17|Transmission Request Bits 32-17 (of All Message Objects)
+     * |        |          |0 = This Message Object is not waiting for transmission.
+     * |        |          |1 = The transmission of this Message Object is requested and is not yet done.
+     * |        |          |These bits are read only.
+     * @var CAN_T::NDAT1
+     * Offset: 0x120  New Data Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |NewData16_1|New Data Bits 16-1 (of All Message Objects)
+     * |        |          |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software.
+     * |        |          |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
+     * @var CAN_T::NDAT2
+     * Offset: 0x124  New Data Register 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |NewData32_17|New Data Bits 32-17 (of All Message Objects)
+     * |        |          |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software.
+     * |        |          |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
+     * @var CAN_T::IPND1
+     * Offset: 0x140  Interrupt Pending Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |IntPnd16_1|Interrupt Pending Bits 16-1 (of All Message Objects)
+     * |        |          |0 = This message object is not the source of an interrupt.
+     * |        |          |1 = This message object is the source of an interrupt.
+     * @var CAN_T::IPND2
+     * Offset: 0x144  Interrupt Pending Register 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |IntPnd32_17|Interrupt Pending Bits 32-17 (of All Message Objects)
+     * |        |          |0 = This message object is not the source of an interrupt.
+     * |        |          |1 = This message object is the source of an interrupt.
+     * @var CAN_T::MVLD1
+     * Offset: 0x160  Message Valid Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |MsgVal16_1|Message Valid Bits 16-1 (of All Message Objects) (Read Only)
+     * |        |          |0 = This Message Object is ignored by the Message Handler.
+     * |        |          |1 = This Message Object is configured and should be considered by the Message Handler.
+     * |        |          |Ex
+     * |        |          |CAN_MVLD1[0] means Message object No.1 is valid or not
+     * |        |          |If CAN_MVLD1[0] is set, message object No.1 is configured.
+     * @var CAN_T::MVLD2
+     * Offset: 0x164  Message Valid Register 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |MsgVal32_17|Message Valid Bits 32-17 (of All Message Objects) (Read Only)
+     * |        |          |0 = This Message Object is ignored by the Message Handler.
+     * |        |          |1 = This Message Object is configured and should be considered by the Message Handler.
+     * |        |          |Ex.CAN_MVLD2[15] means Message object No.32 is valid or not
+     * |        |          |If CAN_MVLD2[15] is set, message object No.32 is configured.
+     * @var CAN_T::WU_EN
+     * Offset: 0x168  Wake-up Enable Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WAKUP_EN  |Wake-up Enable Bit
+     * |        |          |0 = The wake-up function Disabled.
+     * |        |          |1 = The wake-up function Enabled.
+     * |        |          |Note: User can wake-up system when there is a falling edge in the CAN_Rx pin.
+     * @var CAN_T::WU_STATUS
+     * Offset: 0x16C  Wake-up Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WAKUP_STS |Wake-up Status
+     * |        |          |0 = No wake-up event occurred.
+     * |        |          |1 = Wake-up event occurred.
+     * |        |          |Note: This bit can be cleared by writing '0'.
+     */
+    __IO uint32_t CON;                   /*!< [0x0000] Control Register                                                 */
+    __IO uint32_t STATUS;                /*!< [0x0004] Status Register                                                  */
+    __I  uint32_t ERR;                   /*!< [0x0008] Error Counter Register                                           */
+    __IO uint32_t BTIME;                 /*!< [0x000c] Bit Timing Register                                              */
+    __I  uint32_t IIDR;                  /*!< [0x0010] Interrupt Identifier Register                                    */
+    __IO uint32_t TEST;                  /*!< [0x0014] Test Register                                                    */
+    __IO uint32_t BRPE;                  /*!< [0x0018] Baud Rate Prescaler Extension Register                           */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE0[1];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO CAN_IF_T IF[2];
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE2[8];
+    /// @endcond //HIDDEN_SYMBOLS
+    __I  uint32_t TXREQ1;                /*!< [0x0100] Transmission Request Register 1                                  */
+    __I  uint32_t TXREQ2;                /*!< [0x0104] Transmission Request Register 2                                  */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE3[6];
+    /// @endcond //HIDDEN_SYMBOLS
+    __I  uint32_t NDAT1;                 /*!< [0x0120] New Data Register 1                                              */
+    __I  uint32_t NDAT2;                 /*!< [0x0124] New Data Register 2                                              */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE4[6];
+    /// @endcond //HIDDEN_SYMBOLS
+    __I  uint32_t IPND1;                 /*!< [0x0140] Interrupt Pending Register 1                                     */
+    __I  uint32_t IPND2;                 /*!< [0x0144] Interrupt Pending Register 2                                     */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE5[6];
+    /// @endcond //HIDDEN_SYMBOLS
+    __I  uint32_t MVLD1;                 /*!< [0x0160] Message Valid Register 1                                         */
+    __I  uint32_t MVLD2;                 /*!< [0x0164] Message Valid Register 2                                         */
+    __IO uint32_t WU_EN;                 /*!< [0x0168] Wake-up Enable Control Register                                  */
+    __IO uint32_t WU_STATUS;             /*!< [0x016c] Wake-up Status Register                                          */
+
+} CAN_T;
+
+/**
+    @addtogroup CAN_CONST CAN Bit Field Definition
+    Constant Definitions for CAN Controller
+@{ */
+
+#define CAN_CON_INIT_Pos                 (0)                                               /*!< CAN_T::CON: Init Position              */
+#define CAN_CON_INIT_Msk                 (0x1ul << CAN_CON_INIT_Pos)                       /*!< CAN_T::CON: Init Mask                  */
+
+#define CAN_CON_IE_Pos                   (1)                                               /*!< CAN_T::CON: IE Position                */
+#define CAN_CON_IE_Msk                   (0x1ul << CAN_CON_IE_Pos)                         /*!< CAN_T::CON: IE Mask                    */
+
+#define CAN_CON_SIE_Pos                  (2)                                               /*!< CAN_T::CON: SIE Position               */
+#define CAN_CON_SIE_Msk                  (0x1ul << CAN_CON_SIE_Pos)                        /*!< CAN_T::CON: SIE Mask                   */
+
+#define CAN_CON_EIE_Pos                  (3)                                               /*!< CAN_T::CON: EIE Position               */
+#define CAN_CON_EIE_Msk                  (0x1ul << CAN_CON_EIE_Pos)                        /*!< CAN_T::CON: EIE Mask                   */
+
+#define CAN_CON_DAR_Pos                  (5)                                               /*!< CAN_T::CON: DAR Position               */
+#define CAN_CON_DAR_Msk                  (0x1ul << CAN_CON_DAR_Pos)                        /*!< CAN_T::CON: DAR Mask                   */
+
+#define CAN_CON_CCE_Pos                  (6)                                               /*!< CAN_T::CON: CCE Position               */
+#define CAN_CON_CCE_Msk                  (0x1ul << CAN_CON_CCE_Pos)                        /*!< CAN_T::CON: CCE Mask                   */
+
+#define CAN_CON_TEST_Pos                 (7)                                               /*!< CAN_T::CON: Test Position              */
+#define CAN_CON_TEST_Msk                 (0x1ul << CAN_CON_TEST_Pos)                       /*!< CAN_T::CON: Test Mask                  */
+
+#define CAN_STATUS_LEC_Pos               (0)                                               /*!< CAN_T::STATUS: LEC Position            */
+#define CAN_STATUS_LEC_Msk               (0x7ul << CAN_STATUS_LEC_Pos)                     /*!< CAN_T::STATUS: LEC Mask                */
+
+#define CAN_STATUS_TXOK_Pos              (3)                                               /*!< CAN_T::STATUS: TxOK Position           */
+#define CAN_STATUS_TXOK_Msk              (0x1ul << CAN_STATUS_TXOK_Pos)                    /*!< CAN_T::STATUS: TxOK Mask               */
+
+#define CAN_STATUS_RXOK_Pos              (4)                                               /*!< CAN_T::STATUS: RxOK Position           */
+#define CAN_STATUS_RXOK_Msk              (0x1ul << CAN_STATUS_RXOK_Pos)                    /*!< CAN_T::STATUS: RxOK Mask               */
+
+#define CAN_STATUS_EPASS_Pos             (5)                                               /*!< CAN_T::STATUS: EPass Position          */
+#define CAN_STATUS_EPASS_Msk             (0x1ul << CAN_STATUS_EPASS_Pos)                   /*!< CAN_T::STATUS: EPass Mask              */
+
+#define CAN_STATUS_EWARN_Pos             (6)                                               /*!< CAN_T::STATUS: EWarn Position          */
+#define CAN_STATUS_EWARN_Msk             (0x1ul << CAN_STATUS_EWARN_Pos)                   /*!< CAN_T::STATUS: EWarn Mask              */
+
+#define CAN_STATUS_BOFF_Pos              (7)                                               /*!< CAN_T::STATUS: BOff Position           */
+#define CAN_STATUS_BOFF_Msk              (0x1ul << CAN_STATUS_BOFF_Pos)                    /*!< CAN_T::STATUS: BOff Mask               */
+
+#define CAN_ERR_TEC_Pos                  (0)                                               /*!< CAN_T::ERR: TEC Position               */
+#define CAN_ERR_TEC_Msk                  (0xfful << CAN_ERR_TEC_Pos)                       /*!< CAN_T::ERR: TEC Mask                   */
+
+#define CAN_ERR_REC_Pos                  (8)                                               /*!< CAN_T::ERR: REC Position               */
+#define CAN_ERR_REC_Msk                  (0x7ful << CAN_ERR_REC_Pos)                       /*!< CAN_T::ERR: REC Mask                   */
+
+#define CAN_ERR_RP_Pos                   (15)                                              /*!< CAN_T::ERR: RP Position                */
+#define CAN_ERR_RP_Msk                   (0x1ul << CAN_ERR_RP_Pos)                         /*!< CAN_T::ERR: RP Mask                    */
+
+#define CAN_BTIME_BRP_Pos                (0)                                               /*!< CAN_T::BTIME: BRP Position             */
+#define CAN_BTIME_BRP_Msk                (0x3ful << CAN_BTIME_BRP_Pos)                     /*!< CAN_T::BTIME: BRP Mask                 */
+
+#define CAN_BTIME_SJW_Pos                (6)                                               /*!< CAN_T::BTIME: SJW Position             */
+#define CAN_BTIME_SJW_Msk                (0x3ul << CAN_BTIME_SJW_Pos)                      /*!< CAN_T::BTIME: SJW Mask                 */
+
+#define CAN_BTIME_TSEG1_Pos              (8)                                               /*!< CAN_T::BTIME: TSeg1 Position           */
+#define CAN_BTIME_TSEG1_Msk              (0xful << CAN_BTIME_TSEG1_Pos)                    /*!< CAN_T::BTIME: TSeg1 Mask               */
+
+#define CAN_BTIME_TSEG2_Pos              (12)                                              /*!< CAN_T::BTIME: TSeg2 Position           */
+#define CAN_BTIME_TSEG2_Msk              (0x7ul << CAN_BTIME_TSEG2_Pos)                    /*!< CAN_T::BTIME: TSeg2 Mask               */
+
+#define CAN_IIDR_IntId_Pos               (0)                                               /*!< CAN_T::IIDR: IntId Position            */
+#define CAN_IIDR_IntId_Msk               (0xfffful << CAN_IIDR_IntId_Pos)                  /*!< CAN_T::IIDR: IntId Mask                */
+
+#define CAN_TEST_BASIC_Pos               (2)                                               /*!< CAN_T::TEST: Basic Position            */
+#define CAN_TEST_BASIC_Msk               (0x1ul << CAN_TEST_BASIC_Pos)                     /*!< CAN_T::TEST: Basic Mask                */
+
+#define CAN_TEST_SILENT_Pos              (3)                                               /*!< CAN_T::TEST: Silent Position           */
+#define CAN_TEST_SILENT_Msk              (0x1ul << CAN_TEST_SILENT_Pos)                    /*!< CAN_T::TEST: Silent Mask               */
+
+#define CAN_TEST_LBACK_Pos               (4)                                               /*!< CAN_T::TEST: LBack Position            */
+#define CAN_TEST_LBACK_Msk               (0x1ul << CAN_TEST_LBACK_Pos)                     /*!< CAN_T::TEST: LBack Mask                */
+
+#define CAN_TEST_Tx_Pos                  (5)                                               /*!< CAN_T::TEST: Tx Position               */
+#define CAN_TEST_Tx_Msk                  (0x3ul << CAN_TEST_Tx_Pos)                        /*!< CAN_T::TEST: Tx Mask                   */
+
+#define CAN_TEST_Rx_Pos                  (7)                                               /*!< CAN_T::TEST: Rx Position               */
+#define CAN_TEST_Rx_Msk                  (0x1ul << CAN_TEST_Rx_Pos)                        /*!< CAN_T::TEST: Rx Mask                   */
+
+#define CAN_BRPE_BRPE_Pos                (0)                                               /*!< CAN_T::BRPE: BRPE Position             */
+#define CAN_BRPE_BRPE_Msk                (0xful << CAN_BRPE_BRPE_Pos)                      /*!< CAN_T::BRPE: BRPE Mask                 */
+
+#define CAN_IF_CREQ_MSGNUM_Pos   (0)                                               /*!< CAN_IF_T::CREQ: MessageNumber Position*/
+#define CAN_IF_CREQ_MSGNUM_Msk   (0x3ful << CAN_IF_CREQ_MSGNUM_Pos)        /*!< CAN_IF_T::CREQ: MessageNumber Mask    */
+
+#define CAN_IF_CREQ_BUSY_Pos            (15)                                              /*!< CAN_IF_T::CREQ: Busy Position         */
+#define CAN_IF_CREQ_BUSY_Msk            (0x1ul << CAN_IF_CREQ_BUSY_Pos)                   /*!< CAN_IF_T::CREQ: Busy Mask             */
+
+#define CAN_IF_CMASK_DATAB_Pos          (0)                                               /*!< CAN_IF_T::CMASK: DAT_B Position       */
+#define CAN_IF_CMASK_DATAB_Msk          (0x1ul << CAN_IF_CMASK_DATAB_Pos)                /*!< CAN_IF_T::CMASK: DAT_B Mask           */
+
+#define CAN_IF_CMASK_DATAA_Pos          (1)                                               /*!< CAN_IF_T::CMASK: DAT_A Position       */
+#define CAN_IF_CMASK_DATAA_Msk          (0x1ul << CAN_IF_CMASK_DATAA_Pos)                /*!< CAN_IF_T::CMASK: DAT_A Mask           */
+
+#define CAN_IF_CMASK_TXRQSTNEWDAT_Pos  (2)                                               /*!< CAN_IF_T::CMASK: TxRqst_NewDat Position*/
+#define CAN_IF_CMASK_TXRQSTNEWDAT_Msk  (0x1ul << CAN_IF_CMASK_TXRQSTNEWDAT_Pos)        /*!< CAN_IF_T::CMASK: TxRqst_NewDat Mask   */
+
+#define CAN_IF_CMASK_CLRINTPND_Pos      (3)                                               /*!< CAN_IF_T::CMASK: ClrIntPnd Position   */
+#define CAN_IF_CMASK_CLRINTPND_Msk      (0x1ul << CAN_IF_CMASK_CLRINTPND_Pos)            /*!< CAN_IF_T::CMASK: ClrIntPnd Mask       */
+
+#define CAN_IF_CMASK_CONTROL_Pos        (4)                                               /*!< CAN_IF_T::CMASK: Control Position     */
+#define CAN_IF_CMASK_CONTROL_Msk        (0x1ul << CAN_IF_CMASK_CONTROL_Pos)              /*!< CAN_IF_T::CMASK: Control Mask         */
+
+#define CAN_IF_CMASK_ARB_Pos            (5)                                               /*!< CAN_IF_T::CMASK: Arb Position         */
+#define CAN_IF_CMASK_ARB_Msk            (0x1ul << CAN_IF_CMASK_ARB_Pos)                  /*!< CAN_IF_T::CMASK: Arb Mask             */
+
+#define CAN_IF_CMASK_MASK_Pos           (6)                                               /*!< CAN_IF_T::CMASK: Mask Position        */
+#define CAN_IF_CMASK_MASK_Msk           (0x1ul << CAN_IF_CMASK_MASK_Pos)                 /*!< CAN_IF_T::CMASK: Mask Mask            */
+
+#define CAN_IF_CMASK_WRRD_Pos          (7)                                               /*!< CAN_IF_T::CMASK: WR_RD Position       */
+#define CAN_IF_CMASK_WRRD_Msk          (0x1ul << CAN_IF_CMASK_WRRD_Pos)                /*!< CAN_IF_T::CMASK: WR_RD Mask           */
+
+#define CAN_IF_MASK1_Msk_Pos            (0)                                               /*!< CAN_IF_T::MASK1: Msk Position         */
+#define CAN_IF_MASK1_Msk_Msk            (0xfffful << CAN_IF_MASK1_Msk_Pos)               /*!< CAN_IF_T::MASK1: Msk Mask             */
+
+#define CAN_IF_MASK2_Msk_Pos            (0)                                               /*!< CAN_IF_T::MASK2: Msk Position         */
+#define CAN_IF_MASK2_Msk_Msk            (0x1ffful << CAN_IF_MASK2_Msk_Pos)               /*!< CAN_IF_T::MASK2: Msk Mask             */
+
+#define CAN_IF_MASK2_MDIR_Pos           (14)                                              /*!< CAN_IF_T::MASK2: MDir Position        */
+#define CAN_IF_MASK2_MDIR_Msk           (0x1ul << CAN_IF_MASK2_MDIR_Pos)                 /*!< CAN_IF_T::MASK2: MDir Mask            */
+
+#define CAN_IF_MASK2_MXTD_Pos           (15)                                              /*!< CAN_IF_T::MASK2: MXtd Position        */
+#define CAN_IF_MASK2_MXTD_Msk           (0x1ul << CAN_IF_MASK2_MXTD_Pos)                 /*!< CAN_IF_T::MASK2: MXtd Mask            */
+
+#define CAN_IF_ARB1_ID_Pos              (0)                                               /*!< CAN_IF_T::ARB1: ID Position           */
+#define CAN_IF_ARB1_ID_Msk              (0xfffful << CAN_IF_ARB1_ID_Pos)                 /*!< CAN_IF_T::ARB1: ID Mask               */
+
+#define CAN_IF_ARB2_ID_Pos              (0)                                               /*!< CAN_IF_T::ARB2: ID Position           */
+#define CAN_IF_ARB2_ID_Msk              (0x1ffful << CAN_IF_ARB2_ID_Pos)                 /*!< CAN_IF_T::ARB2: ID Mask               */
+
+#define CAN_IF_ARB2_DIR_Pos             (13)                                              /*!< CAN_IF_T::ARB2: Dir Position          */
+#define CAN_IF_ARB2_DIR_Msk             (0x1ul << CAN_IF_ARB2_DIR_Pos)                   /*!< CAN_IF_T::ARB2: Dir Mask              */
+
+#define CAN_IF_ARB2_XTD_Pos             (14)                                              /*!< CAN_IF_T::ARB2: Xtd Position          */
+#define CAN_IF_ARB2_XTD_Msk             (0x1ul << CAN_IF_ARB2_XTD_Pos)                   /*!< CAN_IF_T::ARB2: Xtd Mask              */
+
+#define CAN_IF_ARB2_MSGVAL_Pos          (15)                                              /*!< CAN_IF_T::ARB2: MsgVal Position       */
+#define CAN_IF_ARB2_MSGVAL_Msk          (0x1ul << CAN_IF_ARB2_MSGVAL_Pos)                /*!< CAN_IF_T::ARB2: MsgVal Mask           */
+
+#define CAN_IF_MCON_DLC_Pos             (0)                                               /*!< CAN_IF_T::MCON: DLC Position          */
+#define CAN_IF_MCON_DLC_Msk             (0xful << CAN_IF_MCON_DLC_Pos)                   /*!< CAN_IF_T::MCON: DLC Mask              */
+
+#define CAN_IF_MCON_EOB_Pos             (7)                                               /*!< CAN_IF_T::MCON: EoB Position          */
+#define CAN_IF_MCON_EOB_Msk             (0x1ul << CAN_IF_MCON_EOB_Pos)                   /*!< CAN_IF_T::MCON: EoB Mask              */
+
+#define CAN_IF_MCON_TxRqst_Pos          (8)                                               /*!< CAN_IF_T::MCON: TxRqst Position       */
+#define CAN_IF_MCON_TxRqst_Msk          (0x1ul << CAN_IF_MCON_TxRqst_Pos)                /*!< CAN_IF_T::MCON: TxRqst Mask           */
+
+#define CAN_IF_MCON_RmtEn_Pos           (9)                                               /*!< CAN_IF_T::MCON: RmtEn Position        */
+#define CAN_IF_MCON_RmtEn_Msk           (0x1ul << CAN_IF_MCON_RmtEn_Pos)                 /*!< CAN_IF_T::MCON: RmtEn Mask            */
+
+#define CAN_IF_MCON_RXIE_Pos            (10)                                              /*!< CAN_IF_T::MCON: RxIE Position         */
+#define CAN_IF_MCON_RXIE_Msk            (0x1ul << CAN_IF_MCON_RXIE_Pos)                  /*!< CAN_IF_T::MCON: RxIE Mask             */
+
+#define CAN_IF_MCON_TXIE_Pos            (11)                                              /*!< CAN_IF_T::MCON: TxIE Position         */
+#define CAN_IF_MCON_TXIE_Msk            (0x1ul << CAN_IF_MCON_TXIE_Pos)                  /*!< CAN_IF_T::MCON: TxIE Mask             */
+
+#define CAN_IF_MCON_UMASK_Pos           (12)                                              /*!< CAN_IF_T::MCON: UMask Position        */
+#define CAN_IF_MCON_UMASK_Msk           (0x1ul << CAN_IF_MCON_UMASK_Pos)                 /*!< CAN_IF_T::MCON: UMask Mask            */
+
+#define CAN_IF_MCON_IntPnd_Pos          (13)                                              /*!< CAN_IF_T::MCON: IntPnd Position       */
+#define CAN_IF_MCON_IntPnd_Msk          (0x1ul << CAN_IF_MCON_IntPnd_Pos)                /*!< CAN_IF_T::MCON: IntPnd Mask           */
+
+#define CAN_IF_MCON_MsgLst_Pos          (14)                                              /*!< CAN_IF_T::MCON: MsgLst Position       */
+#define CAN_IF_MCON_MsgLst_Msk          (0x1ul << CAN_IF_MCON_MsgLst_Pos)                /*!< CAN_IF_T::MCON: MsgLst Mask           */
+
+#define CAN_IF_MCON_NEWDAT_Pos          (15)                                              /*!< CAN_IF_T::MCON: NewDat Position       */
+#define CAN_IF_MCON_NEWDAT_Msk          (0x1ul << CAN_IF_MCON_NEWDAT_Pos)                 /*!< CAN_IF_T::MCON: NewDat Mask           */
+
+#define CAN_IF_DAT_A1_DATA0_Pos       (0)                                               /*!< CAN_IF_T::DAT_A1: Data_0_ Position    */
+#define CAN_IF_DAT_A1_DATA0_Msk       (0xfful << CAN_IF_DAT_A1_DATA0_Pos)            /*!< CAN_IF_T::DAT_A1: Data_0_ Mask        */
+
+#define CAN_IF_DAT_A1_DATA1_Pos       (8)                                               /*!< CAN_IF_T::DAT_A1: Data_1_ Position    */
+#define CAN_IF_DAT_A1_DATA1_Msk       (0xfful << CAN_IF_DAT_A1_DATA1_Pos)            /*!< CAN_IF_T::DAT_A1: Data_1_ Mask        */
+
+#define CAN_IF_DAT_A2_DATA2_Pos       (0)                                               /*!< CAN_IF_T::DAT_A2: Data_2_ Position    */
+#define CAN_IF_DAT_A2_DATA2_Msk       (0xfful << CAN_IF_DAT_A2_DATA2_Pos)            /*!< CAN_IF_T::DAT_A2: Data_2_ Mask        */
+
+#define CAN_IF_DAT_A2_DATA3_Pos       (8)                                               /*!< CAN_IF_T::DAT_A2: Data_3_ Position    */
+#define CAN_IF_DAT_A2_DATA3_Msk       (0xfful << CAN_IF_DAT_A2_DATA3_Pos)            /*!< CAN_IF_T::DAT_A2: Data_3_ Mask        */
+
+#define CAN_IF_DAT_B1_DATA4_Pos       (0)                                               /*!< CAN_IF_T::DAT_B1: Data_4_ Position    */
+#define CAN_IF_DAT_B1_DATA4_Msk       (0xfful << CAN_IF_DAT_B1_DATA4_Pos)            /*!< CAN_IF_T::DAT_B1: Data_4_ Mask        */
+
+#define CAN_IF_DAT_B1_DATA5_Pos       (8)                                               /*!< CAN_IF_T::DAT_B1: Data_5_ Position    */
+#define CAN_IF_DAT_B1_DATA5_Msk       (0xfful << CAN_IF_DAT_B1_DATA5_Pos)            /*!< CAN_IF_T::DAT_B1: Data_5_ Mask        */
+
+#define CAN_IF_DAT_B2_DATA6_Pos       (0)                                               /*!< CAN_IF_T::DAT_B2: Data_6_ Position    */
+#define CAN_IF_DAT_B2_DATA6_Msk       (0xfful << CAN_IF_DAT_B2_DATA6_Pos)            /*!< CAN_IF_T::DAT_B2: Data_6_ Mask        */
+
+#define CAN_IF_DAT_B2_DATA7_Pos       (8)                                               /*!< CAN_IF_T::DAT_B2: Data_7_ Position    */
+#define CAN_IF_DAT_B2_DATA7_Msk       (0xfful << CAN_IF_DAT_B2_DATA7_Pos)            /*!< CAN_IF_T::DAT_B2: Data_7_ Mask        */
+
+#define CAN_TXREQ1_TXRQST16_1_Pos        (0)                                               /*!< CAN_T::TXREQ1: TxRqst16_1 Position     */
+#define CAN_TXREQ1_TXRQST16_1_Msk        (0xfffful << CAN_TXREQ1_TXRQST16_1_Pos)           /*!< CAN_T::TXREQ1: TxRqst16_1 Mask         */
+
+#define CAN_TXREQ2_TXRQST32_17_Pos       (0)                                               /*!< CAN_T::TXREQ2: TxRqst32_17 Position    */
+#define CAN_TXREQ2_TXRQST32_17_Msk       (0xfffful << CAN_TXREQ2_TXRQST32_17_Pos)          /*!< CAN_T::TXREQ2: TxRqst32_17 Mask        */
+
+#define CAN_NDAT1_NewData16_1_Pos        (0)                                               /*!< CAN_T::NDAT1: NewData16_1 Position     */
+#define CAN_NDAT1_NewData16_1_Msk        (0xfffful << CAN_NDAT1_NewData16_1_Pos)           /*!< CAN_T::NDAT1: NewData16_1 Mask         */
+
+#define CAN_NDAT2_NewData32_17_Pos       (0)                                               /*!< CAN_T::NDAT2: NewData32_17 Position    */
+#define CAN_NDAT2_NewData32_17_Msk       (0xfffful << CAN_NDAT2_NewData32_17_Pos)          /*!< CAN_T::NDAT2: NewData32_17 Mask        */
+
+#define CAN_IPND1_IntPnd16_1_Pos         (0)                                               /*!< CAN_T::IPND1: IntPnd16_1 Position      */
+#define CAN_IPND1_IntPnd16_1_Msk         (0xfffful << CAN_IPND1_IntPnd16_1_Pos)            /*!< CAN_T::IPND1: IntPnd16_1 Mask          */
+
+#define CAN_IPND2_IntPnd32_17_Pos        (0)                                               /*!< CAN_T::IPND2: IntPnd32_17 Position     */
+#define CAN_IPND2_IntPnd32_17_Msk        (0xfffful << CAN_IPND2_IntPnd32_17_Pos)           /*!< CAN_T::IPND2: IntPnd32_17 Mask         */
+
+#define CAN_MVLD1_MsgVal16_1_Pos         (0)                                               /*!< CAN_T::MVLD1: MsgVal16_1 Position      */
+#define CAN_MVLD1_MsgVal16_1_Msk         (0xfffful << CAN_MVLD1_MsgVal16_1_Pos)            /*!< CAN_T::MVLD1: MsgVal16_1 Mask          */
+
+#define CAN_MVLD2_MsgVal32_17_Pos        (0)                                               /*!< CAN_T::MVLD2: MsgVal32_17 Position     */
+#define CAN_MVLD2_MsgVal32_17_Msk        (0xfffful << CAN_MVLD2_MsgVal32_17_Pos)           /*!< CAN_T::MVLD2: MsgVal32_17 Mask         */
+
+#define CAN_WU_EN_WAKUP_EN_Pos           (0)                                               /*!< CAN_T::WU_EN: WAKUP_EN Position        */
+#define CAN_WU_EN_WAKUP_EN_Msk           (0x1ul << CAN_WU_EN_WAKUP_EN_Pos)                 /*!< CAN_T::WU_EN: WAKUP_EN Mask            */
+
+#define CAN_WU_STATUS_WAKUP_STS_Pos      (0)                                               /*!< CAN_T::WU_STATUS: WAKUP_STS Position   */
+#define CAN_WU_STATUS_WAKUP_STS_Msk      (0x1ul << CAN_WU_STATUS_WAKUP_STS_Pos)            /*!< CAN_T::WU_STATUS: WAKUP_STS Mask       */
+
+/**@}*/ /* CAN_CONST */
+/**@}*/ /* end of CAN register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM   )
+#pragma no_anon_unions
+#endif
+
+#endif /* __CAN_REG_H__ */

dap_link/lib/free-dap/platform/m484/include/ccap_reg.h

@@ -0,0 +1,496 @@
+/**************************************************************************//**
+ * @file     ccap_reg.h
+ * @version  V1.00
+ * @brief    CCAP register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __CCAP_REG_H__
+#define __CCAP_REG_H__
+
+#if defined ( __CC_ARM   )
+#pragma anon_unions
+#endif
+
+/**
+   @addtogroup REGISTER Control Register
+   @{
+*/
+
+/**
+    @addtogroup CCAP Camera Capture Interface Controller (CCAP)
+    Memory Mapped Structure for CCAP Controller
+@{ */
+
+
+typedef struct {
+
+
+    /**
+     * @var CCAP_T::CTL
+     * Offset: 0x00  Camera Capture Interface Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CCAPEN    |Camera Capture Interface Enable
+     * |        |          |0 = Camera Capture Interface Disabled.
+     * |        |          |1 = Camera Capture Interface Enabled.
+     * |[3]     |ADDRSW    |Packet Buffer Address Switch
+     * |        |          |0 = Packet buffer address switch Disabled.
+     * |        |          |1 = Packet buffer address switch Enabled.
+     * |[6]     |PKTEN     |Packet Output Enable
+     * |        |          |0 = Packet output Disabled.
+     * |        |          |1 = Packet output Enabled.
+     * |[7]     |MONO      |Monochrome CMOS Sensor Select
+     * |        |          |0 = Color CMOS Sensor.
+     * |        |          |1 = Monochrome CMOS Sensor. The U/V components are ignored when the MONO is enabled.
+     * |[16]    |SHUTTER   |Image Capture Interface Automatically Disable The Capture Interface After A Frame Had Been Captured
+     * |        |          |0 = Shutter Disabled.
+     * |        |          |1 = Shutter Enabled.
+     * |[20]    |UPDATE    |Update Register At New Frame
+     * |        |          |0 = Update register at new frame Disabled.
+     * |        |          |1 = Update register at new frame Enabled (Auto clear to 0 when register updated).
+     * |[24]    |VPRST     |Capture Interface Reset
+     * |        |          |0 = Capture interface reset Disabled.
+     * |        |          |1 = Capture interface reset Enabled.
+     * @var CCAP_T::PAR
+     * Offset: 0x04  Camera Capture Interface Parameter Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |INFMT     |Sensor Input Data Format
+     * |        |          |0 = YCbCr422.
+     * |        |          |1 = RGB565.
+     * |[1]     |SENTYPE   |Sensor Input Type
+     * |        |          |0 = CCIR601.
+     * |        |          |1 = CCIR656, VSync & Hsync embedded in the data signal.
+     * |[2:3]   |INDATORD  |Sensor Input Data Order
+     * |        |          |If INFMT = 0 (YCbCr),.
+     * |        |          | Byte 0 1 2 3
+     * |        |          |00 = Y0 U0 Y1 V0.
+     * |        |          |01 = Y0 V0 Y1 U0.
+     * |        |          |10 = U0 Y0 V0 Y1.
+     * |        |          |11 = V0 Y0 U0 Y1.
+     * |        |          |If INFMT = 1 (RGB565),.
+     * |        |          |00 = Byte0[R[4:0] G[5:3]] Byte1[G[2:0] B[4:0]]
+     * |        |          |01 = Byte0[B[4:0] G[5:3]] Byte1[G[2:0] R[4:0]]
+     * |        |          |10 = Byte0[G[2:0] B[4:0]] Byte1[R[4:0] G[5:3]]
+     * |        |          |11 = Byte0[G[2:0] R[4:0]] Byte1[B[4:0] G[5:3]]
+     * |[4:5]   |OUTFMT    |Image Data Format Output To System Memory
+     * |        |          |00 = YCbCr422.
+     * |        |          |01 = Only output Y.
+     * |        |          |10 = RGB555.
+     * |        |          |11 = RGB565.
+     * |[6]     |RANGE     |Scale Input YUV CCIR601 Color Range To Full Range
+     * |        |          |0 = default.
+     * |        |          |1 = Scale to full range.
+     * |[8]     |PCLKP     |Sensor Pixel Clock Polarity
+     * |        |          |0 = Input video data and signals are latched by falling edge of Pixel Clock.
+     * |        |          |1 = Input video data and signals are latched by rising edge of Pixel Clock.
+     * |[9]     |HSP       |Sensor Hsync Polarity
+     * |        |          |0 = Sync Low.
+     * |        |          |1 = Sync High.
+     * |[10]    |VSP       |Sensor Vsync Polarity
+     * |        |          |0 = Sync Low.
+     * |        |          |1 = Sync High.
+     * |[18]    |FBB       |Field By Blank
+     * |        |          |Hardware will tag field0 or field1 by vertical blanking instead of FIELD flag in CCIR-656 mode.
+     * |        |          |0 = Field by blank Disabled.
+     * |        |          |1 = Field by blank Enabled.
+     * @var CCAP_T::INT
+     * Offset: 0x08  Camera Capture Interface Interrupt Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |VINTF     |Video Frame End Interrupt
+     * |        |          |If this bit shows 1, receiving a frame completed.
+     * |        |          |Write 1 to clear it.
+     * |[1]     |MEINTF    |Bus Master Transfer Error Interrupt
+     * |        |          |If this bit shows 1, Transfer Error occurred. Write 1 to clear it.
+     * |[3]     |ADDRMINTF |Memory Address Match Interrupt
+     * |        |          |If this bit shows 1, Memory Address Match Interrupt occurred.
+     * |        |          |Write 1 to clear it.
+     * |[4]     |MDINTF    |Motion Detection Output Finish Interrupt
+     * |        |          |If this bit shows 1, Motion Detection Output Finish Interrupt occurred.
+     * |        |          |Write 1 to clear it.
+     * |[16]    |VIEN      |Video Frame End Interrupt Enable
+     * |        |          |0 = Video frame end interrupt Disabled.
+     * |        |          |1 = Video frame end interrupt Enabled.
+     * |[17]    |MEIEN     |System Memory Error Interrupt Enable
+     * |        |          |0 = System memory error interrupt Disabled.
+     * |        |          |1 = System memory error interrupt Enabled.
+     * |[19]    |ADDRMIEN  |Address Match Interrupt Enable
+     * |        |          |0 = Address match interrupt Disabled.
+     * |        |          |1 = Address match interrupt Enabled.
+     * @var CCAP_T::POSTERIZE
+     * Offset: 0x0C  YUV Component Posterizing Factor Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0:7]   |VCOMP     |V Component Posterizing Factor
+     * |        |          |Final_V_Out = Original_V[7:0] & V_Posterizing_Factor.
+     * |[8:15]  |UCOMP     |U Component Posterizing Factor
+     * |        |          |Final_U_Out = Original_U[7:0] & U_Posterizing_Factor.
+     * |[16:23] |YCOMP     |Y Component Posterizing Factor
+     * |        |          |Final_Y_Out = Original_Y[7:0] & Y_Posterizing_Factor.
+     * @var CCAP_T::MD
+     * Offset: 0x10  Motion Detection Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |MDEN      |Motion Detection Enable
+     * |        |          |0 = CCAP_MD Disabled.
+     * |        |          |1 = CCAP_MD Enabled.
+     * |[8]     |MDBS      |Motion Detection Block Size
+     * |        |          |0 = 16x16.
+     * |        |          |1 = 8x8.
+     * |[9]     |MDSM      |Motion Detection Save Mode
+     * |        |          |0 = 1 bit DIFF + 7 bit Y Differential.
+     * |        |          |1 = 1 bit DIFF only.
+     * |[10:11] |MDDF      |Motion Detection Detect Frequency
+     * |        |          |00 = Each frame.
+     * |        |          |01 = Every 2 frame.
+     * |        |          |10 = Every 3 frame.
+     * |        |          |11 = Every 4 frame.
+     * |[16:20] |MDTHR     |Motion Detection Differential Threshold
+     * @var CCAP_T::MDADDR
+     * Offset: 0x14  Motion Detection Output Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0:31]  |MDADDR    |Motion Detection Output Address Register (Word Alignment)
+     * @var CCAP_T::MDYADDR
+     * Offset: 0x18  Motion Detection Temp Y Output Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0:31]  |MDYADDR   |Motion Detection Temp Y Output Address Register (Word Alignment)
+     * @var CCAP_T::SEPIA
+     * Offset: 0x1C  Sepia Effect Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0:7]   |VCOMP     |Define the constant V component while Sepia color effect is turned on.
+     * |[8:15]  |UCOMP     |Define the constant U component while Sepia color effect is turned on.
+     * @var CCAP_T::CWSP
+     * Offset: 0x20  Cropping Window Starting Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0:11]  |CWSADDRH  |Cropping Window Horizontal Starting Address
+     * |[16:26] |CWSADDRV  |Cropping Window Vertical Starting Address
+     * @var CCAP_T::CWS
+     * Offset: 0x24  Cropping Window Size Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0:11]  |CIWW      |Cropping Image Window Width
+     * |[16:26] |CIWH      |Cropping Image Window Height
+     * @var CCAP_T::PKTSL
+     * Offset: 0x28  Packet Scaling Vertical/Horizontal Factor Register (LSB)
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0:7]   |PKTSHML   |Packet Scaling Horizontal Factor M (Lower 8-Bit)
+     * |        |          |Specifies the lower 8-bit of denominator part (M) of the horizontal scaling factor.
+     * |        |          |The lower 8-bit will be cascaded with higher 8-bit (PKDSHMH) to form a 16-bit denominator (M) of vertical factor.
+     * |        |          |The output image width will be equal to the image width * N/M.
+     * |        |          |Note: The value of N must be equal to or less than M.
+     * |[8:15]  |PKTSHNL   |Packet Scaling Horizontal Factor N (Lower 8-Bit)
+     * |        |          |Specify the lower 8-bit of numerator part (N) of the horizontal scaling factor.
+     * |        |          |The lower 8-bit will be cascaded with higher 8-bit (PKDSHNH) to form a 16-bit numerator of horizontal factor.
+     * |[16:23] |PKTSVML   |Packet Scaling Vertical Factor M (Lower 8-Bit)
+     * |        |          |Specify the lower 8-bit of denominator part (M) of the vertical scaling factor.
+     * |        |          |The lower 8-bit will be cascaded with higher 8-bit (PKDSVMH) to form a 16-bit denominator (M) of vertical factor.
+     * |        |          |The output image width will be equal to the image height * N/M.
+     * |        |          |Note: The value of N must be equal to or less than M.
+     * |[24:31] |PKTSVNL   |Packet Scaling Vertical Factor N (Lower 8-Bit)
+     * |        |          |Specify the lower 8-bit of numerator part (N) of the vertical scaling factor.
+     * |        |          |The lower 8-bit will be cascaded with higher 8-bit (PKDSVNH) to form a 16-bit numerator of vertical factor
+     * @var CCAP_T::PLNSL
+     * Offset: 0x2C  Planar Scaling Vertical/Horizontal Factor Register (LSB)
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0:7]   |PLNSHML   |Planar Scaling Horizontal Factor M (Lower 8-Bit)
+     * |        |          |Specify the lower 8-bit of denominator part (M) of the horizontal scaling factor.
+     * |        |          |The lower 8-bit will be cascaded with higher 8-bit (PNDSHMH) to form a 16-bit denominator (M) of vertical factor.
+     * |        |          |The output image width will be equal to the image width * N/M.
+     * |        |          |Note: The value of N must be equal to or less than M.
+     * |[8:15]  |PLNSHNL   |Planar Scaling Horizontal Factor N (Lower 8-Bit)
+     * |        |          |Specify the lower 8-bit of numerator part (N) of the horizontal scaling factor.
+     * |        |          |The lower 8-bit will be cascaded with higher 8-bit (PNDSHNH) to form a 16-bit numerator of horizontal factor.
+     * |[16:23] |PLNSVML   |Planar Scaling Vertical Factor M (Lower 8-Bit)
+     * |        |          |Specify the lower 8-bit of denominator part (M) of the vertical scaling factor.
+     * |        |          |The lower 8-bit will be cascaded with higher 8-bit (PNDSVMH) to form a 16-bit denominator (M) of vertical factor.
+     * |        |          |The output image width will be equal to the image height * N/M.
+     * |        |          |Note: The value of N must be equal to or less than M.
+     * |[24:31] |PLNSVNL   |Planar Scaling Vertical Factor N (Lower 8-Bit)
+     * |        |          |Specify the lower 8-bit of numerator part (N) of the vertical scaling factor.
+     * |        |          |The lower 8-bit will be cascaded with higher 8-bit (PNDSVNH) to form a 16-bit numerator of vertical factor.
+     * @var CCAP_T::FRCTL
+     * Offset: 0x30  Scaling Frame Rate Factor Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0:5]   |FRM       |Scaling Frame Rate Factor M
+     * |        |          |Specify the denominator part (M) of the frame rate scaling factor.
+     * |        |          |The output image frame rate will be equal to input image frame rate * (N/M).
+     * |        |          |Note: The value of N must be equal to or less than M.
+     * |[8:13]  |FRN       |Scaling Frame Rate Factor N
+     * |        |          |Specify the denominator part (N) of the frame rate scaling factor.
+     * @var CCAP_T::STRIDE
+     * Offset: 0x34  Frame Output Pixel Stride Width Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0:13]  |PKTSTRIDE |Packet Frame Output Pixel Stride Width
+     * |        |          |The output pixel stride size of packet pipe.
+     * |[16:29] |PLNSTRIDE |Planar Frame Output Pixel Stride Width
+     * |        |          |The output pixel stride size of planar pipe.
+     * @var CCAP_T::FIFOTH
+     * Offset: 0x3C  FIFO Threshold Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0:3]   |PLNVFTH   |Planar V FIFO Threshold
+     * |[8:11]  |PLNUFTH   |Planar U FIFO Threshold
+     * |[16:20] |PLNYFTH   |Planar Y FIFO Threshold
+     * |[24:28] |PKTFTH    |Packet FIFO Threshold
+     * |[31]    |OVF       |FIFO Overflow Flag
+     * @var CCAP_T::CMPADDR
+     * Offset: 0x40  Compare Memory Base Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0:31]  |CMPADDR   |Compare Memory Base Address
+     * |        |          |Word aligns address; ignore the bits [1:0].
+     * @var CCAP_T::LUMA_Y1_THD
+     * Offset: 0x44  Luminance Y8 to Y1 Threshold Value Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field          |Descriptions
+     * | :----: | :-----------: | :---- |
+     * |[0:8]   |LUMA_Y1_THRESH |Luminance Y8 to Y1 Threshold Value
+     * |        |               |Specify the 8-bit threshold value for the luminance Y bit-8 to the luminance Y 1-bit conversion.
+     * @var CCAP_T::PKTSM
+     * Offset: 0x48  Packet Scaling Vertical/Horizontal Factor Register (MSB)
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0:7]   |PKTSHMH   |Packet Scaling Horizontal Factor M (Higher 8-Bit)
+     * |        |          |Specify the lower 8-bit of denominator part (M) of the horizontal scaling factor.
+     * |        |          |Please refer to the register CCAP_PKTSL?for the detailed operation.
+     * |[8:15]  |PKTSHNH   |Packet Scaling Horizontal Factor N (Higher 8-Bit)
+     * |        |          |Specify the lower 8-bit of numerator part (N) of the horizontal scaling factor.
+     * |        |          |Please refer to the register CCAP_PKTSL for the detailed operation.
+     * |[16:23] |PKTSVMH   |Packet Scaling Vertical Factor M (Higher 8-Bit)
+     * |        |          |Specify the lower 8-bit of denominator part (M) of the vertical scaling factor.
+     * |        |          |Please refer to the register CCAP_PKTSL to check the cooperation between these two registers.
+     * |[24:31] |PKTSVNH   |Packet Scaling Vertical Factor N (Higher 8-Bit)
+     * |        |          |Specify the higher 8-bit of numerator part (N) of the vertical scaling factor.
+     * |        |          |Please refer to the register CCAP_PKTSL?to check the cooperation between these two registers.
+     * @var CCAP_T::PKTBA0
+     * Offset: 0x60  System Memory Packet Base Address 0 Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0:31]  |BASEADDR  |System Memory Packet Base Address 0
+     * |        |          |Word aligns address; ignore the bits [1:0].
+     */
+    __IO uint32_t CTL;
+    __IO uint32_t PAR;
+    __IO uint32_t INT;
+    __IO uint32_t POSTERIZE;
+    __IO uint32_t MD;
+    __IO uint32_t MDADDR;
+    __IO uint32_t MDYADDR;
+    __IO uint32_t SEPIA;
+    __IO uint32_t CWSP;
+    __IO uint32_t CWS;
+    __IO uint32_t PKTSL;
+    __IO uint32_t PLNSL;
+    __IO uint32_t FRCTL;
+    __IO uint32_t STRIDE;
+    /// @cond HIDDEN_SYMBOLS
+    uint32_t RESERVE0[1];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t FIFOTH;
+    __IO uint32_t CMPADDR;
+    __IO uint32_t LUMA_Y1_THD;
+    __IO uint32_t PKTSM;
+    /// @cond HIDDEN_SYMBOLS
+    uint32_t RESERVE2[5];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t PKTBA0;
+} CCAP_T;
+
+/**
+    @addtogroup CCAP_CONST CCAP Bit Field Definition
+    Constant Definitions for CCAP Controller
+@{ */
+
+#define CCAP_CTL_CCAPEN_Pos               (0)                                               /*!< CCAP_T::CTL: CCAPEN Position                */
+#define CCAP_CTL_CCAPEN_Msk               (0x1ul << CCAP_CTL_CCAPEN_Pos)                     /*!< CCAP_T::CTL: CCAPEN Mask                    */
+
+#define CCAP_CTL_ADDRSW_Pos               (3)                                               /*!< CCAP_T::CTL: ADDRSW Position               */
+#define CCAP_CTL_ADDRSW_Msk               (0x1ul << CCAP_CTL_ADDRSW_Pos)                     /*!< CCAP_T::CTL: ADDRSW Mask                   */
+
+#define CCAP_CTL_PLNEN_Pos                (5)                                               /*!< CCAP_T::CTL: PLNEN Position                */
+#define CCAP_CTL_PLNEN_Msk                (0x1ul << CCAP_CTL_PLNEN_Pos)                      /*!< CCAP_T::CTL: PLNEN Mask                    */
+
+#define CCAP_CTL_PKTEN_Pos                (6)                                               /*!< CCAP_T::CTL: PKTEN Position                */
+#define CCAP_CTL_PKTEN_Msk                (0x1ul << CCAP_CTL_PKTEN_Pos)                      /*!< CCAP_T::CTL: PKTEN Mask                    */
+
+#define CCAP_CTL_MONO_Pos                 (7)                                               /*!< CCAP_T::CTL: MONO Position                */
+#define CCAP_CTL_MONO_Msk                 (0x1ul << CCAP_CTL_MONO_Pos)                       /*!< CCAP_T::CTL: MONO Mask                    */
+
+#define CCAP_CTL_SHUTTER_Pos              (16)                                              /*!< CCAP_T::CTL: SHUTTER Position              */
+#define CCAP_CTL_SHUTTER_Msk              (0x1ul << CCAP_CTL_SHUTTER_Pos)                    /*!< CCAP_T::CTL: SHUTTER Mask                  */
+
+#define CCAP_CTL_MY4_SWAP_Pos             (17)                                              /*!< CCAP_T::CTL: MY4_SWAP Position              */
+#define CCAP_CTL_MY4_SWAP_Msk             (0x1ul << CCAP_CTL_MY4_SWAP_Pos)                   /*!< CCAP_T::CTL: MY4_SWAP Mask                  */
+
+#define CCAP_CTL_MY8_MY4_Pos              (18)                                              /*!< CCAP_T::CTL: MY8_MY4 Position              */
+#define CCAP_CTL_MY8_MY4_Msk              (0x1ul << CCAP_CTL_MY8_MY4_Pos)                    /*!< CCAP_T::CTL: MY8_MY4 Mask                  */
+
+#define CCAP_CTL_Luma_Y_One_Pos           (19)                                              /*!< CCAP_T::CTL: Luma_Y_One Position              */
+#define CCAP_CTL_Luma_Y_One_Msk           (0x1ul << CCAP_CTL_Luma_Y_One_Pos)                 /*!< CCAP_T::CTL: Luma_Y_One Mask                  */
+
+#define CCAP_CTL_UPDATE_Pos               (20)                                              /*!< CCAP_T::CTL: UPDATE Position               */
+#define CCAP_CTL_UPDATE_Msk               (0x1ul << CCAP_CTL_UPDATE_Pos)                     /*!< CCAP_T::CTL: UPDATE Mask                   */
+
+#define CCAP_CTL_VPRST_Pos                (24)                                              /*!< CCAP_T::CTL: VPRST Position                */
+#define CCAP_CTL_VPRST_Msk                (0x1ul << CCAP_CTL_VPRST_Pos)                      /*!< CCAP_T::CTL: VPRST Mask                    */
+
+#define CCAP_PAR_INFMT_Pos                (0)                                               /*!< CCAP_T::PAR: INFMT Position                */
+#define CCAP_PAR_INFMT_Msk                (0x1ul << CCAP_PAR_INFMT_Pos)                      /*!< CCAP_T::PAR: INFMT Mask                    */
+
+#define CCAP_PAR_SENTYPE_Pos              (1)                                               /*!< CCAP_T::PAR: SENTYPE Position              */
+#define CCAP_PAR_SENTYPE_Msk              (0x1ul << CCAP_PAR_SENTYPE_Pos)                    /*!< CCAP_T::PAR: SENTYPE Mask                  */
+
+#define CCAP_PAR_INDATORD_Pos             (2)                                               /*!< CCAP_T::PAR: INDATORD Position             */
+#define CCAP_PAR_INDATORD_Msk             (0x3ul << CCAP_PAR_INDATORD_Pos)                   /*!< CCAP_T::PAR: INDATORD Mask                 */
+
+#define CCAP_PAR_OUTFMT_Pos               (4)                                               /*!< CCAP_T::PAR: OUTFMT Position               */
+#define CCAP_PAR_OUTFMT_Msk               (0x3ul << CCAP_PAR_OUTFMT_Pos)                     /*!< CCAP_T::PAR: OUTFMT Mask                   */
+
+#define CCAP_PAR_RANGE_Pos                (6)                                               /*!< CCAP_T::PAR: RANGE Position                */
+#define CCAP_PAR_RANGE_Msk                (0x1ul << CCAP_PAR_RANGE_Pos)                      /*!< CCAP_T::PAR: RANGE Mask                    */
+
+#define CCAP_PAR_PLNFMT_Pos               (7)                                               /*!< CCAP_T::PAR: PLNFMT Position               */
+#define CCAP_PAR_PLNFMT_Msk               (0x1ul << CCAP_PAR_PLNFMT_Pos)                     /*!< CCAP_T::PAR: PLNFMT Mask                   */
+
+#define CCAP_PAR_PCLKP_Pos                (8)                                               /*!< CCAP_T::PAR: PCLKP Position                */
+#define CCAP_PAR_PCLKP_Msk                (0x1ul << CCAP_PAR_PCLKP_Pos)                      /*!< CCAP_T::PAR: PCLKP Mask                    */
+
+#define CCAP_PAR_HSP_Pos                  (9)                                               /*!< CCAP_T::PAR: HSP Position                  */
+#define CCAP_PAR_HSP_Msk                  (0x1ul << CCAP_PAR_HSP_Pos)                        /*!< CCAP_T::PAR: HSP Mask                      */
+
+#define CCAP_PAR_VSP_Pos                  (10)                                              /*!< CCAP_T::PAR: VSP Position                  */
+#define CCAP_PAR_VSP_Msk                  (0x1ul << CCAP_PAR_VSP_Pos)                        /*!< CCAP_T::PAR: VSP Mask                      */
+
+#define CCAP_PAR_COLORCTL_Pos             (11)                                              /*!< CCAP_T::PAR: COLORCTL Position             */
+#define CCAP_PAR_COLORCTL_Msk             (0x3ul << CCAP_PAR_COLORCTL_Pos)                   /*!< CCAP_T::PAR: COLORCTL Mask                 */
+
+#define CCAP_PAR_FBB_Pos                  (18)                                              /*!< CCAP_T::PAR: FBB Position                  */
+#define CCAP_PAR_FBB_Msk                  (0x1ul << CCAP_PAR_FBB_Pos)                        /*!< CCAP_T::PAR: FBB Mask                      */
+
+#define CCAP_INT_VINTF_Pos                (0)                                               /*!< CCAP_T::INT: VINTF Position                */
+#define CCAP_INT_VINTF_Msk                (0x1ul << CCAP_INT_VINTF_Pos)                      /*!< CCAP_T::INT: VINTF Mask                    */
+
+#define CCAP_INT_MEINTF_Pos               (1)                                               /*!< CCAP_T::INT: MEINTF Position               */
+#define CCAP_INT_MEINTF_Msk               (0x1ul << CCAP_INT_MEINTF_Pos)                     /*!< CCAP_T::INT: MEINTF Mask                   */
+
+#define CCAP_INT_ADDRMINTF_Pos            (3)                                               /*!< CCAP_T::INT: ADDRMINTF Position            */
+#define CCAP_INT_ADDRMINTF_Msk            (0x1ul << CCAP_INT_ADDRMINTF_Pos)                  /*!< CCAP_T::INT: ADDRMINTF Mask                */
+
+#define CCAP_INT_MDINTF_Pos               (4)                                               /*!< CCAP_T::INT: MDINTF Position               */
+#define CCAP_INT_MDINTF_Msk               (0x1ul << CCAP_INT_MDINTF_Pos)                     /*!< CCAP_T::INT: MDINTF Mask                   */
+
+#define CCAP_INT_VIEN_Pos                 (16)                                              /*!< CCAP_T::INT: VIEN Position                 */
+#define CCAP_INT_VIEN_Msk                 (0x1ul << CCAP_INT_VIEN_Pos)                       /*!< CCAP_T::INT: VIEN Mask                     */
+
+#define CCAP_INT_MEIEN_Pos                (17)                                              /*!< CCAP_T::INT: MEIEN Position                */
+#define CCAP_INT_MEIEN_Msk                (0x1ul << CCAP_INT_MEIEN_Pos)                      /*!< CCAP_T::INT: MEIEN Mask                    */
+
+#define CCAP_INT_ADDRMIEN_Pos             (19)                                              /*!< CCAP_T::INT: ADDRMIEN Position             */
+#define CCAP_INT_ADDRMIEN_Msk             (0x1ul << CCAP_INT_ADDRMIEN_Pos)                   /*!< CCAP_T::INT: ADDRMIEN Mask                 */
+
+#define CCAP_CWSP_CWSADDRH_Pos            (0)                                               /*!< CCAP_T::CWSP: CWSADDRH Position            */
+#define CCAP_CWSP_CWSADDRH_Msk            (0xffful << CCAP_CWSP_CWSADDRH_Pos)                /*!< CCAP_T::CWSP: CWSADDRH Mask                */
+
+#define CCAP_CWSP_CWSADDRV_Pos            (16)                                              /*!< CCAP_T::CWSP: CWSADDRV Position            */
+#define CCAP_CWSP_CWSADDRV_Msk            (0x7fful << CCAP_CWSP_CWSADDRV_Pos)                /*!< CCAP_T::CWSP: CWSADDRV Mask                */
+
+#define CCAP_CWS_CWW_Pos                  (0)                                               /*!< CCAP_T::CWS: CWW Position                 */
+#define CCAP_CWS_CWW_Msk                  (0xffful << CCAP_CWS_CWW_Pos)                      /*!< CCAP_T::CWS: CWW Mask                     */
+#define CCAP_CWS_CWH_Pos                  (16)                                              /*!< CCAP_T::CWS: CIWH Position                 */
+#define CCAP_CWS_CWH_Msk                  (0x7fful << CCAP_CWS_CWH_Pos)                      /*!< CCAP_T::CWS: CIWH Mask                     */
+
+#define CCAP_PKTSL_PKTSHML_Pos            (0)                                               /*!< CCAP_T::PKTSL: PKTSHML Position            */
+#define CCAP_PKTSL_PKTSHML_Msk            (0xfful << CCAP_PKTSL_PKTSHML_Pos)                 /*!< CCAP_T::PKTSL: PKTSHML Mask                */
+
+#define CCAP_PKTSL_PKTSHNL_Pos            (8)                                               /*!< CCAP_T::PKTSL: PKTSHNL Position            */
+#define CCAP_PKTSL_PKTSHNL_Msk            (0xfful << CCAP_PKTSL_PKTSHNL_Pos)                 /*!< CCAP_T::PKTSL: PKTSHNL Mask                */
+
+#define CCAP_PKTSL_PKTSVML_Pos            (16)                                              /*!< CCAP_T::PKTSL: PKTSVML Position            */
+#define CCAP_PKTSL_PKTSVML_Msk            (0xfful << CCAP_PKTSL_PKTSVML_Pos)                 /*!< CCAP_T::PKTSL: PKTSVML Mask                */
+
+#define CCAP_PKTSL_PKTSVNL_Pos            (24)                                              /*!< CCAP_T::PKTSL: PKTSVNL Position            */
+#define CCAP_PKTSL_PKTSVNL_Msk            (0xfful << CCAP_PKTSL_PKTSVNL_Pos)                 /*!< CCAP_T::PKTSL: PKTSVNL Mask                */
+
+#define CCAP_FRCTL_FRM_Pos                (0)                                               /*!< CCAP_T::FRCTL: FRM Position                */
+#define CCAP_FRCTL_FRM_Msk                (0x3ful << CCAP_FRCTL_FRM_Pos)                     /*!< CCAP_T::FRCTL: FRM Mask                    */
+
+#define CCAP_FRCTL_FRN_Pos                (8)                                               /*!< CCAP_T::FRCTL: FRN Position                */
+#define CCAP_FRCTL_FRN_Msk                (0x3ful << CCAP_FRCTL_FRN_Pos)                     /*!< CCAP_T::FRCTL: FRN Mask                    */
+
+#define CCAP_STRIDE_PKTSTRIDE_Pos         (0)                                               /*!< CCAP_T::STRIDE: PKTSTRIDE Position         */
+#define CCAP_STRIDE_PKTSTRIDE_Msk         (0x3ffful << CCAP_STRIDE_PKTSTRIDE_Pos)            /*!< CCAP_T::STRIDE: PKTSTRIDE Mask             */
+
+#define CCAP_STRIDE_PLNSTRIDE_Pos         (16)                                              /*!< CCAP_T::STRIDE: PLNSTRIDE Position         */
+#define CCAP_STRIDE_PLNSTRIDE_Msk         (0x3ffful << CCAP_STRIDE_PLNSTRIDE_Pos)            /*!< CCAP_T::STRIDE: PLNSTRIDE Mask             */
+
+#define CCAP_FIFOTH_PLNVFTH_Pos           (0)                                               /*!< CCAP_T::FIFOTH: PLNVFTH Position           */
+#define CCAP_FIFOTH_PLNVFTH_Msk           (0xful << CCAP_FIFOTH_PLNVFTH_Pos)                 /*!< CCAP_T::FIFOTH: PLNVFTH Mask               */
+
+#define CCAP_FIFOTH_PLNUFTH_Pos           (8)                                               /*!< CCAP_T::FIFOTH: PLNUFTH Position           */
+#define CCAP_FIFOTH_PLNUFTH_Msk           (0xful << CCAP_FIFOTH_PLNUFTH_Pos)                 /*!< CCAP_T::FIFOTH: PLNUFTH Mask               */
+
+#define CCAP_FIFOTH_PLNYFTH_Pos           (16)                                              /*!< CCAP_T::FIFOTH: PLNYFTH Position           */
+#define CCAP_FIFOTH_PLNYFTH_Msk           (0x1ful << CCAP_FIFOTH_PLNYFTH_Pos)                /*!< CCAP_T::FIFOTH: PLNYFTH Mask               */
+
+#define CCAP_FIFOTH_PKTFTH_Pos            (24)                                              /*!< CCAP_T::FIFOTH: PKTFTH Position            */
+#define CCAP_FIFOTH_PKTFTH_Msk            (0x1ful << CCAP_FIFOTH_PKTFTH_Pos)                 /*!< CCAP_T::FIFOTH: PKTFTH Mask                */
+
+#define CCAP_FIFOTH_OVF_Pos               (31)                                              /*!< CCAP_T::FIFOTH: OVF Position               */
+#define CCAP_FIFOTH_OVF_Msk               (0x1ul << CCAP_FIFOTH_OVF_Pos)                     /*!< CCAP_T::FIFOTH: OVF Mask                   */
+
+#define CCAP_CMPADDR_CMPADDR_Pos          (0)                                               /*!< CCAP_T::CMPADDR: CMPADDR Position          */
+#define CCAP_CMPADDR_CMPADDR_Msk          (0xfffffffful << CCAP_CMPADDR_CMPADDR_Pos)         /*!< CCAP_T::CMPADDR: CMPADDR Mask              */
+
+#define CCAP_PKTSM_PKTSHMH_Pos            (0)                                               /*!< CCAP_T::PKTSM: PKTSHMH Position            */
+#define CCAP_PKTSM_PKTSHMH_Msk            (0xfful << CCAP_PKTSM_PKTSHMH_Pos)                 /*!< CCAP_T::PKTSM: PKTSHMH Mask                */
+
+#define CCAP_PKTSM_PKTSHNH_Pos            (8)                                               /*!< CCAP_T::PKTSM: PKTSHNH Position            */
+#define CCAP_PKTSM_PKTSHNH_Msk            (0xfful << CCAP_PKTSM_PKTSHNH_Pos)                 /*!< CCAP_T::PKTSM: PKTSHNH Mask                */
+
+#define CCAP_PKTSM_PKTSVMH_Pos            (16)                                              /*!< CCAP_T::PKTSM: PKTSVMH Position            */
+#define CCAP_PKTSM_PKTSVMH_Msk            (0xfful << CCAP_PKTSM_PKTSVMH_Pos)                 /*!< CCAP_T::PKTSM: PKTSVMH Mask                */
+
+#define CCAP_PKTSM_PKTSVNH_Pos            (24)                                              /*!< CCAP_T::PKTSM: PKTSVNH Position            */
+#define CCAP_PKTSM_PKTSVNH_Msk            (0xfful << CCAP_PKTSM_PKTSVNH_Pos)                 /*!< CCAP_T::PKTSM: PKTSVNH Mask                */
+
+#define CCAP_PKTBA0_BASEADDR_Pos          (0)                                               /*!< CCAP_T::PKTBA0: BASEADDR Position          */
+#define CCAP_PKTBA0_BASEADDR_Msk          (0xfffffffful << CCAP_PKTBA0_BASEADDR_Pos)         /*!< CCAP_T::PKTBA0: BASEADDR Mask              */
+
+/**@}*/ /* CCAP_CONST */
+/**@}*/ /* end of CCAP register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM   )
+#pragma no_anon_unions
+#endif
+
+#endif /* __CCAP_REG_H__ */

dap_link/lib/free-dap/platform/m484/include/clk_reg.h

@@ -0,0 +1,1698 @@
+/**************************************************************************//**
+ * @file     clk_reg.h
+ * @version  V1.00
+ * @brief    CLK register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __CLK_REG_H__
+#define __CLK_REG_H__
+
+#if defined ( __CC_ARM   )
+#pragma anon_unions
+#endif
+
+/**
+   @addtogroup REGISTER Control Register
+   @{
+*/
+
+/**
+    @addtogroup CLK System Clock Controller(CLK)
+    Memory Mapped Structure for CLK Controller
+@{ */
+
+typedef struct
+{
+
+
+    /**
+     * @var CLK_T::PWRCTL
+     * Offset: 0x00  System Power-down Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |HXTEN     |HXT Enable Bit (Write Protect)
+     * |        |          |The bit default value is set by flash controller user configuration register CONFIG0 [26]
+     * |        |          |When the default clock source is from HXT, this bit is set to 1 automatically.
+     * |        |          |0 = 4~24 MHz external high speed crystal (HXT) Disabled.
+     * |        |          |1 = 4~24 MHz external high speed crystal (HXT) Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[1]     |LXTEN     |LXT Enable Bit (Write Protect)
+     * |        |          |0 = 32.768 kHz external low speed crystal (LXT) Disabled.
+     * |        |          |1 = 32.768 kHz external low speed crystal (LXT) Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[2]     |HIRCEN    |HIRC Enable Bit (Write Protect)
+     * |        |          |0 = 12 MHz internal high speed RC oscillator (HIRC) Disabled.
+     * |        |          |1 = 12 MHz internal high speed RC oscillator (HIRC) Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[3]     |LIRCEN    |LIRC Enable Bit (Write Protect)
+     * |        |          |0 = 10 kHz internal low speed RC oscillator (LIRC) Disabled.
+     * |        |          |1 = 10 kHz internal low speed RC oscillator (LIRC) Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[4]     |PDWKDLY   |Enable the Wake-up Delay Counter (Write Protect)
+     * |        |          |When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.
+     * |        |          |The delayed clock cycle is 4096 clock cycles when chip works at 4~24 MHz external high speed crystal oscillator (HXT), and 256 clock cycles when chip works at 12 MHz internal high speed RC oscillator (HIRC).
+     * |        |          |0 = Clock cycles delay Disabled.
+     * |        |          |1 = Clock cycles delay Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[5]     |PDWKIEN   |Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)
+     * |        |          |0 = Power-down mode wake-up interrupt Disabled.
+     * |        |          |1 = Power-down mode wake-up interrupt Enabled.
+     * |        |          |Note1: The interrupt will occur when both PDWKIF and PDWKIEN are high.
+     * |        |          |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[6]     |PDWKIF    |Power-down Mode Wake-up Interrupt Status
+     * |        |          |Set by "Power-down wake-up event", it indicates that resume from Power-down mode.
+     * |        |          |The flag is set if any wake-up source is occurred. Refer Power Modes and Wake-up Sources chapter.
+     * |        |          |Note1: Write 1 to clear the bit to 0.
+     * |        |          |Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1.
+     * |[7]     |PDEN      |System Power-down Enable (Write Protect)
+     * |        |          |When this bit is set to 1, Power-down mode is enabled and chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode.
+     * |        |          |When chip wakes up from Power-down mode, this bit is auto cleared
+     * |        |          |Users need to set this bit again for next Power-down.
+     * |        |          |In Power-down mode, HXT and the HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode.
+     * |        |          |In Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection
+     * |        |          |The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC.
+     * |        |          |0 = Chip will not enter Power-down mode after CPU sleep command WFI.
+     * |        |          |1 = Chip enters Power-down mode after CPU sleep command WFI.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[11:10] |HXTGAIN   |HXT Gain Control Bit (Write Protect)
+     * |        |          |This is a protected register. Please refer to open lock sequence to program it.
+     * |        |          |Gain control is used to enlarge the gain of crystal to make sure crystal work normally
+     * |        |          |If gain control is enabled, crystal will consume more power than gain control off.
+     * |        |          |00 = HXT frequency is lower than from 8 MHz.
+     * |        |          |01 = HXT frequency is from 8 MHz to 12 MHz.
+     * |        |          |10 = HXT frequency is from 12 MHz to 16 MHz.
+     * |        |          |11 = HXT frequency is higher than 16 MHz.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[12]    |HXTSELTYP |HXT Crystal Type Select Bit (Write Protect)
+     * |        |          |This is a protected register. Please refer to open lock sequence to program it.
+     * |        |          |0 = Select INV type.
+     * |        |          |1 = Select GM type.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[13]    |HXTTBEN   |HXT Crystal TURBO Mode (Write Protect)
+     * |        |          |This is a protected register. Please refer to open lock sequence to program it.
+     * |        |          |0 = HXT Crystal TURBO mode disabled.
+     * |        |          |1 = HXT Crystal TURBO mode enabled.
+     * |[17:16] |HIRCSTBS  |HIRC Stable Count Select (Write Protect)
+     * |        |          |00 = HIRC stable count is 64 clocks.
+     * |        |          |01 = HIRC stable count is 24 clocks.
+     * |        |          |others = Reserved.
+     * |[18]    |HIRCEN    |HIRC48M Enable Bit (Write Protect)
+     * |        |          |0 = 48 MHz internal high speed RC oscillator (HIRC) Disabled.
+     * |        |          |1 = 48 MHz internal high speed RC oscillator (HIRC) Enabled.
+     * @var CLK_T::AHBCLK
+     * Offset: 0x04  AHB Devices Clock Enable Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1]     |PDMACKEN  |PDMA Controller Clock Enable Bit
+     * |        |          |0 = PDMA peripheral clock Disabled.
+     * |        |          |1 = PDMA peripheral clock Enabled.
+     * |[2]     |ISPCKEN   |Flash ISP Controller Clock Enable Bit
+     * |        |          |0 = Flash ISP peripheral clock Disabled.
+     * |        |          |1 = Flash ISP peripheral clock Enabled.
+     * |[3]     |EBICKEN   |EBI Controller Clock Enable Bit
+     * |        |          |0 = EBI peripheral clock Disabled.
+     * |        |          |1 = EBI peripheral clock Enabled.
+     * |[5]     |EMACCKEN  |Ethernet Controller Clock Enable Bit
+     * |        |          |0 = Ethernet Controller engine clock Disabled.
+     * |        |          |1 = Ethernet Controller engine clock Enabled.
+     * |[6]     |SDH0CKEN  |SD0 Controller Clock Enable Bit
+     * |        |          |0 = SD0 engine clock Disabled.
+     * |        |          |1 = SD0 engine clock Enabled.
+     * |[7]     |CRCCKEN   |CRC Generator Controller Clock Enable Bit
+     * |        |          |0 = CRC peripheral clock Disabled.
+     * |        |          |1 = CRC peripheral clock Enabled.
+     * |[10]    |HSUSBDCKEN|HSUSB Device Clock Enable Bit
+     * |        |          |0 = HSUSB device controller's clock Disabled.
+     * |        |          |1 = HSUSB device controller's clock Enabled.
+     * |[12]    |CRPTCKEN  |Cryptographic Accelerator Clock Enable Bit
+     * |        |          |0 = Cryptographic Accelerator clock Disabled.
+     * |        |          |1 = Cryptographic Accelerator clock Enabled.
+     * |[14]    |SPIMCKEN  |SPIM Controller Clock Enable Bit
+     * |        |          |0 = SPIM controller clock Disabled.
+     * |        |          |1 = SPIM controller clock Enabled.
+     * |[15]    |FMCIDLE   |Flash Memory Controller Clock Enable Bit in IDLE Mode
+     * |        |          |0 = FMC clock Disabled when chip is under IDLE mode.
+     * |        |          |1 = FMC clock Enabled when chip is under IDLE mode.
+     * |[16]    |USBHCKEN  |USB HOST Controller Clock Enable Bit
+     * |        |          |0 = USB HOST peripheral clock Disabled.
+     * |        |          |1 = USB HOST peripheral clock Enabled.
+     * |[17]    |SDH1CKEN  |SD1 Controller Clock Enable Bit
+     * |        |          |0 = SD1 engine clock Disabled.
+     * |        |          |1 = SD1 engine clock Enabled.
+     * @var CLK_T::APBCLK0
+     * Offset: 0x08  APB Devices Clock Enable Control Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WDTCKEN   |Watchdog Timer Clock Enable Bit (Write Protect)
+     * |        |          |0 = Watchdog timer clock Disabled.
+     * |        |          |1 = Watchdog timer clock Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[1]     |RTCCKEN   |Real-time-clock APB Interface Clock Enable Bit
+     * |        |          |This bit is used to control the RTC APB clock only
+     * |        |          |The RTC peripheral clock source is selected from RTCSEL(CLK_CLKSEL3[8])
+     * |        |          |It can be selected to 32.768 kHz external low speed crystal or 10 kHz internal low speed RC oscillator (LIRC).
+     * |        |          |0 = RTC clock Disabled.
+     * |        |          |1 = RTC clock Enabled.
+     * |[2]     |TMR0CKEN  |Timer0 Clock Enable Bit
+     * |        |          |0 = Timer0 clock Disabled.
+     * |        |          |1 = Timer0 clock Enabled.
+     * |[3]     |TMR1CKEN  |Timer1 Clock Enable Bit
+     * |        |          |0 = Timer1 clock Disabled.
+     * |        |          |1 = Timer1 clock Enabled.
+     * |[4]     |TMR2CKEN  |Timer2 Clock Enable Bit
+     * |        |          |0 = Timer2 clock Disabled.
+     * |        |          |1 = Timer2 clock Enabled.
+     * |[5]     |TMR3CKEN  |Timer3 Clock Enable Bit
+     * |        |          |0 = Timer3 clock Disabled.
+     * |        |          |1 = Timer3 clock Enabled.
+     * |[6]     |CLKOCKEN  |CLKO Clock Enable Bit
+     * |        |          |0 = CLKO clock Disabled.
+     * |        |          |1 = CLKO clock Enabled.
+     * |[7]     |ACMP01CKEN|Analog Comparator 0/1 Clock Enable Bit
+     * |        |          |0 = Analog comparator 0/1 clock Disabled.
+     * |        |          |1 = Analog comparator 0/1 clock Enabled.
+     * |[8]     |I2C0CKEN  |I2C0 Clock Enable Bit
+     * |        |          |0 = I2C0 clock Disabled.
+     * |        |          |1 = I2C0 clock Enabled.
+     * |[9]     |I2C1CKEN  |I2C1 Clock Enable Bit
+     * |        |          |0 = I2C1 clock Disabled.
+     * |        |          |1 = I2C1 clock Enabled.
+     * |[10]    |I2C2CKEN  |I2C2 Clock Enable Bit
+     * |        |          |0 = I2C2 clock Disabled.
+     * |        |          |1 = I2C2 clock Enabled.
+     * |[12]    |QSPI0CKEN  |QSPI0 Clock Enable Bit
+     * |        |          |0 = QSPI0 clock Disabled.
+     * |        |          |1 = QSPI0 clock Enabled.
+     * |[13]    |SPI0CKEN  |SPI0 Clock Enable Bit
+     * |        |          |0 = SPI0 clock Disabled.
+     * |        |          |1 = SPI0 clock Enabled.
+     * |[14]    |SPI1CKEN  |SPI1 Clock Enable Bit
+     * |        |          |0 = SPI1 clock Disabled.
+     * |        |          |1 = SPI1 clock Enabled.
+     * |[15]    |SPI2CKEN  |SPI2 Clock Enable Bit
+     * |        |          |0 = SPI2 clock Disabled.
+     * |        |          |1 = SPI2 clock Enabled.
+     * |[16]    |UART0CKEN |UART0 Clock Enable Bit
+     * |        |          |0 = UART0 clock Disabled.
+     * |        |          |1 = UART0 clock Enabled.
+     * |[17]    |UART1CKEN |UART1 Clock Enable Bit
+     * |        |          |0 = UART1 clock Disabled.
+     * |        |          |1 = UART1 clock Enabled.
+     * |[18]    |UART2CKEN |UART2 Clock Enable Bit
+     * |        |          |0 = UART2 clock Disabled.
+     * |        |          |1 = UART2 clock Enabled.
+     * |[19]    |UART3CKEN |UART3 Clock Enable Bit
+     * |        |          |0 = UART3 clock Disabled.
+     * |        |          |1 = UART3 clock Enabled.
+     * |[20]    |UART4CKEN |UART4 Clock Enable Bit
+     * |        |          |0 = UART4 clock Disabled.
+     * |        |          |1 = UART4 clock Enabled.
+     * |[21]    |UART5CKEN |UART5 Clock Enable Bit
+     * |        |          |0 = UART5 clock Disabled.
+     * |        |          |1 = UART5 clock Enabled.
+     * |[24]    |CAN0CKEN  |CAN0 Clock Enable Bit
+     * |        |          |0 = CAN0 clock Disabled.
+     * |        |          |1 = CAN0 clock Enabled.
+     * |[25]    |CAN1CKEN  |CAN1 Clock Enable Bit
+     * |        |          |0 = CAN1 clock Disabled.
+     * |        |          |1 = CAN1 clock Enabled.
+     * |[26]    |OTGCKEN   |USB OTG Clock Enable Bit
+     * |        |          |0 = USB OTG clock Disabled.
+     * |        |          |1 = USB OTG clock Enabled.
+     * |[27]    |USBDCKEN  |USB Device Clock Enable Bit
+     * |        |          |0 = USB Device clock Disabled.
+     * |        |          |1 = USB Device clock Enabled.
+     * |[28]    |EADCCKEN  |Enhanced Analog-digital-converter (EADC) Clock Enable Bit
+     * |        |          |0 = EADC clock Disabled.
+     * |        |          |1 = EADC clock Enabled.
+     * |[29]    |I2S0CKEN  |I2S0 Clock Enable Bit
+     * |        |          |0 = I2S0 Clock Disabled.
+     * |        |          |1 = I2S0 Clock Enabled.
+     * |[30]    |HSOTGCKEN |HSUSB OTG Clock Enable Bit
+     * |        |          |0 = HSUSB OTG clock Disabled.
+     * |        |          |1 = HSUSB OTG clock Enabled.
+     * @var CLK_T::APBCLK1
+     * Offset: 0x0C  APB Devices Clock Enable Control Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SC0CKEN   |SC0 Clock Enable Bit
+     * |        |          |0 = SC0 clock Disabled.
+     * |        |          |1 = SC0 clock Enabled.
+     * |[1]     |SC1CKEN   |SC1 Clock Enable Bit
+     * |        |          |0 = SC1 clock Disabled.
+     * |        |          |1 = SC1 clock Enabled.
+     * |[2]     |SC2CKEN   |SC2 Clock Enable Bit
+     * |        |          |0 = SC2 clock Disabled.
+     * |        |          |1 = SC2 clock Enabled.
+     * |[6]     |SPI3CKEN  |SPI3 Clock Enable Bit
+     * |        |          |0 = SPI3 clock Disabled.
+     * |        |          |1 = SPI3 clock Enabled.
+     * |[8]     |USCI0CKEN |USCI0 Clock Enable Bit
+     * |        |          |0 = USCI0 clock Disabled.
+     * |        |          |1 = USCI0 clock Enabled.
+     * |[9]     |USCI1CKEN |USCI1 Clock Enable Bit
+     * |        |          |0 = USCI1 clock Disabled.
+     * |        |          |1 = USCI1 clock Enabled.
+     * |[12]    |DACCKEN   |DAC Clock Enable Bit
+     * |        |          |0 = DAC clock Disabled.
+     * |        |          |1 = DAC clock Enabled.
+     * |[16]    |EPWM0CKEN |EPWM0 Clock Enable Bit
+     * |        |          |0 = EPWM0 clock Disabled.
+     * |        |          |1 = EPWM0 clock Enabled.
+     * |[17]    |EPWM1CKEN |EPWM1 Clock Enable Bit
+     * |        |          |0 = EPWM1 clock Disabled.
+     * |        |          |1 = EPWM1 clock Enabled.
+     * |[18]    |BPWM0CKEN |BPWM0 Clock Enable Bit
+     * |        |          |0 = BPWM0 clock Disabled.
+     * |        |          |1 = BPWM0 clock Enabled.
+     * |[19]    |BPWM1CKEN |BPWM1 Clock Enable Bit
+     * |        |          |0 = BPWM1 clock Disabled.
+     * |        |          |1 = BPWM1 clock Enabled.
+     * |[22]    |QEI0CKEN  |QEI0 Clock Enable Bit
+     * |        |          |0 = QEI0 clock Disabled.
+     * |        |          |1 = QEI0 clock Enabled.
+     * |[23]    |QEI1CKEN  |QEI1 Clock Enable Bit
+     * |        |          |0 = QEI1 clock Disabled.
+     * |        |          |1 = QEI1 clock Enabled.
+     * |[26]    |ECAP0CKEN |ECAP0 Clock Enable Bit
+     * |        |          |0 = ECAP0 clock Disabled.
+     * |        |          |1 = ECAP0 clock Enabled.
+     * |[27]    |ECAP1CKEN |ECAP1 Clock Enable Bit
+     * |        |          |0 = ECAP1 clock Disabled.
+     * |        |          |1 = ECAP1 clock Enabled.
+     * |[30]    |OPACKEN   |OP Amplifier (OPA) Clock Enable Bit
+     * |        |          |0 = OPA clock Disabled.
+     * |        |          |1 = OPA clock Enabled.
+     * @var CLK_T::CLKSEL0
+     * Offset: 0x10  Clock Source Select Control Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |HCLKSEL   |HCLK Clock Source Selection (Write Protect)
+     * |        |          |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on.
+     * |        |          |The default value is reloaded from the value of CFOSC (CONFIG0[26]) in user configuration register of Flash controller by any reset
+     * |        |          |Therefore the default value is either 000b or 111b.
+     * |        |          |000 = Clock source from HXT.
+     * |        |          |001 = Clock source from LXT.
+     * |        |          |010 = Clock source from PLL.
+     * |        |          |011 = Clock source from LIRC.
+     * |        |          |111 = Clock source from HIRC.
+     * |        |          |Other = Reserved.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[5:3]   |STCLKSEL  |Cortex-M4 SysTick Clock Source Selection (Write Protect)
+     * |        |          |If SYST_CTRL[2]=0, SysTick uses listed clock source below.
+     * |        |          |000 = Clock source from HXT.
+     * |        |          |001 = Clock source from LXT.
+     * |        |          |010 = Clock source from HXT/2.
+     * |        |          |011 = Clock source from HCLK/2.
+     * |        |          |111 = Clock source from HIRC/2.
+     * |        |          |Note: if SysTick clock source is not from HCLK (i.e
+     * |        |          |SYST_CTRL[2] = 0), SysTick clock source must less than or equal to HCLK/2.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[8]     |USBSEL    |USB Clock Source Selection (Write Protect)
+     * |        |          |0 = Clock source from RC48M.
+     * |        |          |1 = Clock source from PLL.
+     * |[21:20] |SDH0SEL   |SD0 Engine Clock Source Selection (Write Protect)
+     * |        |          |00 = Clock source from HXT clock.
+     * |        |          |01 = Clock source from PLL clock.
+     * |        |          |10 = Clock source from HCLK.
+     * |        |          |11 = Clock source from HIRC clock.
+     * |[23:22] |SDH1SEL   |SD1 Engine Clock Source Selection (Write Protect)
+     * |        |          |00 = Clock source from HXT clock.
+     * |        |          |01 = Clock source from PLL clock.
+     * |        |          |10 = Clock source from HCLK.
+     * |        |          |11 = Clock source from HIRC clock.
+     * @var CLK_T::CLKSEL1
+     * Offset: 0x14  Clock Source Select Control Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |WDTSEL    |Watchdog Timer Clock Source Selection (Write Protect)
+     * |        |          |00 = Reserved.
+     * |        |          |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |10 = Clock source from HCLK/2048.
+     * |        |          |11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[10:8]  |TMR0SEL   |TIMER0 Clock Source Selection
+     * |        |          |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |010 = Clock source from PCLK0.
+     * |        |          |011 = Clock source from external clock TM0 pin.
+     * |        |          |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).
+     * |        |          |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |        |          |Others = Reserved.
+     * |[14:12] |TMR1SEL   |TIMER1 Clock Source Selection
+     * |        |          |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |010 = Clock source from PCLK0.
+     * |        |          |011 = Clock source from external clock TM1 pin.
+     * |        |          |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).
+     * |        |          |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |        |          |Others = Reserved.
+     * |[18:16] |TMR2SEL   |TIMER2 Clock Source Selection
+     * |        |          |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |010 = Clock source from PCLK1.
+     * |        |          |011 = Clock source from external clock TM2 pin.
+     * |        |          |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).
+     * |        |          |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |        |          |Others = Reserved.
+     * |[22:20] |TMR3SEL   |TIMER3 Clock Source Selection
+     * |        |          |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |010 = Clock source from PCLK1.
+     * |        |          |011 = Clock source from external clock TM3 pin.
+     * |        |          |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).
+     * |        |          |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |        |          |Others = Reserved.
+     * |[25:24] |UART0SEL  |UART0 Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from PLL.
+     * |        |          |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |[27:26] |UART1SEL  |UART1 Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from PLL.
+     * |        |          |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |[29:28] |CLKOSEL   |Clock Divider Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |10 = Clock source from HCLK.
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |[31:30] |WWDTSEL   |Window Watchdog Timer Clock Source Selection
+     * |        |          |10 = Clock source from HCLK/2048.
+     * |        |          |11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).
+     * |        |          |Others = Reserved.
+     * @var CLK_T::CLKSEL2
+     * Offset: 0x18  Clock Source Select Control Register 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |EPWM0SEL  |EPWM0 Clock Source Selection
+     * |        |          |The peripheral clock source of EPWM0 is defined by EPWM0SEL.
+     * |        |          |0 = Clock source from PLL.
+     * |        |          |1 = Clock source from PCLK0.
+     * |[1]     |EPWM1SEL  |EPWM1 Clock Source Selection
+     * |        |          |The peripheral clock source of EPWM1 is defined by EPWM1SEL.
+     * |        |          |0 = Clock source from PLL.
+     * |        |          |1 = Clock source from PCLK1.
+     * |[3:2]   |QSPI0SEL   |QSPI0 Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from PLL.
+     * |        |          |10 = Clock source from PCLK0.
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |[5:4]   |SPI0SEL   |SPI0 Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from PLL.
+     * |        |          |10 = Clock source from PCLK1.
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |[7:6]   |SPI1SEL   |SPI1 Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from PLL.
+     * |        |          |10 = Clock source from PCLK0.
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |[8]     |BPWM0SEL  |BPWM0 Clock Source Selection
+     * |        |          |The peripheral clock source of BPWM0 is defined by BPWM0SEL.
+     * |        |          |0 = Clock source from PLL.
+     * |        |          |1 = Clock source from PCLK0.
+     * |[9]     |BPWM1SEL  |BPWM1 Clock Source Selection
+     * |        |          |The peripheral clock source of BPWM1 is defined by BPWM1SEL.
+     * |        |          |0 = Clock source from PLL.
+     * |        |          |1 = Clock source from PCLK1.
+     * |[11:10] |SPI2SEL   |SPI2 Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from PLL.
+     * |        |          |10 = Clock source from PCLK1.
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |[13:12] |SPI3SEL   |SPI3 Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from PLL.
+     * |        |          |10 = Clock source from PCLK0.
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * @var CLK_T::CLKSEL3
+     * Offset: 0x1C  Clock Source Select Control Register 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |SC0SEL    |SC0 Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from PLL.
+     * |        |          |10 = Clock source from PCLK0.
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |[3:2]   |SC1SEL    |SC0 Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from PLL.
+     * |        |          |10 = Clock source from PCLK1.
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |[5:4]   |SC2SEL    |SC2 Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from PLL.
+     * |        |          |10 = Clock source from PCLK0.
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |[8]     |RTCSEL    |RTC Clock Source Selection
+     * |        |          |0 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |1 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).
+     * |[17:16] |I2S0SEL   |I2S0 Clock Source Selection
+     * |        |          |00 = Clock source from HXT clock.
+     * |        |          |01 = Clock source from PLL clock.
+     * |        |          |10 = Clock source from PCLK.
+     * |        |          |11 = Clock source from HIRC clock.
+     * |[25:24] |UART2SEL  |UART2 Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from PLL.
+     * |        |          |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |[27:26] |UART3SEL  |UART3 Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from PLL.
+     * |        |          |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |[29:28] |UART4SEL  |UART4 Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from PLL.
+     * |        |          |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |[31:30] |UART5SEL  |UART5 Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from PLL.
+     * |        |          |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * @var CLK_T::CLKDIV0
+     * Offset: 0x20  Clock Divider Number Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |HCLKDIV   |HCLK Clock Divide Number From HCLK Clock Source
+     * |        |          |HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1).
+     * |[7:4]   |USBDIV    |USB Clock Divide Number From PLL Clock
+     * |        |          |USB clock frequency = (PLL frequency) / (USBDIV + 1).
+     * |[11:8]  |UART0DIV  |UART0 Clock Divide Number From UART0 Clock Source
+     * |        |          |UART0 clock frequency = (UART0 clock source frequency) / (UART0DIV + 1).
+     * |[15:12] |UART1DIV  |UART1 Clock Divide Number From UART1 Clock Source
+     * |        |          |UART1 clock frequency = (UART1 clock source frequency) / (UART1DIV + 1).
+     * |[23:16] |EADCDIV   |EADC Clock Divide Number From EADC Clock Source
+     * |        |          |EADC clock frequency = (EADC clock source frequency) / (EADCDIV + 1).
+     * |[31:24] |SDH0DIV   |SD0 Clock Divide Number From SD0 Clock Source
+     * |        |          |SD0 clock frequency = (SD0 clock source frequency) / (SDH0DIV + 1).
+     * @var CLK_T::CLKDIV1
+     * Offset: 0x24  Clock Divider Number Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |SC0DIV    |SC0 Clock Divide Number From SC0 Clock Source
+     * |        |          |SC0 clock frequency = (SC0 clock source frequency ) / (SC0DIV + 1).
+     * |[15:8]  |SC1DIV    |SC1 Clock Divide Number From SC1 Clock Source
+     * |        |          |SC1 clock frequency = (SC1 clock source frequency ) / (SC1DIV + 1).
+     * |[23:16] |SC2DIV    |SC2 Clock Divide Number From SC2 Clock Source
+     * |        |          |SC2 clock frequency = (SC2 clock source frequency ) / (SC2DIV + 1).
+     * @var CLK_T::CLKDIV3
+     * Offset: 0x2C  Clock Divider Number Register 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:16] |EMACDIV   |Ethernet Clock Divide Number Form HCLK
+     * |        |          |EMAC MDCLK clock frequency = (HCLK) / (EMACDIV + 1).
+     * |[31:24] |SDH1DIV   |SD1 Clock Divide Number From SD1 Clock Source
+     * |        |          |SD1 clock frequency = (SD1 clock source frequency) / (SDH1DIV + 1).
+     * @var CLK_T::CLKDIV4
+     * Offset: 0x30  Clock Divider Number Register 4
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |UART2DIV  |UART2 Clock Divide Number From UART2 Clock Source
+     * |        |          |UART2 clock frequency = (UART2 clock source frequency) / (UART2DIV + 1).
+     * |[7:4]   |UART3DIV  |UART3 Clock Divide Number From UART3 Clock Source
+     * |        |          |UART3 clock frequency = (UART3 clock source frequency) / (UART3DIV + 1).
+     * |[11:8]  |UART4DIV  |UART4 Clock Divide Number From UART4 Clock Source
+     * |        |          |UART4 clock frequency = (UART4 clock source frequency) / (UART4DIV + 1).
+     * |[15:12] |UART5DIV  |UART5 Clock Divide Number From UART5 Clock Source
+     * |        |          |UART5 clock frequency = (UART5 clock source frequency) / (UART5DIV + 1).
+     * @var CLK_T::PCLKDIV
+     * Offset: 0x34  APB Clock Divider Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |APB0DIV   |APB0 Clock Divider
+     * |        |          |APB0 clock can be divided from HCLK
+     * |        |          |000: PCLK0 = HCLK.
+     * |        |          |001: PCLK0 = 1/2 HCLK.
+     * |        |          |010: PCLK0 = 1/4 HCLK.
+     * |        |          |011: PCLK0 = 1/8 HCLK.
+     * |        |          |100: PCLK0 = 1/16 HCLK.
+     * |        |          |Others: Reserved.
+     * |[6:4]   |APB1DIV   |APB1 Clock Divider
+     * |        |          |APB1 clock can be divided from HCLK
+     * |        |          |000: PCLK1 = HCLK.
+     * |        |          |001: PCLK1 = 1/2 HCLK.
+     * |        |          |010: PCLK1 = 1/4 HCLK.
+     * |        |          |011: PCLK1 = 1/8 HCLK.
+     * |        |          |100: PCLK1 = 1/16 HCLK.
+     * |        |          |Others: Reserved.
+     * @var CLK_T::PLLCTL
+     * Offset: 0x40  PLL Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[8:0]   |FBDIV     |PLL Feedback Divider Control (Write Protect)
+     * |        |          |Refer to the formulas below the table.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[13:9]  |INDIV     |PLL Input Divider Control (Write Protect)
+     * |        |          |Refer to the formulas below the table.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[15:14] |OUTDIV    |PLL Output Divider Control (Write Protect)
+     * |        |          |Refer to the formulas below the table.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[16]    |PD        |Power-down Mode (Write Protect)
+     * |        |          |If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too.
+     * |        |          |0 = PLL is in normal mode.
+     * |        |          |1 = PLL is in Power-down mode (default).
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[17]    |BP        |PLL Bypass Control (Write Protect)
+     * |        |          |0 = PLL is in normal mode (default).
+     * |        |          |1 = PLL clock output is same as PLL input clock FIN.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[18]    |OE        |PLL OE (FOUT Enable) Pin Control (Write Protect)
+     * |        |          |0 = PLL FOUT Enabled.
+     * |        |          |1 = PLL FOUT is fixed low.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[19]    |PLLSRC    |PLL Source Clock Selection (Write Protect)
+     * |        |          |0 = PLL source clock from 4~24 MHz external high-speed crystal oscillator (HXT).
+     * |        |          |1 = PLL source clock from 12 MHz internal high-speed oscillator (HIRC).
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[23]    |STBSEL    |PLL Stable Counter Selection (Write Protect)
+     * |        |          |0 = PLL stable time is 6144 PLL source clock (suitable for source clock is equal to or less than 12 MHz).
+     * |        |          |1 = PLL stable time is 12288 PLL source clock (suitable for source clock is larger than 12 MHz).
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * @var CLK_T::STATUS
+     * Offset: 0x50  Clock Status Monitor Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |HXTSTB    |HXT Clock Source Stable Flag (Read Only)
+     * |        |          |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled.
+     * |        |          |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock is stable and enabled.
+     * |[1]     |LXTSTB    |LXT Clock Source Stable Flag (Read Only)
+     * |        |          |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled.
+     * |        |          |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled.
+     * |[2]     |PLLSTB    |Internal PLL Clock Source Stable Flag (Read Only)
+     * |        |          |0 = Internal PLL clock is not stable or disabled.
+     * |        |          |1 = Internal PLL clock is stable and enabled.
+     * |[3]     |LIRCSTB   |LIRC Clock Source Stable Flag (Read Only)
+     * |        |          |0 = 10 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled.
+     * |        |          |1 = 10 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled.
+     * |[4]     |HIRCSTB   |HIRC Clock Source Stable Flag (Read Only)
+     * |        |          |0 = 12 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled.
+     * |        |          |1 = 12 MHz internal high speed RC oscillator (HIRC) clock is stable and enabled.
+     * |        |          |Note: This bit is read only.
+     * |[6]     |HIRC48MSTB|HIRC 48MHz Clock Source Stable Flag (Read Only)
+     * |        |          |0 = 48 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled.
+     * |        |          |1 = 48 MHz internal high speed RC oscillator (HIRC) clock is stable and enabled.
+     * |        |          |Note: This bit is read only.
+     * |[7]     |CLKSFAIL  |Clock Switching Fail Flag (Read Only)
+     * |        |          |This bit is updated when software switches system clock source
+     * |        |          |If switch target clock is stable, this bit will be set to 0
+     * |        |          |If switch target clock is not stable, this bit will be set to 1.
+     * |        |          |0 = Clock switching success.
+     * |        |          |1 = Clock switching failure.
+     * |        |          |Note: Write 1 to clear the bit to 0.
+     * @var CLK_T::CLKOCTL
+     * Offset: 0x60  Clock Output Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |FREQSEL   |Clock Output Frequency Selection
+     * |        |          |The formula of output frequency is
+     * |        |          |Fout = Fin/2(N+1).
+     * |        |          |Fin is the input clock frequency.
+     * |        |          |Fout is the frequency of divider output clock.
+     * |        |          |N is the 4-bit value of FREQSEL[3:0].
+     * |[4]     |CLKOEN    |Clock Output Enable Bit
+     * |        |          |0 = Clock Output function Disabled.
+     * |        |          |1 = Clock Output function Enabled.
+     * |[5]     |DIV1EN    |Clock Output Divide One Enable Bit
+     * |        |          |0 = Clock Output will output clock with source frequency divided by FREQSEL.
+     * |        |          |1 = Clock Output will output clock with source frequency.
+     * |[6]     |CLK1HZEN  |Clock Output 1Hz Enable Bit
+     * |        |          |0 = 1 Hz clock output for 32.768 kHz frequency compensation Disabled.
+     * |        |          |1 = 1 Hz clock output for 32.768 kHz frequency compensation Enabled.
+     * @var CLK_T::CLKDCTL
+     * Offset: 0x70  Clock Fail Detector Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[4]     |HXTFDEN   |HXT Clock Fail Detector Enable Bit
+     * |        |          |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Disabled.
+     * |        |          |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Enabled.
+     * |[5]     |HXTFIEN   |HXT Clock Fail Interrupt Enable Bit
+     * |        |          |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Disabled.
+     * |        |          |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Enabled.
+     * |[12]    |LXTFDEN   |LXT Clock Fail Detector Enable Bit
+     * |        |          |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Disabled.
+     * |        |          |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Enabled.
+     * |[13]    |LXTFIEN   |LXT Clock Fail Interrupt Enable Bit
+     * |        |          |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Disabled.
+     * |        |          |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Enabled.
+     * |[16]    |HXTFQDEN  |HXT Clock Frequency Range Detector Enable Bit
+     * |        |          |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector Disabled.
+     * |        |          |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector Enabled.
+     * |[17]    |HXTFQIEN  |HXT Clock Frequency Range Detector Interrupt Enable Bit
+     * |        |          |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Disabled.
+     * |        |          |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Enabled.
+     * @var CLK_T::CLKDSTS
+     * Offset: 0x74  Clock Fail Detector Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |HXTFIF    |HXT Clock Fail Interrupt Flag
+     * |        |          |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is normal.
+     * |        |          |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock stops.
+     * |        |          |Note: Write 1 to clear the bit to 0.
+     * |[1]     |LXTFIF    |LXT Clock Fail Interrupt Flag
+     * |        |          |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is normal.
+     * |        |          |1 = 32.768 kHz external low speed crystal oscillator (LXT) stops.
+     * |        |          |Note: Write 1 to clear the bit to 0.
+     * |[8]     |HXTFQIF   |HXT Clock Frequency Range Detector Interrupt Flag
+     * |        |          |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency is normal.
+     * |        |          |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency is abnormal.
+     * |        |          |Note: Write 1 to clear the bit to 0.
+     * @var CLK_T::CDUPB
+     * Offset: 0x78  Clock Frequency Range Detector Upper Boundary Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[9:0]   |UPERBD    |HXT Clock Frequency Range Detector Upper Boundary Value
+     * |        |          |The bits define the maximum value of frequency range detector window.
+     * |        |          |When HXT frequency higher than this maximum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1.
+     * @var CLK_T::CDLOWB
+     * Offset: 0x7C  Clock Frequency Range Detector Lower Boundary Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[9:0]   |LOWERBD   |HXT Clock Frequency Range Detector Lower Boundary Value
+     * |        |          |The bits define the minimum value of frequency range detector window.
+     * |        |          |When HXT frequency lower than this minimum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1.
+     * @var CLK_T::PMUCTL
+     * Offset: 0x90  Power Manager Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |PDMSEL    |Power-down Mode Selection (Write Protect)
+     * |        |          |This is a protected register. Please refer to open lock sequence to program it.
+     * |        |          |These bits control chip power-down mode grade selection when CPU execute WFI/WFE instruction.
+     * |        |          |000 = Power-down mode is selected. (PD)
+     * |        |          |001 = Low leakage Power-down mode is selected (LLPD).
+     * |        |          |010 =Fast wake-up Power-down mode is selected (FWPD).
+     * |        |          |011 = Reserved.
+     * |        |          |100 = Standby Power-down mode 0 is selected (SPD0) (SRAM retention).
+     * |        |          |101 = Standby Power-down mode 1 is selected (SPD1).
+     * |        |          |110 = Deep Power-down mode is selected (DPD).
+     * |        |          |111 = Reserved.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[3]     |DPDHOLDEN |Deep-Power-Down Mode GPIO Hold Enable
+     * |        |          |0 = When GPIO enters deep power-down mode, all I/O status are tri-state.
+     * |        |          |1 = When GPIO enters deep power-down mode, all I/O status are hold to keep normal operating status.
+     * |        |          |    After chip was waked up from deep power-down mode, the I/O are still keep hold status until user set CLK_IOPDCTL[0]
+     * |        |          |    to release I/O hold status.
+     * |[8]     |WKTMREN   |Wake-up Timer Enable (Write Protect)
+     * |        |          |This is a protected register. Please refer to open lock sequence to program it.
+     * |        |          |0 = Wake-up timer disable at DPD/SPD mode.
+     * |        |          |1 = Wake-up timer enabled at DPD/SPD mode.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[11:9]  |WKTMRIS   |Wake-up Timer Time-out Interval Select (Write Protect)
+     * |        |          |This is a protected register. Please refer to open lock sequence to program it.
+     * |        |          |These bits control wake-up timer time-out interval when chip at DPD/SPD mode.
+     * |        |          |000 = Time-out interval is 128 OSC10K clocks (12.8 ms).
+     * |        |          |001 = Time-out interval is 256 OSC10K clocks (25.6 ms).
+     * |        |          |010 = Time-out interval is 512 OSC10K clocks (51.2 ms).
+     * |        |          |011 = Time-out interval is 1024 OSC10K clocks (102.4ms).
+     * |        |          |100 = Time-out interval is 4096 OSC10K clocks (409.6ms).
+     * |        |          |101 = Time-out interval is 8192 OSC10K clocks (819.2ms).
+     * |        |          |110 = Time-out interval is 16384 OSC10K clocks (1638.4ms).
+     * |        |          |111 = Time-out interval is 65536 OSC10K clocks (6553.6ms).
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[17:16] |WKPINEN   |Wake-up Pin Enable (Write Protect)
+     * |        |          |This is a protected register. Please refer to open lock sequence to program it.
+     * |        |          |00 = Wake-up pin disable at Deep Power-down mode.
+     * |        |          |01 = Wake-up pin rising edge enabled at Deep Power-down mode.
+     * |        |          |10 = Wake-up pin falling edge enabled at Deep Power-down mode.
+     * |        |          |11 = Wake-up pin both edge enabled at Deep Power-down mode.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[18]    |ACMPSPWK  |ACMP Standby Power-down Mode Wake-up Enable (Write Protect)
+     * |        |          |This is a protected register. Please refer to open lock sequence to program it.
+     * |        |          |0 = ACMP wake-up disable at Standby Power-down mode.
+     * |        |          |1 = ACMP wake-up enabled at Standby Power-down mode.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[23]    |RTCWKEN   |RTC Wake-up Enable (Write Protect)
+     * |        |          |This is a protected register. Please refer to open lock sequence to program it.
+     * |        |          |0 = RTC wake-up disable at Deep Power-down mode or Standby Power-down mode.
+     * |        |          |1 = RTC wake-up enabled at Deep Power-down mode or Standby Power-down mode.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * @var CLK_T::PMUSTS
+     * Offset: 0x94  Power Manager Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |PINWK     |Pin Wake-up Flag (Read Only)
+     * |        |          |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (GPC.0)
+     * |        |          |This flag is cleared when DPD mode is entered.
+     * |[1]     |TMRWK     |Timer Wake-up Flag (Read Only)
+     * |        |          |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested by wakeup timer time-out
+     * |        |          |This flag is cleared when DPD or SPD mode is entered.
+     * |[2]     |RTCWK     |RTC Wake-up Flag (Read Only)
+     * |        |          |This flag indicates that wakeup of device from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested with a RTC alarm, tick time or tamper happened
+     * |        |          |This flag is cleared when DPD or SPD mode is entered.
+     * |[8]     |GPAWK     |GPA Wake-up Flag (Read Only)
+     * |        |          |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPA group pins
+     * |        |          |This flag is cleared when SPD mode is entered.
+     * |[9]     |GPBWK     |GPB Wake-up Flag (Read Only)
+     * |        |          |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPB group pins
+     * |        |          |This flag is cleared when SPD mode is entered.
+     * |[10]    |GPCWK     |GPC Wake-up Flag (Read Only)
+     * |        |          |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPC group pins
+     * |        |          |This flag is cleared when SPD mode is entered.
+     * |[11]    |GPDWK     |GPD Wake-up Flag (Read Only)
+     * |        |          |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPD group pins
+     * |        |          |This flag is cleared when SPD mode is entered.
+     * |[12]    |LVRWK     |LVR Wake-up Flag (Read Only)
+     * |        |          |This flag indicates that wakeup of device from Standby Power-down mode was requested with a LVR happened
+     * |        |          |This flag is cleared when SPD mode is entered.
+     * |[13]    |BODWK     |BOD Wake-up Flag (Read Only)
+     * |        |          |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a BOD happened
+     * |        |          |This flag is cleared when SPD mode is entered.
+     * |[14]    |ACMPWK    |ACMP Wake-up Flag (Read Only)
+     * |        |          |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a ACMP transition
+     * |        |          |This flag is cleared when SPD mode is entered.
+     * |[31]    |CLRWK     |Clear Wake-up Flag
+     * |        |          |0 = No clear.
+     * |        |          |1 = Clear all wake-up flag.
+     * @var CLK_T::LDOCTL
+     * Offset: 0x98  LDO Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[18]    |PDBIASEN  |Power-down Bias Enable Bit
+     * |        |          |0 = Reserved.
+     * |        |          |1 = Power-down bias enabled.
+     * |        |          |Note: This bit should set to 1 before chip enter power-down mode.
+     * @var CLK_T::SWKDBCTL
+     * Offset: 0x9C  Standby Power-down Wake-up De-bounce Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |SWKDBCLKSEL|Standby Power-down Wake-up De-bounce Sampling Cycle Selection
+     * |        |          |0000 = Sample wake-up input once per 1 clocks.
+     * |        |          |0001 = Sample wake-up input once per 2 clocks.
+     * |        |          |0010 = Sample wake-up input once per 4 clocks.
+     * |        |          |0011 = Sample wake-up input once per 8 clocks.
+     * |        |          |0100 = Sample wake-up input once per 16 clocks.
+     * |        |          |0101 = Sample wake-up input once per 32 clocks.
+     * |        |          |0110 = Sample wake-up input once per 64 clocks.
+     * |        |          |0111 = Sample wake-up input once per 128 clocks.
+     * |        |          |1000 = Sample wake-up input once per 256 clocks.
+     * |        |          |1001 = Sample wake-up input once per 2*256 clocks.
+     * |        |          |1010 = Sample wake-up input once per 4*256 clocks.
+     * |        |          |1011 = Sample wake-up input once per 8*256 clocks.
+     * |        |          |1100 = Sample wake-up input once per 16*256 clocks.
+     * |        |          |1101 = Sample wake-up input once per 32*256 clocks.
+     * |        |          |1110 = Sample wake-up input once per 64*256 clocks.
+     * |        |          |1111 = Sample wake-up input once per 128*256 clocks.
+     * |        |          |Note: De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC).
+     * @var CLK_T::PASWKCTL
+     * Offset: 0xA0  GPA Standby Power-down Wake-up Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WKEN      |Standby Power-down Pin Wake-up Enable Bit
+     * |        |          |0 = GPA group pin wake-up function disabled.
+     * |        |          |1 = GPA group pin wake-up function enabled.
+     * |[1]     |PRWKEN    |Pin Rising Edge Wake-up Enable Bit
+     * |        |          |0 = GPA group pin rising edge wake-up function disabled.
+     * |        |          |1 = GPA group pin rising edge wake-up function enabled.
+     * |[2]     |PFWKEN    |Pin Falling Edge Wake-up Enable Bit
+     * |        |          |0 = GPA group pin falling edge wake-up function disabled.
+     * |        |          |1 = GPA group pin falling edge wake-up function enabled.
+     * |[7:4]   |WKPSEL    |GPA Standby Power-down Wake-up Pin Select
+     * |        |          |0000 = GPA.0 wake-up function enabled.
+     * |        |          |0001 = GPA.1 wake-up function enabled.
+     * |        |          |0010 = GPA.2 wake-up function enabled.
+     * |        |          |0011 = GPA.3 wake-up function enabled.
+     * |        |          |0100 = GPA.4 wake-up function enabled.
+     * |        |          |0101 = GPA.5 wake-up function enabled.
+     * |        |          |0110 = GPA.6 wake-up function enabled.
+     * |        |          |0111 = GPA.7 wake-up function enabled.
+     * |        |          |1000 = GPA.8 wake-up function enabled.
+     * |        |          |1001 = GPA.9 wake-up function enabled.
+     * |        |          |1010 = GPA.10 wake-up function enabled.
+     * |        |          |1011 = GPA.11 wake-up function enabled.
+     * |        |          |1100 = GPA.12 wake-up function enabled.
+     * |        |          |1101 = GPA.13 wake-up function enabled.
+     * |        |          |1110 = GPA.14 wake-up function enabled.
+     * |        |          |1111 = GPA.15 wake-up function enabled.
+     * |[8]     |DBEN      |GPA Input Signal De-bounce Enable Bit
+     * |        |          |The DBEN bit is used to enable the de-bounce function for each corresponding IO
+     * |        |          |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up
+     * |        |          |The de-bounce clock source is the 10 kHz internal low speed RC oscillator.
+     * |        |          |0 = Standby power-down wake-up pin De-bounce function disable.
+     * |        |          |1 = Standby power-down wake-up pin De-bounce function enable.
+     * |        |          |The de-bounce function is valid only for edge triggered.
+     * @var CLK_T::PBSWKCTL
+     * Offset: 0xA4  GPB Standby Power-down Wake-up Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WKEN      |Standby Power-down Pin Wake-up Enable Bit
+     * |        |          |0 = GPB group pin wake-up function disabled.
+     * |        |          |1 = GPB group pin wake-up function enabled.
+     * |[1]     |PRWKEN    |Pin Rising Edge Wake-up Enable Bit
+     * |        |          |0 = GPB group pin rising edge wake-up function disabled.
+     * |        |          |1 = GPB group pin rising edge wake-up function enabled.
+     * |[2]     |PFWKEN    |Pin Falling Edge Wake-up Enable Bit
+     * |        |          |0 = GPB group pin falling edge wake-up function disabled.
+     * |        |          |1 = GPB group pin falling edge wake-up function enabled.
+     * |[7:4]   |WKPSEL    |GPB Standby Power-down Wake-up Pin Select
+     * |        |          |0000 = GPB.0 wake-up function enabled.
+     * |        |          |0001 = GPB.1 wake-up function enabled.
+     * |        |          |0010 = GPB.2 wake-up function enabled.
+     * |        |          |0011 = GPB.3 wake-up function enabled.
+     * |        |          |0100 = GPB.4 wake-up function enabled.
+     * |        |          |0101 = GPB.5 wake-up function enabled.
+     * |        |          |0110 = GPB.6 wake-up function enabled.
+     * |        |          |0111 = GPB.7 wake-up function enabled.
+     * |        |          |1000 = GPB.8 wake-up function enabled.
+     * |        |          |1001 = GPB.9 wake-up function enabled.
+     * |        |          |1010 = GPB.10 wake-up function enabled.
+     * |        |          |1011 = GPB.11 wake-up function enabled.
+     * |        |          |1100 = GPB.12 wake-up function enabled.
+     * |        |          |1101 = GPB.13 wake-up function enabled.
+     * |        |          |1110 = GPB.14 wake-up function enabled.
+     * |        |          |1111 = GPB.15 wake-up function enabled.
+     * |[8]     |DBEN      |GPB Input Signal De-bounce Enable Bit
+     * |        |          |The DBEN bit is used to enable the de-bounce function for each corresponding IO
+     * |        |          |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up
+     * |        |          |The de-bounce clock source is the 10 kHz internal low speed RC oscillator.
+     * |        |          |0 = Standby power-down wake-up pin De-bounce function disable.
+     * |        |          |1 = Standby power-down wake-up pin De-bounce function enable.
+     * |        |          |The de-bounce function is valid only for edge triggered.
+     * @var CLK_T::PCSWKCTL
+     * Offset: 0xA8  GPC Standby Power-down Wake-up Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WKEN      |Standby Power-down Pin Wake-up Enable Bit
+     * |        |          |0 = GPC group pin wake-up function disabled.
+     * |        |          |1 = GPC group pin wake-up function enabled.
+     * |[1]     |PRWKEN    |Pin Rising Edge Wake-up Enable Bit
+     * |        |          |0 = GPC group pin rising edge wake-up function disabled.
+     * |        |          |1 = GPC group pin rising edge wake-up function enabled.
+     * |[2]     |PFWKEN    |Pin Falling Edge Wake-up Enable Bit
+     * |        |          |0 = GPC group pin falling edge wake-up function disabled.
+     * |        |          |1 = GPC group pin falling edge wake-up function enabled.
+     * |[7:4]   |WKPSEL    |GPC Standby Power-down Wake-up Pin Select
+     * |        |          |0000 = GPC.0 wake-up function enabled.
+     * |        |          |0001 = GPC.1 wake-up function enabled.
+     * |        |          |0010 = GPC.2 wake-up function enabled.
+     * |        |          |0011 = GPC.3 wake-up function enabled.
+     * |        |          |0100 = GPC.4 wake-up function enabled.
+     * |        |          |0101 = GPC.5 wake-up function enabled.
+     * |        |          |0110 = GPC.6 wake-up function enabled.
+     * |        |          |0111 = GPC.7 wake-up function enabled.
+     * |        |          |1000 = GPC.8 wake-up function enabled.
+     * |        |          |1001 = GPC.9 wake-up function enabled.
+     * |        |          |1010 = GPC.10 wake-up function enabled.
+     * |        |          |1011 = GPC.11 wake-up function enabled.
+     * |        |          |1100 = GPC.12 wake-up function enabled.
+     * |        |          |1101 = GPC.13 wake-up function enabled.
+     * |        |          |1110 = GPC.14 wake-up function enabled.
+     * |        |          |1111 = GPC.15 wake-up function enabled.
+     * |[8]     |DBEN      |GPC Input Signal De-bounce Enable Bit
+     * |        |          |The DBEN bit is used to enable the de-bounce function for each corresponding IO
+     * |        |          |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up
+     * |        |          |The de-bounce clock source is the 10 kHz internal low speed RC oscillator.
+     * |        |          |0 = Standby power-down wake-up pin De-bounce function disable.
+     * |        |          |1 = Standby power-down wake-up pin De-bounce function enable.
+     * |        |          |The de-bounce function is valid only for edge triggered.
+     * @var CLK_T::PDSWKCTL
+     * Offset: 0xAC  GPD Standby Power-down Wake-up Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WKEN      |Standby Power-down Pin Wake-up Enable Bit
+     * |        |          |0 = GPD group pin wake-up function disabled.
+     * |        |          |1 = GPD group pin wake-up function enabled.
+     * |[1]     |PRWKEN    |Pin Rising Edge Wake-up Enable Bit
+     * |        |          |0 = GPD group pin rising edge wake-up function disabled.
+     * |        |          |1 = GPD group pin rising edge wake-up function enabled.
+     * |[2]     |PFWKEN    |Pin Falling Edge Wake-up Enable Bit
+     * |        |          |0 = GPD group pin falling edge wake-up function disabled.
+     * |        |          |1 = GPD group pin falling edge wake-up function enabled.
+     * |[7:4]   |WKPSEL    |GPD Standby Power-down Wake-up Pin Select
+     * |        |          |0000 = GPD.0 wake-up function enabled.
+     * |        |          |0001 = GPD.1 wake-up function enabled.
+     * |        |          |0010 = GPD.2 wake-up function enabled.
+     * |        |          |0011 = GPD.3 wake-up function enabled.
+     * |        |          |0100 = GPD.4 wake-up function enabled.
+     * |        |          |0101 = GPD.5 wake-up function enabled.
+     * |        |          |0110 = GPD.6 wake-up function enabled.
+     * |        |          |0111 = GPD.7 wake-up function enabled.
+     * |        |          |1000 = GPD.8 wake-up function enabled.
+     * |        |          |1001 = GPD.9 wake-up function enabled.
+     * |        |          |1010 = GPD.10 wake-up function enabled.
+     * |        |          |1011 = GPD.11 wake-up function enabled.
+     * |        |          |1100 = GPD.12 wake-up function enabled.
+     * |        |          |1101 = GPD.13 wake-up function enabled.
+     * |        |          |1110 = GPD.14 wake-up function enabled.
+     * |        |          |1111 = GPD.15 wake-up function enabled.
+     * |[8]     |DBEN      |GPD Input Signal De-bounce Enable Bit
+     * |        |          |The DBEN bit is used to enable the de-bounce function for each corresponding IO
+     * |        |          |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up
+     * |        |          |The de-bounce clock source is the 10 kHz internal low speed RC oscillator.
+     * |        |          |0 = Standby power-down wake-up pin De-bounce function disable.
+     * |        |          |1 = Standby power-down wake-up pin De-bounce function enable.
+     * |        |          |The de-bounce function is valid only for edge triggered.
+     * @var CLK_T::IOPDCTL
+     * Offset: 0xB0  GPIO Standby Power-down Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |IOHR      |GPIO Hold Release
+     * |        |          |When GPIO enter standby power-down mode, all I/O status are hold to keep normal operating status
+     * |        |          |After chip was waked up from standby power-down mode, the I/O are still keep hold status until user set this bit to release I/O hold status.
+     * |        |          |This bit is auto cleared by hardware.
+     */
+    __IO uint32_t PWRCTL;                /*!< [0x0000] System Power-down Control Register                               */
+    __IO uint32_t AHBCLK;                /*!< [0x0004] AHB Devices Clock Enable Control Register                        */
+    __IO uint32_t APBCLK0;               /*!< [0x0008] APB Devices Clock Enable Control Register 0                      */
+    __IO uint32_t APBCLK1;               /*!< [0x000c] APB Devices Clock Enable Control Register 1                      */
+    __IO uint32_t CLKSEL0;               /*!< [0x0010] Clock Source Select Control Register 0                           */
+    __IO uint32_t CLKSEL1;               /*!< [0x0014] Clock Source Select Control Register 1                           */
+    __IO uint32_t CLKSEL2;               /*!< [0x0018] Clock Source Select Control Register 2                           */
+    __IO uint32_t CLKSEL3;               /*!< [0x001c] Clock Source Select Control Register 3                           */
+    __IO uint32_t CLKDIV0;               /*!< [0x0020] Clock Divider Number Register 0                                  */
+    __IO uint32_t CLKDIV1;               /*!< [0x0024] Clock Divider Number Register 1                                  */
+    __IO uint32_t CLKDIV2;               /*!< [0x0028] Clock Divider Number Register 2                                  */
+    __IO uint32_t CLKDIV3;               /*!< [0x002c] Clock Divider Number Register 3                                  */
+    __IO uint32_t CLKDIV4;               /*!< [0x0030] Clock Divider Number Register 4                                  */
+    __IO uint32_t PCLKDIV;               /*!< [0x0034] APB Clock Divider Register                                       */
+    /** @cond HIDDEN_SYMBOLS */
+    __I  uint32_t RESERVE1[2];
+    /** @endcond */
+    __IO uint32_t PLLCTL;                /*!< [0x0040] PLL Control Register                                             */
+    /** @cond HIDDEN_SYMBOLS */
+    __I  uint32_t RESERVE2[3];
+    /** @endcond */
+    __I  uint32_t STATUS;                /*!< [0x0050] Clock Status Monitor Register                                    */
+    /** @cond HIDDEN_SYMBOLS */
+    __I  uint32_t RESERVE3[3];
+    /** @endcond */
+    __IO uint32_t CLKOCTL;               /*!< [0x0060] Clock Output Control Register                                    */
+    /** @cond HIDDEN_SYMBOLS */
+    __I  uint32_t RESERVE4[3];
+    /** @endcond */
+    __IO uint32_t CLKDCTL;               /*!< [0x0070] Clock Fail Detector Control Register                             */
+    __IO uint32_t CLKDSTS;               /*!< [0x0074] Clock Fail Detector Status Register                              */
+    __IO uint32_t CDUPB;                 /*!< [0x0078] Clock Frequency Range Detector Upper Boundary Register           */
+    __IO uint32_t CDLOWB;                /*!< [0x007c] Clock Frequency Range Detector Lower Boundary Register           */
+    /** @cond HIDDEN_SYMBOLS */
+    __I  uint32_t RESERVE5[4];
+    /** @endcond */
+    __IO uint32_t PMUCTL;                /*!< [0x0090] Power Manager Control Register                                   */
+    __IO uint32_t PMUSTS;                /*!< [0x0094] Power Manager Status Register                                    */
+    __IO uint32_t LDOCTL;                /*!< [0x0098] LDO Control Register                                             */
+    __IO uint32_t SWKDBCTL;              /*!< [0x009c] Standby Power-down Wake-up De-bounce Control Register            */
+    __IO uint32_t PASWKCTL;              /*!< [0x00a0] GPA Standby Power-down Wake-up Control Register                  */
+    __IO uint32_t PBSWKCTL;              /*!< [0x00a4] GPB Standby Power-down Wake-up Control Register                  */
+    __IO uint32_t PCSWKCTL;              /*!< [0x00a8] GPC Standby Power-down Wake-up Control Register                  */
+    __IO uint32_t PDSWKCTL;              /*!< [0x00ac] GPD Standby Power-down Wake-up Control Register                  */
+    __IO uint32_t IOPDCTL;               /*!< [0x00b0] GPIO Standby Power-down Control Register                         */
+
+} CLK_T;
+
+/**
+    @addtogroup CLK_CONST CLK Bit Field Definition
+    Constant Definitions for CLK Controller
+@{ */
+
+#define CLK_PWRCTL_HXTEN_Pos             (0)                                               /*!< CLK_T::PWRCTL: HXTEN Position          */
+#define CLK_PWRCTL_HXTEN_Msk             (0x1ul << CLK_PWRCTL_HXTEN_Pos)                   /*!< CLK_T::PWRCTL: HXTEN Mask              */
+
+#define CLK_PWRCTL_LXTEN_Pos             (1)                                               /*!< CLK_T::PWRCTL: LXTEN Position          */
+#define CLK_PWRCTL_LXTEN_Msk             (0x1ul << CLK_PWRCTL_LXTEN_Pos)                   /*!< CLK_T::PWRCTL: LXTEN Mask              */
+
+#define CLK_PWRCTL_HIRCEN_Pos            (2)                                               /*!< CLK_T::PWRCTL: HIRCEN Position         */
+#define CLK_PWRCTL_HIRCEN_Msk            (0x1ul << CLK_PWRCTL_HIRCEN_Pos)                  /*!< CLK_T::PWRCTL: HIRCEN Mask             */
+
+#define CLK_PWRCTL_LIRCEN_Pos            (3)                                               /*!< CLK_T::PWRCTL: LIRCEN Position         */
+#define CLK_PWRCTL_LIRCEN_Msk            (0x1ul << CLK_PWRCTL_LIRCEN_Pos)                  /*!< CLK_T::PWRCTL: LIRCEN Mask             */
+
+#define CLK_PWRCTL_PDWKDLY_Pos           (4)                                               /*!< CLK_T::PWRCTL: PDWKDLY Position        */
+#define CLK_PWRCTL_PDWKDLY_Msk           (0x1ul << CLK_PWRCTL_PDWKDLY_Pos)                 /*!< CLK_T::PWRCTL: PDWKDLY Mask            */
+
+#define CLK_PWRCTL_PDWKIEN_Pos           (5)                                               /*!< CLK_T::PWRCTL: PDWKIEN Position        */
+#define CLK_PWRCTL_PDWKIEN_Msk           (0x1ul << CLK_PWRCTL_PDWKIEN_Pos)                 /*!< CLK_T::PWRCTL: PDWKIEN Mask            */
+
+#define CLK_PWRCTL_PDWKIF_Pos            (6)                                               /*!< CLK_T::PWRCTL: PDWKIF Position         */
+#define CLK_PWRCTL_PDWKIF_Msk            (0x1ul << CLK_PWRCTL_PDWKIF_Pos)                  /*!< CLK_T::PWRCTL: PDWKIF Mask             */
+
+#define CLK_PWRCTL_PDEN_Pos              (7)                                               /*!< CLK_T::PWRCTL: PDEN Position           */
+#define CLK_PWRCTL_PDEN_Msk              (0x1ul << CLK_PWRCTL_PDEN_Pos)                    /*!< CLK_T::PWRCTL: PDEN Mask               */
+
+#define CLK_PWRCTL_HXTGAIN_Pos           (10)                                              /*!< CLK_T::PWRCTL: HXTGAIN Position        */
+#define CLK_PWRCTL_HXTGAIN_Msk           (0x3ul << CLK_PWRCTL_HXTGAIN_Pos)                 /*!< CLK_T::PWRCTL: HXTGAIN Mask            */
+
+#define CLK_PWRCTL_HXTSELTYP_Pos         (12)                                              /*!< CLK_T::PWRCTL: HXTSELTYP Position      */
+#define CLK_PWRCTL_HXTSELTYP_Msk         (0x1ul << CLK_PWRCTL_HXTSELTYP_Pos)               /*!< CLK_T::PWRCTL: HXTSELTYP Mask          */
+
+#define CLK_PWRCTL_HXTTBEN_Pos           (13)                                              /*!< CLK_T::PWRCTL: HXTTBEN Position        */
+#define CLK_PWRCTL_HXTTBEN_Msk           (0x1ul << CLK_PWRCTL_HXTTBEN_Pos)                 /*!< CLK_T::PWRCTL: HXTTBEN Mask            */
+
+#define CLK_PWRCTL_HIRCSTBS_Pos          (16)                                              /*!< CLK_T::PWRCTL: HIRCSTBS Position       */
+#define CLK_PWRCTL_HIRCSTBS_Msk          (0x3ul << CLK_PWRCTL_HIRCSTBS_Pos)                /*!< CLK_T::PWRCTL: HIRCSTBS Mask           */
+
+#define CLK_PWRCTL_HIRC48MEN_Pos         (18)                                              /*!< CLK_T::PWRCTL: HIRC48MEN Position      */
+#define CLK_PWRCTL_HIRC48MEN_Msk         (0x1ul << CLK_PWRCTL_HIRC48MEN_Pos)               /*!< CLK_T::PWRCTL: HIRC48MEN Mask          */
+
+#define CLK_AHBCLK_PDMACKEN_Pos          (1)                                               /*!< CLK_T::AHBCLK: PDMACKEN Position       */
+#define CLK_AHBCLK_PDMACKEN_Msk          (0x1ul << CLK_AHBCLK_PDMACKEN_Pos)                /*!< CLK_T::AHBCLK: PDMACKEN Mask           */
+
+#define CLK_AHBCLK_ISPCKEN_Pos           (2)                                               /*!< CLK_T::AHBCLK: ISPCKEN Position        */
+#define CLK_AHBCLK_ISPCKEN_Msk           (0x1ul << CLK_AHBCLK_ISPCKEN_Pos)                 /*!< CLK_T::AHBCLK: ISPCKEN Mask            */
+
+#define CLK_AHBCLK_EBICKEN_Pos           (3)                                               /*!< CLK_T::AHBCLK: EBICKEN Position        */
+#define CLK_AHBCLK_EBICKEN_Msk           (0x1ul << CLK_AHBCLK_EBICKEN_Pos)                 /*!< CLK_T::AHBCLK: EBICKEN Mask            */
+
+#define CLK_AHBCLK_EMACCKEN_Pos          (5)                                               /*!< CLK_T::AHBCLK: EMACCKEN Position       */
+#define CLK_AHBCLK_EMACCKEN_Msk          (0x1ul << CLK_AHBCLK_EMACCKEN_Pos)                /*!< CLK_T::AHBCLK: EMACCKEN Mask           */
+
+#define CLK_AHBCLK_SDH0CKEN_Pos          (6)                                               /*!< CLK_T::AHBCLK: SDH0CKEN Position       */
+#define CLK_AHBCLK_SDH0CKEN_Msk          (0x1ul << CLK_AHBCLK_SDH0CKEN_Pos)                /*!< CLK_T::AHBCLK: SDH0CKEN Mask           */
+
+#define CLK_AHBCLK_CRCCKEN_Pos           (7)                                               /*!< CLK_T::AHBCLK: CRCCKEN Position        */
+#define CLK_AHBCLK_CRCCKEN_Msk           (0x1ul << CLK_AHBCLK_CRCCKEN_Pos)                 /*!< CLK_T::AHBCLK: CRCCKEN Mask            */
+
+#define CLK_AHBCLK_CCAPCKEN_Pos          (8)                                               /*!< CLK_T::AHBCLK: CCAPCKEN Position       */
+#define CLK_AHBCLK_CCAPCKEN_Msk          (0x1ul << CLK_AHBCLK_CCAPCKEN_Pos)                /*!< CLK_T::AHBCLK: CCAPCKEN Mask           */
+
+#define CLK_AHBCLK_SENCKEN_Pos           (9)                                               /*!< CLK_T::AHBCLK: SENCKEN Position        */
+#define CLK_AHBCLK_SENCKEN_Msk           (0x1ul << CLK_AHBCLK_SENCKEN_Pos)                 /*!< CLK_T::AHBCLK: SENCKEN Mask            */
+
+#define CLK_AHBCLK_HSUSBDCKEN_Pos        (10)                                              /*!< CLK_T::AHBCLK: HSUSBDCKEN Position     */
+#define CLK_AHBCLK_HSUSBDCKEN_Msk        (0x1ul << CLK_AHBCLK_HSUSBDCKEN_Pos)              /*!< CLK_T::AHBCLK: HSUSBDCKEN Mask         */
+
+#define CLK_AHBCLK_CRPTCKEN_Pos          (12)                                              /*!< CLK_T::AHBCLK: CRPTCKEN Position       */
+#define CLK_AHBCLK_CRPTCKEN_Msk          (0x1ul << CLK_AHBCLK_CRPTCKEN_Pos)                /*!< CLK_T::AHBCLK: CRPTCKEN Mask           */
+
+#define CLK_AHBCLK_SPIMCKEN_Pos          (14)                                              /*!< CLK_T::AHBCLK: SPIMCKEN Position       */
+#define CLK_AHBCLK_SPIMCKEN_Msk          (0x1ul << CLK_AHBCLK_SPIMCKEN_Pos)                /*!< CLK_T::AHBCLK: SPIMCKEN Mask           */
+
+#define CLK_AHBCLK_FMCIDLE_Pos           (15)                                              /*!< CLK_T::AHBCLK: FMCIDLE Position        */
+#define CLK_AHBCLK_FMCIDLE_Msk           (0x1ul << CLK_AHBCLK_FMCIDLE_Pos)                 /*!< CLK_T::AHBCLK: FMCIDLE Mask            */
+
+#define CLK_AHBCLK_USBHCKEN_Pos          (16)                                              /*!< CLK_T::AHBCLK: USBHCKEN Position       */
+#define CLK_AHBCLK_USBHCKEN_Msk          (0x1ul << CLK_AHBCLK_USBHCKEN_Pos)                /*!< CLK_T::AHBCLK: USBHCKEN Mask           */
+
+#define CLK_AHBCLK_SDH1CKEN_Pos          (17)                                              /*!< CLK_T::AHBCLK: SDH1CKEN Position       */
+#define CLK_AHBCLK_SDH1CKEN_Msk          (0x1ul << CLK_AHBCLK_SDH1CKEN_Pos)                /*!< CLK_T::AHBCLK: SDH1CKEN Mask           */
+
+#define CLK_APBCLK0_WDTCKEN_Pos          (0)                                               /*!< CLK_T::APBCLK0: WDTCKEN Position       */
+#define CLK_APBCLK0_WDTCKEN_Msk          (0x1ul << CLK_APBCLK0_WDTCKEN_Pos)                /*!< CLK_T::APBCLK0: WDTCKEN Mask           */
+
+#define CLK_APBCLK0_RTCCKEN_Pos          (1)                                               /*!< CLK_T::APBCLK0: RTCCKEN Position       */
+#define CLK_APBCLK0_RTCCKEN_Msk          (0x1ul << CLK_APBCLK0_RTCCKEN_Pos)                /*!< CLK_T::APBCLK0: RTCCKEN Mask           */
+
+#define CLK_APBCLK0_TMR0CKEN_Pos         (2)                                               /*!< CLK_T::APBCLK0: TMR0CKEN Position      */
+#define CLK_APBCLK0_TMR0CKEN_Msk         (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos)               /*!< CLK_T::APBCLK0: TMR0CKEN Mask          */
+
+#define CLK_APBCLK0_TMR1CKEN_Pos         (3)                                               /*!< CLK_T::APBCLK0: TMR1CKEN Position      */
+#define CLK_APBCLK0_TMR1CKEN_Msk         (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos)               /*!< CLK_T::APBCLK0: TMR1CKEN Mask          */
+
+#define CLK_APBCLK0_TMR2CKEN_Pos         (4)                                               /*!< CLK_T::APBCLK0: TMR2CKEN Position      */
+#define CLK_APBCLK0_TMR2CKEN_Msk         (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos)               /*!< CLK_T::APBCLK0: TMR2CKEN Mask          */
+
+#define CLK_APBCLK0_TMR3CKEN_Pos         (5)                                               /*!< CLK_T::APBCLK0: TMR3CKEN Position      */
+#define CLK_APBCLK0_TMR3CKEN_Msk         (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos)               /*!< CLK_T::APBCLK0: TMR3CKEN Mask          */
+
+#define CLK_APBCLK0_CLKOCKEN_Pos         (6)                                               /*!< CLK_T::APBCLK0: CLKOCKEN Position      */
+#define CLK_APBCLK0_CLKOCKEN_Msk         (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos)               /*!< CLK_T::APBCLK0: CLKOCKEN Mask          */
+
+#define CLK_APBCLK0_ACMP01CKEN_Pos       (7)                                               /*!< CLK_T::APBCLK0: ACMP01CKEN Position    */
+#define CLK_APBCLK0_ACMP01CKEN_Msk       (0x1ul << CLK_APBCLK0_ACMP01CKEN_Pos)             /*!< CLK_T::APBCLK0: ACMP01CKEN Mask        */
+
+#define CLK_APBCLK0_I2C0CKEN_Pos         (8)                                               /*!< CLK_T::APBCLK0: I2C0CKEN Position      */
+#define CLK_APBCLK0_I2C0CKEN_Msk         (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos)               /*!< CLK_T::APBCLK0: I2C0CKEN Mask          */
+
+#define CLK_APBCLK0_I2C1CKEN_Pos         (9)                                               /*!< CLK_T::APBCLK0: I2C1CKEN Position      */
+#define CLK_APBCLK0_I2C1CKEN_Msk         (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos)               /*!< CLK_T::APBCLK0: I2C1CKEN Mask          */
+
+#define CLK_APBCLK0_I2C2CKEN_Pos         (10)                                              /*!< CLK_T::APBCLK0: I2C2CKEN Position      */
+#define CLK_APBCLK0_I2C2CKEN_Msk         (0x1ul << CLK_APBCLK0_I2C2CKEN_Pos)               /*!< CLK_T::APBCLK0: I2C2CKEN Mask          */
+
+#define CLK_APBCLK0_QSPI0CKEN_Pos        (12)                                              /*!< CLK_T::APBCLK0: QSPI0CKEN Position     */
+#define CLK_APBCLK0_QSPI0CKEN_Msk        (0x1ul << CLK_APBCLK0_QSPI0CKEN_Pos)              /*!< CLK_T::APBCLK0: QSPI0CKEN Mask         */
+
+#define CLK_APBCLK0_SPI0CKEN_Pos         (13)                                              /*!< CLK_T::APBCLK0: SPI0CKEN Position      */
+#define CLK_APBCLK0_SPI0CKEN_Msk         (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos)               /*!< CLK_T::APBCLK0: SPI0CKEN Mask          */
+
+#define CLK_APBCLK0_SPI1CKEN_Pos         (14)                                              /*!< CLK_T::APBCLK0: SPI1CKEN Position      */
+#define CLK_APBCLK0_SPI1CKEN_Msk         (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos)               /*!< CLK_T::APBCLK0: SPI1CKEN Mask          */
+
+#define CLK_APBCLK0_SPI2CKEN_Pos         (15)                                              /*!< CLK_T::APBCLK0: SPI2CKEN Position      */
+#define CLK_APBCLK0_SPI2CKEN_Msk         (0x1ul << CLK_APBCLK0_SPI2CKEN_Pos)               /*!< CLK_T::APBCLK0: SPI2CKEN Mask          */
+
+#define CLK_APBCLK0_UART0CKEN_Pos        (16)                                              /*!< CLK_T::APBCLK0: UART0CKEN Position     */
+#define CLK_APBCLK0_UART0CKEN_Msk        (0x1ul << CLK_APBCLK0_UART0CKEN_Pos)              /*!< CLK_T::APBCLK0: UART0CKEN Mask         */
+
+#define CLK_APBCLK0_UART1CKEN_Pos        (17)                                              /*!< CLK_T::APBCLK0: UART1CKEN Position     */
+#define CLK_APBCLK0_UART1CKEN_Msk        (0x1ul << CLK_APBCLK0_UART1CKEN_Pos)              /*!< CLK_T::APBCLK0: UART1CKEN Mask         */
+
+#define CLK_APBCLK0_UART2CKEN_Pos        (18)                                              /*!< CLK_T::APBCLK0: UART2CKEN Position     */
+#define CLK_APBCLK0_UART2CKEN_Msk        (0x1ul << CLK_APBCLK0_UART2CKEN_Pos)              /*!< CLK_T::APBCLK0: UART2CKEN Mask         */
+
+#define CLK_APBCLK0_UART3CKEN_Pos        (19)                                              /*!< CLK_T::APBCLK0: UART3CKEN Position     */
+#define CLK_APBCLK0_UART3CKEN_Msk        (0x1ul << CLK_APBCLK0_UART3CKEN_Pos)              /*!< CLK_T::APBCLK0: UART3CKEN Mask         */
+
+#define CLK_APBCLK0_UART4CKEN_Pos        (20)                                              /*!< CLK_T::APBCLK0: UART4CKEN Position     */
+#define CLK_APBCLK0_UART4CKEN_Msk        (0x1ul << CLK_APBCLK0_UART4CKEN_Pos)              /*!< CLK_T::APBCLK0: UART4CKEN Mask         */
+
+#define CLK_APBCLK0_UART5CKEN_Pos        (21)                                              /*!< CLK_T::APBCLK0: UART5CKEN Position     */
+#define CLK_APBCLK0_UART5CKEN_Msk        (0x1ul << CLK_APBCLK0_UART5CKEN_Pos)              /*!< CLK_T::APBCLK0: UART5CKEN Mask         */
+
+#define CLK_APBCLK0_UART6CKEN_Pos        (22)                                              /*!< CLK_T::APBCLK0: UART6CKEN Position     */
+#define CLK_APBCLK0_UART6CKEN_Msk        (0x1ul << CLK_APBCLK0_UART6CKEN_Pos)              /*!< CLK_T::APBCLK0: UART6CKEN Mask         */
+
+#define CLK_APBCLK0_UART7CKEN_Pos        (23)                                              /*!< CLK_T::APBCLK0: UART7CKEN Position     */
+#define CLK_APBCLK0_UART7CKEN_Msk        (0x1ul << CLK_APBCLK0_UART7CKEN_Pos)              /*!< CLK_T::APBCLK0: UART7CKEN Mask         */
+
+#define CLK_APBCLK0_CAN0CKEN_Pos         (24)                                              /*!< CLK_T::APBCLK0: CAN0CKEN Position      */
+#define CLK_APBCLK0_CAN0CKEN_Msk         (0x1ul << CLK_APBCLK0_CAN0CKEN_Pos)               /*!< CLK_T::APBCLK0: CAN0CKEN Mask          */
+
+#define CLK_APBCLK0_CAN1CKEN_Pos         (25)                                              /*!< CLK_T::APBCLK0: CAN1CKEN Position      */
+#define CLK_APBCLK0_CAN1CKEN_Msk         (0x1ul << CLK_APBCLK0_CAN1CKEN_Pos)               /*!< CLK_T::APBCLK0: CAN1CKEN Mask          */
+
+#define CLK_APBCLK0_OTGCKEN_Pos          (26)                                              /*!< CLK_T::APBCLK0: OTGCKEN Position       */
+#define CLK_APBCLK0_OTGCKEN_Msk          (0x1ul << CLK_APBCLK0_OTGCKEN_Pos)                /*!< CLK_T::APBCLK0: OTGCKEN Mask           */
+
+#define CLK_APBCLK0_USBDCKEN_Pos         (27)                                              /*!< CLK_T::APBCLK0: USBDCKEN Position      */
+#define CLK_APBCLK0_USBDCKEN_Msk         (0x1ul << CLK_APBCLK0_USBDCKEN_Pos)               /*!< CLK_T::APBCLK0: USBDCKEN Mask          */
+
+#define CLK_APBCLK0_EADCCKEN_Pos         (28)                                              /*!< CLK_T::APBCLK0: EADCCKEN Position      */
+#define CLK_APBCLK0_EADCCKEN_Msk         (0x1ul << CLK_APBCLK0_EADCCKEN_Pos)               /*!< CLK_T::APBCLK0: EADCCKEN Mask          */
+
+#define CLK_APBCLK0_I2S0CKEN_Pos         (29)                                              /*!< CLK_T::APBCLK0: I2S0CKEN Position      */
+#define CLK_APBCLK0_I2S0CKEN_Msk         (0x1ul << CLK_APBCLK0_I2S0CKEN_Pos)               /*!< CLK_T::APBCLK0: I2S0CKEN Mask          */
+
+#define CLK_APBCLK0_HSOTGCKEN_Pos        (30)                                              /*!< CLK_T::APBCLK0: HSOTGCKEN Position     */
+#define CLK_APBCLK0_HSOTGCKEN_Msk        (0x1ul << CLK_APBCLK0_HSOTGCKEN_Pos)              /*!< CLK_T::APBCLK0: HSOTGCKEN Mask         */
+
+#define CLK_APBCLK1_SC0CKEN_Pos          (0)                                               /*!< CLK_T::APBCLK1: SC0CKEN Position       */
+#define CLK_APBCLK1_SC0CKEN_Msk          (0x1ul << CLK_APBCLK1_SC0CKEN_Pos)                /*!< CLK_T::APBCLK1: SC0CKEN Mask           */
+
+#define CLK_APBCLK1_SC1CKEN_Pos          (1)                                               /*!< CLK_T::APBCLK1: SC1CKEN Position       */
+#define CLK_APBCLK1_SC1CKEN_Msk          (0x1ul << CLK_APBCLK1_SC1CKEN_Pos)                /*!< CLK_T::APBCLK1: SC1CKEN Mask           */
+
+#define CLK_APBCLK1_SC2CKEN_Pos          (2)                                               /*!< CLK_T::APBCLK1: SC2CKEN Position       */
+#define CLK_APBCLK1_SC2CKEN_Msk          (0x1ul << CLK_APBCLK1_SC2CKEN_Pos)                /*!< CLK_T::APBCLK1: SC2CKEN Mask           */
+
+#define CLK_APBCLK1_QSPI1CKEN_Pos        (4)                                               /*!< CLK_T::APBCLK1: QSPI1CKEN Position     */
+#define CLK_APBCLK1_QSPI1CKEN_Msk        (0x1ul << CLK_APBCLK1_QSPI1CKEN_Pos)              /*!< CLK_T::APBCLK1: QSPI1CKEN Mask         */
+
+#define CLK_APBCLK1_SPI3CKEN_Pos         (6)                                               /*!< CLK_T::APBCLK1: SPI3CKEN Position      */
+#define CLK_APBCLK1_SPI3CKEN_Msk         (0x1ul << CLK_APBCLK1_SPI3CKEN_Pos)               /*!< CLK_T::APBCLK1: SPI3CKEN Mask          */
+
+#define CLK_APBCLK1_USCI0CKEN_Pos        (8)                                               /*!< CLK_T::APBCLK1: USCI0CKEN Position     */
+#define CLK_APBCLK1_USCI0CKEN_Msk        (0x1ul << CLK_APBCLK1_USCI0CKEN_Pos)              /*!< CLK_T::APBCLK1: USCI0CKEN Mask         */
+
+#define CLK_APBCLK1_USCI1CKEN_Pos        (9)                                               /*!< CLK_T::APBCLK1: USCI1CKEN Position     */
+#define CLK_APBCLK1_USCI1CKEN_Msk        (0x1ul << CLK_APBCLK1_USCI1CKEN_Pos)              /*!< CLK_T::APBCLK1: USCI1CKEN Mask         */
+
+#define CLK_APBCLK1_DACCKEN_Pos          (12)                                              /*!< CLK_T::APBCLK1: DACCKEN Position       */
+#define CLK_APBCLK1_DACCKEN_Msk          (0x1ul << CLK_APBCLK1_DACCKEN_Pos)                /*!< CLK_T::APBCLK1: DACCKEN Mask           */
+
+#define CLK_APBCLK1_EPWM0CKEN_Pos        (16)                                              /*!< CLK_T::APBCLK1: EPWM0CKEN Position     */
+#define CLK_APBCLK1_EPWM0CKEN_Msk        (0x1ul << CLK_APBCLK1_EPWM0CKEN_Pos)              /*!< CLK_T::APBCLK1: EPWM0CKEN Mask         */
+
+#define CLK_APBCLK1_EPWM1CKEN_Pos        (17)                                              /*!< CLK_T::APBCLK1: EPWM1CKEN Position     */
+#define CLK_APBCLK1_EPWM1CKEN_Msk        (0x1ul << CLK_APBCLK1_EPWM1CKEN_Pos)              /*!< CLK_T::APBCLK1: EPWM1CKEN Mask         */
+
+#define CLK_APBCLK1_BPWM0CKEN_Pos        (18)                                              /*!< CLK_T::APBCLK1: BPWM0CKEN Position     */
+#define CLK_APBCLK1_BPWM0CKEN_Msk        (0x1ul << CLK_APBCLK1_BPWM0CKEN_Pos)              /*!< CLK_T::APBCLK1: BPWM0CKEN Mask         */
+
+#define CLK_APBCLK1_BPWM1CKEN_Pos        (19)                                              /*!< CLK_T::APBCLK1: BPWM1CKEN Position     */
+#define CLK_APBCLK1_BPWM1CKEN_Msk        (0x1ul << CLK_APBCLK1_BPWM1CKEN_Pos)              /*!< CLK_T::APBCLK1: BPWM1CKEN Mask         */
+
+#define CLK_APBCLK1_QEI0CKEN_Pos         (22)                                              /*!< CLK_T::APBCLK1: QEI0CKEN Position      */
+#define CLK_APBCLK1_QEI0CKEN_Msk         (0x1ul << CLK_APBCLK1_QEI0CKEN_Pos)               /*!< CLK_T::APBCLK1: QEI0CKEN Mask          */
+
+#define CLK_APBCLK1_QEI1CKEN_Pos         (23)                                              /*!< CLK_T::APBCLK1: QEI1CKEN Position      */
+#define CLK_APBCLK1_QEI1CKEN_Msk         (0x1ul << CLK_APBCLK1_QEI1CKEN_Pos)               /*!< CLK_T::APBCLK1: QEI1CKEN Mask          */
+
+#define CLK_APBCLK1_TRNGCKEN_Pos         (25)                                              /*!< CLK_T::APBCLK1: TRNGCKEN Position     */
+#define CLK_APBCLK1_TRNGCKEN_Msk         (0x1ul << CLK_APBCLK1_TRNGCKEN_Pos)               /*!< CLK_T::APBCLK1: TRNGCKEN Mask         */
+
+#define CLK_APBCLK1_ECAP0CKEN_Pos        (26)                                              /*!< CLK_T::APBCLK1: ECAP0CKEN Position     */
+#define CLK_APBCLK1_ECAP0CKEN_Msk        (0x1ul << CLK_APBCLK1_ECAP0CKEN_Pos)              /*!< CLK_T::APBCLK1: ECAP0CKEN Mask         */
+
+#define CLK_APBCLK1_ECAP1CKEN_Pos        (27)                                              /*!< CLK_T::APBCLK1: ECAP1CKEN Position     */
+#define CLK_APBCLK1_ECAP1CKEN_Msk        (0x1ul << CLK_APBCLK1_ECAP1CKEN_Pos)              /*!< CLK_T::APBCLK1: ECAP1CKEN Mask         */
+
+#define CLK_APBCLK1_CAN2CKEN_Pos         (28)                                              /*!< CLK_T::APBCLK1: CAN2CKEN Position      */
+#define CLK_APBCLK1_CAN2CKEN_Msk         (0x1ul << CLK_APBCLK1_CAN2CKEN_Pos)               /*!< CLK_T::APBCLK1: CAN2CKEN Mask          */
+
+#define CLK_APBCLK1_OPACKEN_Pos          (30)                                              /*!< CLK_T::APBCLK1: OPACKEN Position       */
+#define CLK_APBCLK1_OPACKEN_Msk          (0x1ul << CLK_APBCLK1_OPACKEN_Pos)                /*!< CLK_T::APBCLK1: OPACKEN Mask           */
+
+#define CLK_APBCLK1_EADC1CKEN_Pos        (31)                                              /*!< CLK_T::APBCLK1: EADC1CKEN Position     */
+#define CLK_APBCLK1_EADC1CKEN_Msk        (0x1ul << CLK_APBCLK1_EADC1CKEN_Pos)              /*!< CLK_T::APBCLK1: EADC1CKEN Mask         */
+
+#define CLK_CLKSEL0_HCLKSEL_Pos          (0)                                               /*!< CLK_T::CLKSEL0: HCLKSEL Position       */
+#define CLK_CLKSEL0_HCLKSEL_Msk          (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos)                /*!< CLK_T::CLKSEL0: HCLKSEL Mask           */
+
+#define CLK_CLKSEL0_STCLKSEL_Pos         (3)                                               /*!< CLK_T::CLKSEL0: STCLKSEL Position      */
+#define CLK_CLKSEL0_STCLKSEL_Msk         (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos)               /*!< CLK_T::CLKSEL0: STCLKSEL Mask          */
+
+#define CLK_CLKSEL0_USBSEL_Pos           (8)                                               /*!< CLK_T::CLKSEL0: PCLK0SEL Position      */
+#define CLK_CLKSEL0_USBSEL_Msk           (0x1ul << CLK_CLKSEL0_USBSEL_Pos)                 /*!< CLK_T::CLKSEL0: PCLK0SEL Mask          */
+
+#define CLK_CLKSEL0_CCAPSEL_Pos          (16)                                              /*!< CLK_T::CLKSEL0: CCAPSEL Position      */
+#define CLK_CLKSEL0_CCAPSEL_Msk          (0x3ul << CLK_CLKSEL0_CCAPSEL_Pos)                /*!< CLK_T::CLKSEL0: CCAPSEL Mask          */
+
+#define CLK_CLKSEL0_SDH0SEL_Pos          (20)                                              /*!< CLK_T::CLKSEL0: SDH0SEL Position       */
+#define CLK_CLKSEL0_SDH0SEL_Msk          (0x3ul << CLK_CLKSEL0_SDH0SEL_Pos)                /*!< CLK_T::CLKSEL0: SDH0SEL Mask           */
+
+#define CLK_CLKSEL0_SDH1SEL_Pos          (22)                                              /*!< CLK_T::CLKSEL0: SDH1SEL Position       */
+#define CLK_CLKSEL0_SDH1SEL_Msk          (0x3ul << CLK_CLKSEL0_SDH1SEL_Pos)                /*!< CLK_T::CLKSEL0: SDH1SEL Mask           */
+
+#define CLK_CLKSEL1_WDTSEL_Pos           (0)                                               /*!< CLK_T::CLKSEL1: WDTSEL Position        */
+#define CLK_CLKSEL1_WDTSEL_Msk           (0x3ul << CLK_CLKSEL1_WDTSEL_Pos)                 /*!< CLK_T::CLKSEL1: WDTSEL Mask            */
+
+#define CLK_CLKSEL1_TMR0SEL_Pos          (8)                                               /*!< CLK_T::CLKSEL1: TMR0SEL Position       */
+#define CLK_CLKSEL1_TMR0SEL_Msk          (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos)                /*!< CLK_T::CLKSEL1: TMR0SEL Mask           */
+
+#define CLK_CLKSEL1_TMR1SEL_Pos          (12)                                              /*!< CLK_T::CLKSEL1: TMR1SEL Position       */
+#define CLK_CLKSEL1_TMR1SEL_Msk          (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos)                /*!< CLK_T::CLKSEL1: TMR1SEL Mask           */
+
+#define CLK_CLKSEL1_TMR2SEL_Pos          (16)                                              /*!< CLK_T::CLKSEL1: TMR2SEL Position       */
+#define CLK_CLKSEL1_TMR2SEL_Msk          (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos)                /*!< CLK_T::CLKSEL1: TMR2SEL Mask           */
+
+#define CLK_CLKSEL1_TMR3SEL_Pos          (20)                                              /*!< CLK_T::CLKSEL1: TMR3SEL Position       */
+#define CLK_CLKSEL1_TMR3SEL_Msk          (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos)                /*!< CLK_T::CLKSEL1: TMR3SEL Mask           */
+
+#define CLK_CLKSEL1_UART0SEL_Pos         (24)                                              /*!< CLK_T::CLKSEL1: UART0SEL Position      */
+#define CLK_CLKSEL1_UART0SEL_Msk         (0x3ul << CLK_CLKSEL1_UART0SEL_Pos)               /*!< CLK_T::CLKSEL1: UART0SEL Mask          */
+
+#define CLK_CLKSEL1_UART1SEL_Pos         (26)                                              /*!< CLK_T::CLKSEL1: UART1SEL Position      */
+#define CLK_CLKSEL1_UART1SEL_Msk         (0x3ul << CLK_CLKSEL1_UART1SEL_Pos)               /*!< CLK_T::CLKSEL1: UART1SEL Mask          */
+
+#define CLK_CLKSEL1_CLKOSEL_Pos          (28)                                              /*!< CLK_T::CLKSEL1: CLKOSEL Position       */
+#define CLK_CLKSEL1_CLKOSEL_Msk          (0x3ul << CLK_CLKSEL1_CLKOSEL_Pos)                /*!< CLK_T::CLKSEL1: CLKOSEL Mask           */
+
+#define CLK_CLKSEL1_WWDTSEL_Pos          (30)                                              /*!< CLK_T::CLKSEL1: WWDTSEL Position       */
+#define CLK_CLKSEL1_WWDTSEL_Msk          (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos)                /*!< CLK_T::CLKSEL1: WWDTSEL Mask           */
+
+#define CLK_CLKSEL2_EPWM0SEL_Pos         (0)                                               /*!< CLK_T::CLKSEL2: EPWM0SEL Position      */
+#define CLK_CLKSEL2_EPWM0SEL_Msk         (0x1ul << CLK_CLKSEL2_EPWM0SEL_Pos)               /*!< CLK_T::CLKSEL2: EPWM0SEL Mask          */
+
+#define CLK_CLKSEL2_EPWM1SEL_Pos         (1)                                               /*!< CLK_T::CLKSEL2: EPWM1SEL Position      */
+#define CLK_CLKSEL2_EPWM1SEL_Msk         (0x1ul << CLK_CLKSEL2_EPWM1SEL_Pos)               /*!< CLK_T::CLKSEL2: EPWM1SEL Mask          */
+
+#define CLK_CLKSEL2_QSPI0SEL_Pos         (2)                                               /*!< CLK_T::CLKSEL2: QSPI0SEL Position      */
+#define CLK_CLKSEL2_QSPI0SEL_Msk         (0x3ul << CLK_CLKSEL2_QSPI0SEL_Pos)               /*!< CLK_T::CLKSEL2: QSPI0SEL Mask          */
+
+#define CLK_CLKSEL2_SPI0SEL_Pos          (4)                                               /*!< CLK_T::CLKSEL2: SPI0SEL Position       */
+#define CLK_CLKSEL2_SPI0SEL_Msk          (0x3ul << CLK_CLKSEL2_SPI0SEL_Pos)                /*!< CLK_T::CLKSEL2: SPI0SEL Mask           */
+
+#define CLK_CLKSEL2_SPI1SEL_Pos          (6)                                               /*!< CLK_T::CLKSEL2: SPI1SEL Position       */
+#define CLK_CLKSEL2_SPI1SEL_Msk          (0x3ul << CLK_CLKSEL2_SPI1SEL_Pos)                /*!< CLK_T::CLKSEL2: SPI1SEL Mask           */
+
+#define CLK_CLKSEL2_BPWM0SEL_Pos         (8)                                               /*!< CLK_T::CLKSEL2: BPWM0SEL Position      */
+#define CLK_CLKSEL2_BPWM0SEL_Msk         (0x1ul << CLK_CLKSEL2_BPWM0SEL_Pos)               /*!< CLK_T::CLKSEL2: BPWM0SEL Mask          */
+
+#define CLK_CLKSEL2_BPWM1SEL_Pos         (9)                                               /*!< CLK_T::CLKSEL2: BPWM1SEL Position      */
+#define CLK_CLKSEL2_BPWM1SEL_Msk         (0x1ul << CLK_CLKSEL2_BPWM1SEL_Pos)               /*!< CLK_T::CLKSEL2: BPWM1SEL Mask          */
+
+#define CLK_CLKSEL2_SPI2SEL_Pos          (10)                                              /*!< CLK_T::CLKSEL2: SPI2SEL Position       */
+#define CLK_CLKSEL2_SPI2SEL_Msk          (0x3ul << CLK_CLKSEL2_SPI2SEL_Pos)                /*!< CLK_T::CLKSEL2: SPI2SEL Mask           */
+
+#define CLK_CLKSEL2_SPI3SEL_Pos          (12)                                              /*!< CLK_T::CLKSEL2: SPI3SEL Position       */
+#define CLK_CLKSEL2_SPI3SEL_Msk          (0x3ul << CLK_CLKSEL2_SPI3SEL_Pos)                /*!< CLK_T::CLKSEL2: SPI3SEL Mask           */
+
+#define CLK_CLKSEL3_SC0SEL_Pos           (0)                                               /*!< CLK_T::CLKSEL3: SC0SEL Position        */
+#define CLK_CLKSEL3_SC0SEL_Msk           (0x3ul << CLK_CLKSEL3_SC0SEL_Pos)                 /*!< CLK_T::CLKSEL3: SC0SEL Mask            */
+
+#define CLK_CLKSEL3_SC1SEL_Pos           (2)                                               /*!< CLK_T::CLKSEL3: SC1SEL Position        */
+#define CLK_CLKSEL3_SC1SEL_Msk           (0x3ul << CLK_CLKSEL3_SC1SEL_Pos)                 /*!< CLK_T::CLKSEL3: SC1SEL Mask            */
+
+#define CLK_CLKSEL3_SC2SEL_Pos           (4)                                               /*!< CLK_T::CLKSEL3: SC2SEL Position        */
+#define CLK_CLKSEL3_SC2SEL_Msk           (0x3ul << CLK_CLKSEL3_SC2SEL_Pos)                 /*!< CLK_T::CLKSEL3: SC2SEL Mask            */
+
+#define CLK_CLKSEL3_RTCSEL_Pos           (8)                                               /*!< CLK_T::CLKSEL3: RTCSEL Position        */
+#define CLK_CLKSEL3_RTCSEL_Msk           (0x1ul << CLK_CLKSEL3_RTCSEL_Pos)                 /*!< CLK_T::CLKSEL3: RTCSEL Mask            */
+
+#define CLK_CLKSEL3_QSPI1SEL_Pos         (12)                                              /*!< CLK_T::CLKSEL3: QSPI1SEL Position      */
+#define CLK_CLKSEL3_QSPI1SEL_Msk         (0x3ul << CLK_CLKSEL3_QSPI1SEL_Pos)               /*!< CLK_T::CLKSEL3: QSPI1SEL Mask          */
+
+#define CLK_CLKSEL3_I2S0SEL_Pos          (16)                                              /*!< CLK_T::CLKSEL3: I2S0SEL Position       */
+#define CLK_CLKSEL3_I2S0SEL_Msk          (0x3ul << CLK_CLKSEL3_I2S0SEL_Pos)                /*!< CLK_T::CLKSEL3: I2S0SEL Mask           */
+
+#define CLK_CLKSEL3_UART6SEL_Pos         (20)                                              /*!< CLK_T::CLKSEL3: UART6SEL Position      */
+#define CLK_CLKSEL3_UART6SEL_Msk         (0x3ul << CLK_CLKSEL3_UART6SEL_Pos)               /*!< CLK_T::CLKSEL3: UART6SEL Mask          */
+
+#define CLK_CLKSEL3_UART7SEL_Pos         (22)                                              /*!< CLK_T::CLKSEL3: UART7SEL Position      */
+#define CLK_CLKSEL3_UART7SEL_Msk         (0x3ul << CLK_CLKSEL3_UART7SEL_Pos)               /*!< CLK_T::CLKSEL3: UART7SEL Mask          */
+
+#define CLK_CLKSEL3_UART2SEL_Pos         (24)                                              /*!< CLK_T::CLKSEL3: UART2SEL Position      */
+#define CLK_CLKSEL3_UART2SEL_Msk         (0x3ul << CLK_CLKSEL3_UART2SEL_Pos)               /*!< CLK_T::CLKSEL3: UART2SEL Mask          */
+
+#define CLK_CLKSEL3_UART3SEL_Pos         (26)                                              /*!< CLK_T::CLKSEL3: UART3SEL Position      */
+#define CLK_CLKSEL3_UART3SEL_Msk         (0x3ul << CLK_CLKSEL3_UART3SEL_Pos)               /*!< CLK_T::CLKSEL3: UART3SEL Mask          */
+
+#define CLK_CLKSEL3_UART4SEL_Pos         (28)                                              /*!< CLK_T::CLKSEL3: UART4SEL Position      */
+#define CLK_CLKSEL3_UART4SEL_Msk         (0x3ul << CLK_CLKSEL3_UART4SEL_Pos)               /*!< CLK_T::CLKSEL3: UART4SEL Mask          */
+
+#define CLK_CLKSEL3_UART5SEL_Pos         (30)                                              /*!< CLK_T::CLKSEL3: UART5SEL Position      */
+#define CLK_CLKSEL3_UART5SEL_Msk         (0x3ul << CLK_CLKSEL3_UART5SEL_Pos)               /*!< CLK_T::CLKSEL3: UART5SEL Mask          */
+
+#define CLK_CLKDIV0_HCLKDIV_Pos          (0)                                               /*!< CLK_T::CLKDIV0: HCLKDIV Position       */
+#define CLK_CLKDIV0_HCLKDIV_Msk          (0xful << CLK_CLKDIV0_HCLKDIV_Pos)                /*!< CLK_T::CLKDIV0: HCLKDIV Mask           */
+
+#define CLK_CLKDIV0_USBDIV_Pos           (4)                                               /*!< CLK_T::CLKDIV0: USBDIV Position        */
+#define CLK_CLKDIV0_USBDIV_Msk           (0xful << CLK_CLKDIV0_USBDIV_Pos)                 /*!< CLK_T::CLKDIV0: USBDIV Mask            */
+
+#define CLK_CLKDIV0_UART0DIV_Pos         (8)                                               /*!< CLK_T::CLKDIV0: UART0DIV Position      */
+#define CLK_CLKDIV0_UART0DIV_Msk         (0xful << CLK_CLKDIV0_UART0DIV_Pos)               /*!< CLK_T::CLKDIV0: UART0DIV Mask          */
+
+#define CLK_CLKDIV0_UART1DIV_Pos         (12)                                              /*!< CLK_T::CLKDIV0: UART1DIV Position      */
+#define CLK_CLKDIV0_UART1DIV_Msk         (0xful << CLK_CLKDIV0_UART1DIV_Pos)               /*!< CLK_T::CLKDIV0: UART1DIV Mask          */
+
+#define CLK_CLKDIV0_EADCDIV_Pos          (16)                                              /*!< CLK_T::CLKDIV0: EADCDIV Position       */
+#define CLK_CLKDIV0_EADCDIV_Msk          (0xfful << CLK_CLKDIV0_EADCDIV_Pos)               /*!< CLK_T::CLKDIV0: EADCDIV Mask           */
+
+#define CLK_CLKDIV0_SDH0DIV_Pos          (24)                                              /*!< CLK_T::CLKDIV0: SDH0DIV Position       */
+#define CLK_CLKDIV0_SDH0DIV_Msk          (0xfful << CLK_CLKDIV0_SDH0DIV_Pos)               /*!< CLK_T::CLKDIV0: SDH0DIV Mask           */
+
+#define CLK_CLKDIV1_SC0DIV_Pos           (0)                                               /*!< CLK_T::CLKDIV1: SC0DIV Position        */
+#define CLK_CLKDIV1_SC0DIV_Msk           (0xfful << CLK_CLKDIV1_SC0DIV_Pos)                /*!< CLK_T::CLKDIV1: SC0DIV Mask            */
+
+#define CLK_CLKDIV1_SC1DIV_Pos           (8)                                               /*!< CLK_T::CLKDIV1: SC1DIV Position        */
+#define CLK_CLKDIV1_SC1DIV_Msk           (0xfful << CLK_CLKDIV1_SC1DIV_Pos)                /*!< CLK_T::CLKDIV1: SC1DIV Mask            */
+
+#define CLK_CLKDIV1_SC2DIV_Pos           (16)                                              /*!< CLK_T::CLKDIV1: SC2DIV Position        */
+#define CLK_CLKDIV1_SC2DIV_Msk           (0xfful << CLK_CLKDIV1_SC2DIV_Pos)                /*!< CLK_T::CLKDIV1: SC2DIV Mask            */
+
+#define CLK_CLKDIV2_I2SDIV_Pos           (0)                                               /*!< CLK_T::CLKDIV2: I2SDIV Position        */
+#define CLK_CLKDIV2_I2SDIV_Msk           (0xful << CLK_CLKDIV2_I2SDIV_Pos)                 /*!< CLK_T::CLKDIV2: I2SDIV Mask            */
+
+#define CLK_CLKDIV2_EADC1DIV_Pos         (24)                                              /*!< CLK_T::CLKDIV2: EADC1DIV Position      */
+#define CLK_CLKDIV2_EADC1DIV_Msk         (0xfful << CLK_CLKDIV2_EADC1DIV_Pos)              /*!< CLK_T::CLKDIV2: EADC1DIV Mask          */
+
+#define CLK_CLKDIV3_CCAPDIV_Pos          (0)                                               /*!< CLK_T::CLKDIV3: CCAPDIV Position       */
+#define CLK_CLKDIV3_CCAPDIV_Msk          (0xfful << CLK_CLKDIV3_CCAPDIV_Pos)               /*!< CLK_T::CLKDIV3: CCAPDIV Mask           */
+
+#define CLK_CLKDIV3_VSENSEDIV_Pos        (8)                                               /*!< CLK_T::CLKDIV3: VSENSEDIV Position     */
+#define CLK_CLKDIV3_VSENSEDIV_Msk        (0xfful << CLK_CLKDIV3_VSENSEDIV_Pos)             /*!< CLK_T::CLKDIV3: VSENSEDIV Mask         */
+
+#define CLK_CLKDIV3_EMACDIV_Pos          (16)                                              /*!< CLK_T::CLKDIV3: EMACDIV Position       */
+#define CLK_CLKDIV3_EMACDIV_Msk          (0xfful << CLK_CLKDIV3_EMACDIV_Pos)               /*!< CLK_T::CLKDIV3: EMACDIV Mask           */
+
+#define CLK_CLKDIV3_SDH1DIV_Pos          (24)                                              /*!< CLK_T::CLKDIV3: SDH1DIV Position       */
+#define CLK_CLKDIV3_SDH1DIV_Msk          (0xfful << CLK_CLKDIV3_SDH1DIV_Pos)               /*!< CLK_T::CLKDIV3: SDH1DIV Mask           */
+
+#define CLK_CLKDIV4_UART2DIV_Pos         (0)                                               /*!< CLK_T::CLKDIV4: UART2DIV Position      */
+#define CLK_CLKDIV4_UART2DIV_Msk         (0xful << CLK_CLKDIV4_UART2DIV_Pos)               /*!< CLK_T::CLKDIV4: UART2DIV Mask          */
+
+#define CLK_CLKDIV4_UART3DIV_Pos         (4)                                               /*!< CLK_T::CLKDIV4: UART3DIV Position      */
+#define CLK_CLKDIV4_UART3DIV_Msk         (0xful << CLK_CLKDIV4_UART3DIV_Pos)               /*!< CLK_T::CLKDIV4: UART3DIV Mask          */
+
+#define CLK_CLKDIV4_UART4DIV_Pos         (8)                                               /*!< CLK_T::CLKDIV4: UART4DIV Position      */
+#define CLK_CLKDIV4_UART4DIV_Msk         (0xful << CLK_CLKDIV4_UART4DIV_Pos)               /*!< CLK_T::CLKDIV4: UART4DIV Mask          */
+
+#define CLK_CLKDIV4_UART5DIV_Pos         (12)                                              /*!< CLK_T::CLKDIV4: UART5DIV Position      */
+#define CLK_CLKDIV4_UART5DIV_Msk         (0xful << CLK_CLKDIV4_UART5DIV_Pos)               /*!< CLK_T::CLKDIV4: UART5DIV Mask          */
+
+#define CLK_CLKDIV4_UART6DIV_Pos         (16)                                              /*!< CLK_T::CLKDIV4: UART6DIV Position      */
+#define CLK_CLKDIV4_UART6DIV_Msk         (0xful << CLK_CLKDIV4_UART6DIV_Pos)               /*!< CLK_T::CLKDIV4: UART6DIV Mask          */
+
+#define CLK_CLKDIV4_UART7DIV_Pos         (20)                                              /*!< CLK_T::CLKDIV4: UART7DIV Position      */
+#define CLK_CLKDIV4_UART7DIV_Msk         (0xful << CLK_CLKDIV4_UART7DIV_Pos)               /*!< CLK_T::CLKDIV4: UART7DIV Mask          */
+
+#define CLK_PCLKDIV_APB0DIV_Pos          (0)                                               /*!< CLK_T::PCLKDIV: APB0DIV Position       */
+#define CLK_PCLKDIV_APB0DIV_Msk          (0x7ul << CLK_PCLKDIV_APB0DIV_Pos)                /*!< CLK_T::PCLKDIV: APB0DIV Mask           */
+
+#define CLK_PCLKDIV_APB1DIV_Pos          (4)                                               /*!< CLK_T::PCLKDIV: APB1DIV Position       */
+#define CLK_PCLKDIV_APB1DIV_Msk          (0x7ul << CLK_PCLKDIV_APB1DIV_Pos)                /*!< CLK_T::PCLKDIV: APB1DIV Mask           */
+
+#define CLK_PLLCTL_FBDIV_Pos             (0)                                               /*!< CLK_T::PLLCTL: FBDIV Position          */
+#define CLK_PLLCTL_FBDIV_Msk             (0x1fful << CLK_PLLCTL_FBDIV_Pos)                 /*!< CLK_T::PLLCTL: FBDIV Mask              */
+
+#define CLK_PLLCTL_INDIV_Pos             (9)                                               /*!< CLK_T::PLLCTL: INDIV Position          */
+#define CLK_PLLCTL_INDIV_Msk             (0x1ful << CLK_PLLCTL_INDIV_Pos)                  /*!< CLK_T::PLLCTL: INDIV Mask              */
+
+#define CLK_PLLCTL_OUTDIV_Pos            (14)                                              /*!< CLK_T::PLLCTL: OUTDIV Position         */
+#define CLK_PLLCTL_OUTDIV_Msk            (0x3ul << CLK_PLLCTL_OUTDIV_Pos)                  /*!< CLK_T::PLLCTL: OUTDIV Mask             */
+
+#define CLK_PLLCTL_PD_Pos                (16)                                              /*!< CLK_T::PLLCTL: PD Position             */
+#define CLK_PLLCTL_PD_Msk                (0x1ul << CLK_PLLCTL_PD_Pos)                      /*!< CLK_T::PLLCTL: PD Mask                 */
+
+#define CLK_PLLCTL_BP_Pos                (17)                                              /*!< CLK_T::PLLCTL: BP Position             */
+#define CLK_PLLCTL_BP_Msk                (0x1ul << CLK_PLLCTL_BP_Pos)                      /*!< CLK_T::PLLCTL: BP Mask                 */
+
+#define CLK_PLLCTL_OE_Pos                (18)                                              /*!< CLK_T::PLLCTL: OE Position             */
+#define CLK_PLLCTL_OE_Msk                (0x1ul << CLK_PLLCTL_OE_Pos)                      /*!< CLK_T::PLLCTL: OE Mask                 */
+
+#define CLK_PLLCTL_PLLSRC_Pos            (19)                                              /*!< CLK_T::PLLCTL: PLLSRC Position         */
+#define CLK_PLLCTL_PLLSRC_Msk            (0x1ul << CLK_PLLCTL_PLLSRC_Pos)                  /*!< CLK_T::PLLCTL: PLLSRC Mask             */
+
+#define CLK_PLLCTL_STBSEL_Pos            (23)                                              /*!< CLK_T::PLLCTL: STBSEL Position         */
+#define CLK_PLLCTL_STBSEL_Msk            (0x1ul << CLK_PLLCTL_STBSEL_Pos)                  /*!< CLK_T::PLLCTL: STBSEL Mask             */
+
+#define CLK_STATUS_HXTSTB_Pos            (0)                                               /*!< CLK_T::STATUS: HXTSTB Position         */
+#define CLK_STATUS_HXTSTB_Msk            (0x1ul << CLK_STATUS_HXTSTB_Pos)                  /*!< CLK_T::STATUS: HXTSTB Mask             */
+
+#define CLK_STATUS_LXTSTB_Pos            (1)                                               /*!< CLK_T::STATUS: LXTSTB Position         */
+#define CLK_STATUS_LXTSTB_Msk            (0x1ul << CLK_STATUS_LXTSTB_Pos)                  /*!< CLK_T::STATUS: LXTSTB Mask             */
+
+#define CLK_STATUS_PLLSTB_Pos            (2)                                               /*!< CLK_T::STATUS: PLLSTB Position         */
+#define CLK_STATUS_PLLSTB_Msk            (0x1ul << CLK_STATUS_PLLSTB_Pos)                  /*!< CLK_T::STATUS: PLLSTB Mask             */
+
+#define CLK_STATUS_LIRCSTB_Pos           (3)                                               /*!< CLK_T::STATUS: LIRCSTB Position        */
+#define CLK_STATUS_LIRCSTB_Msk           (0x1ul << CLK_STATUS_LIRCSTB_Pos)                 /*!< CLK_T::STATUS: LIRCSTB Mask            */
+
+#define CLK_STATUS_HIRCSTB_Pos           (4)                                               /*!< CLK_T::STATUS: HIRCSTB Position        */
+#define CLK_STATUS_HIRCSTB_Msk           (0x1ul << CLK_STATUS_HIRCSTB_Pos)                 /*!< CLK_T::STATUS: HIRCSTB Mask            */
+
+#define CLK_STATUS_HIRC48MSTB_Pos        (6)                                               /*!< CLK_T::STATUS: HIRC48MSTB Position     */
+#define CLK_STATUS_HIRC48MSTB_Msk        (0x1ul << CLK_STATUS_HIRC48MSTB_Pos)              /*!< CLK_T::STATUS: HIRC48MSTB Mask         */
+
+#define CLK_STATUS_CLKSFAIL_Pos          (7)                                               /*!< CLK_T::STATUS: CLKSFAIL Position       */
+#define CLK_STATUS_CLKSFAIL_Msk          (0x1ul << CLK_STATUS_CLKSFAIL_Pos)                /*!< CLK_T::STATUS: CLKSFAIL Mask           */
+
+#define CLK_CLKOCTL_FREQSEL_Pos          (0)                                               /*!< CLK_T::CLKOCTL: FREQSEL Position       */
+#define CLK_CLKOCTL_FREQSEL_Msk          (0xful << CLK_CLKOCTL_FREQSEL_Pos)                /*!< CLK_T::CLKOCTL: FREQSEL Mask           */
+
+#define CLK_CLKOCTL_CLKOEN_Pos           (4)                                               /*!< CLK_T::CLKOCTL: CLKOEN Position        */
+#define CLK_CLKOCTL_CLKOEN_Msk           (0x1ul << CLK_CLKOCTL_CLKOEN_Pos)                 /*!< CLK_T::CLKOCTL: CLKOEN Mask            */
+
+#define CLK_CLKOCTL_DIV1EN_Pos           (5)                                               /*!< CLK_T::CLKOCTL: DIV1EN Position        */
+#define CLK_CLKOCTL_DIV1EN_Msk           (0x1ul << CLK_CLKOCTL_DIV1EN_Pos)                 /*!< CLK_T::CLKOCTL: DIV1EN Mask            */
+
+#define CLK_CLKOCTL_CLK1HZEN_Pos         (6)                                               /*!< CLK_T::CLKOCTL: CLK1HZEN Position      */
+#define CLK_CLKOCTL_CLK1HZEN_Msk         (0x1ul << CLK_CLKOCTL_CLK1HZEN_Pos)               /*!< CLK_T::CLKOCTL: CLK1HZEN Mask          */
+
+#define CLK_CLKDCTL_HXTFDEN_Pos          (4)                                               /*!< CLK_T::CLKDCTL: HXTFDEN Position       */
+#define CLK_CLKDCTL_HXTFDEN_Msk          (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos)                /*!< CLK_T::CLKDCTL: HXTFDEN Mask           */
+
+#define CLK_CLKDCTL_HXTFIEN_Pos          (5)                                               /*!< CLK_T::CLKDCTL: HXTFIEN Position       */
+#define CLK_CLKDCTL_HXTFIEN_Msk          (0x1ul << CLK_CLKDCTL_HXTFIEN_Pos)                /*!< CLK_T::CLKDCTL: HXTFIEN Mask           */
+
+#define CLK_CLKDCTL_LXTFDEN_Pos          (12)                                              /*!< CLK_T::CLKDCTL: LXTFDEN Position       */
+#define CLK_CLKDCTL_LXTFDEN_Msk          (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos)                /*!< CLK_T::CLKDCTL: LXTFDEN Mask           */
+
+#define CLK_CLKDCTL_LXTFIEN_Pos          (13)                                              /*!< CLK_T::CLKDCTL: LXTFIEN Position       */
+#define CLK_CLKDCTL_LXTFIEN_Msk          (0x1ul << CLK_CLKDCTL_LXTFIEN_Pos)                /*!< CLK_T::CLKDCTL: LXTFIEN Mask           */
+
+#define CLK_CLKDCTL_HXTFQDEN_Pos         (16)                                              /*!< CLK_T::CLKDCTL: HXTFQDEN Position      */
+#define CLK_CLKDCTL_HXTFQDEN_Msk         (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos)               /*!< CLK_T::CLKDCTL: HXTFQDEN Mask          */
+
+#define CLK_CLKDCTL_HXTFQIEN_Pos         (17)                                              /*!< CLK_T::CLKDCTL: HXTFQIEN Position      */
+#define CLK_CLKDCTL_HXTFQIEN_Msk         (0x1ul << CLK_CLKDCTL_HXTFQIEN_Pos)               /*!< CLK_T::CLKDCTL: HXTFQIEN Mask          */
+
+#define CLK_CLKDSTS_HXTFIF_Pos           (0)                                               /*!< CLK_T::CLKDSTS: HXTFIF Position        */
+#define CLK_CLKDSTS_HXTFIF_Msk           (0x1ul << CLK_CLKDSTS_HXTFIF_Pos)                 /*!< CLK_T::CLKDSTS: HXTFIF Mask            */
+
+#define CLK_CLKDSTS_LXTFIF_Pos           (1)                                               /*!< CLK_T::CLKDSTS: LXTFIF Position        */
+#define CLK_CLKDSTS_LXTFIF_Msk           (0x1ul << CLK_CLKDSTS_LXTFIF_Pos)                 /*!< CLK_T::CLKDSTS: LXTFIF Mask            */
+
+#define CLK_CLKDSTS_HXTFQIF_Pos          (8)                                               /*!< CLK_T::CLKDSTS: HXTFQIF Position       */
+#define CLK_CLKDSTS_HXTFQIF_Msk          (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos)                /*!< CLK_T::CLKDSTS: HXTFQIF Mask           */
+
+#define CLK_CDUPB_UPERBD_Pos             (0)                                               /*!< CLK_T::CDUPB: UPERBD Position          */
+#define CLK_CDUPB_UPERBD_Msk             (0x3fful << CLK_CDUPB_UPERBD_Pos)                 /*!< CLK_T::CDUPB: UPERBD Mask              */
+
+#define CLK_CDLOWB_LOWERBD_Pos           (0)                                               /*!< CLK_T::CDLOWB: LOWERBD Position        */
+#define CLK_CDLOWB_LOWERBD_Msk           (0x3fful << CLK_CDLOWB_LOWERBD_Pos)               /*!< CLK_T::CDLOWB: LOWERBD Mask            */
+
+#define CLK_PMUCTL_PDMSEL_Pos            (0)                                               /*!< CLK_T::PMUCTL: PDMSEL Position         */
+#define CLK_PMUCTL_PDMSEL_Msk            (0x7ul << CLK_PMUCTL_PDMSEL_Pos)                  /*!< CLK_T::PMUCTL: PDMSEL Mask             */
+
+#define CLK_PMUCTL_DPDHOLDEN_Pos         (3)                                               /*!< CLK_T::PMUCTL: DPDHOLDEN Position      */
+#define CLK_PMUCTL_DPDHOLDEN_Msk         (0x1ul << CLK_PMUCTL_DPDHOLDEN_Pos)               /*!< CLK_T::PMUCTL: DPDHOLDEN Mask          */
+
+#define CLK_PMUCTL_SRETSEL_Pos           (4)                                               /*!< CLK_T::PMUCTL: SRETSEL Position        */
+#define CLK_PMUCTL_SRETSEL_Msk           (0x7ul << CLK_PMUCTL_SRETSEL_Pos)                 /*!< CLK_T::PMUCTL: SRETSEL Mask            */
+
+#define CLK_PMUCTL_WKTMREN_Pos           (8)                                               /*!< CLK_T::PMUCTL: WKTMREN Position        */
+#define CLK_PMUCTL_WKTMREN_Msk           (0x1ul << CLK_PMUCTL_WKTMREN_Pos)                 /*!< CLK_T::PMUCTL: WKTMREN Mask            */
+
+#define CLK_PMUCTL_WKTMRIS_Pos           (9)                                               /*!< CLK_T::PMUCTL: WKTMRIS Position        */
+#define CLK_PMUCTL_WKTMRIS_Msk           (0xful << CLK_PMUCTL_WKTMRIS_Pos)                 /*!< CLK_T::PMUCTL: WKTMRIS Mask            */
+
+#define CLK_PMUCTL_WKPINEN_Pos           (16)                                              /*!< CLK_T::PMUCTL: WKPINEN Position        */
+#define CLK_PMUCTL_WKPINEN_Msk           (0x3ul << CLK_PMUCTL_WKPINEN_Pos)                 /*!< CLK_T::PMUCTL: WKPINEN Mask            */
+
+#define CLK_PMUCTL_ACMPSPWK_Pos          (18)                                              /*!< CLK_T::PMUCTL: ACMPSPWK Position       */
+#define CLK_PMUCTL_ACMPSPWK_Msk          (0x1ul << CLK_PMUCTL_ACMPSPWK_Pos)                /*!< CLK_T::PMUCTL: ACMPSPWK Mask           */
+
+#define CLK_PMUCTL_RTCWKEN_Pos           (23)                                              /*!< CLK_T::PMUCTL: RTCWKEN Position        */
+#define CLK_PMUCTL_RTCWKEN_Msk           (0x1ul << CLK_PMUCTL_RTCWKEN_Pos)                 /*!< CLK_T::PMUCTL: RTCWKEN Mask            */
+
+#define CLK_PMUCTL_WKPINEN1_Pos          (24)                                              /*!< CLK_T::PMUCTL: WKPINEN1 Position       */
+#define CLK_PMUCTL_WKPINEN1_Msk          (0x3ul << CLK_PMUCTL_WKPINEN1_Pos)                /*!< CLK_T::PMUCTL: WKPINEN1 Mask           */
+
+#define CLK_PMUCTL_WKPINEN2_Pos          (26)                                              /*!< CLK_T::PMUCTL: WKPINEN2 Position       */
+#define CLK_PMUCTL_WKPINEN2_Msk          (0x3ul << CLK_PMUCTL_WKPINEN2_Pos)                /*!< CLK_T::PMUCTL: WKPINEN2 Mask           */
+
+#define CLK_PMUCTL_WKPINEN3_Pos          (28)                                              /*!< CLK_T::PMUCTL: WKPINEN3 Position       */
+#define CLK_PMUCTL_WKPINEN3_Msk          (0x3ul << CLK_PMUCTL_WKPINEN3_Pos)                /*!< CLK_T::PMUCTL: WKPINEN3 Mask           */
+
+#define CLK_PMUCTL_WKPINEN4_Pos          (30)                                              /*!< CLK_T::PMUCTL: WKPINEN4 Position       */
+#define CLK_PMUCTL_WKPINEN4_Msk          (0x3ul << CLK_PMUCTL_WKPINEN4_Pos)                /*!< CLK_T::PMUCTL: WKPINEN4 Mask           */
+
+#define CLK_PMUSTS_PINWK_Pos             (0)                                               /*!< CLK_T::PMUSTS: PINWK Position          */
+#define CLK_PMUSTS_PINWK_Msk             (0x1ul << CLK_PMUSTS_PINWK_Pos)                   /*!< CLK_T::PMUSTS: PINWK Mask              */
+
+#define CLK_PMUSTS_TMRWK_Pos             (1)                                               /*!< CLK_T::PMUSTS: TMRWK Position          */
+#define CLK_PMUSTS_TMRWK_Msk             (0x1ul << CLK_PMUSTS_TMRWK_Pos)                   /*!< CLK_T::PMUSTS: TMRWK Mask              */
+
+#define CLK_PMUSTS_RTCWK_Pos             (2)                                               /*!< CLK_T::PMUSTS: RTCWK Position          */
+#define CLK_PMUSTS_RTCWK_Msk             (0x1ul << CLK_PMUSTS_RTCWK_Pos)                   /*!< CLK_T::PMUSTS: RTCWK Mask              */
+
+#define CLK_PMUSTS_PINWK1_Pos            (3)                                               /*!< CLK_T::PMUSTS: PINWK1 Position         */
+#define CLK_PMUSTS_PINWK1_Msk            (0x1ul << CLK_PMUSTS_PINWK1_Pos)                  /*!< CLK_T::PMUSTS: PINWK1 Mask             */
+
+#define CLK_PMUSTS_PINWK2_Pos            (4)                                               /*!< CLK_T::PMUSTS: PINWK2 Position         */
+#define CLK_PMUSTS_PINWK2_Msk            (0x1ul << CLK_PMUSTS_PINWK2_Pos)                  /*!< CLK_T::PMUSTS: PINWK2 Mask             */
+
+#define CLK_PMUSTS_PINWK3_Pos            (5)                                               /*!< CLK_T::PMUSTS: PINWK3 Position         */
+#define CLK_PMUSTS_PINWK3_Msk            (0x1ul << CLK_PMUSTS_PINWK3_Pos)                  /*!< CLK_T::PMUSTS: PINWK3 Mask             */
+
+#define CLK_PMUSTS_PINWK4_Pos            (6)                                               /*!< CLK_T::PMUSTS: PINWK4 Position         */
+#define CLK_PMUSTS_PINWK4_Msk            (0x1ul << CLK_PMUSTS_PINWK4_Pos)                  /*!< CLK_T::PMUSTS: PINWK4 Mask             */
+
+#define CLK_PMUSTS_GPAWK_Pos             (8)                                               /*!< CLK_T::PMUSTS: GPAWK Position          */
+#define CLK_PMUSTS_GPAWK_Msk             (0x1ul << CLK_PMUSTS_GPAWK_Pos)                   /*!< CLK_T::PMUSTS: GPAWK Mask              */
+
+#define CLK_PMUSTS_GPBWK_Pos             (9)                                               /*!< CLK_T::PMUSTS: GPBWK Position          */
+#define CLK_PMUSTS_GPBWK_Msk             (0x1ul << CLK_PMUSTS_GPBWK_Pos)                   /*!< CLK_T::PMUSTS: GPBWK Mask              */
+
+#define CLK_PMUSTS_GPCWK_Pos             (10)                                              /*!< CLK_T::PMUSTS: GPCWK Position          */
+#define CLK_PMUSTS_GPCWK_Msk             (0x1ul << CLK_PMUSTS_GPCWK_Pos)                   /*!< CLK_T::PMUSTS: GPCWK Mask              */
+
+#define CLK_PMUSTS_GPDWK_Pos             (11)                                              /*!< CLK_T::PMUSTS: GPDWK Position          */
+#define CLK_PMUSTS_GPDWK_Msk             (0x1ul << CLK_PMUSTS_GPDWK_Pos)                   /*!< CLK_T::PMUSTS: GPDWK Mask              */
+
+#define CLK_PMUSTS_LVRWK_Pos             (12)                                              /*!< CLK_T::PMUSTS: LVRWK Position          */
+#define CLK_PMUSTS_LVRWK_Msk             (0x1ul << CLK_PMUSTS_LVRWK_Pos)                   /*!< CLK_T::PMUSTS: LVRWK Mask              */
+
+#define CLK_PMUSTS_BODWK_Pos             (13)                                              /*!< CLK_T::PMUSTS: BODWK Position          */
+#define CLK_PMUSTS_BODWK_Msk             (0x1ul << CLK_PMUSTS_BODWK_Pos)                   /*!< CLK_T::PMUSTS: BODWK Mask              */
+
+#define CLK_PMUSTS_ACMPWK_Pos            (14)                                              /*!< CLK_T::PMUSTS: ACMPWK Position         */
+#define CLK_PMUSTS_ACMPWK_Msk            (0x1ul << CLK_PMUSTS_ACMPWK_Pos)                  /*!< CLK_T::PMUSTS: ACMPWK Mask             */
+
+#define CLK_PMUSTS_CLRWK_Pos             (31)                                              /*!< CLK_T::PMUSTS: CLRWK Position          */
+#define CLK_PMUSTS_CLRWK_Msk             (0x1ul << CLK_PMUSTS_CLRWK_Pos)                   /*!< CLK_T::PMUSTS: CLRWK Mask              */
+
+#define CLK_LDOCTL_PDBIASEN_Pos          (18)                                              /*!< CLK_T::LDOCTL: PDBIASEN Position       */
+#define CLK_LDOCTL_PDBIASEN_Msk          (0x1ul << CLK_LDOCTL_PDBIASEN_Pos)                /*!< CLK_T::LDOCTL: PDBIASEN Mask           */
+
+#define CLK_SWKDBCTL_SWKDBCLKSEL_Pos     (0)                                               /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Position  */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_Msk     (0xful << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)           /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Mask      */
+
+#define CLK_PASWKCTL_WKEN_Pos            (0)                                               /*!< CLK_T::PASWKCTL: WKEN Position         */
+#define CLK_PASWKCTL_WKEN_Msk            (0x1ul << CLK_PASWKCTL_WKEN_Pos)                  /*!< CLK_T::PASWKCTL: WKEN Mask             */
+
+#define CLK_PASWKCTL_PRWKEN_Pos          (1)                                               /*!< CLK_T::PASWKCTL: PRWKEN Position       */
+#define CLK_PASWKCTL_PRWKEN_Msk          (0x1ul << CLK_PASWKCTL_PRWKEN_Pos)                /*!< CLK_T::PASWKCTL: PRWKEN Mask           */
+
+#define CLK_PASWKCTL_PFWKEN_Pos          (2)                                               /*!< CLK_T::PASWKCTL: PFWKEN Position       */
+#define CLK_PASWKCTL_PFWKEN_Msk          (0x1ul << CLK_PASWKCTL_PFWKEN_Pos)                /*!< CLK_T::PASWKCTL: PFWKEN Mask           */
+
+#define CLK_PASWKCTL_WKPSEL_Pos          (4)                                               /*!< CLK_T::PASWKCTL: WKPSEL Position       */
+#define CLK_PASWKCTL_WKPSEL_Msk          (0xful << CLK_PASWKCTL_WKPSEL_Pos)                /*!< CLK_T::PASWKCTL: WKPSEL Mask           */
+
+#define CLK_PASWKCTL_DBEN_Pos            (8)                                               /*!< CLK_T::PASWKCTL: DBEN Position         */
+#define CLK_PASWKCTL_DBEN_Msk            (0x1ul << CLK_PASWKCTL_DBEN_Pos)                  /*!< CLK_T::PASWKCTL: DBEN Mask             */
+
+#define CLK_PBSWKCTL_WKEN_Pos            (0)                                               /*!< CLK_T::PBSWKCTL: WKEN Position         */
+#define CLK_PBSWKCTL_WKEN_Msk            (0x1ul << CLK_PBSWKCTL_WKEN_Pos)                  /*!< CLK_T::PBSWKCTL: WKEN Mask             */
+
+#define CLK_PBSWKCTL_PRWKEN_Pos          (1)                                               /*!< CLK_T::PBSWKCTL: PRWKEN Position       */
+#define CLK_PBSWKCTL_PRWKEN_Msk          (0x1ul << CLK_PBSWKCTL_PRWKEN_Pos)                /*!< CLK_T::PBSWKCTL: PRWKEN Mask           */
+
+#define CLK_PBSWKCTL_PFWKEN_Pos          (2)                                               /*!< CLK_T::PBSWKCTL: PFWKEN Position       */
+#define CLK_PBSWKCTL_PFWKEN_Msk          (0x1ul << CLK_PBSWKCTL_PFWKEN_Pos)                /*!< CLK_T::PBSWKCTL: PFWKEN Mask           */
+
+#define CLK_PBSWKCTL_WKPSEL_Pos          (4)                                               /*!< CLK_T::PBSWKCTL: WKPSEL Position       */
+#define CLK_PBSWKCTL_WKPSEL_Msk          (0xful << CLK_PBSWKCTL_WKPSEL_Pos)                /*!< CLK_T::PBSWKCTL: WKPSEL Mask           */
+
+#define CLK_PBSWKCTL_DBEN_Pos            (8)                                               /*!< CLK_T::PBSWKCTL: DBEN Position         */
+#define CLK_PBSWKCTL_DBEN_Msk            (0x1ul << CLK_PBSWKCTL_DBEN_Pos)                  /*!< CLK_T::PBSWKCTL: DBEN Mask             */
+
+#define CLK_PCSWKCTL_WKEN_Pos            (0)                                               /*!< CLK_T::PCSWKCTL: WKEN Position         */
+#define CLK_PCSWKCTL_WKEN_Msk            (0x1ul << CLK_PCSWKCTL_WKEN_Pos)                  /*!< CLK_T::PCSWKCTL: WKEN Mask             */
+
+#define CLK_PCSWKCTL_PRWKEN_Pos          (1)                                               /*!< CLK_T::PCSWKCTL: PRWKEN Position       */
+#define CLK_PCSWKCTL_PRWKEN_Msk          (0x1ul << CLK_PCSWKCTL_PRWKEN_Pos)                /*!< CLK_T::PCSWKCTL: PRWKEN Mask           */
+
+#define CLK_PCSWKCTL_PFWKEN_Pos          (2)                                               /*!< CLK_T::PCSWKCTL: PFWKEN Position       */
+#define CLK_PCSWKCTL_PFWKEN_Msk          (0x1ul << CLK_PCSWKCTL_PFWKEN_Pos)                /*!< CLK_T::PCSWKCTL: PFWKEN Mask           */
+
+#define CLK_PCSWKCTL_WKPSEL_Pos          (4)                                               /*!< CLK_T::PCSWKCTL: WKPSEL Position       */
+#define CLK_PCSWKCTL_WKPSEL_Msk          (0xful << CLK_PCSWKCTL_WKPSEL_Pos)                /*!< CLK_T::PCSWKCTL: WKPSEL Mask           */
+
+#define CLK_PCSWKCTL_DBEN_Pos            (8)                                               /*!< CLK_T::PCSWKCTL: DBEN Position         */
+#define CLK_PCSWKCTL_DBEN_Msk            (0x1ul << CLK_PCSWKCTL_DBEN_Pos)                  /*!< CLK_T::PCSWKCTL: DBEN Mask             */
+
+#define CLK_PDSWKCTL_WKEN_Pos            (0)                                               /*!< CLK_T::PDSWKCTL: WKEN Position         */
+#define CLK_PDSWKCTL_WKEN_Msk            (0x1ul << CLK_PDSWKCTL_WKEN_Pos)                  /*!< CLK_T::PDSWKCTL: WKEN Mask             */
+
+#define CLK_PDSWKCTL_PRWKEN_Pos          (1)                                               /*!< CLK_T::PDSWKCTL: PRWKEN Position       */
+#define CLK_PDSWKCTL_PRWKEN_Msk          (0x1ul << CLK_PDSWKCTL_PRWKEN_Pos)                /*!< CLK_T::PDSWKCTL: PRWKEN Mask           */
+
+#define CLK_PDSWKCTL_PFWKEN_Pos          (2)                                               /*!< CLK_T::PDSWKCTL: PFWKEN Position       */
+#define CLK_PDSWKCTL_PFWKEN_Msk          (0x1ul << CLK_PDSWKCTL_PFWKEN_Pos)                /*!< CLK_T::PDSWKCTL: PFWKEN Mask           */
+
+#define CLK_PDSWKCTL_WKPSEL_Pos          (4)                                               /*!< CLK_T::PDSWKCTL: WKPSEL Position       */
+#define CLK_PDSWKCTL_WKPSEL_Msk          (0xful << CLK_PDSWKCTL_WKPSEL_Pos)                /*!< CLK_T::PDSWKCTL: WKPSEL Mask           */
+
+#define CLK_PDSWKCTL_DBEN_Pos            (8)                                               /*!< CLK_T::PDSWKCTL: DBEN Position         */
+#define CLK_PDSWKCTL_DBEN_Msk            (0x1ul << CLK_PDSWKCTL_DBEN_Pos)                  /*!< CLK_T::PDSWKCTL: DBEN Mask             */
+
+#define CLK_IOPDCTL_IOHR_Pos             (0)                                               /*!< CLK_T::IOPDCTL: IOHR Position          */
+#define CLK_IOPDCTL_IOHR_Msk             (0x1ul << CLK_IOPDCTL_IOHR_Pos)                   /*!< CLK_T::IOPDCTL: IOHR Mask              */
+
+/**@}*/ /* CLK_CONST */
+/**@}*/ /* end of CLK register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM   )
+#pragma no_anon_unions
+#endif
+
+#endif /* __CLK_REG_H__ */

dap_link/lib/free-dap/platform/m484/include/core_cm4.h

@@ -0,0 +1,1692 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V3.00
+ * @date     03. February 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+  
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'. 
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+   
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code. 
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+  @{
+ */
+
+/*  CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM4_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TASKING__ )
+    /* add preprocessor checks to define __FPU_USED */
+    #define __FPU_USED         0
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+#include <core_cm4_simd.h>               /* Compiler specific SIMD Intrinsics               */
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+ 
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                          /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)             /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                          /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                   /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                          /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)          /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                          /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                          /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)             /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                          /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                 /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_TXENA_Pos                   3                                          /*!< ITM TCR: TXENA Position */
+#define ITM_TCR_TXENA_Msk                  (1UL << ITM_TCR_TXENA_Pos)                  /*!< ITM TCR: TXENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                          /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                          /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                  /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                          /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                 /*!< ITM TCR: ITM Enable bit Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+    \brief      Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
+  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
+  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+#if (__FPU_PRESENT == 1)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+/*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
+  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+    
+    \param [in]      IRQn  Interrupt number.
+    
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt. 
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number. 
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.   
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+    
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+    
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
+
+  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+    
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif

dap_link/lib/free-dap/platform/m484/include/core_cm4_simd.h

@@ -0,0 +1,652 @@
+/**************************************************************************//**
+ * @file     core_cm4_simd.h
+ * @brief    CMSIS Cortex-M4 SIMD Header File
+ * @version  V3.00
+ * @date     19. January 2012
+ *
+ * @note
+ * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __CORE_CM4_SIMD_H
+#define __CORE_CM4_SIMD_H
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_iar.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_ccs.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+  
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+  
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+  
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLALD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLALDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLSLD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLSLDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+/* not yet supported */
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CORE_CM4_SIMD_H */
+
+#ifdef __cplusplus
+}
+#endif

dap_link/lib/free-dap/platform/m484/include/core_cmFunc.h

@@ -0,0 +1,619 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V3.00
+ * @date     19. January 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface   
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+ 
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+ 
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) );
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+ 
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+ 
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
+}
+ 
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+  
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) );
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+  
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */

dap_link/lib/free-dap/platform/m484/include/core_cmInstr.h

@@ -0,0 +1,621 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V3.00
+ * @date     07. February 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+ /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+
+  __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
+  return(op1);
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint8_t result;
+
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint16_t result;
+
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+  uint8_t result;
+
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */

dap_link/lib/free-dap/platform/m484/include/crc_reg.h

@@ -0,0 +1,150 @@
+/**************************************************************************//**
+ * @file     crc_reg.h
+ * @version  V1.00
+ * @brief    CRC register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __CRC_REG_H__
+#define __CRC_REG_H__
+
+#if defined ( __CC_ARM   )
+#pragma anon_unions
+#endif
+
+/**
+   @addtogroup REGISTER Control Register
+   @{
+*/
+
+/**
+    @addtogroup CRC Cyclic Redundancy Check Controller(CRC)
+    Memory Mapped Structure for CRC Controller
+@{ */
+
+typedef struct
+{
+
+
+    /**
+     * @var CRC_T::CTL
+     * Offset: 0x00  CRC Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CRCEN     |CRC Channel Enable Bit
+     * |        |          |0 = No effect.
+     * |        |          |1 = CRC operation Enabled.
+     * |[1]     |CHKSINIT  |Checksum Initialization
+     * |        |          |0 = No effect.
+     * |        |          |1 = Initial checksum value by auto reload CRC_SEED register value to CRC_CHECKSUM register value.
+     * |        |          |Note: This bit will be cleared automatically.
+     * |[24]    |DATREV    |Write Data Bit Order Reverse
+     * |        |          |This bit is used to enable the bit order reverse function per byte for write data value in CRC_DAT register.
+     * |        |          |0 = Bit order reversed for CRC write data in Disabled.
+     * |        |          |1 = Bit order reversed for CRC write data in Enabled (per byte).
+     * |        |          |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB.
+     * |[25]    |CHKSREV   |Checksum Bit Order Reverse
+     * |        |          |This bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register.
+     * |        |          |0 = Bit order reverse for CRC checksum Disabled.
+     * |        |          |1 = Bit order reverse for CRC checksum Enabled.
+     * |        |          |Note: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB.
+     * |[26]    |DATFMT    |Write Data 1's Complement
+     * |        |          |This bit is used to enable the 1's complement function for write data value in CRC_DAT register.
+     * |        |          |0 = 1's complement for CRC writes data in Disabled.
+     * |        |          |1 = 1's complement for CRC writes data in Enabled.
+     * |[27]    |CHKSFMT   |Checksum 1's Complement
+     * |        |          |This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register.
+     * |        |          |0 = 1's complement for CRC checksum Disabled.
+     * |        |          |1 = 1's complement for CRC checksum Enabled.
+     * |[29:28] |DATLEN    |CPU Write Data Length
+     * |        |          |This field indicates the write data length.
+     * |        |          |00 = Data length is 8-bit mode.
+     * |        |          |01 = Data length is 16-bit mode.
+     * |        |          |1x = Data length is 32-bit mode.
+     * |        |          |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]
+     * |[31:30] |CRCMODE   |CRC Polynomial Mode
+     * |        |          |This field indicates the CRC operation polynomial mode.
+     * |        |          |00 = CRC-CCITT Polynomial mode.
+     * |        |          |01 = CRC-8 Polynomial mode.
+     * |        |          |10 = CRC-16 Polynomial mode.
+     * |        |          |11 = CRC-32 Polynomial mode.
+     * @var CRC_T::DAT
+     * Offset: 0x04  CRC Write Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DATA      |CRC Write Data Bits
+     * |        |          |User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.
+     * |        |          |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
+     * @var CRC_T::SEED
+     * Offset: 0x08  CRC Seed Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SEED      |CRC Seed Value
+     * |        |          |This field indicates the CRC seed value.
+     * |        |          |Note: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after perform CHKSINIT (CRC_CTL[1]).
+     * @var CRC_T::CHECKSUM
+     * Offset: 0x0C  CRC Checksum Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CHECKSUM  |CRC Checksum Results
+     * |        |          |This field indicates the CRC checksum result.
+     */
+    __IO uint32_t CTL;                   /*!< [0x0000] CRC Control Register                                             */
+    __IO uint32_t DAT;                   /*!< [0x0004] CRC Write Data Register                                          */
+    __IO uint32_t SEED;                  /*!< [0x0008] CRC Seed Register                                                */
+    __I  uint32_t CHECKSUM;              /*!< [0x000c] CRC Checksum Register                                            */
+
+} CRC_T;
+
+/**
+    @addtogroup CRC_CONST CRC Bit Field Definition
+    Constant Definitions for CRC Controller
+@{ */
+
+#define CRC_CTL_CRCEN_Pos                (0)                                               /*!< CRC_T::CTL: CRCEN Position             */
+#define CRC_CTL_CRCEN_Msk                (0x1ul << CRC_CTL_CRCEN_Pos)                      /*!< CRC_T::CTL: CRCEN Mask                 */
+
+#define CRC_CTL_CHKSINIT_Pos             (1)                                               /*!< CRC_T::CTL: CHKSINIT Position          */
+#define CRC_CTL_CHKSINIT_Msk             (0x1ul << CRC_CTL_CHKSINIT_Pos)                   /*!< CRC_T::CTL: CHKSINIT Mask              */
+
+#define CRC_CTL_DATREV_Pos               (24)                                              /*!< CRC_T::CTL: DATREV Position            */
+#define CRC_CTL_DATREV_Msk               (0x1ul << CRC_CTL_DATREV_Pos)                     /*!< CRC_T::CTL: DATREV Mask                */
+
+#define CRC_CTL_CHKSREV_Pos              (25)                                              /*!< CRC_T::CTL: CHKSREV Position           */
+#define CRC_CTL_CHKSREV_Msk              (0x1ul << CRC_CTL_CHKSREV_Pos)                    /*!< CRC_T::CTL: CHKSREV Mask               */
+
+#define CRC_CTL_DATFMT_Pos               (26)                                              /*!< CRC_T::CTL: DATFMT Position            */
+#define CRC_CTL_DATFMT_Msk               (0x1ul << CRC_CTL_DATFMT_Pos)                     /*!< CRC_T::CTL: DATFMT Mask                */
+
+#define CRC_CTL_CHKSFMT_Pos              (27)                                              /*!< CRC_T::CTL: CHKSFMT Position           */
+#define CRC_CTL_CHKSFMT_Msk              (0x1ul << CRC_CTL_CHKSFMT_Pos)                    /*!< CRC_T::CTL: CHKSFMT Mask               */
+
+#define CRC_CTL_DATLEN_Pos               (28)                                              /*!< CRC_T::CTL: DATLEN Position            */
+#define CRC_CTL_DATLEN_Msk               (0x3ul << CRC_CTL_DATLEN_Pos)                     /*!< CRC_T::CTL: DATLEN Mask                */
+
+#define CRC_CTL_CRCMODE_Pos              (30)                                              /*!< CRC_T::CTL: CRCMODE Position           */
+#define CRC_CTL_CRCMODE_Msk              (0x3ul << CRC_CTL_CRCMODE_Pos)                    /*!< CRC_T::CTL: CRCMODE Mask               */
+
+#define CRC_DAT_DATA_Pos                 (0)                                               /*!< CRC_T::DAT: DATA Position              */
+#define CRC_DAT_DATA_Msk                 (0xfffffffful << CRC_DAT_DATA_Pos)                /*!< CRC_T::DAT: DATA Mask                  */
+
+#define CRC_SEED_SEED_Pos                (0)                                               /*!< CRC_T::SEED: SEED Position             */
+#define CRC_SEED_SEED_Msk                (0xfffffffful << CRC_SEED_SEED_Pos)               /*!< CRC_T::SEED: SEED Mask                 */
+
+#define CRC_CHECKSUM_CHECKSUM_Pos        (0)                                               /*!< CRC_T::CHECKSUM: CHECKSUM Position     */
+#define CRC_CHECKSUM_CHECKSUM_Msk        (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos)       /*!< CRC_T::CHECKSUM: CHECKSUM Mask         */
+
+/**@}*/ /* CRC_CONST */
+/**@}*/ /* end of CRC register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM   )
+#pragma no_anon_unions
+#endif
+
+#endif /* __CRC_REG_H__ */

dap_link/lib/free-dap/platform/m484/include/crypto_reg.h

@@ -0,0 +1,2219 @@
+/**************************************************************************//**
+ * @file     crypto_reg.h
+ * @version  V1.00
+ * @brief    CRYPTO register definition header file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __CRYPTO_REG_H__
+#define __CRYPTO_REG_H__
+
+#if defined ( __CC_ARM   )
+#pragma anon_unions
+#endif
+
+/**
+   @addtogroup REGISTER Control Register
+   @{
+*/
+
+/**
+    @addtogroup CRPT Cryptographic Accelerator(CRPT)
+    Memory Mapped Structure for Cryptographic Accelerator
+@{ */
+
+typedef struct
+{
+
+    /**
+     * @var CRPT_T::INTEN
+     * Offset: 0x00  Crypto Interrupt Enable Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |AESIEN    |AES Interrupt Enable Control
+     * |        |          |0 = AES interrupt Disabled.
+     * |        |          |1 = AES interrupt Enabled.
+     * |        |          |In DMA mode, an interrupt will be triggered when amount of data set in AES_DMA_CNT is fed into the AES engine.
+     * |        |          |In Non-DMA mode, an interrupt will be triggered when the AES engine finishes the operation.
+     * |[1]     |AESEIEN   |AES Error Flag Enable Control
+     * |        |          |0 = AES error interrupt flag Disabled.
+     * |        |          |1 = AES error interrupt flag Enabled.
+     * |[8]     |TDESIEN   |TDES/DES Interrupt Enable Control
+     * |        |          |0 = TDES/DES interrupt Disabled.
+     * |        |          |1 = TDES/DES interrupt Enabled.
+     * |        |          |In DMA mode, an interrupt will be triggered when amount of data set in TDES_DMA_CNT is fed into the TDES engine.
+     * |        |          |In Non-DMA mode, an interrupt will be triggered when the TDES engine finishes the operation.
+     * |[9]     |TDESEIEN  |TDES/DES Error Flag Enable Control
+     * |        |          |0 = TDES/DES error interrupt flag Disabled.
+     * |        |          |1 = TDES/DES error interrupt flag Enabled.
+     * |[16]    |PRNGIEN   |PRNG Interrupt Enable Control
+     * |        |          |0 = PRNG interrupt Disabled.
+     * |        |          |1 = PRNG interrupt Enabled.
+     * |[22]    |ECCIEN    |ECC Interrupt Enable Control
+     * |        |          |0 = ECC interrupt Disabled.
+     * |        |          |1 = ECC interrupt Enabled.
+     * |        |          |In DMA mode, an interrupt will be triggered when amount of data set in ECC_DMA_CNT is fed into the ECC engine.
+     * |        |          |In Non-DMA mode, an interrupt will be triggered when the ECC engine finishes the operation.
+     * |[23]    |ECCEIEN   |ECC Error Interrupt Enable Control
+     * |        |          |0 = ECC error interrupt flag Disabled.
+     * |        |          |1 = ECC error interrupt flag Enabled.
+     * |[24]    |HMACIEN   |SHA/HMAC Interrupt Enable Control
+     * |        |          |0 = SHA/HMAC interrupt Disabled.
+     * |        |          |1 = SHA/HMAC interrupt Enabled.
+     * |        |          |In DMA mode, an interrupt will be triggered when amount of data set in SHA _DMA_CNT is fed into the SHA/HMAC engine
+     * |        |          |In Non-DMA mode, an interrupt will be triggered when the SHA/HMAC engine finishes the operation.
+     * |[25]    |HMACEIEN  |SHA/HMAC Error Interrupt Enable Control
+     * |        |          |0 = SHA/HMAC error interrupt flag Disabled.
+     * |        |          |1 = SHA/HMAC error interrupt flag Enabled.
+     * @var CRPT_T::INTSTS
+     * Offset: 0x04  Crypto Interrupt Flag
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |AESIF     |AES Finish Interrupt Flag
+     * |        |          |This bit is cleared by writing 1, and it has no effect by writing 0.
+     * |        |          |0 = No AES interrupt.
+     * |        |          |= AES encryption/decryption done interrupt.
+     * |[1]     |AESEIF    |AES Error Flag
+     * |        |          |This bit is cleared by writing 1, and it has no effect by writing 0.
+     * |        |          |0 = No AES error.
+     * |        |          |1 = AES encryption/decryption done interrupt.
+     * |[8]     |TDESIF    |TDES/DES Finish Interrupt Flag
+     * |        |          |This bit is cleared by writing 1, and it has no effect by writing 0.
+     * |        |          |0 = No TDES/DES interrupt.
+     * |        |          |1 = TDES/DES encryption/decryption done interrupt.
+     * |[9]     |TDESEIF   |TDES/DES Error Flag
+     * |        |          |This bit includes the operating and setting error
+     * |        |          |The detailed flag is shown in the CRPT_TDES_STS register
+     * |        |          |This includes operating and setting error.
+     * |        |          |This bit is cleared by writing 1, and it has no effect by writing 0.
+     * |        |          |0 = No TDES/DES error.
+     * |        |          |1 = TDES/DES encryption/decryption error interrupt.
+     * |[16]    |PRNGIF    |PRNG Finish Interrupt Flag
+     * |        |          |This bit is cleared by writing 1, and it has no effect by writing 0.
+     * |        |          |0 = No PRNG interrupt.
+     * |        |          |1 = PRNG key generation done interrupt.
+     * |[22]    |ECCIF     |ECC Finish Interrupt Flag
+     * |        |          |This bit is cleared by writing 1, and it has no effect by writing 0.
+     * |        |          |0 = No ECC interrupt.
+     * |        |          |1 = ECC operation done interrupt.
+     * |[23]    |ECCEIF    |ECC Error Flag
+     * |        |          |This register includes operating and setting error. The detail flag is shown in CRPT_ECC_STS register.
+     * |        |          |This bit is cleared by writing 1, and it has no effect by writing 0.
+     * |        |          |0 = No ECC error.
+     * |        |          |1 = ECC error interrupt.
+     * |[24]    |HMACIF    |SHA/HMAC Finish Interrupt Flag
+     * |        |          |This bit is cleared by writing 1, and it has no effect by writing 0.
+     * |        |          |0 = No SHA/HMAC interrupt.
+     * |        |          |1 = SHA/HMAC operation done interrupt.
+     * |[25]    |HMACEIF   |SHA/HMAC Error Flag
+     * |        |          |This register includes operating and setting error. The detail flag is shown in CRPT_HMAC_STS register.
+     * |        |          |This bit is cleared by writing 1, and it has no effect by writing 0.
+     * |        |          |0 = No SHA/HMAC error.
+     * |        |          |1 = SHA/HMAC error interrupt.
+     * @var CRPT_T::PRNG_CTL
+     * Offset: 0x08  PRNG Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |START     |Start PRNG Engine
+     * |        |          |0 = Stop PRNG engine.
+     * |        |          |1 = Generate new key and store the new key to register CRPT_PRNG_KEYx , which will be cleared when the new key is generated.
+     * |[1]     |SEEDRLD   |Reload New Seed for PRNG Engine
+     * |        |          |0 = Generating key based on the current seed.
+     * |        |          |1 = Reload new seed.
+     * |[3:2]   |KEYSZ     |PRNG Generate Key Size
+     * |        |          |00 = 64 bits.
+     * |        |          |01 = 128 bits.
+     * |        |          |10 = 192 bits.
+     * |        |          |11 = 256 bits.
+     * |[8]     |BUSY      |PRNG Busy (Read Only)
+     * |        |          |0 = PRNG engine is idle.
+     * |        |          |1 = Indicate that the PRNG engine is generating CRPT_PRNG_KEYx.
+     * @var CRPT_T::PRNG_SEED
+     * Offset: 0x0C  Seed for PRNG
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SEED      |Seed for PRNG (Write Only)
+     * |        |          |The bits store the seed for PRNG engine.
+     * @var CRPT_T::PRNG_KEY[8]
+     * Offset: 0x10 ~ 0x2C  PRNG Generated Key0 ~ Key7
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |Store PRNG Generated Key (Read Only)
+     * |        |          |The bits store the key that is generated by PRNG.
+     * @var CRPT_T::AES_FDBCK[4]
+     * Offset: 0x50 ~ 0x5C  AES Engine Output Feedback Data after Cryptographic Operation
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |FDBCK     |AES Feedback Information
+     * |        |          |The feedback value is 128 bits in size.
+     * |        |          |The AES engine uses the data from CRPT_AES_FDBCKx as the data inputted to CRPT_AESn_IVx for the next block in DMA cascade mode.
+     * |        |          |The AES engine outputs feedback information for IV in the next block's operation
+     * |        |          |Software can use this feedback information to implement more than four DMA channels
+     * |        |          |Software can store that feedback value temporarily
+     * |        |          |After switching back, fill the stored feedback value to this register in the same channel operation, and then continue the operation with the original setting.
+     * @var CRPT_T::TDES_FDBCKH
+     * Offset: 0x60  TDES/DES Engine Output Feedback High Word Data after Cryptographic Operation
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |FDBCK     |TDES/DES Feedback
+     * |        |          |The feedback value is 64 bits in size.
+     * |        |          |The TDES/DES engine uses the data from {CRPT_TDES_FDBCKH, CRPT_TDES_FDBCKL} as the data inputted to {CRPT_TDESn_IVH, CRPT_TDESn_IVL} for the next block in DMA cascade mode
+     * |        |          |The feedback register is for CBC, CFB, and OFB mode.
+     * |        |          |TDES/DES engine outputs feedback information for IV in the next block's operation
+     * |        |          |Software can use this feedback information to implement more than four DMA channels
+     * |        |          |Software can store that feedback value temporarily
+     * |        |          |After switching back, fill the stored feedback value to this register in the same channel operation
+     * |        |          |Then can continue the operation with the original setting.
+     * @var CRPT_T::TDES_FDBCKL
+     * Offset: 0x64  TDES/DES Engine Output Feedback Low Word Data after Cryptographic Operation
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |FDBCK     |TDES/DES Feedback
+     * |        |          |The feedback value is 64 bits in size.
+     * |        |          |The TDES/DES engine uses the data from {CRPT_TDES_FDBCKH, CRPT_TDES_FDBCKL} as the data inputted to {CRPT_TDESn_IVH, CRPT_TDESn_IVL} for the next block in DMA cascade mode
+     * |        |          |The feedback register is for CBC, CFB, and OFB mode.
+     * |        |          |TDES/DES engine outputs feedback information for IV in the next block's operation
+     * |        |          |Software can use this feedback information to implement more than four DMA channels
+     * |        |          |Software can store that feedback value temporarily
+     * |        |          |After switching back, fill the stored feedback value to this register in the same channel operation
+     * |        |          |Then can continue the operation with the original setting.
+     * @var CRPT_T::AES_CTL
+     * Offset: 0x100  AES Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |START     |AES Engine Start
+     * |        |          |0 = No effect.
+     * |        |          |1 = Start AES engine. BUSY flag will be set.
+     * |        |          |Note: This bit is always 0 when it's read back.
+     * |[1]     |STOP      |AES Engine Stop
+     * |        |          |0 = No effect.
+     * |        |          |1 = Stop AES engine.
+     * |        |          |Note: This bit is always 0 when it's read back.
+     * |[3:2]   |KEYSZ     |AES Key Size
+     * |        |          |This bit defines three different key size for AES operation.
+     * |        |          |2'b00 = 128 bits key.
+     * |        |          |2'b01 = 192 bits key.
+     * |        |          |2'b10 = 256 bits key.
+     * |        |          |2'b11 = Reserved.
+     * |        |          |If the AES accelerator is operating and the corresponding flag BUSY is 1, updating this register has no effect.
+     * |[5]     |DMALAST   |AES Last Block
+     * |        |          |In DMA mode, this bit must be set as beginning the last DMA cascade round.
+     * |        |          |In Non-DMA mode, this bit must be set when feeding in the last block of data in ECB, CBC, CTR, OFB, and CFB mode, and feeding in the (last-1) block of data at CBC-CS1, CBC-CS2, and CBC-CS3 mode.
+     * |        |          |This bit is always 0 when it's read back. Must be written again once START is triggered.
+     * |[6]     |DMACSCAD  |AES Engine DMA with Cascade Mode
+     * |        |          |0 = DMA cascade function Disabled.
+     * |        |          |1 = In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation.
+     * |[7]     |DMAEN     |AES Engine DMA Enable Control
+     * |        |          |0 = AES DMA engine Disabled.
+     * |        |          |The AES engine operates in Non-DMA mode, and gets data from the port CRPT_AES_DATIN.
+     * |        |          |1 = AES_DMA engine Enabled.
+     * |        |          |The AES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
+     * |[15:8]  |OPMODE    |AES Engine Operation Modes
+     * |        |          |0x00 = ECB (Electronic Codebook Mode)  0x01 = CBC (Cipher Block Chaining Mode).
+     * |        |          |0x02 = CFB (Cipher Feedback Mode).
+     * |        |          |0x03 = OFB (Output Feedback Mode).
+     * |        |          |0x04 = CTR (Counter Mode).
+     * |        |          |0x10 = CBC-CS1 (CBC Ciphertext-Stealing 1 Mode).
+     * |        |          |0x11 = CBC-CS2 (CBC Ciphertext-Stealing 2 Mode).
+     * |        |          |0x12 = CBC-CS3 (CBC Ciphertext-Stealing 3 Mode).
+     * |[16]    |ENCRPT    |AES Encryption/Decryption
+     * |        |          |0 = AES engine executes decryption operation.
+     * |        |          |1 = AES engine executes encryption operation.
+     * |[22]    |OUTSWAP   |AES Engine Output Data Swap
+     * |        |          |0 = Keep the original order.
+     * |        |          |1 = The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
+     * |[23]    |INSWAP    |AES Engine Input Data Swap
+     * |        |          |0 = Keep the original order.
+     * |        |          |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
+     * |[25:24] |CHANNEL   |AES Engine Working Channel
+     * |        |          |00 = Current control register setting is for channel 0.
+     * |        |          |01 = Current control register setting is for channel 1.
+     * |        |          |10 = Current control register setting is for channel 2.
+     * |        |          |11 = Current control register setting is for channel 3.
+     * |[30:26] |KEYUNPRT  |Unprotect Key
+     * |        |          |Writing 0 to CRPT_AES_CTL[31] and "10110" to CRPT_AES_CTL[30:26] is to unprotect the AES key.
+     * |        |          |The KEYUNPRT can be read and written
+     * |        |          |When it is written as the AES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT.
+     * |[31]    |KEYPRT    |Protect Key
+     * |        |          |Read as a flag to reflect KEYPRT.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Protect the content of the AES key from reading
+     * |        |          |The return value for reading CRPT_AESn_KEYx is not the content of the registers CRPT_AESn_KEYx
+     * |        |          |Once it is set, it can be cleared by asserting KEYUNPRT
+     * |        |          |And the key content would be cleared as well.
+     * @var CRPT_T::AES_STS
+     * Offset: 0x104  AES Engine Flag
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BUSY      |AES Engine Busy
+     * |        |          |0 = The AES engine is idle or finished.
+     * |        |          |1 = The AES engine is under processing.
+     * |[8]     |INBUFEMPTY|AES Input Buffer Empty
+     * |        |          |0 = There are some data in input buffer waiting for the AES engine to process.
+     * |        |          |1 = AES input buffer is empty
+     * |        |          |Software needs to feed data to the AES engine
+     * |        |          |Otherwise, the AES engine will be pending to wait for input data.
+     * |[9]     |INBUFFULL |AES Input Buffer Full Flag
+     * |        |          |0 = AES input buffer is not full. Software can feed the data into the AES engine.
+     * |        |          |1 = AES input buffer is full
+     * |        |          |Software cannot feed data to the AES engine
+     * |        |          |Otherwise, the flag INBUFERR will be set to 1.
+     * |[10]    |INBUFERR  |AES Input Buffer Error Flag
+     * |        |          |0 = No error.
+     * |        |          |1 = Error happens during feeding data to the AES engine.
+     * |[12]    |CNTERR    |CRPT_AESn_CNT Setting Error
+     * |        |          |0 = No error in CRPT_AESn_CNT setting.
+     * |        |          |1 = CRPT_AESn_CNT is not a multiply of 16 in ECB, CBC, CFB, OFB, and CTR mode.
+     * |[16]    |OUTBUFEMPTY|AES Out Buffer Empty
+     * |        |          |0 = AES output buffer is not empty. There are some valid data kept in output buffer.
+     * |        |          |1 = AES output buffer is empty
+     * |        |          |Software cannot get data from CRPT_AES_DATOUT
+     * |        |          |Otherwise, the flag OUTBUFERR will be set to 1 since the output buffer is empty.
+     * |[17]    |OUTBUFFULL|AES Out Buffer Full Flag
+     * |        |          |0 = AES output buffer is not full.
+     * |        |          |1 = AES output buffer is full, and software needs to get data from CRPT_AES_DATOUT
+     * |        |          |Otherwise, the AES engine will be pending since the output buffer is full.
+     * |[18]    |OUTBUFERR |AES Out Buffer Error Flag
+     * |        |          |0 = No error.
+     * |        |          |1 = Error happens during getting the result from AES engine.
+     * |[20]    |BUSERR    |AES DMA Access Bus Error Flag
+     * |        |          |0 = No error.
+     * |        |          |1 = Bus error will stop DMA operation and AES engine.
+     * @var CRPT_T::AES_DATIN
+     * Offset: 0x108  AES Engine Data Input Port Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DATIN     |AES Engine Input Port
+     * |        |          |CPU feeds data to AES engine through this port by checking CRPT_AES_STS. Feed data as INBUFFULL is 0.
+     * @var CRPT_T::AES_DATOUT
+     * Offset: 0x10C  AES Engine Data Output Port Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DATOUT    |AES Engine Output Port
+     * |        |          |CPU gets results from the AES engine through this port by checking CRPT_AES_STS
+     * |        |          |Get data as OUTBUFEMPTY is 0.
+     * @var CRPT_T::AES0_KEY[8]
+     * Offset: 0x110 ~ 0x12C  AES Key Word 0 ~ 7 Register for Channel 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |CRPT_AESn_KEYx
+     * |        |          |The KEY keeps the security key for AES operation.
+     * |        |          |n = 0, 1..3.
+     * |        |          |x = 0, 1..7.
+     * |        |          |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key
+     * |        |          |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation
+     * |        |          |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation
+     * |        |          |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation.
+     * @var CRPT_T::AES0_IV[4]
+     * Offset: 0x130 ~ 0x13C  AES Initial Vector Word 0 ~ 3 Register for Channel 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |IV        |AES Initial Vectors
+     * |        |          |n = 0, 1..3.
+     * |        |          |x = 0, 1..3.
+     * |        |          |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode
+     * |        |          |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
+     * @var CRPT_T::AES0_SADDR
+     * Offset: 0x140  AES DMA Source Address Register for Channel 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SADDR     |AES DMA Source Address
+     * |        |          |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
+     * |        |          |The SADDR keeps the source address of the data buffer where the source text is stored
+     * |        |          |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation
+     * |        |          |The start of source address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of SADDR are ignored.
+     * |        |          |SADDR can be read and written
+     * |        |          |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation
+     * |        |          |But the value of SADDR will be updated later on
+     * |        |          |Consequently, software can prepare the DMA source address for the next AES operation.
+     * |        |          |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START.
+     * |        |          |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
+     * @var CRPT_T::AES0_DADDR
+     * Offset: 0x144  AES DMA Destination Address Register for Channel 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DADDR     |AES DMA Destination Address
+     * |        |          |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
+     * |        |          |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored
+     * |        |          |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished
+     * |        |          |The start of destination address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of DADDR are ignored.
+     * |        |          |DADDR can be read and written
+     * |        |          |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation
+     * |        |          |But the value of DADDR will be updated later on
+     * |        |          |Consequently, software can prepare the destination address for the next AES operation.
+     * |        |          |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START.
+     * |        |          |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
+     * @var CRPT_T::AES0_CNT
+     * Offset: 0x148  AES Byte Count Register for Channel 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CNT       |AES Byte Count
+     * |        |          |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode
+     * |        |          |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
+     * |        |          |CRPT_AESn_CNT can be read and written
+     * |        |          |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation
+     * |        |          |But the value of CRPT_AESn_CNT will be updated later on
+     * |        |          |Consequently, software can prepare the byte count of data for the next AES operation.
+     * |        |          |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block
+     * |        |          |Operations that are less than one block will output unexpected result.
+     * |        |          |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data
+     * |        |          |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
+     * @var CRPT_T::AES1_KEY[8]
+     * Offset: 0x14C ~ 0x168  AES Key Word 0 ~ 7 Register for Channel 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |CRPT_AESn_KEYx
+     * |        |          |The KEY keeps the security key for AES operation.
+     * |        |          |n = 0, 1..3.
+     * |        |          |x = 0, 1..7.
+     * |        |          |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key
+     * |        |          |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation
+     * |        |          |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation
+     * |        |          |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation.
+     * @var CRPT_T::AES1_IV[4]
+     * Offset: 0x16C ~ 0x178  AES Initial Vector Word 0 ~ 3 Register for Channel 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |IV        |AES Initial Vectors
+     * |        |          |n = 0, 1..3.
+     * |        |          |x = 0, 1..3.
+     * |        |          |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode
+     * |        |          |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
+     * @var CRPT_T::AES1_SADDR
+     * Offset: 0x17C  AES DMA Source Address Register for Channel 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SADDR     |AES DMA Source Address
+     * |        |          |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
+     * |        |          |The SADDR keeps the source address of the data buffer where the source text is stored
+     * |        |          |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation
+     * |        |          |The start of source address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of SADDR are ignored.
+     * |        |          |SADDR can be read and written
+     * |        |          |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation
+     * |        |          |But the value of SADDR will be updated later on
+     * |        |          |Consequently, software can prepare the DMA source address for the next AES operation.
+     * |        |          |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START.
+     * |        |          |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
+     * @var CRPT_T::AES1_DADDR
+     * Offset: 0x180  AES DMA Destination Address Register for Channel 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DADDR     |AES DMA Destination Address
+     * |        |          |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
+     * |        |          |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored
+     * |        |          |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished
+     * |        |          |The start of destination address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of DADDR are ignored.
+     * |        |          |DADDR can be read and written
+     * |        |          |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation
+     * |        |          |But the value of DADDR will be updated later on
+     * |        |          |Consequently, software can prepare the destination address for the next AES operation.
+     * |        |          |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START.
+     * |        |          |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
+     * @var CRPT_T::AES1_CNT
+     * Offset: 0x184  AES Byte Count Register for Channel 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CNT       |AES Byte Count
+     * |        |          |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode
+     * |        |          |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
+     * |        |          |CRPT_AESn_CNT can be read and written
+     * |        |          |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation
+     * |        |          |But the value of CRPT_AESn_CNT will be updated later on
+     * |        |          |Consequently, software can prepare the byte count of data for the next AES operation.
+     * |        |          |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block
+     * |        |          |Operations that are less than one block will output unexpected result.
+     * |        |          |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data
+     * |        |          |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
+     * @var CRPT_T::AES2_KEY[8]
+     * Offset: 0x188 ~ 0x1A4  AES Key Word 0 ~ 7 Register for Channel 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |CRPT_AESn_KEYx
+     * |        |          |The KEY keeps the security key for AES operation.
+     * |        |          |n = 0, 1..3.
+     * |        |          |x = 0, 1..7.
+     * |        |          |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key
+     * |        |          |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation
+     * |        |          |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation
+     * |        |          |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation.
+     * @var CRPT_T::AES2_IV[4]
+     * Offset: 0x1A8 ~ 0x1B4  AES Initial Vector Word 0 ~ 3 Register for Channel 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |IV        |AES Initial Vectors
+     * |        |          |n = 0, 1..3.
+     * |        |          |x = 0, 1..3.
+     * |        |          |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode
+     * |        |          |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
+     * @var CRPT_T::AES2_SADDR
+     * Offset: 0x1B8  AES DMA Source Address Register for Channel 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SADDR     |AES DMA Source Address
+     * |        |          |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
+     * |        |          |The SADDR keeps the source address of the data buffer where the source text is stored
+     * |        |          |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation
+     * |        |          |The start of source address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of SADDR are ignored.
+     * |        |          |SADDR can be read and written
+     * |        |          |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation
+     * |        |          |But the value of SADDR will be updated later on
+     * |        |          |Consequently, software can prepare the DMA source address for the next AES operation.
+     * |        |          |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START.
+     * |        |          |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
+     * @var CRPT_T::AES2_DADDR
+     * Offset: 0x1BC  AES DMA Destination Address Register for Channel 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DADDR     |AES DMA Destination Address
+     * |        |          |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
+     * |        |          |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored
+     * |        |          |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished
+     * |        |          |The start of destination address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of DADDR are ignored.
+     * |        |          |DADDR can be read and written
+     * |        |          |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation
+     * |        |          |But the value of DADDR will be updated later on
+     * |        |          |Consequently, software can prepare the destination address for the next AES operation.
+     * |        |          |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START.
+     * |        |          |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
+     * @var CRPT_T::AES2_CNT
+     * Offset: 0x1C0  AES Byte Count Register for Channel 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CNT       |AES Byte Count
+     * |        |          |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode
+     * |        |          |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
+     * |        |          |CRPT_AESn_CNT can be read and written
+     * |        |          |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation
+     * |        |          |But the value of CRPT_AESn_CNT will be updated later on
+     * |        |          |Consequently, software can prepare the byte count of data for the next AES operation.
+     * |        |          |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block
+     * |        |          |Operations that are less than one block will output unexpected result.
+     * |        |          |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data
+     * |        |          |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
+     * @var CRPT_T::AES3_KEY[8]
+     * Offset: 0x1C4 ~ 0x1E0  AES Key Word 0 ~ 7 Register for Channel 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |CRPT_AESn_KEYx
+     * |        |          |The KEY keeps the security key for AES operation.
+     * |        |          |n = 0, 1..3.
+     * |        |          |x = 0, 1..7.
+     * |        |          |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key
+     * |        |          |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation
+     * |        |          |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation
+     * |        |          |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation.
+     * @var CRPT_T::AES3_IV[4]
+     * Offset: 0x1E4 ~ 0x1F0  AES Initial Vector Word 0 ~ 3 Register for Channel 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |IV        |AES Initial Vectors
+     * |        |          |n = 0, 1..3.
+     * |        |          |x = 0, 1..3.
+     * |        |          |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode
+     * |        |          |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
+     * @var CRPT_T::AES3_SADDR
+     * Offset: 0x1F4  AES DMA Source Address Register for Channel 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SADDR     |AES DMA Source Address
+     * |        |          |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
+     * |        |          |The SADDR keeps the source address of the data buffer where the source text is stored
+     * |        |          |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation
+     * |        |          |The start of source address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of SADDR are ignored.
+     * |        |          |SADDR can be read and written
+     * |        |          |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation
+     * |        |          |But the value of SADDR will be updated later on
+     * |        |          |Consequently, software can prepare the DMA source address for the next AES operation.
+     * |        |          |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START.
+     * |        |          |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
+     * @var CRPT_T::AES3_DADDR
+     * Offset: 0x1F8  AES DMA Destination Address Register for Channel 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DADDR     |AES DMA Destination Address
+     * |        |          |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
+     * |        |          |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored
+     * |        |          |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished
+     * |        |          |The start of destination address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of DADDR are ignored.
+     * |        |          |DADDR can be read and written
+     * |        |          |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation
+     * |        |          |But the value of DADDR will be updated later on
+     * |        |          |Consequently, software can prepare the destination address for the next AES operation.
+     * |        |          |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START.
+     * |        |          |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
+     * @var CRPT_T::AES3_CNT
+     * Offset: 0x1FC  AES Byte Count Register for Channel 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CNT       |AES Byte Count
+     * |        |          |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode
+     * |        |          |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
+     * |        |          |CRPT_AESn_CNT can be read and written
+     * |        |          |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation
+     * |        |          |But the value of CRPT_AESn_CNT will be updated later on
+     * |        |          |Consequently, software can prepare the byte count of data for the next AES operation.
+     * |        |          |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block
+     * |        |          |Operations that are less than one block will output unexpected result.
+     * |        |          |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data
+     * |        |          |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
+     * @var CRPT_T::TDES_CTL
+     * Offset: 0x200  TDES/DES Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |START     |TDES/DES Engine Start
+     * |        |          |0 = No effect.
+     * |        |          |1 = Start TDES/DES engine. The flag BUSY would be set.
+     * |        |          |Note: The bit is always 0 when it's read back.
+     * |[1]     |STOP      |TDES/DES Engine Stop
+     * |        |          |0 = No effect.
+     * |        |          |1 = Stop TDES/DES engine.
+     * |        |          |Note: The bit is always 0 when it's read back.
+     * |[2]     |TMODE     |TDES/DES Engine Operating Mode
+     * |        |          |0 = Set DES mode for TDES/DES engine.
+     * |        |          |1 = Set Triple DES mode for TDES/DES engine.
+     * |[3]     |3KEYS     |TDES/DES Key Number
+     * |        |          |0 = Select KEY1 and KEY2 in TDES/DES engine.
+     * |        |          |1 = Triple keys in TDES/DES engine Enabled.
+     * |[5]     |DMALAST   |TDES/DES Engine Start for the Last Block
+     * |        |          |In DMA mode, this bit must be set as beginning the last DMA cascade round.
+     * |        |          |In Non-DMA mode, this bit must be set as feeding in last block of data.
+     * |[6]     |DMACSCAD  |TDES/DES Engine DMA with Cascade Mode
+     * |        |          |0 = DMA cascade function Disabled.
+     * |        |          |1 = In DMA Cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation.
+     * |[7]     |DMAEN     |TDES/DES Engine DMA Enable Control
+     * |        |          |0 = TDES_DMA engine Disabled.
+     * |        |          |TDES engine operates in Non-DMA mode, and get data from the port CRPT_TDES_DATIN.
+     * |        |          |1 = TDES_DMA engine Enabled.
+     * |        |          |TDES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
+     * |[10:8]  |OPMODE    |TDES/DES Engine Operation Mode
+     * |        |          |0x00 = ECB (Electronic Codebook Mode).
+     * |        |          |0x01 = CBC (Cipher Block Chaining Mode).
+     * |        |          |0x02 = CFB (Cipher Feedback Mode).
+     * |        |          |0x03 = OFB (Output Feedback Mode).
+     * |        |          |0x04 = CTR (Counter Mode).
+     * |        |          |Others = CTR (Counter Mode).
+     * |[16]    |ENCRPT    |TDES/DES Encryption/Decryption
+     * |        |          |0 = TDES engine executes decryption operation.
+     * |        |          |1 = TDES engine executes encryption operation.
+     * |[21]    |BLKSWAP   |TDES/DES Engine Block Double Word Endian Swap
+     * |        |          |0 = Keep the original order, e.g. {WORD_H, WORD_L}.
+     * |        |          |1 = When this bit is set to 1, the TDES engine would exchange high and low word in the sequence {WORD_L, WORD_H}.
+     * |[22]    |OUTSWAP   |TDES/DES Engine Output Data Swap
+     * |        |          |0 = Keep the original order.
+     * |        |          |1 = The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
+     * |[23]    |INSWAP    |TDES/DES Engine Input Data Swap
+     * |        |          |0 = Keep the original order.
+     * |        |          |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
+     * |[25:24] |CHANNEL   |TDES/DES Engine Working Channel
+     * |        |          |00 = Current control register setting is for channel 0.
+     * |        |          |01 = Current control register setting is for channel 1.
+     * |        |          |10 = Current control register setting is for channel 2.
+     * |        |          |11 = Current control register setting is for channel 3.
+     * |[30:26] |KEYUNPRT  |Unprotect Key
+     * |        |          |Writing 0 to CRPT_TDES_CTL [31] and "10110" to CRPT_TDES_CTL [30:26] is to unprotect TDES key.
+     * |        |          |The KEYUNPRT can be read and written
+     * |        |          |When it is written as the TDES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT.
+     * |[31]    |KEYPRT    |Protect Key
+     * |        |          |Read as a flag to reflect KEYPRT.
+     * |        |          |0 = No effect.
+     * |        |          |1 = This bit is to protect the content of TDES key from reading
+     * |        |          |The return value for reading CRPT_ TDESn_KEYxH/L is not the content in the registers CRPT_ TDESn_KEYxH/L
+     * |        |          |Once it is set, it can be cleared by asserting KEYUNPRT
+     * |        |          |The key content would be cleared as well.
+     * @var CRPT_T::TDES_STS
+     * Offset: 0x204  TDES/DES Engine Flag
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BUSY      |TDES/DES Engine Busy
+     * |        |          |0 = TDES/DES engine is idle or finished.
+     * |        |          |1 = TDES/DES engine is under processing.
+     * |[8]     |INBUFEMPTY|TDES/DES in Buffer Empty
+     * |        |          |0 = There are some data in input buffer waiting for the TDES/DES engine to process.
+     * |        |          |1 = TDES/DES input buffer is empty
+     * |        |          |Software needs to feed data to the TDES/DES engine
+     * |        |          |Otherwise, the TDES/DES engine will be pending to wait for input data.
+     * |[9]     |INBUFFULL |TDES/DES in Buffer Full Flag
+     * |        |          |0 = TDES/DES input buffer is not full. Software can feed the data into the TDES/DES engine.
+     * |        |          |1 = TDES input buffer is full
+     * |        |          |Software cannot feed data to the TDES/DES engine
+     * |        |          |Otherwise, the flag INBUFERR will be set to 1.
+     * |[10]    |INBUFERR  |TDES/DES in Buffer Error Flag
+     * |        |          |0 = No error.
+     * |        |          |1 = Error happens during feeding data to the TDES/DES engine.
+     * |[16]    |OUTBUFEMPTY|TDES/DES Output Buffer Empty Flag
+     * |        |          |0 = TDES/DES output buffer is not empty. There are some valid data kept in output buffer.
+     * |        |          |1 = TDES/DES output buffer is empty, Software cannot get data from TDES_DATA_OUT
+     * |        |          |Otherwise the flag OUTBUFERR will be set to 1, since output buffer is empty.
+     * |[17]    |OUTBUFFULL|TDES/DES Output Buffer Full Flag
+     * |        |          |0 = TDES/DES output buffer is not full.
+     * |        |          |1 = TDES/DES output buffer is full, and software needs to get data from TDES_DATA_OUT
+     * |        |          |Otherwise, the TDES/DES engine will be pending since output buffer is full.
+     * |[18]    |OUTBUFERR |TDES/DES Out Buffer Error Flag
+     * |        |          |0 = No error.
+     * |        |          |1 = Error happens during getting test result from TDES/DES engine.
+     * |[20]    |BUSERR    |TDES/DES DMA Access Bus Error Flag
+     * |        |          |0 = No error.
+     * |        |          |1 = Bus error will stop DMA operation and TDES/DES engine.
+     * @var CRPT_T::TDES0_KEY1H
+     * Offset: 0x208  TDES/DES Key 1 High Word Register for Channel 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 1 High Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES0_KEY1L
+     * Offset: 0x20C  TDES/DES Key 1 Low Word Register for Channel 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 1 Low Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES0_KEY2H
+     * Offset: 0x210  TDES Key 2 High Word Register for Channel 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 2 High Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES0_KEY2L
+     * Offset: 0x214  TDES Key 2 Low Word Register for Channel 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 2 Low Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES0_KEY3H
+     * Offset: 0x218  TDES Key 3 High Word Register for Channel 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 3 High Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES0_KEY3L
+     * Offset: 0x21C  TDES Key 3 Low Word Register for Channel 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 3 Low Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES0_IVH
+     * Offset: 0x220  TDES/DES Initial Vector High Word Register for Channel 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |IV        |TDES/DES Initial Vector High Word
+     * |        |          |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
+     * |        |          |IV is Nonce counter for TDES/DES engine in CTR mode.
+     * @var CRPT_T::TDES0_IVL
+     * Offset: 0x224  TDES/DES Initial Vector Low Word Register for Channel 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |IV        |TDES/DES Initial Vector Low Word
+     * |        |          |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
+     * |        |          |IV is Nonce counter for TDES/DES engine in CTR mode.
+     * @var CRPT_T::TDES0_SA
+     * Offset: 0x228  TDES/DES DMA Source Address Register for Channel 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SADDR     |TDES/DES DMA Source Address
+     * |        |          |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
+     * |        |          |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored
+     * |        |          |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation
+     * |        |          |The start of source address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored.
+     * |        |          |CRPT_TDESn_SA can be read and written
+     * |        |          |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
+     * |        |          |But the value of CRPT_TDESn_SA will be updated later on
+     * |        |          |Consequently, software can prepare the DMA source address for the next TDES/DES operation.
+     * |        |          |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START.
+     * |        |          |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value.
+     * @var CRPT_T::TDES0_DA
+     * Offset: 0x22C  TDES/DES DMA Destination Address Register for Channel 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DADDR     |TDES/DES DMA Destination Address
+     * |        |          |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
+     * |        |          |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored
+     * |        |          |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished
+     * |        |          |The start of destination address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored.
+     * |        |          |CRPT_TDESn_DA can be read and written
+     * |        |          |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
+     * |        |          |But the value of CRPT_TDESn_DA will be updated later on
+     * |        |          |Consequently, software can prepare the destination address for the next TDES/DES operation.
+     * |        |          |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START.
+     * |        |          |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value.
+     * @var CRPT_T::TDES0_CNT
+     * Offset: 0x230  TDES/DES Byte Count Register for Channel 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CNT       |TDES/DES Byte Count
+     * |        |          |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode
+     * |        |          |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
+     * |        |          |CRPT_TDESn_CNT can be read and written
+     * |        |          |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
+     * |        |          |But the value of CRPT_TDESn_CNT will be updated later on
+     * |        |          |Consequently, software can prepare the byte count of data for the next TDES /DES operation.
+     * |        |          |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data.
+     * @var CRPT_T::TDES_DATIN
+     * Offset: 0x234  TDES/DES Engine Input data Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DATIN     |TDES/DES Engine Input Port
+     * |        |          |CPU feeds data to TDES/DES engine through this port by checking CRPT_TDES_STS
+     * |        |          |Feed data as INBUFFULL is 0.
+     * @var CRPT_T::TDES_DATOUT
+     * Offset: 0x238  TDES/DES Engine Output data Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DATOUT    |TDES/DES Engine Output Port
+     * |        |          |CPU gets result from the TDES/DES engine through this port by checking CRPT_TDES_STS
+     * |        |          |Get data as OUTBUFEMPTY is 0.
+     * @var CRPT_T::TDES1_KEY1H
+     * Offset: 0x248  TDES/DES Key 1 High Word Register for Channel 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 1 High Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES1_KEY1L
+     * Offset: 0x24C  TDES/DES Key 1 Low Word Register for Channel 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 1 Low Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES1_KEY2H
+     * Offset: 0x250  TDES Key 2 High Word Register for Channel 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 2 High Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES1_KEY2L
+     * Offset: 0x254  TDES Key 2 Low Word Register for Channel 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 2 Low Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES1_KEY3H
+     * Offset: 0x258  TDES Key 3 High Word Register for Channel 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 3 High Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES1_KEY3L
+     * Offset: 0x25C  TDES Key 3 Low Word Register for Channel 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 3 Low Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES1_IVH
+     * Offset: 0x260  TDES/DES Initial Vector High Word Register for Channel 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |IV        |TDES/DES Initial Vector High Word
+     * |        |          |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
+     * |        |          |IV is Nonce counter for TDES/DES engine in CTR mode.
+     * @var CRPT_T::TDES1_IVL
+     * Offset: 0x264  TDES/DES Initial Vector Low Word Register for Channel 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |IV        |TDES/DES Initial Vector Low Word
+     * |        |          |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
+     * |        |          |IV is Nonce counter for TDES/DES engine in CTR mode.
+     * @var CRPT_T::TDES1_SA
+     * Offset: 0x268  TDES/DES DMA Source Address Register for Channel 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SADDR     |TDES/DES DMA Source Address
+     * |        |          |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
+     * |        |          |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored
+     * |        |          |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation
+     * |        |          |The start of source address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored.
+     * |        |          |CRPT_TDESn_SA can be read and written
+     * |        |          |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
+     * |        |          |But the value of CRPT_TDESn_SA will be updated later on
+     * |        |          |Consequently, software can prepare the DMA source address for the next TDES/DES operation.
+     * |        |          |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START.
+     * |        |          |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value.
+     * @var CRPT_T::TDES1_DA
+     * Offset: 0x26C  TDES/DES DMA Destination Address Register for Channel 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DADDR     |TDES/DES DMA Destination Address
+     * |        |          |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
+     * |        |          |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored
+     * |        |          |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished
+     * |        |          |The start of destination address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored.
+     * |        |          |CRPT_TDESn_DA can be read and written
+     * |        |          |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
+     * |        |          |But the value of CRPT_TDESn_DA will be updated later on
+     * |        |          |Consequently, software can prepare the destination address for the next TDES/DES operation.
+     * |        |          |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START.
+     * |        |          |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value.
+     * @var CRPT_T::TDES1_CNT
+     * Offset: 0x270  TDES/DES Byte Count Register for Channel 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CNT       |TDES/DES Byte Count
+     * |        |          |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode
+     * |        |          |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
+     * |        |          |CRPT_TDESn_CNT can be read and written
+     * |        |          |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
+     * |        |          |But the value of CRPT_TDESn_CNT will be updated later on
+     * |        |          |Consequently, software can prepare the byte count of data for the next TDES /DES operation.
+     * |        |          |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data.
+     * @var CRPT_T::TDES2_KEY1H
+     * Offset: 0x288  TDES/DES Key 1 High Word Register for Channel 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 1 High Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES2_KEY1L
+     * Offset: 0x28C  TDES/DES Key 1 Low Word Register for Channel 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 1 Low Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES2_KEY2H
+     * Offset: 0x290  TDES Key 2 High Word Register for Channel 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 2 High Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES2_KEY2L
+     * Offset: 0x294  TDES Key 2 Low Word Register for Channel 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 2 Low Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES2_KEY3H
+     * Offset: 0x298  TDES Key 3 High Word Register for Channel 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 3 High Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES2_KEY3L
+     * Offset: 0x29C  TDES Key 3 Low Word Register for Channel 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 3 Low Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES2_IVH
+     * Offset: 0x2A0  TDES/DES Initial Vector High Word Register for Channel 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |IV        |TDES/DES Initial Vector High Word
+     * |        |          |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
+     * |        |          |IV is Nonce counter for TDES/DES engine in CTR mode.
+     * @var CRPT_T::TDES2_IVL
+     * Offset: 0x2A4  TDES/DES Initial Vector Low Word Register for Channel 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |IV        |TDES/DES Initial Vector Low Word
+     * |        |          |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
+     * |        |          |IV is Nonce counter for TDES/DES engine in CTR mode.
+     * @var CRPT_T::TDES2_SA
+     * Offset: 0x2A8  TDES/DES DMA Source Address Register for Channel 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SADDR     |TDES/DES DMA Source Address
+     * |        |          |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
+     * |        |          |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored
+     * |        |          |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation
+     * |        |          |The start of source address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored.
+     * |        |          |CRPT_TDESn_SA can be read and written
+     * |        |          |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
+     * |        |          |But the value of CRPT_TDESn_SA will be updated later on
+     * |        |          |Consequently, software can prepare the DMA source address for the next TDES/DES operation.
+     * |        |          |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START.
+     * |        |          |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value.
+     * @var CRPT_T::TDES2_DA
+     * Offset: 0x2AC  TDES/DES DMA Destination Address Register for Channel 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DADDR     |TDES/DES DMA Destination Address
+     * |        |          |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
+     * |        |          |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored
+     * |        |          |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished
+     * |        |          |The start of destination address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored.
+     * |        |          |CRPT_TDESn_DA can be read and written
+     * |        |          |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
+     * |        |          |But the value of CRPT_TDESn_DA will be updated later on
+     * |        |          |Consequently, software can prepare the destination address for the next TDES/DES operation.
+     * |        |          |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START.
+     * |        |          |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value.
+     * @var CRPT_T::TDES2_CNT
+     * Offset: 0x2B0  TDES/DES Byte Count Register for Channel 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CNT       |TDES/DES Byte Count
+     * |        |          |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode
+     * |        |          |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
+     * |        |          |CRPT_TDESn_CNT can be read and written
+     * |        |          |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
+     * |        |          |But the value of CRPT_TDESn_CNT will be updated later on
+     * |        |          |Consequently, software can prepare the byte count of data for the next TDES /DES operation.
+     * |        |          |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data.
+     * @var CRPT_T::TDES3_KEY1H
+     * Offset: 0x2C8  TDES/DES Key 1 High Word Register for Channel 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 1 High Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES3_KEY1L
+     * Offset: 0x2CC  TDES/DES Key 1 Low Word Register for Channel 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 1 High Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES3_KEY2H
+     * Offset: 0x2D0  TDES Key 2 High Word Register for Channel 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 2 High Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES3_KEY2L
+     * Offset: 0x2D4  TDES Key 2 Low Word Register for Channel 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 2 Low Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES3_KEY3H
+     * Offset: 0x2D8  TDES Key 3 High Word Register for Channel 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 3 High Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES3_KEY3L
+     * Offset: 0x2DC  TDES Key 3 Low Word Register for Channel 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |TDES/DES Key 3 Low Word
+     * |        |          |The key registers for TDES/DES algorithm calculation
+     * |        |          |The security key for the TDES/DES accelerator is 64 bits
+     * |        |          |Thus, it needs two 32-bit registers to store a security key
+     * |        |          |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
+     * @var CRPT_T::TDES3_IVH
+     * Offset: 0x2E0  TDES/DES Initial Vector High Word Register for Channel 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |IV        |TDES/DES Initial Vector High Word
+     * |        |          |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
+     * |        |          |IV is Nonce counter for TDES/DES engine in CTR mode.
+     * @var CRPT_T::TDES3_IVL
+     * Offset: 0x2E4  TDES/DES Initial Vector Low Word Register for Channel 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |IV        |TDES/DES Initial Vector Low Word
+     * |        |          |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
+     * |        |          |IV is Nonce counter for TDES/DES engine in CTR mode.
+     * @var CRPT_T::TDES3_SA
+     * Offset: 0x2E8  TDES/DES DMA Source Address Register for Channel 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SADDR     |TDES/DES DMA Source Address
+     * |        |          |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
+     * |        |          |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored
+     * |        |          |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation
+     * |        |          |The start of source address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored.
+     * |        |          |CRPT_TDESn_SA can be read and written
+     * |        |          |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
+     * |        |          |But the value of CRPT_TDESn_SA will be updated later on
+     * |        |          |Consequently, software can prepare the DMA source address for the next TDES/DES operation.
+     * |        |          |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START.
+     * |        |          |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value.
+     * @var CRPT_T::TDES3_DA
+     * Offset: 0x2EC  TDES/DES DMA Destination Address Register for Channel 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DADDR     |TDES/DES DMA Destination Address
+     * |        |          |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
+     * |        |          |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored
+     * |        |          |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished
+     * |        |          |The start of destination address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored.
+     * |        |          |CRPT_TDESn_DA can be read and written
+     * |        |          |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
+     * |        |          |But the value of CRPT_TDESn_DA will be updated later on
+     * |        |          |Consequently, software can prepare the destination address for the next TDES/DES operation.
+     * |        |          |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START.
+     * |        |          |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value.
+     * @var CRPT_T::TDES3_CNT
+     * Offset: 0x2F0  TDES/DES Byte Count Register for Channel 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CNT       |TDES/DES Byte Count
+     * |        |          |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode
+     * |        |          |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
+     * |        |          |CRPT_TDESn_CNT can be read and written
+     * |        |          |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
+     * |        |          |But the value of CRPT_TDESn_CNT will be updated later on
+     * |        |          |Consequently, software can prepare the byte count of data for the next TDES /DES operation.
+     * |        |          |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data.
+     * @var CRPT_T::HMAC_CTL
+     * Offset: 0x300  SHA/HMAC Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |START     |SHA/HMAC Engine Start
+     * |        |          |0 = No effect.
+     * |        |          |1 = Start SHA/HMAC engine. BUSY flag will be set.
+     * |        |          |This bit is always 0 when it's read back.
+     * |[1]     |STOP      |SHA/HMAC Engine Stop
+     * |        |          |0 = No effect.
+     * |        |          |1 = Stop SHA/HMAC engine.
+     * |        |          |This bit is always 0 when it's read back.
+     * |[4]     |HMACEN    |HMAC_SHA Engine Operating Mode
+     * |        |          |0 = execute SHA function.
+     * |        |          |1 = execute HMAC function.
+     * |[5]     |DMALAST   |SHA/HMAC Last Block
+     * |        |          |This bit must be set as feeding in last byte of data.
+     * |[7]     |DMAEN     |SHA/HMAC Engine DMA Enable Control
+     * |        |          |0 = SHA/HMAC DMA engine Disabled.
+     * |        |          |SHA/HMAC engine operates in Non-DMA mode, and gets data from the port CRPT_HMAC_DATIN.
+     * |        |          |1 = SHA/HMAC DMA engine Enabled.
+     * |        |          |SHA/HMAC engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
+     * |[10:8]  |OPMODE    |SHA/HMAC Engine Operation Modes
+     * |        |          |0x0xx: SHA160
+     * |        |          |0x100: SHA256
+     * |        |          |0x101: SHA224
+     * |        |          |0x110: SHA512
+     * |        |          |0x111: SHA384
+     * |        |          |These bits can be read and written. But writing to them wouldn't take effect as BUSY is 1.
+     * |[22]    |OUTSWAP   |SHA/HMAC Engine Output Data Swap
+     * |        |          |0 = Keep the original order.
+     * |        |          |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
+     * |[23]    |INSWAP    |SHA/HMAC Engine Input Data Swap
+     * |        |          |0 = Keep the original order.
+     * |        |          |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
+     * @var CRPT_T::HMAC_STS
+     * Offset: 0x304  SHA/HMAC Status Flag
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BUSY      |SHA/HMAC Engine Busy
+     * |        |          |0 = SHA/HMAC engine is idle or finished.
+     * |        |          |1 = SHA/HMAC engine is busy.
+     * |[1]     |DMABUSY   |SHA/HMAC Engine DMA Busy Flag
+     * |        |          |0 = SHA/HMAC DMA engine is idle or finished.
+     * |        |          |1 = SHA/HMAC DMA engine is busy.
+     * |[8]     |DMAERR    |SHA/HMAC Engine DMA Error Flag
+     * |        |          |0 = Show the SHA/HMAC engine access normal.
+     * |        |          |1 = Show the SHA/HMAC engine access error.
+     * |[16]    |DATINREQ  |SHA/HMAC Non-DMA Mode Data Input Request
+     * |        |          |0 = No effect.
+     * |        |          |1 = Request SHA/HMAC Non-DMA mode data input.
+     * @var CRPT_T::HMAC_DGST[16]
+     * Offset: 0x308 ~ 0x344  SHA/HMAC Digest Message 0 ~ 15
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DGST      |SHA/HMAC Digest Message Output Register
+     * |        |          |For SHA-160, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST4.
+     * |        |          |For SHA-224, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST6.
+     * |        |          |For SHA-256, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST7.
+     * |        |          |For SHA-384, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST11.
+     * |        |          |For SHA-512, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST15.
+     * @var CRPT_T::HMAC_KEYCNT
+     * Offset: 0x348  SHA/HMAC Key Byte Count Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEYCNT    |SHA/HMAC Key Byte Count
+     * |        |          |The CRPT_HMAC_KEYCNT keeps the byte count of key that SHA/HMAC engine operates
+     * |        |          |The register is 32-bit and the maximum byte count is 4G bytes
+     * |        |          |It can be read and written.
+     * |        |          |Writing to the register CRPT_HMAC_KEYCNT as the SHA/HMAC accelerator operating doesn't affect the current SHA/HMAC operation
+     * |        |          |But the value of CRPT_SHA _KEYCNT will be updated later on
+     * |        |          |Consequently, software can prepare the key count for the next SHA/HMAC operation.
+     * @var CRPT_T::HMAC_SADDR
+     * Offset: 0x34C  SHA/HMAC DMA Source Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SADDR     |SHA/HMAC DMA Source Address
+     * |        |          |The SHA/HMAC accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
+     * |        |          |The CRPT_HMAC_SADDR keeps the source address of the data buffer where the source text is stored
+     * |        |          |Based on the source address, the SHA/HMAC accelerator can read the plain text from system memory and do SHA/HMAC operation
+     * |        |          |The start of source address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of CRPT_HMAC_SADDR are ignored.
+     * |        |          |CRPT_HMAC_SADDR can be read and written
+     * |        |          |Writing to CRPT_HMAC_SADDR while the SHA/HMAC accelerator is operating doesn't affect the current SHA/HMAC operation
+     * |        |          |But the value of CRPT_HMAC_SADDR will be updated later on
+     * |        |          |Consequently, software can prepare the DMA source address for the next SHA/HMAC operation.
+     * |        |          |In DMA mode, software can update the next CRPT_HMAC_SADDR before triggering START.
+     * |        |          |CRPT_HMAC_SADDR and CRPT_HMAC_DADDR can be the same in the value.
+     * @var CRPT_T::HMAC_DMACNT
+     * Offset: 0x350  SHA/HMAC Byte Count Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DMACNT    |SHA/HMAC Operation Byte Count
+     * |        |          |The CRPT_HMAC_DMACNT keeps the byte count of source text that is for the SHA/HMAC engine operating in DMA mode
+     * |        |          |The CRPT_HMAC_DMACNT is 32-bit and the maximum of byte count is 4G bytes.
+     * |        |          |CRPT_HMAC_DMACNT can be read and written
+     * |        |          |Writing to CRPT_HMAC_DMACNT while the SHA/HMAC accelerator is operating doesn't affect the current SHA/HMAC operation
+     * |        |          |But the value of CRPT_HMAC_DMACNT will be updated later on
+     * |        |          |Consequently, software can prepare the byte count of data for the next SHA/HMAC operation.
+     * |        |          |In Non-DMA mode, CRPT_HMAC_DMACNT must be set as the byte count of the last block before feeding in the last block of data.
+     * @var CRPT_T::HMAC_DATIN
+     * Offset: 0x354  SHA/HMAC Engine Non-DMA Mode Data Input Port Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DATIN     |SHA/HMAC Engine Input Port
+     * |        |          |CPU feeds data to SHA/HMAC engine through this port by checking CRPT_HMAC_STS
+     * |        |          |Feed data as DATINREQ is 1.
+     * @var CRPT_T::ECC_CTL
+     * Offset: 0x800  ECC Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |START     |ECC Accelerator Start
+     * |        |          |0 = No effect.
+     * |        |          |1 = Start ECC accelerator. BUSY flag will be set.
+     * |        |          |This bit is always 0 when it's read back.
+     * |        |          |ECC accelerator will ignore this START signal when BUSY flag is 1.
+     * |[1]     |STOP      |ECC Accelerator Stop
+     * |        |          |0 = No effect.
+     * |        |          |1 = Abort ECC accelerator and make it into idle state.
+     * |        |          |This bit is always 0 when it's read back.
+     * |        |          |Remember to clear ECC interrupt flag after stopping ECC accelerator.
+     * |[7]     |DMAEN     |ECC Accelerator DMA Enable Control
+     * |        |          |0 = ECC DMA engine Disabled.
+     * |        |          |1 = ECC DMA engine Enabled.
+     * |        |          |Only when START and DMAEN are 1, ECC DMA engine will be active
+     * |[8]     |FSEL      |Field Selection
+     * |        |          |0 = Binary Field (GF(2^m)).
+     * |        |          |1 = Prime Field (GF(p)).
+     * |[10:9]  |ECCOP     |Point Operation for BF and PF
+     * |        |          |00 = Point multiplication :.
+     * |        |          |(POINTX1, POINTY1) = SCALARK * (POINTX1, POINTY1).
+     * |        |          |01 = Modulus operation : choose by MODOP (CRPT_ECC_CTL[12:11]).
+     * |        |          |10 = Point addition :.
+     * |        |          |(POINTX1, POINTY1) = (POINTX1, POINTY1) +.
+     * |        |          |(POINTX2, POINTY2)
+     * |        |          |11 = Point doubling :.
+     * |        |          |(POINTX1, POINTY1) = 2 * (POINTX1, POINTY1).
+     * |        |          |Besides above three input data, point operations still need the parameters of elliptic curve (CURVEA, CURVEB, CURVEN and CURVEM) as shown in Figure 6.27-11
+     * |[12:11] |MODOP     |Modulus Operation for PF
+     * |        |          |00 = Division :.
+     * |        |          |POINTX1 = (POINTY1 / POINTX1) % CURVEN.
+     * |        |          |01 = Multiplication :.
+     * |        |          |POINTX1 = (POINTX1 * POINTY1) % CURVEN.
+     * |        |          |10 = Addition :.
+     * |        |          |POINTX1 = (POINTX1 + POINTY1) % CURVEN.
+     * |        |          |11 = Subtraction :.
+     * |        |          |POINTX1 = (POINTX1 - POINTY1) % CURVEN.
+     * |        |          |MODOP is active only when ECCOP = 01.
+     * |[16]    |LDP1      |The Control Signal of Register for the X and Y Coordinate of the First Point (POINTX1, POINTY1)
+     * |        |          |0 = The register for POINTX1 and POINTY1 is not modified by DMA or user.
+     * |        |          |1 = The register for POINTX1 and POINTY1 is modified by DMA or user.
+     * |[17]    |LDP2      |The Control Signal of Register for the X and Y Coordinate of the Second Point (POINTX2, POINTY2)
+     * |        |          |0 = The register for POINTX2 and POINTY2 is not modified by DMA or user.
+     * |        |          |1 = The register for POINTX2 and POINTY2 is modified by DMA or user.
+     * |[18]    |LDA       |The Control Signal of Register for the Parameter CURVEA of Elliptic Curve
+     * |        |          |0 = The register for CURVEA is not modified by DMA or user.
+     * |        |          |1 = The register for CURVEA is modified by DMA or user.
+     * |[19]    |LDB       |The Control Signal of Register for the Parameter CURVEB of Elliptic Curve
+     * |        |          |0 = The register for CURVEB is not modified by DMA or user.
+     * |        |          |1 = The register for CURVEB is modified by DMA or user.
+     * |[20]    |LDN       |The Control Signal of Register for the Parameter CURVEN of Elliptic Curve
+     * |        |          |0 = The register for CURVEN is not modified by DMA or user.
+     * |        |          |1 = The register for CURVEN is modified by DMA or user.
+     * |[21]    |LDK       |The Control Signal of Register for SCALARK
+     * |        |          |0 = The register for SCALARK is not modified by DMA or user.
+     * |        |          |1 = The register for SCALARK is modified by DMA or user.
+     * |[31:22] |CURVEM    |The key length of elliptic curve.
+     * @var CRPT_T::ECC_STS
+     * Offset: 0x804  ECC Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BUSY      |ECC Accelerator Busy Flag
+     * |        |          |0 = The ECC accelerator is idle or finished.
+     * |        |          |1 = The ECC accelerator is under processing and protects all registers.
+     * |        |          |Remember to clear ECC interrupt flag after ECC accelerator finished
+     * |[1]     |DMABUSY   |ECC DMA Busy Flag
+     * |        |          |0 = ECC DMA is idle or finished.
+     * |        |          |1 = ECC DMA is busy.
+     * |[16]    |BUSERR    |ECC DMA Access Bus Error Flag
+     * |        |          |0 = No error.
+     * |        |          |1 = Bus error will stop DMA operation and ECC accelerator.
+     * @var CRPT_T::ECC_X1[18]
+     * Offset: 0x808 ~ 0x84C  ECC The X-coordinate word 0 ~ 17 of the first point
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |POINTX1   |ECC the x-coordinate Value of the First Point (POINTX1)
+     * |        |          |For B-163 or K-163, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05
+     * |        |          |For B-233 or K-233, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07
+     * |        |          |For B-283 or K-283, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_08
+     * |        |          |For B-409 or K-409, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_12
+     * |        |          |For B-571 or K-571, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_17
+     * |        |          |For P-192, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05
+     * |        |          |For P-224, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_06
+     * |        |          |For P-256, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07
+     * |        |          |For P-384, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_11
+     * |        |          |For P-521, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_16
+     * @var CRPT_T::ECC_Y1[18]
+     * Offset: 0x850 ~ 0x894  ECC The Y-coordinate word 0 ~ 17 of the first point
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |POINTY1   |ECC the Y-coordinate Value of the First Point (POINTY1)
+     * |        |          |For B-163 or K-163, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05
+     * |        |          |For B-233 or K-233, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07
+     * |        |          |For B-283 or K-283, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_08
+     * |        |          |For B-409 or K-409, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_12
+     * |        |          |For B-571 or K-571, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_17
+     * |        |          |For P-192, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05
+     * |        |          |For P-224, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_06
+     * |        |          |For P-256, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07
+     * |        |          |For P-384, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_11
+     * |        |          |For P-521, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_16
+     * @var CRPT_T::ECC_X2[18]
+     * Offset: 0x898 ~ 0x8DC  ECC The X-coordinate word 0 ~ 17 of the second point
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |POINTX2   |ECC the x-coordinate Value of the Second Point (POINTX2)
+     * |        |          |For B-163 or K-163, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05
+     * |        |          |For B-233 or K-233, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07
+     * |        |          |For B-283 or K-283, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_08
+     * |        |          |For B-409 or K-409, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_12
+     * |        |          |For B-571 or K-571, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_17
+     * |        |          |For P-192, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05
+     * |        |          |For P-224, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_06
+     * |        |          |For P-256, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07
+     * |        |          |For P-384, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_11
+     * |        |          |For P-521, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_16
+     * @var CRPT_T::ECC_Y2[18]
+     * Offset: 0x8E0 ~ 0x924  ECC The Y-coordinate word 0 ~ 17 of the second point
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |POINTY2   |ECC the Y-coordinate Value of the Second Point (POINTY2)
+     * |        |          |For B-163 or K-163, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05
+     * |        |          |For B-233 or K-233, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07
+     * |        |          |For B-283 or K-283, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_08
+     * |        |          |For B-409 or K-409, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_12
+     * |        |          |For B-571 or K-571, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_17
+     * |        |          |For P-192, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05
+     * |        |          |For P-224, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_06
+     * |        |          |For P-256, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07
+     * |        |          |For P-384, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_11
+     * |        |          |For P-521, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_16
+     * @var CRPT_T::ECC_A[18]
+     * Offset: 0x928 ~ 0x96C  ECC The parameter CURVEA word 0 ~ 17 of elliptic curve
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CURVEA    |ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)
+     * |        |          |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2^m).
+     * |        |          |For B-163 or K-163, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05
+     * |        |          |For B-233 or K-233, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07
+     * |        |          |For B-283 or K-283, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_08
+     * |        |          |For B-409 or K-409, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_12
+     * |        |          |For B-571 or K-571, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_17
+     * |        |          |For P-192, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05
+     * |        |          |For P-224, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_06
+     * |        |          |For P-256, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07
+     * |        |          |For P-384, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_11
+     * |        |          |For P-521, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_16
+     * @var CRPT_T::ECC_B[18]
+     * Offset: 0x970 ~ 0x9B4  ECC The parameter CURVEB word 0 ~ 17 of elliptic curve
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CURVEB    |ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)
+     * |        |          |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2^m).
+     * |        |          |For B-163 or K-163, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05
+     * |        |          |For B-233 or K-233, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07
+     * |        |          |For B-283 or K-283, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_08
+     * |        |          |For B-409 or K-409, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_12
+     * |        |          |For B-521 or K-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_17
+     * |        |          |For P-192, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05
+     * |        |          |For P-224, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_06
+     * |        |          |For P-256, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07
+     * |        |          |For P-384, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_11
+     * |        |          |For P-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_16
+     * @var CRPT_T::ECC_N[18]
+     * Offset: 0x9B8 ~ 0x9FC  ECC The parameter CURVEN word 0 ~ 17 of elliptic curve
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CURVEN    |ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)
+     * |        |          |In GF(p), CURVEN is the prime p.
+     * |        |          |In GF(2^m), CURVEN is the irreducible polynomial.
+     * |        |          |For B-163 or K-163, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05
+     * |        |          |For B-233 or K-233, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07
+     * |        |          |For B-283 or K-283, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_08
+     * |        |          |For B-409 or K-409, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_12
+     * |        |          |For B-571 or K-571, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_17
+     * |        |          |For P-192, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05
+     * |        |          |For P-224, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_06
+     * |        |          |For P-256, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07
+     * |        |          |For P-384, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_11
+     * |        |          |For P-521, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_16
+     * @var CRPT_T::ECC_K[18]
+     * Offset: 0xA00 ~ 0xA44  ECC The scalar SCALARK word0 of point multiplication
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SCALARK   |ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)
+     * |        |          |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK.
+     * |        |          |For B-163 or K-163, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05
+     * |        |          |For B-233 or K-233, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07
+     * |        |          |For B-283 or K-283, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_08
+     * |        |          |For B-409 or K-409, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_12
+     * |        |          |For B-571 or K-571, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_17
+     * |        |          |For P-192, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05
+     * |        |          |For P-224, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_06
+     * |        |          |For P-256, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07
+     * |        |          |For P-384, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_11
+     * |        |          |For P-521, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_16
+     * @var CRPT_T::ECC_SADDR
+     * Offset: 0xA48  ECC DMA Source Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SADDR     |ECC DMA Source Address
+     * |        |          |The ECC accelerator supports DMA function to transfer the DATA and PARAMETER between
+     * |        |          |SRAM memory space and ECC accelerator. The SADDR keeps the source address of the data
+     * |        |          |buffer where the source text is stored. Based on the source address, the ECC accelerator
+     * |        |          |can read the DATA and PARAMETER from SRAM memory space and do ECC operation. The start
+     * |        |          |of source address should be located at word boundary. That is, bit 1 and 0 of SADDR are
+     * |        |          |ignored. SADDR can be read and written. In DMA mode, software must update the CRPT_ECC_SADDR
+     * |        |          |before triggering START.
+     * @var CRPT_T::ECC_DADDR
+     * Offset: 0xA4C  ECC DMA Destination Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DADDR     |ECC DMA Destination Address
+     * |        |          |The ECC accelerator supports DMA function to transfer the DATA and PARAMETER between system memory and ECC accelerator
+     * |        |          |The DADDR keeps the destination address of the data buffer where output data of ECC engine will be stored
+     * |        |          |Based on the destination address, the ECC accelerator can write the result data back to system memory after the ECC operation is finished
+     * |        |          |The start of destination address should be located at word boundary
+     * |        |          |That is, bit 1 and 0 of DADDR are ignored
+     * |        |          |DADDR can be read and written
+     * |        |          |In DMA mode, software must update the CRPT_ECC_DADDR before triggering START
+     * @var CRPT_T::ECC_STARTREG
+     * Offset: 0xA50  ECC Starting Address of Updated Registers
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |STARTREG  |ECC Starting Address of Updated Registers
+     * |        |          |The address of the updated registers that DMA feeds the first data or parameter to ECC engine
+     * |        |          |When ECC engine is active, ECC accelerator does not allow users to modify STARTREG
+     * |        |          |For example, we want to updated input data from register CRPT_ECC POINTX1
+     * |        |          |Thus, the value of STARTREG is 0x808.
+     * @var CRPT_T::ECC_WORDCNT
+     * Offset: 0xA54  ECC DMA Word Count
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |WORDCNT   |ECC DMA Word Count
+     * |        |          |The CRPT_ECC_WORDCNT keeps the word count of source data that is for the required input data of ECC accelerator with various operations in DMA mode
+     * |        |          |Although CRPT_ECC_WORDCNT is 32-bit, the maximum of word count in ECC accelerator is 144 words
+     * |        |          |CRPT_ECC_WORDCNT can be read and written
+     */
+    __IO uint32_t INTEN;                 /*!< [0x0000] Crypto Interrupt Enable Control Register                         */
+    __IO uint32_t INTSTS;                /*!< [0x0004] Crypto Interrupt Flag                                            */
+    __IO uint32_t PRNG_CTL;              /*!< [0x0008] PRNG Control Register                                            */
+    __O  uint32_t PRNG_SEED;             /*!< [0x000c] Seed for PRNG                                                    */
+    __I  uint32_t PRNG_KEY[8];           /*!< [0x0010] ~ [0x002c] PRNG Generated Key0 ~ Key7                            */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE0[8];
+    /// @endcond //HIDDEN_SYMBOLS
+    __I  uint32_t AES_FDBCK[4];          /*!< [0x0050] ~ [0x005c] AES Engine Output Feedback Data after Cryptographic Operation     */
+    __I  uint32_t TDES_FDBCKH;           /*!< [0x0060] TDES/DES Engine Output Feedback High Word Data after Cryptographic Operation */
+    __I  uint32_t TDES_FDBCKL;           /*!< [0x0064] TDES/DES Engine Output Feedback Low Word Data after Cryptographic Operation  */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE1[38];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t AES_CTL;               /*!< [0x0100] AES Control Register                                             */
+    __I  uint32_t AES_STS;               /*!< [0x0104] AES Engine Flag                                                  */
+    __IO uint32_t AES_DATIN;             /*!< [0x0108] AES Engine Data Input Port Register                              */
+    __I  uint32_t AES_DATOUT;            /*!< [0x010c] AES Engine Data Output Port Register                             */
+    __IO uint32_t AES0_KEY[8];           /*!< [0x0110] ~ [0x012c] AES Key Word 0~7 Register for Channel 0               */
+    __IO uint32_t AES0_IV[4];            /*!< [0x0130] ~ [0x013c] AES Initial Vector Word 0 ~ 3 Register for Channel 0  */
+    __IO uint32_t AES0_SADDR;            /*!< [0x0140] AES DMA Source Address Register for Channel 0                    */
+    __IO uint32_t AES0_DADDR;            /*!< [0x0144] AES DMA Destination Address Register for Channel 0               */
+    __IO uint32_t AES0_CNT;              /*!< [0x0148] AES Byte Count Register for Channel 0                            */
+    __IO uint32_t AES1_KEY[8];           /*!< [0x014c] ~ [0x0168] AES Key Word 0~7 Register for Channel 1               */
+    __IO uint32_t AES1_IV[4];            /*!< [0x016c] ~ [0x0178] AES Initial Vector Word 0~3 Register for Channel 1    */
+    __IO uint32_t AES1_SADDR;            /*!< [0x017c] AES DMA Source Address Register for Channel 1                    */
+    __IO uint32_t AES1_DADDR;            /*!< [0x0180] AES DMA Destination Address Register for Channel 1               */
+    __IO uint32_t AES1_CNT;              /*!< [0x0184] AES Byte Count Register for Channel 1                            */
+    __IO uint32_t AES2_KEY[8];           /*!< [0x0188] ~ [0x01a4] AES Key Word 0~7 Register for Channel 2               */
+    __IO uint32_t AES2_IV[4];            /*!< [0x01a8] ~ [0x01b4] AES Initial Vector Word 0~3 Register for Channel 2    */
+    __IO uint32_t AES2_SADDR;            /*!< [0x01b8] AES DMA Source Address Register for Channel 2                    */
+    __IO uint32_t AES2_DADDR;            /*!< [0x01bc] AES DMA Destination Address Register for Channel 2               */
+    __IO uint32_t AES2_CNT;              /*!< [0x01c0] AES Byte Count Register for Channel 2                            */
+    __IO uint32_t AES3_KEY[8];           /*!< [0x01c4] ~ [0x01e0] AES Key Word 0~7 Register for Channel 3               */
+    __IO uint32_t AES3_IV[4];            /*!< [0x01e4] ~ [0x01f0] AES Initial Vector Word 0~3 Register for Channel 3    */
+    __IO uint32_t AES3_SADDR;            /*!< [0x01f4] AES DMA Source Address Register for Channel 3                    */
+    __IO uint32_t AES3_DADDR;            /*!< [0x01f8] AES DMA Destination Address Register for Channel 3               */
+    __IO uint32_t AES3_CNT;              /*!< [0x01fc] AES Byte Count Register for Channel 3                            */
+    __IO uint32_t TDES_CTL;              /*!< [0x0200] TDES/DES Control Register                                        */
+    __I  uint32_t TDES_STS;              /*!< [0x0204] TDES/DES Engine Flag                                             */
+    __IO uint32_t TDES0_KEY1H;           /*!< [0x0208] TDES/DES Key 1 High Word Register for Channel 0                  */
+    __IO uint32_t TDES0_KEY1L;           /*!< [0x020c] TDES/DES Key 1 Low Word Register for Channel 0                   */
+    __IO uint32_t TDES0_KEY2H;           /*!< [0x0210] TDES Key 2 High Word Register for Channel 0                      */
+    __IO uint32_t TDES0_KEY2L;           /*!< [0x0214] TDES Key 2 Low Word Register for Channel 0                       */
+    __IO uint32_t TDES0_KEY3H;           /*!< [0x0218] TDES Key 3 High Word Register for Channel 0                      */
+    __IO uint32_t TDES0_KEY3L;           /*!< [0x021c] TDES Key 3 Low Word Register for Channel 0                       */
+    __IO uint32_t TDES0_IVH;             /*!< [0x0220] TDES/DES Initial Vector High Word Register for Channel 0         */
+    __IO uint32_t TDES0_IVL;             /*!< [0x0224] TDES/DES Initial Vector Low Word Register for Channel 0          */
+    __IO uint32_t TDES0_SA;              /*!< [0x0228] TDES/DES DMA Source Address Register for Channel 0               */
+    __IO uint32_t TDES0_DA;              /*!< [0x022c] TDES/DES DMA Destination Address Register for Channel 0          */
+    __IO uint32_t TDES0_CNT;             /*!< [0x0230] TDES/DES Byte Count Register for Channel 0                       */
+    __IO uint32_t TDES_DATIN;            /*!< [0x0234] TDES/DES Engine Input data Word Register                         */
+    __I  uint32_t TDES_DATOUT;           /*!< [0x0238] TDES/DES Engine Output data Word Register                        */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE2[3];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t TDES1_KEY1H;           /*!< [0x0248] TDES/DES Key 1 High Word Register for Channel 1                  */
+    __IO uint32_t TDES1_KEY1L;           /*!< [0x024c] TDES/DES Key 1 Low Word Register for Channel 1                   */
+    __IO uint32_t TDES1_KEY2H;           /*!< [0x0250] TDES Key 2 High Word Register for Channel 1                      */
+    __IO uint32_t TDES1_KEY2L;           /*!< [0x0254] TDES Key 2 Low Word Register for Channel 1                       */
+    __IO uint32_t TDES1_KEY3H;           /*!< [0x0258] TDES Key 3 High Word Register for Channel 1                      */
+    __IO uint32_t TDES1_KEY3L;           /*!< [0x025c] TDES Key 3 Low Word Register for Channel 1                       */
+    __IO uint32_t TDES1_IVH;             /*!< [0x0260] TDES/DES Initial Vector High Word Register for Channel 1         */
+    __IO uint32_t TDES1_IVL;             /*!< [0x0264] TDES/DES Initial Vector Low Word Register for Channel 1          */
+    __IO uint32_t TDES1_SA;              /*!< [0x0268] TDES/DES DMA Source Address Register for Channel 1               */
+    __IO uint32_t TDES1_DA;              /*!< [0x026c] TDES/DES DMA Destination Address Register for Channel 1          */
+    __IO uint32_t TDES1_CNT;             /*!< [0x0270] TDES/DES Byte Count Register for Channel 1                       */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE3[5];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t TDES2_KEY1H;           /*!< [0x0288] TDES/DES Key 1 High Word Register for Channel 2                  */
+    __IO uint32_t TDES2_KEY1L;           /*!< [0x028c] TDES/DES Key 1 Low Word Register for Channel 2                   */
+    __IO uint32_t TDES2_KEY2H;           /*!< [0x0290] TDES Key 2 High Word Register for Channel 2                      */
+    __IO uint32_t TDES2_KEY2L;           /*!< [0x0294] TDES Key 2 Low Word Register for Channel 2                       */
+    __IO uint32_t TDES2_KEY3H;           /*!< [0x0298] TDES Key 3 High Word Register for Channel 2                      */
+    __IO uint32_t TDES2_KEY3L;           /*!< [0x029c] TDES Key 3 Low Word Register for Channel 2                       */
+    __IO uint32_t TDES2_IVH;             /*!< [0x02a0] TDES/DES Initial Vector High Word Register for Channel 2         */
+    __IO uint32_t TDES2_IVL;             /*!< [0x02a4] TDES/DES Initial Vector Low Word Register for Channel 2          */
+    __IO uint32_t TDES2_SA;              /*!< [0x02a8] TDES/DES DMA Source Address Register for Channel 2               */
+    __IO uint32_t TDES2_DA;              /*!< [0x02ac] TDES/DES DMA Destination Address Register for Channel 2          */
+    __IO uint32_t TDES2_CNT;             /*!< [0x02b0] TDES/DES Byte Count Register for Channel 2                       */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE4[5];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t TDES3_KEY1H;           /*!< [0x02c8] TDES/DES Key 1 High Word Register for Channel 3                  */
+    __IO uint32_t TDES3_KEY1L;           /*!< [0x02cc] TDES/DES Key 1 Low Word Register for Channel 3                   */
+    __IO uint32_t TDES3_KEY2H;           /*!< [0x02d0] TDES Key 2 High Word Register for Channel 3                      */
+    __IO uint32_t TDES3_KEY2L;           /*!< [0x02d4] TDES Key 2 Low Word Register for Channel 3                       */
+    __IO uint32_t TDES3_KEY3H;           /*!< [0x02d8] TDES Key 3 High Word Register for Channel 3                      */
+    __IO uint32_t TDES3_KEY3L;           /*!< [0x02dc] TDES Key 3 Low Word Register for Channel 3                       */
+    __IO uint32_t TDES3_IVH;             /*!< [0x02e0] TDES/DES Initial Vector High Word Register for Channel 3         */
+    __IO uint32_t TDES3_IVL;             /*!< [0x02e4] TDES/DES Initial Vector Low Word Register for Channel 3          */
+    __IO uint32_t TDES3_SA;              /*!< [0x02e8] TDES/DES DMA Source Address Register for Channel 3               */
+    __IO uint32_t TDES3_DA;              /*!< [0x02ec] TDES/DES DMA Destination Address Register for Channel 3          */
+    __IO uint32_t TDES3_CNT;             /*!< [0x02f0] TDES/DES Byte Count Register for Channel 3                       */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE5[3];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t HMAC_CTL;              /*!< [0x0300] SHA/HMAC Control Register                                        */
+    __I  uint32_t HMAC_STS;              /*!< [0x0304] SHA/HMAC Status Flag                                             */
+    __I  uint32_t HMAC_DGST[16];         /*!< [0x0308] ~ [0x0344] SHA/HMAC Digest Message 0~15                          */
+    __IO uint32_t HMAC_KEYCNT;           /*!< [0x0348] SHA/HMAC Key Byte Count Register                                 */
+    __IO uint32_t HMAC_SADDR;            /*!< [0x034c] SHA/HMAC DMA Source Address Register                             */
+    __IO uint32_t HMAC_DMACNT;           /*!< [0x0350] SHA/HMAC Byte Count Register                                     */
+    __IO uint32_t HMAC_DATIN;            /*!< [0x0354] SHA/HMAC Engine Non-DMA Mode Data Input Port Register            */
+    /// @cond HIDDEN_SYMBOLS
+    __I  uint32_t RESERVE6[298];
+    /// @endcond //HIDDEN_SYMBOLS
+    __IO uint32_t ECC_CTL;               /*!< [0x0800] ECC Control Register                                             */
+    __I  uint32_t ECC_STS;               /*!< [0x0804] ECC Status Register                                              */
+    __IO uint32_t ECC_X1[18];            /*!< [0x0808] ~ [0x084c] ECC The X-coordinate word 0~17 of the first point     */
+    __IO uint32_t ECC_Y1[18];            /*!< [0x0850] ~ [0x0894] ECC The Y-coordinate word 0~17 of the first point     */
+    __IO uint32_t ECC_X2[18];            /*!< [0x0898] ~ [0x08dc] ECC The X-coordinate word 0~17 of the second point    */
+    __IO uint32_t ECC_Y2[18];            /*!< [0x08e0] ~ [0x0924] ECC The Y-coordinate word 0~17 of the second point    */
+    __IO uint32_t ECC_A[18];             /*!< [0x0928] ~ [0x096c] ECC The parameter CURVEA word 0~17 of elliptic curve  */
+    __IO uint32_t ECC_B[18];             /*!< [0x0970] ~ [0x09b4] ECC The parameter CURVEB word 0~17 of elliptic curve  */
+    __IO uint32_t ECC_N[18];             /*!< [0x09b8] ~ [0x09fc] ECC The parameter CURVEN word 0~17 of elliptic curve  */
+    __O  uint32_t ECC_K[18];             /*!< [0x0a00] ~ [0x0a44] ECC The scalar SCALARK word 0~17 of point multiplication */
+    __IO uint32_t ECC_SADDR;             /*!< [0x0a48] ECC DMA Source Address Register                                  */
+    __IO uint32_t ECC_DADDR;             /*!< [0x0a4c] ECC DMA Destination Address Register                             */
+    __IO uint32_t ECC_STARTREG;          /*!< [0x0a50] ECC Starting Address of Updated Registers                        */
+    __IO uint32_t ECC_WORDCNT;           /*!< [0x0a54] ECC DMA Word Count                                               */
+
+} CRPT_T;
+
+/**
+    @addtogroup CRPT_CONST CRPT Bit Field Definition
+    Constant Definitions for CRPT Controller
+@{ */
+
+#define CRPT_INTEN_AESIEN_Pos            (0)                                               /*!< CRPT_T::INTEN: AESIEN Position         */
+#define CRPT_INTEN_AESIEN_Msk            (0x1ul << CRPT_INTEN_AESIEN_Pos)                  /*!< CRPT_T::INTEN: AESIEN Mask             */
+
+#define CRPT_INTEN_AESEIEN_Pos           (1)                                               /*!< CRPT_T::INTEN: AESEIEN Position        */
+#define CRPT_INTEN_AESEIEN_Msk           (0x1ul << CRPT_INTEN_AESEIEN_Pos)                 /*!< CRPT_T::INTEN: AESEIEN Mask            */
+
+#define CRPT_INTEN_TDESIEN_Pos           (8)                                               /*!< CRPT_T::INTEN: TDESIEN Position        */
+#define CRPT_INTEN_TDESIEN_Msk           (0x1ul << CRPT_INTEN_TDESIEN_Pos)                 /*!< CRPT_T::INTEN: TDESIEN Mask            */
+
+#define CRPT_INTEN_TDESEIEN_Pos          (9)                                               /*!< CRPT_T::INTEN: TDESEIEN Position       */
+#define CRPT_INTEN_TDESEIEN_Msk          (0x1ul << CRPT_INTEN_TDESEIEN_Pos)                /*!< CRPT_T::INTEN: TDESEIEN Mask           */
+
+#define CRPT_INTEN_PRNGIEN_Pos           (16)                                              /*!< CRPT_T::INTEN: PRNGIEN Position        */
+#define CRPT_INTEN_PRNGIEN_Msk           (0x1ul << CRPT_INTEN_PRNGIEN_Pos)                 /*!< CRPT_T::INTEN: PRNGIEN Mask            */
+
+#define CRPT_INTEN_ECCIEN_Pos            (22)                                              /*!< CRPT_T::INTEN: ECCIEN Position         */
+#define CRPT_INTEN_ECCIEN_Msk            (0x1ul << CRPT_INTEN_ECCIEN_Pos)                  /*!< CRPT_T::INTEN: ECCIEN Mask             */
+
+#define CRPT_INTEN_ECCEIEN_Pos           (23)                                              /*!< CRPT_T::INTEN: ECCEIEN Position        */
+#define CRPT_INTEN_ECCEIEN_Msk           (0x1ul << CRPT_INTEN_ECCEIEN_Pos)                 /*!< CRPT_T::INTEN: ECCEIEN Mask            */
+
+#define CRPT_INTEN_HMACIEN_Pos           (24)                                              /*!< CRPT_T::INTEN: HMACIEN Position        */
+#define CRPT_INTEN_HMACIEN_Msk           (0x1ul << CRPT_INTEN_HMACIEN_Pos)                 /*!< CRPT_T::INTEN: HMACIEN Mask            */
+
+#define CRPT_INTEN_HMACEIEN_Pos          (25)                                              /*!< CRPT_T::INTEN: HMACEIEN Position       */
+#define CRPT_INTEN_HMACEIEN_Msk          (0x1ul << CRPT_INTEN_HMACEIEN_Pos)                /*!< CRPT_T::INTEN: HMACEIEN Mask           */
+
+#define CRPT_INTSTS_AESIF_Pos            (0)                                               /*!< CRPT_T::INTSTS: AESIF Position         */
+#define CRPT_INTSTS_AESIF_Msk            (0x1ul << CRPT_INTSTS_AESIF_Pos)                  /*!< CRPT_T::INTSTS: AESIF Mask             */
+
+#define CRPT_INTSTS_AESEIF_Pos           (1)                                               /*!< CRPT_T::INTSTS: AESEIF Position        */
+#define CRPT_INTSTS_AESEIF_Msk           (0x1ul << CRPT_INTSTS_AESEIF_Pos)                 /*!< CRPT_T::INTSTS: AESEIF Mask            */
+
+#define CRPT_INTSTS_TDESIF_Pos           (8)                                               /*!< CRPT_T::INTSTS: TDESIF Position        */
+#define CRPT_INTSTS_TDESIF_Msk           (0x1ul << CRPT_INTSTS_TDESIF_Pos)                 /*!< CRPT_T::INTSTS: TDESIF Mask            */
+
+#define CRPT_INTSTS_TDESEIF_Pos          (9)                                               /*!< CRPT_T::INTSTS: TDESEIF Position       */
+#define CRPT_INTSTS_TDESEIF_Msk          (0x1ul << CRPT_INTSTS_TDESEIF_Pos)                /*!< CRPT_T::INTSTS: TDESEIF Mask           */
+
+#define CRPT_INTSTS_PRNGIF_Pos           (16)                                              /*!< CRPT_T::INTSTS: PRNGIF Position        */
+#define CRPT_INTSTS_PRNGIF_Msk           (0x1ul << CRPT_INTSTS_PRNGIF_Pos)                 /*!< CRPT_T::INTSTS: PRNGIF Mask            */
+
+#define CRPT_INTSTS_ECCIF_Pos            (22)                                              /*!< CRPT_T::INTSTS: ECCIF Position         */
+#define CRPT_INTSTS_ECCIF_Msk            (0x1ul << CRPT_INTSTS_ECCIF_Pos)                  /*!< CRPT_T::INTSTS: ECCIF Mask             */
+
+#define CRPT_INTSTS_ECCEIF_Pos           (23)                                              /*!< CRPT_T::INTSTS: ECCEIF Position        */
+#define CRPT_INTSTS_ECCEIF_Msk           (0x1ul << CRPT_INTSTS_ECCEIF_Pos)                 /*!< CRPT_T::INTSTS: ECCEIF Mask            */
+
+#define CRPT_INTSTS_HMACIF_Pos           (24)                                              /*!< CRPT_T::INTSTS: HMACIF Position        */
+#define CRPT_INTSTS_HMACIF_Msk           (0x1ul << CRPT_INTSTS_HMACIF_Pos)                 /*!< CRPT_T::INTSTS: HMACIF Mask            */
+
+#define CRPT_INTSTS_HMACEIF_Pos          (25)                                              /*!< CRPT_T::INTSTS: HMACEIF Position       */
+#define CRPT_INTSTS_HMACEIF_Msk          (0x1ul << CRPT_INTSTS_HMACEIF_Pos)                /*!< CRPT_T::INTSTS: HMACEIF Mask           */
+
+#define CRPT_PRNG_CTL_START_Pos          (0)                                               /*!< CRPT_T::PRNG_CTL: START Position       */
+#define CRPT_PRNG_CTL_START_Msk          (0x1ul << CRPT_PRNG_CTL_START_Pos)                /*!< CRPT_T::PRNG_CTL: START Mask           */
+
+#define CRPT_PRNG_CTL_SEEDRLD_Pos        (1)                                               /*!< CRPT_T::PRNG_CTL: SEEDRLD Position     */
+#define CRPT_PRNG_CTL_SEEDRLD_Msk        (0x1ul << CRPT_PRNG_CTL_SEEDRLD_Pos)              /*!< CRPT_T::PRNG_CTL: SEEDRLD Mask         */
+
+#define CRPT_PRNG_CTL_KEYSZ_Pos          (2)                                               /*!< CRPT_T::PRNG_CTL: KEYSZ Position       */
+#define CRPT_PRNG_CTL_KEYSZ_Msk          (0x3ul << CRPT_PRNG_CTL_KEYSZ_Pos)                /*!< CRPT_T::PRNG_CTL: KEYSZ Mask           */
+
+#define CRPT_PRNG_CTL_BUSY_Pos           (8)                                               /*!< CRPT_T::PRNG_CTL: BUSY Position        */
+#define CRPT_PRNG_CTL_BUSY_Msk           (0x1ul << CRPT_PRNG_CTL_BUSY_Pos)                 /*!< CRPT_T::PRNG_CTL: BUSY Mask            */
+
+#define CRPT_PRNG_SEED_SEED_Pos          (0)                                               /*!< CRPT_T::PRNG_SEED: SEED Position       */
+#define CRPT_PRNG_SEED_SEED_Msk          (0xfffffffful << CRPT_PRNG_SEED_SEED_Pos)         /*!< CRPT_T::PRNG_SEED: SEED Mask           */
+
+#define CRPT_PRNG_KEYx_KEY_Pos           (0)                                               /*!< CRPT_T::PRNG_KEY[8]: KEY Position      */
+#define CRPT_PRNG_KEYx_KEY_Msk           (0xfffffffful << CRPT_PRNG_KEYx_KEY_Pos)          /*!< CRPT_T::PRNG_KEY[8]: KEY Mask          */
+
+#define CRPT_AES_FDBCKx_FDBCK_Pos        (0)                                               /*!< CRPT_T::AES_FDBCK[4]: FDBCK Position   */
+#define CRPT_AES_FDBCKx_FDBCK_Msk        (0xfffffffful << CRPT_AES_FDBCKx_FDBCK_Pos)       /*!< CRPT_T::AES_FDBCK[4]: FDBCK Mask       */
+
+#define CRPT_TDES_FDBCKH_FDBCK_Pos       (0)                                               /*!< CRPT_T::TDES_FDBCKH: FDBCK Position    */
+#define CRPT_TDES_FDBCKH_FDBCK_Msk       (0xfffffffful << CRPT_TDES_FDBCKH_FDBCK_Pos)      /*!< CRPT_T::TDES_FDBCKH: FDBCK Mask        */
+
+#define CRPT_TDES_FDBCKL_FDBCK_Pos       (0)                                               /*!< CRPT_T::TDES_FDBCKL: FDBCK Position    */
+#define CRPT_TDES_FDBCKL_FDBCK_Msk       (0xfffffffful << CRPT_TDES_FDBCKL_FDBCK_Pos)      /*!< CRPT_T::TDES_FDBCKL: FDBCK Mask        */
+
+#define CRPT_AES_CTL_START_Pos           (0)                                               /*!< CRPT_T::AES_CTL: START Position        */
+#define CRPT_AES_CTL_START_Msk           (0x1ul << CRPT_AES_CTL_START_Pos)                 /*!< CRPT_T::AES_CTL: START Mask            */
+
+#define CRPT_AES_CTL_STOP_Pos            (1)                                               /*!< CRPT_T::AES_CTL: STOP Position         */
+#define CRPT_AES_CTL_STOP_Msk            (0x1ul << CRPT_AES_CTL_STOP_Pos)                  /*!< CRPT_T::AES_CTL: STOP Mask             */
+
+#define CRPT_AES_CTL_KEYSZ_Pos           (2)                                               /*!< CRPT_T::AES_CTL: KEYSZ Position        */
+#define CRPT_AES_CTL_KEYSZ_Msk           (0x3ul << CRPT_AES_CTL_KEYSZ_Pos)                 /*!< CRPT_T::AES_CTL: KEYSZ Mask            */
+
+#define CRPT_AES_CTL_DMALAST_Pos         (5)                                               /*!< CRPT_T::AES_CTL: DMALAST Position      */
+#define CRPT_AES_CTL_DMALAST_Msk         (0x1ul << CRPT_AES_CTL_DMALAST_Pos)               /*!< CRPT_T::AES_CTL: DMALAST Mask          */
+
+#define CRPT_AES_CTL_DMACSCAD_Pos        (6)                                               /*!< CRPT_T::AES_CTL: DMACSCAD Position     */
+#define CRPT_AES_CTL_DMACSCAD_Msk        (0x1ul << CRPT_AES_CTL_DMACSCAD_Pos)              /*!< CRPT_T::AES_CTL: DMACSCAD Mask         */
+
+#define CRPT_AES_CTL_DMAEN_Pos           (7)                                               /*!< CRPT_T::AES_CTL: DMAEN Position        */
+#define CRPT_AES_CTL_DMAEN_Msk           (0x1ul << CRPT_AES_CTL_DMAEN_Pos)                 /*!< CRPT_T::AES_CTL: DMAEN Mask            */
+
+#define CRPT_AES_CTL_OPMODE_Pos          (8)                                               /*!< CRPT_T::AES_CTL: OPMODE Position       */
+#define CRPT_AES_CTL_OPMODE_Msk          (0xfful << CRPT_AES_CTL_OPMODE_Pos)               /*!< CRPT_T::AES_CTL: OPMODE Mask           */
+
+#define CRPT_AES_CTL_ENCRPT_Pos          (16)                                              /*!< CRPT_T::AES_CTL: ENCRPT Position       */
+#define CRPT_AES_CTL_ENCRPT_Msk          (0x1ul << CRPT_AES_CTL_ENCRPT_Pos)                /*!< CRPT_T::AES_CTL: ENCRPT Mask           */
+
+#define CRPT_AES_CTL_OUTSWAP_Pos         (22)                                              /*!< CRPT_T::AES_CTL: OUTSWAP Position      */
+#define CRPT_AES_CTL_OUTSWAP_Msk         (0x1ul << CRPT_AES_CTL_OUTSWAP_Pos)               /*!< CRPT_T::AES_CTL: OUTSWAP Mask          */
+
+#define CRPT_AES_CTL_INSWAP_Pos          (23)                                              /*!< CRPT_T::AES_CTL: INSWAP Position       */
+#define CRPT_AES_CTL_INSWAP_Msk          (0x1ul << CRPT_AES_CTL_INSWAP_Pos)                /*!< CRPT_T::AES_CTL: INSWAP Mask           */
+
+#define CRPT_AES_CTL_CHANNEL_Pos         (24)                                              /*!< CRPT_T::AES_CTL: CHANNEL Position      */
+#define CRPT_AES_CTL_CHANNEL_Msk         (0x3ul << CRPT_AES_CTL_CHANNEL_Pos)               /*!< CRPT_T::AES_CTL: CHANNEL Mask          */
+
+#define CRPT_AES_CTL_KEYUNPRT_Pos        (26)                                              /*!< CRPT_T::AES_CTL: KEYUNPRT Position     */
+#define CRPT_AES_CTL_KEYUNPRT_Msk        (0x1ful << CRPT_AES_CTL_KEYUNPRT_Pos)             /*!< CRPT_T::AES_CTL: KEYUNPRT Mask         */
+
+#define CRPT_AES_CTL_KEYPRT_Pos          (31)                                              /*!< CRPT_T::AES_CTL: KEYPRT Position       */
+#define CRPT_AES_CTL_KEYPRT_Msk          (0x1ul << CRPT_AES_CTL_KEYPRT_Pos)                /*!< CRPT_T::AES_CTL: KEYPRT Mask           */
+
+#define CRPT_AES_STS_BUSY_Pos            (0)                                               /*!< CRPT_T::AES_STS: BUSY Position         */
+#define CRPT_AES_STS_BUSY_Msk            (0x1ul << CRPT_AES_STS_BUSY_Pos)                  /*!< CRPT_T::AES_STS: BUSY Mask             */
+
+#define CRPT_AES_STS_INBUFEMPTY_Pos      (8)                                               /*!< CRPT_T::AES_STS: INBUFEMPTY Position   */
+#define CRPT_AES_STS_INBUFEMPTY_Msk      (0x1ul << CRPT_AES_STS_INBUFEMPTY_Pos)            /*!< CRPT_T::AES_STS: INBUFEMPTY Mask       */
+
+#define CRPT_AES_STS_INBUFFULL_Pos       (9)                                               /*!< CRPT_T::AES_STS: INBUFFULL Position    */
+#define CRPT_AES_STS_INBUFFULL_Msk       (0x1ul << CRPT_AES_STS_INBUFFULL_Pos)             /*!< CRPT_T::AES_STS: INBUFFULL Mask        */
+
+#define CRPT_AES_STS_INBUFERR_Pos        (10)                                              /*!< CRPT_T::AES_STS: INBUFERR Position     */
+#define CRPT_AES_STS_INBUFERR_Msk        (0x1ul << CRPT_AES_STS_INBUFERR_Pos)              /*!< CRPT_T::AES_STS: INBUFERR Mask         */
+
+#define CRPT_AES_STS_CNTERR_Pos          (12)                                              /*!< CRPT_T::AES_STS: CNTERR Position       */
+#define CRPT_AES_STS_CNTERR_Msk          (0x1ul << CRPT_AES_STS_CNTERR_Pos)                /*!< CRPT_T::AES_STS: CNTERR Mask           */
+
+#define CRPT_AES_STS_OUTBUFEMPTY_Pos     (16)                                              /*!< CRPT_T::AES_STS: OUTBUFEMPTY Position  */
+#define CRPT_AES_STS_OUTBUFEMPTY_Msk     (0x1ul << CRPT_AES_STS_OUTBUFEMPTY_Pos)           /*!< CRPT_T::AES_STS: OUTBUFEMPTY Mask      */
+
+#define CRPT_AES_STS_OUTBUFFULL_Pos      (17)                                              /*!< CRPT_T::AES_STS: OUTBUFFULL Position   */
+#define CRPT_AES_STS_OUTBUFFULL_Msk      (0x1ul << CRPT_AES_STS_OUTBUFFULL_Pos)            /*!< CRPT_T::AES_STS: OUTBUFFULL Mask       */
+
+#define CRPT_AES_STS_OUTBUFERR_Pos       (18)                                              /*!< CRPT_T::AES_STS: OUTBUFERR Position    */
+#define CRPT_AES_STS_OUTBUFERR_Msk       (0x1ul << CRPT_AES_STS_OUTBUFERR_Pos)             /*!< CRPT_T::AES_STS: OUTBUFERR Mask        */
+
+#define CRPT_AES_STS_BUSERR_Pos          (20)                                              /*!< CRPT_T::AES_STS: BUSERR Position       */
+#define CRPT_AES_STS_BUSERR_Msk          (0x1ul << CRPT_AES_STS_BUSERR_Pos)                /*!< CRPT_T::AES_STS: BUSERR Mask           */
+
+#define CRPT_AES_DATIN_DATIN_Pos         (0)                                               /*!< CRPT_T::AES_DATIN: DATIN Position      */
+#define CRPT_AES_DATIN_DATIN_Msk         (0xfffffffful << CRPT_AES_DATIN_DATIN_Pos)        /*!< CRPT_T::AES_DATIN: DATIN Mask          */
+
+#define CRPT_AES_DATOUT_DATOUT_Pos       (0)                                               /*!< CRPT_T::AES_DATOUT: DATOUT Position    */
+#define CRPT_AES_DATOUT_DATOUT_Msk       (0xfffffffful << CRPT_AES_DATOUT_DATOUT_Pos)      /*!< CRPT_T::AES_DATOUT: DATOUT Mask        */
+
+#define CRPT_AES0_KEYx_KEY_Pos           (0)                                               /*!< CRPT_T::AES0_KEY[8]: KEY Position      */
+#define CRPT_AES0_KEYx_KEY_Msk           (0xfffffffful << CRPT_AES0_KEYx_KEY_Pos)          /*!< CRPT_T::AES0_KEY[8]: KEY Mask          */
+
+#define CRPT_AES0_IVx_IV_Pos             (0)                                               /*!< CRPT_T::AES0_IV[4]: IV Position        */
+#define CRPT_AES0_IVx_IV_Msk             (0xfffffffful << CRPT_AES0_IVx_IV_Pos)            /*!< CRPT_T::AES0_IV[4]: IV Mask            */
+
+#define CRPT_AES0_SADDR_SADDR_Pos        (0)                                               /*!< CRPT_T::AES0_SADDR: SADDR Position     */
+#define CRPT_AES0_SADDR_SADDR_Msk        (0xfffffffful << CRPT_AES0_SADDR_SADDR_Pos)       /*!< CRPT_T::AES0_SADDR: SADDR Mask         */
+
+#define CRPT_AES0_DADDR_DADDR_Pos        (0)                                               /*!< CRPT_T::AES0_DADDR: DADDR Position     */
+#define CRPT_AES0_DADDR_DADDR_Msk        (0xfffffffful << CRPT_AES0_DADDR_DADDR_Pos)       /*!< CRPT_T::AES0_DADDR: DADDR Mask         */
+
+#define CRPT_AES0_CNT_CNT_Pos            (0)                                               /*!< CRPT_T::AES0_CNT: CNT Position         */
+#define CRPT_AES0_CNT_CNT_Msk            (0xfffffffful << CRPT_AES0_CNT_CNT_Pos)           /*!< CRPT_T::AES0_CNT: CNT Mask             */
+
+#define CRPT_AES1_KEYx_KEY_Pos           (0)                                               /*!< CRPT_T::AES1_KEY[8]: KEY Position      */
+#define CRPT_AES1_KEYx_KEY_Msk           (0xfffffffful << CRPT_AES1_KEYx_KEY_Pos)          /*!< CRPT_T::AES1_KEY[8]: KEY Mask          */
+
+#define CRPT_AES1_IVx_IV_Pos             (0)                                               /*!< CRPT_T::AES1_IV[4]: IV Position        */
+#define CRPT_AES1_IVx_IV_Msk             (0xfffffffful << CRPT_AES1_IVx_IV_Pos)            /*!< CRPT_T::AES1_IV[4]: IV Mask            */
+
+#define CRPT_AES1_SADDR_SADDR_Pos        (0)                                               /*!< CRPT_T::AES1_SADDR: SADDR Position     */
+#define CRPT_AES1_SADDR_SADDR_Msk        (0xfffffffful << CRPT_AES1_SADDR_SADDR_Pos)       /*!< CRPT_T::AES1_SADDR: SADDR Mask         */
+
+#define CRPT_AES1_DADDR_DADDR_Pos        (0)                                               /*!< CRPT_T::AES1_DADDR: DADDR Position     */
+#define CRPT_AES1_DADDR_DADDR_Msk        (0xfffffffful << CRPT_AES1_DADDR_DADDR_Pos)       /*!< CRPT_T::AES1_DADDR: DADDR Mask         */
+
+#define CRPT_AES1_CNT_CNT_Pos            (0)                                               /*!< CRPT_T::AES1_CNT: CNT Position         */
+#define CRPT_AES1_CNT_CNT_Msk            (0xfffffffful << CRPT_AES1_CNT_CNT_Pos)           /*!< CRPT_T::AES1_CNT: CNT Mask             */
+
+#define CRPT_AES2_KEYx_KEY_Pos           (0)                                               /*!< CRPT_T::AES2_KEY[8]: KEY Position      */
+#define CRPT_AES2_KEYx_KEY_Msk           (0xfffffffful << CRPT_AES2_KEYx_KEY_Pos)          /*!< CRPT_T::AES2_KEY[8]: KEY Mask          */
+
+#define CRPT_AES2_IVx_IV_Pos             (0)                                               /*!< CRPT_T::AES2_IV[4]: IV Position        */
+#define CRPT_AES2_IVx_IV_Msk             (0xfffffffful << CRPT_AES2_IVx_IV_Pos)            /*!< CRPT_T::AES2_IV[4]: IV Mask            */
+
+#define CRPT_AES2_SADDR_SADDR_Pos        (0)                                               /*!< CRPT_T::AES2_SADDR: SADDR Position     */
+#define CRPT_AES2_SADDR_SADDR_Msk        (0xfffffffful << CRPT_AES2_SADDR_SADDR_Pos)       /*!< CRPT_T::AES2_SADDR: SADDR Mask         */
+
+#define CRPT_AES2_DADDR_DADDR_Pos        (0)                                               /*!< CRPT_T::AES2_DADDR: DADDR Position     */
+#define CRPT_AES2_DADDR_DADDR_Msk        (0xfffffffful << CRPT_AES2_DADDR_DADDR_Pos)       /*!< CRPT_T::AES2_DADDR: DADDR Mask         */
+
+#define CRPT_AES2_CNT_CNT_Pos            (0)                                               /*!< CRPT_T::AES2_CNT: CNT Position         */
+#define CRPT_AES2_CNT_CNT_Msk            (0xfffffffful << CRPT_AES2_CNT_CNT_Pos)           /*!< CRPT_T::AES2_CNT: CNT Mask             */
+
+#define CRPT_AES3_KEYx_KEY_Pos           (0)                                               /*!< CRPT_T::AES3_KEY[8]: KEY Position      */
+#define CRPT_AES3_KEYx_KEY_Msk           (0xfffffffful << CRPT_AES3_KEYx_KEY_Pos)          /*!< CRPT_T::AES3_KEY[8]: KEY Mask          */
+
+#define CRPT_AES3_IVx_IV_Pos             (0)                                               /*!< CRPT_T::AES3_IV[4]: IV Position        */
+#define CRPT_AES3_IVx_IV_Msk             (0xfffffffful << CRPT_AES3_IVx_IV_Pos)            /*!< CRPT_T::AES3_IV[4]: IV Mask            */
+
+#define CRPT_AES3_SADDR_SADDR_Pos        (0)                                               /*!< CRPT_T::AES3_SADDR: SADDR Position     */
+#define CRPT_AES3_SADDR_SADDR_Msk        (0xfffffffful << CRPT_AES3_SADDR_SADDR_Pos)       /*!< CRPT_T::AES3_SADDR: SADDR Mask         */
+
+#define CRPT_AES3_DADDR_DADDR_Pos        (0)                                               /*!< CRPT_T::AES3_DADDR: DADDR Position     */
+#define CRPT_AES3_DADDR_DADDR_Msk        (0xfffffffful << CRPT_AES3_DADDR_DADDR_Pos)       /*!< CRPT_T::AES3_DADDR: DADDR Mask         */
+
+#define CRPT_AES3_CNT_CNT_Pos            (0)                                               /*!< CRPT_T::AES3_CNT: CNT Position         */
+#define CRPT_AES3_CNT_CNT_Msk            (0xfffffffful << CRPT_AES3_CNT_CNT_Pos)           /*!< CRPT_T::AES3_CNT: CNT Mask             */
+
+#define CRPT_TDES_CTL_START_Pos          (0)                                               /*!< CRPT_T::TDES_CTL: START Position       */
+#define CRPT_TDES_CTL_START_Msk          (0x1ul << CRPT_TDES_CTL_START_Pos)                /*!< CRPT_T::TDES_CTL: START Mask           */
+
+#define CRPT_TDES_CTL_STOP_Pos           (1)                                               /*!< CRPT_T::TDES_CTL: STOP Position        */
+#define CRPT_TDES_CTL_STOP_Msk           (0x1ul << CRPT_TDES_CTL_STOP_Pos)                 /*!< CRPT_T::TDES_CTL: STOP Mask            */
+
+#define CRPT_TDES_CTL_TMODE_Pos          (2)                                               /*!< CRPT_T::TDES_CTL: TMODE Position       */
+#define CRPT_TDES_CTL_TMODE_Msk          (0x1ul << CRPT_TDES_CTL_TMODE_Pos)                /*!< CRPT_T::TDES_CTL: TMODE Mask           */
+
+#define CRPT_TDES_CTL_3KEYS_Pos          (3)                                               /*!< CRPT_T::TDES_CTL: 3KEYS Position       */
+#define CRPT_TDES_CTL_3KEYS_Msk          (0x1ul << CRPT_TDES_CTL_3KEYS_Pos)                /*!< CRPT_T::TDES_CTL: 3KEYS Mask           */
+
+#define CRPT_TDES_CTL_DMALAST_Pos        (5)                                               /*!< CRPT_T::TDES_CTL: DMALAST Position     */
+#define CRPT_TDES_CTL_DMALAST_Msk        (0x1ul << CRPT_TDES_CTL_DMALAST_Pos)              /*!< CRPT_T::TDES_CTL: DMALAST Mask         */
+
+#define CRPT_TDES_CTL_DMACSCAD_Pos       (6)                                               /*!< CRPT_T::TDES_CTL: DMACSCAD Position    */
+#define CRPT_TDES_CTL_DMACSCAD_Msk       (0x1ul << CRPT_TDES_CTL_DMACSCAD_Pos)             /*!< CRPT_T::TDES_CTL: DMACSCAD Mask        */
+
+#define CRPT_TDES_CTL_DMAEN_Pos          (7)                                               /*!< CRPT_T::TDES_CTL: DMAEN Position       */
+#define CRPT_TDES_CTL_DMAEN_Msk          (0x1ul << CRPT_TDES_CTL_DMAEN_Pos)                /*!< CRPT_T::TDES_CTL: DMAEN Mask           */
+
+#define CRPT_TDES_CTL_OPMODE_Pos         (8)                                               /*!< CRPT_T::TDES_CTL: OPMODE Position      */
+#define CRPT_TDES_CTL_OPMODE_Msk         (0x7ul << CRPT_TDES_CTL_OPMODE_Pos)               /*!< CRPT_T::TDES_CTL: OPMODE Mask          */
+
+#define CRPT_TDES_CTL_ENCRPT_Pos         (16)                                              /*!< CRPT_T::TDES_CTL: ENCRPT Position      */
+#define CRPT_TDES_CTL_ENCRPT_Msk         (0x1ul << CRPT_TDES_CTL_ENCRPT_Pos)               /*!< CRPT_T::TDES_CTL: ENCRPT Mask          */
+
+#define CRPT_TDES_CTL_BLKSWAP_Pos        (21)                                              /*!< CRPT_T::TDES_CTL: BLKSWAP Position     */
+#define CRPT_TDES_CTL_BLKSWAP_Msk        (0x1ul << CRPT_TDES_CTL_BLKSWAP_Pos)              /*!< CRPT_T::TDES_CTL: BLKSWAP Mask         */
+
+#define CRPT_TDES_CTL_OUTSWAP_Pos        (22)                                              /*!< CRPT_T::TDES_CTL: OUTSWAP Position     */
+#define CRPT_TDES_CTL_OUTSWAP_Msk        (0x1ul << CRPT_TDES_CTL_OUTSWAP_Pos)              /*!< CRPT_T::TDES_CTL: OUTSWAP Mask         */
+
+#define CRPT_TDES_CTL_INSWAP_Pos         (23)                                              /*!< CRPT_T::TDES_CTL: INSWAP Position      */
+#define CRPT_TDES_CTL_INSWAP_Msk         (0x1ul << CRPT_TDES_CTL_INSWAP_Pos)               /*!< CRPT_T::TDES_CTL: INSWAP Mask          */
+
+#define CRPT_TDES_CTL_CHANNEL_Pos        (24)                                              /*!< CRPT_T::TDES_CTL: CHANNEL Position     */
+#define CRPT_TDES_CTL_CHANNEL_Msk        (0x3ul << CRPT_TDES_CTL_CHANNEL_Pos)              /*!< CRPT_T::TDES_CTL: CHANNEL Mask         */
+
+#define CRPT_TDES_CTL_KEYUNPRT_Pos       (26)                                              /*!< CRPT_T::TDES_CTL: KEYUNPRT Position    */
+#define CRPT_TDES_CTL_KEYUNPRT_Msk       (0x1ful << CRPT_TDES_CTL_KEYUNPRT_Pos)            /*!< CRPT_T::TDES_CTL: KEYUNPRT Mask        */
+
+#define CRPT_TDES_CTL_KEYPRT_Pos         (31)                                              /*!< CRPT_T::TDES_CTL: KEYPRT Position      */
+#define CRPT_TDES_CTL_KEYPRT_Msk         (0x1ul << CRPT_TDES_CTL_KEYPRT_Pos)               /*!< CRPT_T::TDES_CTL: KEYPRT Mask          */
+
+#define CRPT_TDES_STS_BUSY_Pos           (0)                                               /*!< CRPT_T::TDES_STS: BUSY Position        */
+#define CRPT_TDES_STS_BUSY_Msk           (0x1ul << CRPT_TDES_STS_BUSY_Pos)                 /*!< CRPT_T::TDES_STS: BUSY Mask            */
+
+#define CRPT_TDES_STS_INBUFEMPTY_Pos     (8)                                               /*!< CRPT_T::TDES_STS: INBUFEMPTY Position  */
+#define CRPT_TDES_STS_INBUFEMPTY_Msk     (0x1ul << CRPT_TDES_STS_INBUFEMPTY_Pos)           /*!< CRPT_T::TDES_STS: INBUFEMPTY Mask      */
+
+#define CRPT_TDES_STS_INBUFFULL_Pos      (9)                                               /*!< CRPT_T::TDES_STS: INBUFFULL Position   */
+#define CRPT_TDES_STS_INBUFFULL_Msk      (0x1ul << CRPT_TDES_STS_INBUFFULL_Pos)            /*!< CRPT_T::TDES_STS: INBUFFULL Mask       */
+
+#define CRPT_TDES_STS_INBUFERR_Pos       (10)                                              /*!< CRPT_T::TDES_STS: INBUFERR Position    */
+#define CRPT_TDES_STS_INBUFERR_Msk       (0x1ul << CRPT_TDES_STS_INBUFERR_Pos)             /*!< CRPT_T::TDES_STS: INBUFERR Mask        */
+
+#define CRPT_TDES_STS_OUTBUFEMPTY_Pos    (16)                                              /*!< CRPT_T::TDES_STS: OUTBUFEMPTY Position */
+#define CRPT_TDES_STS_OUTBUFEMPTY_Msk    (0x1ul << CRPT_TDES_STS_OUTBUFEMPTY_Pos)          /*!< CRPT_T::TDES_STS: OUTBUFEMPTY Mask     */
+
+#define CRPT_TDES_STS_OUTBUFFULL_Pos     (17)                                              /*!< CRPT_T::TDES_STS: OUTBUFFULL Position  */
+#define CRPT_TDES_STS_OUTBUFFULL_Msk     (0x1ul << CRPT_TDES_STS_OUTBUFFULL_Pos)           /*!< CRPT_T::TDES_STS: OUTBUFFULL Mask      */
+
+#define CRPT_TDES_STS_OUTBUFERR_Pos      (18)                                              /*!< CRPT_T::TDES_STS: OUTBUFERR Position   */
+#define CRPT_TDES_STS_OUTBUFERR_Msk      (0x1ul << CRPT_TDES_STS_OUTBUFERR_Pos)            /*!< CRPT_T::TDES_STS: OUTBUFERR Mask       */
+
+#define CRPT_TDES_STS_BUSERR_Pos         (20)                                              /*!< CRPT_T::TDES_STS: BUSERR Position      */
+#define CRPT_TDES_STS_BUSERR_Msk         (0x1ul << CRPT_TDES_STS_BUSERR_Pos)               /*!< CRPT_T::TDES_STS: BUSERR Mask          */
+
+#define CRPT_TDES0_KEYxH_KEY_Pos         (0)                                               /*!< CRPT_T::TDES0_KEYxH: KEY Position      */
+#define CRPT_TDES0_KEYxH_KEY_Msk         (0xfffffffful << CRPT_TDES0_KEYxH_KEY_Pos)        /*!< CRPT_T::TDES0_KEYxH: KEY Mask          */
+
+#define CRPT_TDES0_KEYxL_KEY_Pos         (0)                                               /*!< CRPT_T::TDES0_KEYxL: KEY Position      */
+#define CRPT_TDES0_KEYxL_KEY_Msk         (0xfffffffful << CRPT_TDES0_KEYxL_KEY_Pos)        /*!< CRPT_T::TDES0_KEYxL: KEY Mask          */
+
+#define CRPT_TDES0_IVH_IV_Pos            (0)                                               /*!< CRPT_T::TDES0_IVH: IV Position         */
+#define CRPT_TDES0_IVH_IV_Msk            (0xfffffffful << CRPT_TDES0_IVH_IV_Pos)           /*!< CRPT_T::TDES0_IVH: IV Mask             */
+
+#define CRPT_TDES0_IVL_IV_Pos            (0)                                               /*!< CRPT_T::TDES0_IVL: IV Position         */
+#define CRPT_TDES0_IVL_IV_Msk            (0xfffffffful << CRPT_TDES0_IVL_IV_Pos)           /*!< CRPT_T::TDES0_IVL: IV Mask             */
+
+#define CRPT_TDES0_SADDR_SADDR_Pos       (0)                                               /*!< CRPT_T::TDES0_SADDR: SADDR Position    */
+#define CRPT_TDES0_SADDR_SADDR_Msk       (0xfffffffful << CRPT_TDES0_SADDR_SADDR_Pos)      /*!< CRPT_T::TDES0_SADDR: SADDR Mask        */
+
+#define CRPT_TDES0_DADDR_DADDR_Pos       (0)                                               /*!< CRPT_T::TDES0_DADDR: DADDR Position    */
+#define CRPT_TDES0_DADDR_DADDR_Msk       (0xfffffffful << CRPT_TDES0_DADDR_DADDR_Pos)      /*!< CRPT_T::TDES0_DADDR: DADDR Mask        */
+
+#define CRPT_TDES0_CNT_CNT_Pos           (0)                                               /*!< CRPT_T::TDES0_CNT: CNT Position        */
+#define CRPT_TDES0_CNT_CNT_Msk           (0xfffffffful << CRPT_TDES0_CNT_CNT_Pos)          /*!< CRPT_T::TDES0_CNT: CNT Mask            */
+
+#define CRPT_TDES_DATIN_DATIN_Pos        (0)                                               /*!< CRPT_T::TDES_DATIN: DATIN Position     */
+#define CRPT_TDES_DATIN_DATIN_Msk        (0xfffffffful << CRPT_TDES_DATIN_DATIN_Pos)       /*!< CRPT_T::TDES_DATIN: DATIN Mask         */
+
+#define CRPT_TDES_DATOUT_DATOUT_Pos      (0)                                               /*!< CRPT_T::TDES_DATOUT: DATOUT Position   */
+#define CRPT_TDES_DATOUT_DATOUT_Msk      (0xfffffffful << CRPT_TDES_DATOUT_DATOUT_Pos)     /*!< CRPT_T::TDES_DATOUT: DATOUT Mask       */
+
+#define CRPT_TDES1_KEYxH_KEY_Pos         (0)                                               /*!< CRPT_T::TDES1_KEYxH: KEY Position      */
+#define CRPT_TDES1_KEYxH_KEY_Msk         (0xfffffffful << CRPT_TDES1_KEYxH_KEY_Pos)        /*!< CRPT_T::TDES1_KEYxH: KEY Mask          */
+
+#define CRPT_TDES1_KEYxL_KEY_Pos         (0)                                               /*!< CRPT_T::TDES1_KEYxL: KEY Position      */
+#define CRPT_TDES1_KEYxL_KEY_Msk         (0xfffffffful << CRPT_TDES1_KEY1L_KEY_Pos)        /*!< CRPT_T::TDES1_KEYxL: KEY Mask          */
+
+#define CRPT_TDES1_IVH_IV_Pos            (0)                                               /*!< CRPT_T::TDES1_IVH: IV Position         */
+#define CRPT_TDES1_IVH_IV_Msk            (0xfffffffful << CRPT_TDES1_IVH_IV_Pos)           /*!< CRPT_T::TDES1_IVH: IV Mask             */
+
+#define CRPT_TDES1_IVL_IV_Pos            (0)                                               /*!< CRPT_T::TDES1_IVL: IV Position         */
+#define CRPT_TDES1_IVL_IV_Msk            (0xfffffffful << CRPT_TDES1_IVL_IV_Pos)           /*!< CRPT_T::TDES1_IVL: IV Mask             */
+
+#define CRPT_TDES1_SADDR_SADDR_Pos       (0)                                               /*!< CRPT_T::TDES1_SADDR: SADDR Position    */
+#define CRPT_TDES1_SADDR_SADDR_Msk       (0xfffffffful << CRPT_TDES1_SADDR_SADDR_Pos)      /*!< CRPT_T::TDES1_SADDR: SADDR Mask        */
+
+#define CRPT_TDES1_DADDR_DADDR_Pos       (0)                                               /*!< CRPT_T::TDES1_DADDR: DADDR Position    */
+#define CRPT_TDES1_DADDR_DADDR_Msk       (0xfffffffful << CRPT_TDES1_DADDR_DADDR_Pos)      /*!< CRPT_T::TDES1_DADDR: DADDR Mask        */
+
+#define CRPT_TDES1_CNT_CNT_Pos           (0)                                               /*!< CRPT_T::TDES1_CNT: CNT Position        */
+#define CRPT_TDES1_CNT_CNT_Msk           (0xfffffffful << CRPT_TDES1_CNT_CNT_Pos)          /*!< CRPT_T::TDES1_CNT: CNT Mask            */
+
+#define CRPT_TDES2_KEYxH_KEY_Pos         (0)                                               /*!< CRPT_T::TDES2_KEYxH: KEY Position      */
+#define CRPT_TDES2_KEYxH_KEY_Msk         (0xfffffffful << CRPT_TDES2_KEYxH_KEY_Pos)        /*!< CRPT_T::TDES2_KEYxH: KEY Mask          */
+
+#define CRPT_TDES2_KEYxL_KEY_Pos         (0)                                               /*!< CRPT_T::TDES2_KEYxL: KEY Position      */
+#define CRPT_TDES2_KEYxL_KEY_Msk         (0xfffffffful << CRPT_TDES2_KEYxL_KEY_Pos)        /*!< CRPT_T::TDES2_KEYxL: KEY Mask          */
+
+#define CRPT_TDES2_IVH_IV_Pos            (0)                                               /*!< CRPT_T::TDES2_IVH: IV Position         */
+#define CRPT_TDES2_IVH_IV_Msk            (0xfffffffful << CRPT_TDES2_IVH_IV_Pos)           /*!< CRPT_T::TDES2_IVH: IV Mask             */
+
+#define CRPT_TDES2_IVL_IV_Pos            (0)                                               /*!< CRPT_T::TDES2_IVL: IV Position         */
+#define CRPT_TDES2_IVL_IV_Msk            (0xfffffffful << CRPT_TDES2_IVL_IV_Pos)           /*!< CRPT_T::TDES2_IVL: IV Mask             */
+
+#define CRPT_TDES2_SADDR_SADDR_Pos       (0)                                               /*!< CRPT_T::TDES2_SADDR: SADDR Position    */
+#define CRPT_TDES2_SADDR_SADDR_Msk       (0xfffffffful << CRPT_TDES2_SADDR_SADDR_Pos)      /*!< CRPT_T::TDES2_SADDR: SADDR Mask        */
+
+#define CRPT_TDES2_DADDR_DADDR_Pos       (0)                                               /*!< CRPT_T::TDES2_DADDR: DADDR Position    */
+#define CRPT_TDES2_DADDR_DADDR_Msk       (0xfffffffful << CRPT_TDES2_DADDR_DADDR_Pos)      /*!< CRPT_T::TDES2_DADDR: DADDR Mask        */
+
+#define CRPT_TDES2_CNT_CNT_Pos           (0)                                               /*!< CRPT_T::TDES2_CNT: CNT Position        */
+#define CRPT_TDES2_CNT_CNT_Msk           (0xfffffffful << CRPT_TDES2_CNT_CNT_Pos)          /*!< CRPT_T::TDES2_CNT: CNT Mask            */
+
+#define CRPT_TDES3_KEYxH_KEY_Pos         (0)                                               /*!< CRPT_T::TDES3_KEYxH: KEY Position      */
+#define CRPT_TDES3_KEYxH_KEY_Msk         (0xfffffffful << CRPT_TDES3_KEYxH_KEY_Pos)        /*!< CRPT_T::TDES3_KEYxH: KEY Mask          */
+
+#define CRPT_TDES3_KEYxL_KEY_Pos         (0)                                               /*!< CRPT_T::TDES3_KEYxL: KEY Position      */
+#define CRPT_TDES3_KEYxL_KEY_Msk         (0xfffffffful << CRPT_TDES3_KEYxL_KEY_Pos)        /*!< CRPT_T::TDES3_KEYxL: KEY Mask          */
+
+#define CRPT_TDES3_IVH_IV_Pos            (0)                                               /*!< CRPT_T::TDES3_IVH: IV Position         */
+#define CRPT_TDES3_IVH_IV_Msk            (0xfffffffful << CRPT_TDES3_IVH_IV_Pos)           /*!< CRPT_T::TDES3_IVH: IV Mask             */
+
+#define CRPT_TDES3_IVL_IV_Pos            (0)                                               /*!< CRPT_T::TDES3_IVL: IV Position         */
+#define CRPT_TDES3_IVL_IV_Msk            (0xfffffffful << CRPT_TDES3_IVL_IV_Pos)           /*!< CRPT_T::TDES3_IVL: IV Mask             */
+
+#define CRPT_TDES3_SADDR_SADDR_Pos       (0)                                               /*!< CRPT_T::TDES3_SADDR: SADDR Position    */
+#define CRPT_TDES3_SADDR_SADDR_Msk       (0xfffffffful << CRPT_TDES3_SADDR_SADDR_Pos)      /*!< CRPT_T::TDES3_SADDR: SADDR Mask        */
+
+#define CRPT_TDES3_DADDR_DADDR_Pos       (0)                                               /*!< CRPT_T::TDES3_DADDR: DADDR Position    */
+#define CRPT_TDES3_DADDR_DADDR_Msk       (0xfffffffful << CRPT_TDES3_DADDR_DADDR_Pos)      /*!< CRPT_T::TDES3_DADDR: DADDR Mask        */
+
+#define CRPT_TDES3_CNT_CNT_Pos           (0)                                               /*!< CRPT_T::TDES3_CNT: CNT Position        */
+#define CRPT_TDES3_CNT_CNT_Msk           (0xfffffffful << CRPT_TDES3_CNT_CNT_Pos)          /*!< CRPT_T::TDES3_CNT: CNT Mask            */
+
+#define CRPT_HMAC_CTL_START_Pos          (0)                                               /*!< CRPT_T::HMAC_CTL: START Position       */
+#define CRPT_HMAC_CTL_START_Msk          (0x1ul << CRPT_HMAC_CTL_START_Pos)                /*!< CRPT_T::HMAC_CTL: START Mask           */
+
+#define CRPT_HMAC_CTL_STOP_Pos           (1)                                               /*!< CRPT_T::HMAC_CTL: STOP Position        */
+#define CRPT_HMAC_CTL_STOP_Msk           (0x1ul << CRPT_HMAC_CTL_STOP_Pos)                 /*!< CRPT_T::HMAC_CTL: STOP Mask            */
+
+#define CRPT_HMAC_CTL_HMACEN_Pos         (4)                                               /*!< CRPT_T::HMAC_CTL: HMACEN Position      */
+#define CRPT_HMAC_CTL_HMACEN_Msk         (0x1ul << CRPT_HMAC_CTL_HMACEN_Pos)               /*!< CRPT_T::HMAC_CTL: HMACEN Mask          */
+
+#define CRPT_HMAC_CTL_DMALAST_Pos        (5)                                               /*!< CRPT_T::HMAC_CTL: DMALAST Position     */
+#define CRPT_HMAC_CTL_DMALAST_Msk        (0x1ul << CRPT_HMAC_CTL_DMALAST_Pos)              /*!< CRPT_T::HMAC_CTL: DMALAST Mask         */
+
+#define CRPT_HMAC_CTL_DMAEN_Pos          (7)                                               /*!< CRPT_T::HMAC_CTL: DMAEN Position       */
+#define CRPT_HMAC_CTL_DMAEN_Msk          (0x1ul << CRPT_HMAC_CTL_DMAEN_Pos)                /*!< CRPT_T::HMAC_CTL: DMAEN Mask           */
+
+#define CRPT_HMAC_CTL_OPMODE_Pos         (8)                                               /*!< CRPT_T::HMAC_CTL: OPMODE Position      */
+#define CRPT_HMAC_CTL_OPMODE_Msk         (0x7ul << CRPT_HMAC_CTL_OPMODE_Pos)               /*!< CRPT_T::HMAC_CTL: OPMODE Mask          */
+
+#define CRPT_HMAC_CTL_OUTSWAP_Pos        (22)                                              /*!< CRPT_T::HMAC_CTL: OUTSWAP Position     */
+#define CRPT_HMAC_CTL_OUTSWAP_Msk        (0x1ul << CRPT_HMAC_CTL_OUTSWAP_Pos)              /*!< CRPT_T::HMAC_CTL: OUTSWAP Mask         */
+
+#define CRPT_HMAC_CTL_INSWAP_Pos         (23)                                              /*!< CRPT_T::HMAC_CTL: INSWAP Position      */
+#define CRPT_HMAC_CTL_INSWAP_Msk         (0x1ul << CRPT_HMAC_CTL_INSWAP_Pos)               /*!< CRPT_T::HMAC_CTL: INSWAP Mask          */
+
+#define CRPT_HMAC_STS_BUSY_Pos           (0)                                               /*!< CRPT_T::HMAC_STS: BUSY Position        */
+#define CRPT_HMAC_STS_BUSY_Msk           (0x1ul << CRPT_HMAC_STS_BUSY_Pos)                 /*!< CRPT_T::HMAC_STS: BUSY Mask            */
+
+#define CRPT_HMAC_STS_DMABUSY_Pos        (1)                                               /*!< CRPT_T::HMAC_STS: DMABUSY Position     */
+#define CRPT_HMAC_STS_DMABUSY_Msk        (0x1ul << CRPT_HMAC_STS_DMABUSY_Pos)              /*!< CRPT_T::HMAC_STS: DMABUSY Mask         */
+
+#define CRPT_HMAC_STS_DMAERR_Pos         (8)                                               /*!< CRPT_T::HMAC_STS: DMAERR Position      */
+#define CRPT_HMAC_STS_DMAERR_Msk         (0x1ul << CRPT_HMAC_STS_DMAERR_Pos)               /*!< CRPT_T::HMAC_STS: DMAERR Mask          */
+
+#define CRPT_HMAC_STS_DATINREQ_Pos       (16)                                              /*!< CRPT_T::HMAC_STS: DATINREQ Position    */
+#define CRPT_HMAC_STS_DATINREQ_Msk       (0x1ul << CRPT_HMAC_STS_DATINREQ_Pos)             /*!< CRPT_T::HMAC_STS: DATINREQ Mask        */
+
+#define CRPT_HMAC_DGSTx_DGST_Pos         (0)                                               /*!< CRPT_T::HMAC_DGST[16]: DGST Position   */
+#define CRPT_HMAC_DGSTx_DGST_Msk         (0xfffffffful << CRPT_HMAC_DGSTx_DGST_Pos)        /*!< CRPT_T::HMAC_DGST[16]: DGST Mask       */
+
+#define CRPT_HMAC_KEYCNT_KEYCNT_Pos      (0)                                               /*!< CRPT_T::HMAC_KEYCNT: KEYCNT Position   */
+#define CRPT_HMAC_KEYCNT_KEYCNT_Msk      (0xfffffffful << CRPT_HMAC_KEYCNT_KEYCNT_Pos)     /*!< CRPT_T::HMAC_KEYCNT: KEYCNT Mask       */
+
+#define CRPT_HMAC_SADDR_SADDR_Pos        (0)                                               /*!< CRPT_T::HMAC_SADDR: SADDR Position     */
+#define CRPT_HMAC_SADDR_SADDR_Msk        (0xfffffffful << CRPT_HMAC_SADDR_SADDR_Pos)       /*!< CRPT_T::HMAC_SADDR: SADDR Mask         */
+
+#define CRPT_HMAC_DMACNT_DMACNT_Pos      (0)                                               /*!< CRPT_T::HMAC_DMACNT: DMACNT Position   */
+#define CRPT_HMAC_DMACNT_DMACNT_Msk      (0xfffffffful << CRPT_HMAC_DMACNT_DMACNT_Pos)     /*!< CRPT_T::HMAC_DMACNT: DMACNT Mask       */
+
+#define CRPT_HMAC_DATIN_DATIN_Pos        (0)                                               /*!< CRPT_T::HMAC_DATIN: DATIN Position     */
+#define CRPT_HMAC_DATIN_DATIN_Msk        (0xfffffffful << CRPT_HMAC_DATIN_DATIN_Pos)       /*!< CRPT_T::HMAC_DATIN: DATIN Mask         */
+
+#define CRPT_ECC_CTL_START_Pos           (0)                                               /*!< CRPT_T::ECC_CTL: START Position        */
+#define CRPT_ECC_CTL_START_Msk           (0x1ul << CRPT_ECC_CTL_START_Pos)                 /*!< CRPT_T::ECC_CTL: START Mask            */
+
+#define CRPT_ECC_CTL_STOP_Pos            (1)                                               /*!< CRPT_T::ECC_CTL: STOP Position         */
+#define CRPT_ECC_CTL_STOP_Msk            (0x1ul << CRPT_ECC_CTL_STOP_Pos)                  /*!< CRPT_T::ECC_CTL: STOP Mask             */
+
+#define CRPT_ECC_CTL_DMAEN_Pos           (7)                                               /*!< CRPT_T::ECC_CTL: DMAEN Position        */
+#define CRPT_ECC_CTL_DMAEN_Msk           (0x1ul << CRPT_ECC_CTL_DMAEN_Pos)                 /*!< CRPT_T::ECC_CTL: DMAEN Mask            */
+
+#define CRPT_ECC_CTL_FSEL_Pos            (8)                                               /*!< CRPT_T::ECC_CTL: FSEL Position         */
+#define CRPT_ECC_CTL_FSEL_Msk            (0x1ul << CRPT_ECC_CTL_FSEL_Pos)                  /*!< CRPT_T::ECC_CTL: FSEL Mask             */
+
+#define CRPT_ECC_CTL_ECCOP_Pos           (9)                                               /*!< CRPT_T::ECC_CTL: ECCOP Position        */
+#define CRPT_ECC_CTL_ECCOP_Msk           (0x3ul << CRPT_ECC_CTL_ECCOP_Pos)                 /*!< CRPT_T::ECC_CTL: ECCOP Mask            */
+
+#define CRPT_ECC_CTL_MODOP_Pos           (11)                                              /*!< CRPT_T::ECC_CTL: MODOP Position        */
+#define CRPT_ECC_CTL_MODOP_Msk           (0x3ul << CRPT_ECC_CTL_MODOP_Pos)                 /*!< CRPT_T::ECC_CTL: MODOP Mask            */
+
+#define CRPT_ECC_CTL_LDP1_Pos            (16)                                              /*!< CRPT_T::ECC_CTL: LDP1 Position         */
+#define CRPT_ECC_CTL_LDP1_Msk            (0x1ul << CRPT_ECC_CTL_LDP1_Pos)                  /*!< CRPT_T::ECC_CTL: LDP1 Mask             */
+
+#define CRPT_ECC_CTL_LDP2_Pos            (17)                                              /*!< CRPT_T::ECC_CTL: LDP2 Position         */
+#define CRPT_ECC_CTL_LDP2_Msk            (0x1ul << CRPT_ECC_CTL_LDP2_Pos)                  /*!< CRPT_T::ECC_CTL: LDP2 Mask             */
+
+#define CRPT_ECC_CTL_LDA_Pos             (18)                                              /*!< CRPT_T::ECC_CTL: LDA Position          */
+#define CRPT_ECC_CTL_LDA_Msk             (0x1ul << CRPT_ECC_CTL_LDA_Pos)                   /*!< CRPT_T::ECC_CTL: LDA Mask              */
+
+#define CRPT_ECC_CTL_LDB_Pos             (19)                                              /*!< CRPT_T::ECC_CTL: LDB Position          */
+#define CRPT_ECC_CTL_LDB_Msk             (0x1ul << CRPT_ECC_CTL_LDB_Pos)                   /*!< CRPT_T::ECC_CTL: LDB Mask              */
+
+#define CRPT_ECC_CTL_LDN_Pos             (20)                                              /*!< CRPT_T::ECC_CTL: LDN Position          */
+#define CRPT_ECC_CTL_LDN_Msk             (0x1ul << CRPT_ECC_CTL_LDN_Pos)                   /*!< CRPT_T::ECC_CTL: LDN Mask              */
+
+#define CRPT_ECC_CTL_LDK_Pos             (21)                                              /*!< CRPT_T::ECC_CTL: LDK Position          */
+#define CRPT_ECC_CTL_LDK_Msk             (0x1ul << CRPT_ECC_CTL_LDK_Pos)                   /*!< CRPT_T::ECC_CTL: LDK Mask              */
+
+#define CRPT_ECC_CTL_CURVEM_Pos          (22)                                              /*!< CRPT_T::ECC_CTL: CURVEM Position       */
+#define CRPT_ECC_CTL_CURVEM_Msk          (0x3fful << CRPT_ECC_CTL_CURVEM_Pos)              /*!< CRPT_T::ECC_CTL: CURVEM Mask           */
+
+#define CRPT_ECC_STS_BUSY_Pos            (0)                                               /*!< CRPT_T::ECC_STS: BUSY Position         */
+#define CRPT_ECC_STS_BUSY_Msk            (0x1ul << CRPT_ECC_STS_BUSY_Pos)                  /*!< CRPT_T::ECC_STS: BUSY Mask             */
+
+#define CRPT_ECC_STS_DMABUSY_Pos         (1)                                               /*!< CRPT_T::ECC_STS: DMABUSY Position      */
+#define CRPT_ECC_STS_DMABUSY_Msk         (0x1ul << CRPT_ECC_STS_DMABUSY_Pos)               /*!< CRPT_T::ECC_STS: DMABUSY Mask          */
+
+#define CRPT_ECC_STS_BUSERR_Pos          (16)                                              /*!< CRPT_T::ECC_STS: BUSERR Position       */
+#define CRPT_ECC_STS_BUSERR_Msk          (0x1ul << CRPT_ECC_STS_BUSERR_Pos)                /*!< CRPT_T::ECC_STS: BUSERR Mask           */
+
+#define CRPT_ECC_X1_POINTX1_Pos          (0)                                               /*!< CRPT_T::ECC_X1[18]:  POINTX1 Position  */
+#define CRPT_ECC_X1_POINTX1_Msk          (0xfffffffful << CRPT_ECC_X1_POINTX1_Pos)         /*!< CRPT_T::ECC_X1[18]:  POINTX1 Mask      */
+
+#define CRPT_ECC_Y1_POINTY1_Pos          (0)                                               /*!< CRPT_T::ECC_Y1[18]: POINTY1 Position   */
+#define CRPT_ECC_Y1_POINTY1_Msk          (0xfffffffful << CRPT_ECC_Y1_POINTY1_Pos)         /*!< CRPT_T::ECC_Y1[18]: POINTY1 Mask       */
+
+#define CRPT_ECC_X2_POINTX2_Pos          (0)                                               /*!< CRPT_T::ECC_X2[18]: POINTX2 Position   */
+#define CRPT_ECC_X2_POINTX2_Msk          (0xfffffffful << CRPT_ECC_X2_POINTX2_Pos)         /*!< CRPT_T::ECC_X2[18]: POINTX2 Mask       */
+
+#define CRPT_ECC_Y2_POINTY2_Pos          (0)                                               /*!< CRPT_T::ECC_Y2[18]: POINTY2 Position   */
+#define CRPT_ECC_Y2_POINTY2_Msk          (0xfffffffful << CRPT_ECC_Y2_POINTY2_Pos)         /*!< CRPT_T::ECC_Y2[18]: POINTY2 Mask       */
+
+#define CRPT_ECC_A_CURVEA_Pos            (0)                                               /*!< CRPT_T::ECC_A[18]: CURVEA Position     */
+#define CRPT_ECC_A_CURVEA_Msk            (0xfffffffful << CRPT_ECC_A_CURVEA_Pos)           /*!< CRPT_T::ECC_A[18]: CURVEA Mask         */
+
+#define CRPT_ECC_B_CURVEB_Pos            (0)                                               /*!< CRPT_T::ECC_B[18]: CURVEB Position     */
+#define CRPT_ECC_B_CURVEB_Msk            (0xfffffffful << CRPT_ECC_B_CURVEB_Pos)           /*!< CRPT_T::ECC_B[18]: CURVEB Mask         */
+
+#define CRPT_ECC_N_CURVEN_Pos            (0)                                               /*!< CRPT_T::ECC_N[18]: CURVEN Position     */
+#define CRPT_ECC_N_CURVEN_Msk            (0xfffffffful << CRPT_ECC_N_CURVEN_Pos)           /*!< CRPT_T::ECC_N[18]: CURVEN Mask         */
+
+#define CRPT_ECC_K_SCALARK_Pos           (0)                                               /*!< CRPT_T::ECC_K[18]: SCALARK Position    */
+#define CRPT_ECC_K_SCALARK_Msk           (0xfffffffful << CRPT_ECC_K_SCALARK_Pos)          /*!< CRPT_T::ECC_K[18]: SCALARK Mask        */
+
+#define CRPT_ECC_DADDR_DADDR_Pos         (0)                                               /*!< CRPT_T::ECC_DADDR: DADDR Position      */
+#define CRPT_ECC_DADDR_DADDR_Msk         (0xfffffffful << CRPT_ECC_DADDR_DADDR_Pos)        /*!< CRPT_T::ECC_DADDR: DADDR Mask          */
+
+#define CRPT_ECC_STARTREG_STARTREG_Pos   (0)                                               /*!< CRPT_T::ECC_STARTREG: STARTREG Position*/
+#define CRPT_ECC_STARTREG_STARTREG_Msk   (0xfffffffful << CRPT_ECC_STARTREG_STARTREG_Pos)  /*!< CRPT_T::ECC_STARTREG: STARTREG Mask    */
+
+#define CRPT_ECC_WORDCNT_WORDCNT_Pos     (0)                                               /*!< CRPT_T::ECC_WORDCNT: WORDCNT Position  */
+#define CRPT_ECC_WORDCNT_WORDCNT_Msk     (0xfffffffful << CRPT_ECC_WORDCNT_WORDCNT_Pos)    /*!< CRPT_T::ECC_WORDCNT: WORDCNT Mask      */
+
+/**@}*/ /* CRPT_CONST CRYPTO */
+/**@}*/ /* end of CRYPTO register group */
+/**@}*/ /* end of REGISTER group */
+
+#if defined ( __CC_ARM   )
+#pragma no_anon_unions
+#endif
+
+#endif /* __CRYPTO_REG_H__ */