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@@ -244,6 +244,54 @@ static const uint8_t furi_hal_subghz_preset_2fsk_dev4_76khz_async_regs[][2] = {
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/* End */
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/* End */
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{0, 0},
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{0, 0},
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};
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};
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+static const uint8_t furi_hal_subghz_preset_msk_99_97kb_async_regs[][2] = {
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+ /* GPIO GD0 */
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+ {CC1101_IOCFG0, 0x06},
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+
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+ {CC1101_FIFOTHR, 0x07}, // The only important bit is ADC_RETENTION
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+ {CC1101_SYNC1, 0x46},
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+ {CC1101_SYNC0, 0x4C},
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+ {CC1101_ADDR, 0x00},
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+ {CC1101_PKTLEN, 0x00},
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+ {CC1101_CHANNR, 0x00},
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+
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+ {CC1101_PKTCTRL0, 0x05},
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+
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+ {CC1101_FSCTRL0, 0x23},
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+ {CC1101_FSCTRL1, 0x06},
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+
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+ {CC1101_MDMCFG0, 0xF8},
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+ {CC1101_MDMCFG1, 0x22},
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+ {CC1101_MDMCFG2, 0x72},
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+ {CC1101_MDMCFG3, 0xF8},
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+ {CC1101_MDMCFG4, 0x5B},
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+ {CC1101_DEVIATN, 0x47},
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+
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+ {CC1101_MCSM0, 0x18},
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+ {CC1101_FOCCFG, 0x16},
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+
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+ {CC1101_AGCCTRL0, 0xB2},
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+ {CC1101_AGCCTRL1, 0x00},
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+ {CC1101_AGCCTRL2, 0xC7},
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+
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+ {CC1101_FREND0, 0x10},
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+ {CC1101_FREND1, 0x56},
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+
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+ {CC1101_FSCAL3, 0xE9},
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+ {CC1101_FSCAL2, 0x2A},
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+ {CC1101_FSCAL1, 0x00},
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+ {CC1101_FSCAL0, 0x1F},
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+
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+ {CC1101_BSCFG, 0x1C},
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+ {CC1101_FSTEST, 0x59},
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+
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+ {CC1101_TEST2, 0x81},
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+ {CC1101_TEST1, 0x35},
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+ {CC1101_TEST0, 0x09},
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+ /* End */
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+ {0, 0},
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+};
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+
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static const uint8_t furi_hal_subghz_preset_ook_async_patable[8] = {
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static const uint8_t furi_hal_subghz_preset_ook_async_patable[8] = {
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0x00,
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0x00,
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0xC0, // 10dBm 0xC0, 7dBm 0xC8, 5dBm 0x84, 0dBm 0x60, -10dBm 0x34, -15dBm 0x1D, -20dBm 0x0E, -30dBm 0x12
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0xC0, // 10dBm 0xC0, 7dBm 0xC8, 5dBm 0x84, 0dBm 0x60, -10dBm 0x34, -15dBm 0x1D, -20dBm 0x0E, -30dBm 0x12
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@@ -261,9 +309,16 @@ static const uint8_t furi_hal_subghz_preset_2fsk_async_patable[8] = {
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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- 0x00
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-
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-};
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+ 0x00};
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+static const uint8_t furi_hal_subghz_preset_msk_async_patable[8] = {
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+ 0xC0, // 10dBm 0xC0, 7dBm 0xC8, 5dBm 0x84, 0dBm 0x60, -10dBm 0x34, -15dBm 0x1D, -20dBm 0x0E, -30dBm 0x12
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+ 0x00,
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+ 0x00,
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+ 0x00,
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+ 0x00,
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+ 0x00,
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+ 0x00,
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+ 0x00};
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void furi_hal_subghz_init() {
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void furi_hal_subghz_init() {
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furi_assert(furi_hal_subghz_state == SubGhzStateInit);
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furi_assert(furi_hal_subghz_state == SubGhzStateInit);
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@@ -344,6 +399,9 @@ void furi_hal_subghz_load_preset(FuriHalSubGhzPreset preset) {
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} else if(preset == FuriHalSubGhzPreset2FSKDev476Async) {
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} else if(preset == FuriHalSubGhzPreset2FSKDev476Async) {
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furi_hal_subghz_load_registers(furi_hal_subghz_preset_2fsk_dev4_76khz_async_regs);
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furi_hal_subghz_load_registers(furi_hal_subghz_preset_2fsk_dev4_76khz_async_regs);
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furi_hal_subghz_load_patable(furi_hal_subghz_preset_2fsk_async_patable);
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furi_hal_subghz_load_patable(furi_hal_subghz_preset_2fsk_async_patable);
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+ } else if(preset == FuriHalSubGhzPresetMSK99_97KbAsync) {
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+ furi_hal_subghz_load_registers(furi_hal_subghz_preset_msk_99_97kb_async_regs);
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+ furi_hal_subghz_load_patable(furi_hal_subghz_preset_msk_async_patable);
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} else {
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} else {
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furi_crash(NULL);
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furi_crash(NULL);
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}
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}
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@@ -369,6 +427,7 @@ void furi_hal_subghz_load_patable(const uint8_t data[8]) {
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void furi_hal_subghz_write_packet(const uint8_t* data, uint8_t size) {
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void furi_hal_subghz_write_packet(const uint8_t* data, uint8_t size) {
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furi_hal_spi_acquire(&furi_hal_spi_bus_handle_subghz);
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furi_hal_spi_acquire(&furi_hal_spi_bus_handle_subghz);
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cc1101_flush_tx(&furi_hal_spi_bus_handle_subghz);
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cc1101_flush_tx(&furi_hal_spi_bus_handle_subghz);
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+ cc1101_write_reg(&furi_hal_spi_bus_handle_subghz, CC1101_FIFO, size);
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cc1101_write_fifo(&furi_hal_spi_bus_handle_subghz, data, size);
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cc1101_write_fifo(&furi_hal_spi_bus_handle_subghz, data, size);
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furi_hal_spi_release(&furi_hal_spi_bus_handle_subghz);
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furi_hal_spi_release(&furi_hal_spi_bus_handle_subghz);
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}
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}
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@@ -379,6 +438,31 @@ void furi_hal_subghz_flush_rx() {
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furi_hal_spi_release(&furi_hal_spi_bus_handle_subghz);
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furi_hal_spi_release(&furi_hal_spi_bus_handle_subghz);
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}
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}
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+bool furi_hal_subghz_rx_pipe_not_empty() {
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+ CC1101RxBytes status[1];
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+ furi_hal_spi_acquire(&furi_hal_spi_bus_handle_subghz);
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+ cc1101_read_reg(&furi_hal_spi_bus_handle_subghz, (CC1101_STATUS_RXBYTES) | CC1101_BURST, (uint8_t*)status);
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+ furi_hal_spi_release(&furi_hal_spi_bus_handle_subghz);
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+ // TODO: you can add a buffer overflow flag if needed
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+ if(status->NUM_RXBYTES > 0) {
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+ return true;
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+ } else {
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+ return false;
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+ }
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+}
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+
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+bool furi_hal_subghz_is_rx_data_crc_valid() {
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+ furi_hal_spi_acquire(&furi_hal_spi_bus_handle_subghz);
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+ uint8_t data[1];
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+ cc1101_read_reg(&furi_hal_spi_bus_handle_subghz, CC1101_STATUS_LQI | CC1101_BURST, data);
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+ furi_hal_spi_release(&furi_hal_spi_bus_handle_subghz);
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+ if(((data[0] >> 7) & 0x01)) {
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+ return true;
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+ } else {
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+ return false;
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+ }
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+}
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+
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void furi_hal_subghz_read_packet(uint8_t* data, uint8_t* size) {
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void furi_hal_subghz_read_packet(uint8_t* data, uint8_t* size) {
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furi_hal_spi_acquire(&furi_hal_spi_bus_handle_subghz);
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furi_hal_spi_acquire(&furi_hal_spi_bus_handle_subghz);
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cc1101_read_fifo(&furi_hal_spi_bus_handle_subghz, data, size);
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cc1101_read_fifo(&furi_hal_spi_bus_handle_subghz, data, size);
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@@ -460,18 +544,16 @@ uint32_t furi_hal_subghz_set_frequency_and_path(uint32_t value) {
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return value;
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return value;
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}
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}
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-uint32_t furi_hal_subghz_set_frequency(uint32_t value) {
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- furi_hal_spi_acquire(&furi_hal_spi_bus_handle_subghz);
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-
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+bool furi_hal_subghz_is_tx_allowed(uint32_t value) {
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//checking regional settings
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//checking regional settings
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- bool txrx = false;
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+ bool is_allowed = false;
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switch(furi_hal_version_get_hw_region()) {
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switch(furi_hal_version_get_hw_region()) {
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case FuriHalVersionRegionEuRu:
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case FuriHalVersionRegionEuRu:
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//433,05..434,79; 868,15..868,55
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//433,05..434,79; 868,15..868,55
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if(!(value >= 433050000 && value <= 434790000) &&
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if(!(value >= 433050000 && value <= 434790000) &&
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!(value >= 868150000 && value <= 868550000)) {
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!(value >= 868150000 && value <= 868550000)) {
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} else {
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} else {
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- txrx = true;
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+ is_allowed = true;
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}
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}
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break;
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break;
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case FuriHalVersionRegionUsCaAu:
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case FuriHalVersionRegionUsCaAu:
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@@ -480,7 +562,7 @@ uint32_t furi_hal_subghz_set_frequency(uint32_t value) {
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!(value >= 433050000 && value <= 434790000) &&
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!(value >= 433050000 && value <= 434790000) &&
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!(value >= 915000000 && value <= 928000000)) {
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!(value >= 915000000 && value <= 928000000)) {
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} else {
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} else {
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- txrx = true;
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+ is_allowed = true;
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}
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}
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break;
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break;
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case FuriHalVersionRegionJp:
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case FuriHalVersionRegionJp:
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@@ -488,16 +570,21 @@ uint32_t furi_hal_subghz_set_frequency(uint32_t value) {
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if(!(value >= 312000000 && value <= 315250000) &&
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if(!(value >= 312000000 && value <= 315250000) &&
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!(value >= 920500000 && value <= 923500000)) {
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!(value >= 920500000 && value <= 923500000)) {
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} else {
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} else {
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- txrx = true;
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+ is_allowed = true;
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}
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}
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break;
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break;
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default:
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default:
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- txrx = true;
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+ is_allowed = true;
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break;
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break;
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}
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}
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+ return is_allowed;
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+}
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+
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+uint32_t furi_hal_subghz_set_frequency(uint32_t value) {
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+ furi_hal_spi_acquire(&furi_hal_spi_bus_handle_subghz);
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- if(txrx) {
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+ if(furi_hal_subghz_is_tx_allowed(value)) {
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furi_hal_subghz_regulation = SubGhzRegulationTxRx;
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furi_hal_subghz_regulation = SubGhzRegulationTxRx;
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} else {
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} else {
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furi_hal_subghz_regulation = SubGhzRegulationOnlyRx;
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furi_hal_subghz_regulation = SubGhzRegulationOnlyRx;
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