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@@ -22,7 +22,7 @@ void nrf24_deinit() {
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}
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}
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void nrf24_spi_trx(
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void nrf24_spi_trx(
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- FuriHalSpiBusHandle* handle,
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+ const FuriHalSpiBusHandle* handle,
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uint8_t* tx,
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uint8_t* tx,
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uint8_t* rx,
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uint8_t* rx,
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uint8_t size) {
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uint8_t size) {
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@@ -31,14 +31,14 @@ void nrf24_spi_trx(
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furi_hal_gpio_write(handle->cs, true);
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furi_hal_gpio_write(handle->cs, true);
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}
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}
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-uint8_t nrf24_write_reg(FuriHalSpiBusHandle* handle, uint8_t reg, uint8_t data) {
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+uint8_t nrf24_write_reg(const FuriHalSpiBusHandle* handle, uint8_t reg, uint8_t data) {
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uint8_t buf[] = {W_REGISTER | (REGISTER_MASK & reg), data};
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uint8_t buf[] = {W_REGISTER | (REGISTER_MASK & reg), data};
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nrf24_spi_trx(handle, buf, buf, 2);
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nrf24_spi_trx(handle, buf, buf, 2);
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//FURI_LOG_D("NRF_WR", " #%02X=%02X", reg, data);
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//FURI_LOG_D("NRF_WR", " #%02X=%02X", reg, data);
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return buf[0];
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return buf[0];
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}
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}
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-uint8_t nrf24_write_buf_reg(FuriHalSpiBusHandle* handle, uint8_t reg, uint8_t* data, uint8_t size) {
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+uint8_t nrf24_write_buf_reg(const FuriHalSpiBusHandle* handle, uint8_t reg, uint8_t* data, uint8_t size) {
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uint8_t buf[size + 1];
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uint8_t buf[size + 1];
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buf[0] = W_REGISTER | (REGISTER_MASK & reg);
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buf[0] = W_REGISTER | (REGISTER_MASK & reg);
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memcpy(&buf[1], data, size);
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memcpy(&buf[1], data, size);
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@@ -47,7 +47,7 @@ uint8_t nrf24_write_buf_reg(FuriHalSpiBusHandle* handle, uint8_t reg, uint8_t* d
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return buf[0];
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return buf[0];
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}
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}
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-uint8_t nrf24_read_reg(FuriHalSpiBusHandle* handle, uint8_t reg, uint8_t* data, uint8_t size) {
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+uint8_t nrf24_read_reg(const FuriHalSpiBusHandle* handle, uint8_t reg, uint8_t* data, uint8_t size) {
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uint8_t buf[size + 1];
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uint8_t buf[size + 1];
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memset(buf, 0, size + 1);
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memset(buf, 0, size + 1);
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buf[0] = R_REGISTER | (REGISTER_MASK & reg);
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buf[0] = R_REGISTER | (REGISTER_MASK & reg);
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@@ -56,47 +56,47 @@ uint8_t nrf24_read_reg(FuriHalSpiBusHandle* handle, uint8_t reg, uint8_t* data,
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return buf[0];
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return buf[0];
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}
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}
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-uint8_t nrf24_read_register(FuriHalSpiBusHandle* handle, uint8_t reg) {
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+uint8_t nrf24_read_register(const FuriHalSpiBusHandle* handle, uint8_t reg) {
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uint8_t buf[] = { R_REGISTER | (REGISTER_MASK & reg), 0 };
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uint8_t buf[] = { R_REGISTER | (REGISTER_MASK & reg), 0 };
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nrf24_spi_trx(handle, buf, buf, 2);
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nrf24_spi_trx(handle, buf, buf, 2);
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return buf[1];
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return buf[1];
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}
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}
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-uint8_t nrf24_flush_rx(FuriHalSpiBusHandle* handle) {
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+uint8_t nrf24_flush_rx(const FuriHalSpiBusHandle* handle) {
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uint8_t tx[] = {FLUSH_RX};
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uint8_t tx[] = {FLUSH_RX};
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uint8_t rx[] = {0};
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uint8_t rx[] = {0};
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nrf24_spi_trx(handle, tx, rx, 1);
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nrf24_spi_trx(handle, tx, rx, 1);
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return rx[0];
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return rx[0];
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}
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}
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-uint8_t nrf24_flush_tx(FuriHalSpiBusHandle* handle) {
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+uint8_t nrf24_flush_tx(const FuriHalSpiBusHandle* handle) {
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uint8_t tx[] = {FLUSH_TX};
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uint8_t tx[] = {FLUSH_TX};
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uint8_t rx[] = {0};
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uint8_t rx[] = {0};
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nrf24_spi_trx(handle, tx, rx, 1);
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nrf24_spi_trx(handle, tx, rx, 1);
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return rx[0];
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return rx[0];
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}
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}
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-uint8_t nrf24_get_maclen(FuriHalSpiBusHandle* handle) {
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+uint8_t nrf24_get_maclen(const FuriHalSpiBusHandle* handle) {
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uint8_t maclen;
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uint8_t maclen;
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nrf24_read_reg(handle, REG_SETUP_AW, &maclen, 1);
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nrf24_read_reg(handle, REG_SETUP_AW, &maclen, 1);
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maclen &= 3;
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maclen &= 3;
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return maclen + 2;
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return maclen + 2;
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}
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}
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-uint8_t nrf24_set_maclen(FuriHalSpiBusHandle* handle, uint8_t maclen) {
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+uint8_t nrf24_set_maclen(const FuriHalSpiBusHandle* handle, uint8_t maclen) {
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assert(maclen > 1 && maclen < 6);
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assert(maclen > 1 && maclen < 6);
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uint8_t status = 0;
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uint8_t status = 0;
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status = nrf24_write_reg(handle, REG_SETUP_AW, maclen - 2);
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status = nrf24_write_reg(handle, REG_SETUP_AW, maclen - 2);
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return status;
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return status;
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}
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}
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-uint8_t nrf24_status(FuriHalSpiBusHandle* handle) {
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+uint8_t nrf24_status(const FuriHalSpiBusHandle* handle) {
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uint8_t tx = RF24_NOP;
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uint8_t tx = RF24_NOP;
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nrf24_spi_trx(handle, &tx, &tx, 1);
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nrf24_spi_trx(handle, &tx, &tx, 1);
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return tx;
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return tx;
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}
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}
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-uint32_t nrf24_get_rate(FuriHalSpiBusHandle* handle) {
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+uint32_t nrf24_get_rate(const FuriHalSpiBusHandle* handle) {
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uint8_t setup = 0;
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uint8_t setup = 0;
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uint32_t rate = 0;
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uint32_t rate = 0;
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nrf24_read_reg(handle, REG_RF_SETUP, &setup, 1);
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nrf24_read_reg(handle, REG_RF_SETUP, &setup, 1);
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@@ -111,7 +111,7 @@ uint32_t nrf24_get_rate(FuriHalSpiBusHandle* handle) {
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return rate;
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return rate;
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}
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}
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-uint8_t nrf24_set_rate(FuriHalSpiBusHandle* handle, uint32_t rate) {
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+uint8_t nrf24_set_rate(const FuriHalSpiBusHandle* handle, uint32_t rate) {
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uint8_t r6 = 0;
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uint8_t r6 = 0;
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uint8_t status = 0;
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uint8_t status = 0;
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if(!rate) rate = 2000000;
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if(!rate) rate = 2000000;
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@@ -129,19 +129,19 @@ uint8_t nrf24_set_rate(FuriHalSpiBusHandle* handle, uint32_t rate) {
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return status;
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return status;
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}
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}
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-uint8_t nrf24_get_chan(FuriHalSpiBusHandle* handle) {
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+uint8_t nrf24_get_chan(const FuriHalSpiBusHandle* handle) {
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uint8_t channel = 0;
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uint8_t channel = 0;
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nrf24_read_reg(handle, REG_RF_CH, &channel, 1);
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nrf24_read_reg(handle, REG_RF_CH, &channel, 1);
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return channel;
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return channel;
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}
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}
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-uint8_t nrf24_set_chan(FuriHalSpiBusHandle* handle, uint8_t chan) {
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+uint8_t nrf24_set_chan(const FuriHalSpiBusHandle* handle, uint8_t chan) {
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uint8_t status;
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uint8_t status;
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status = nrf24_write_reg(handle, REG_RF_CH, chan);
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status = nrf24_write_reg(handle, REG_RF_CH, chan);
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return status;
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return status;
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}
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}
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-uint8_t nrf24_get_src_mac(FuriHalSpiBusHandle* handle, uint8_t* mac) {
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+uint8_t nrf24_get_src_mac(const FuriHalSpiBusHandle* handle, uint8_t* mac) {
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uint8_t size = 0;
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uint8_t size = 0;
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uint8_t status = 0;
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uint8_t status = 0;
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size = nrf24_get_maclen(handle);
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size = nrf24_get_maclen(handle);
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@@ -149,7 +149,7 @@ uint8_t nrf24_get_src_mac(FuriHalSpiBusHandle* handle, uint8_t* mac) {
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return status;
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return status;
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}
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}
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-uint8_t nrf24_set_src_mac(FuriHalSpiBusHandle* handle, uint8_t* mac, uint8_t size) {
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+uint8_t nrf24_set_src_mac(const FuriHalSpiBusHandle* handle, uint8_t* mac, uint8_t size) {
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uint8_t status = 0;
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uint8_t status = 0;
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uint8_t clearmac[] = {0, 0, 0, 0, 0};
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uint8_t clearmac[] = {0, 0, 0, 0, 0};
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nrf24_set_maclen(handle, size);
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nrf24_set_maclen(handle, size);
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@@ -158,7 +158,7 @@ uint8_t nrf24_set_src_mac(FuriHalSpiBusHandle* handle, uint8_t* mac, uint8_t siz
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return status;
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return status;
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}
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}
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-uint8_t nrf24_get_dst_mac(FuriHalSpiBusHandle* handle, uint8_t* mac) {
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+uint8_t nrf24_get_dst_mac(const FuriHalSpiBusHandle* handle, uint8_t* mac) {
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uint8_t size = 0;
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uint8_t size = 0;
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uint8_t status = 0;
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uint8_t status = 0;
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size = nrf24_get_maclen(handle);
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size = nrf24_get_maclen(handle);
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@@ -166,7 +166,7 @@ uint8_t nrf24_get_dst_mac(FuriHalSpiBusHandle* handle, uint8_t* mac) {
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return status;
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return status;
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}
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}
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-uint8_t nrf24_set_dst_mac(FuriHalSpiBusHandle* handle, uint8_t* mac, uint8_t size) {
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+uint8_t nrf24_set_dst_mac(const FuriHalSpiBusHandle* handle, uint8_t* mac, uint8_t size) {
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uint8_t status = 0;
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uint8_t status = 0;
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uint8_t clearmac[] = {0, 0, 0, 0, 0};
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uint8_t clearmac[] = {0, 0, 0, 0, 0};
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nrf24_set_maclen(handle, size);
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nrf24_set_maclen(handle, size);
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@@ -175,14 +175,14 @@ uint8_t nrf24_set_dst_mac(FuriHalSpiBusHandle* handle, uint8_t* mac, uint8_t siz
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return status;
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return status;
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}
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}
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-uint8_t nrf24_get_packetlen(FuriHalSpiBusHandle* handle, uint8_t pipe) {
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+uint8_t nrf24_get_packetlen(const FuriHalSpiBusHandle* handle, uint8_t pipe) {
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uint8_t len = 0;
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uint8_t len = 0;
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if(pipe > 5) pipe = 0;
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if(pipe > 5) pipe = 0;
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nrf24_read_reg(handle, RX_PW_P0 + pipe, &len, 1);
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nrf24_read_reg(handle, RX_PW_P0 + pipe, &len, 1);
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return len;
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return len;
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}
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}
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-uint8_t nrf24_set_packetlen(FuriHalSpiBusHandle* handle, uint8_t len) {
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+uint8_t nrf24_set_packetlen(const FuriHalSpiBusHandle* handle, uint8_t len) {
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uint8_t status = 0;
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uint8_t status = 0;
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status = nrf24_write_reg(handle, RX_PW_P0, len);
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status = nrf24_write_reg(handle, RX_PW_P0, len);
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return status;
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return status;
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@@ -190,7 +190,7 @@ uint8_t nrf24_set_packetlen(FuriHalSpiBusHandle* handle, uint8_t len) {
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// packet_size: 0 - dyn payload (read from PL_WID), 1 - read from pipe size, >1 - override
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// packet_size: 0 - dyn payload (read from PL_WID), 1 - read from pipe size, >1 - override
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// Return STATUS reg + additional: RX_DR - new data available, 0x80 - NRF24 hardware error
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// Return STATUS reg + additional: RX_DR - new data available, 0x80 - NRF24 hardware error
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-uint8_t nrf24_rxpacket(FuriHalSpiBusHandle* handle, uint8_t* packet, uint8_t* ret_packetsize, uint8_t packet_size) {
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+uint8_t nrf24_rxpacket(const FuriHalSpiBusHandle* handle, uint8_t* packet, uint8_t* ret_packetsize, uint8_t packet_size) {
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uint8_t status = 0;
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uint8_t status = 0;
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uint8_t buf[33]; // 32 max payload size + 1 for command
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uint8_t buf[33]; // 32 max payload size + 1 for command
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@@ -228,7 +228,7 @@ uint8_t nrf24_rxpacket(FuriHalSpiBusHandle* handle, uint8_t* packet, uint8_t* re
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}
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}
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// Return 0 when error
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// Return 0 when error
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-uint8_t nrf24_txpacket(FuriHalSpiBusHandle* handle, uint8_t* payload, uint8_t size, bool ack) {
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+uint8_t nrf24_txpacket(const FuriHalSpiBusHandle* handle, uint8_t* payload, uint8_t size, bool ack) {
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uint8_t status = 0;
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uint8_t status = 0;
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uint8_t buf[size + 1];
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uint8_t buf[size + 1];
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buf[0] = ack ? W_TX_PAYLOAD : W_TX_PAYLOAD_NOACK;
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buf[0] = ack ? W_TX_PAYLOAD : W_TX_PAYLOAD_NOACK;
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@@ -250,7 +250,7 @@ uint8_t nrf24_txpacket(FuriHalSpiBusHandle* handle, uint8_t* payload, uint8_t si
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return status & TX_DS;
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return status & TX_DS;
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}
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}
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-uint8_t nrf24_power_up(FuriHalSpiBusHandle* handle) {
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+uint8_t nrf24_power_up(const FuriHalSpiBusHandle* handle) {
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uint8_t status = 0;
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uint8_t status = 0;
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uint8_t cfg = 0;
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uint8_t cfg = 0;
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nrf24_read_reg(handle, REG_CONFIG, &cfg, 1);
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nrf24_read_reg(handle, REG_CONFIG, &cfg, 1);
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@@ -260,7 +260,7 @@ uint8_t nrf24_power_up(FuriHalSpiBusHandle* handle) {
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return status;
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return status;
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}
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}
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-uint8_t nrf24_set_idle(FuriHalSpiBusHandle* handle) {
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+uint8_t nrf24_set_idle(const FuriHalSpiBusHandle* handle) {
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uint8_t status = 0;
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uint8_t status = 0;
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uint8_t cfg = 0;
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uint8_t cfg = 0;
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nrf24_read_reg(handle, REG_CONFIG, &cfg, 1);
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nrf24_read_reg(handle, REG_CONFIG, &cfg, 1);
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@@ -270,7 +270,7 @@ uint8_t nrf24_set_idle(FuriHalSpiBusHandle* handle) {
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return status;
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return status;
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}
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}
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-uint8_t nrf24_set_rx_mode(FuriHalSpiBusHandle* handle) {
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+uint8_t nrf24_set_rx_mode(const FuriHalSpiBusHandle* handle) {
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uint8_t cfg = 0;
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uint8_t cfg = 0;
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cfg = nrf24_read_register(handle, REG_CONFIG);
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cfg = nrf24_read_register(handle, REG_CONFIG);
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cfg |= 0x03; // PWR_UP, and PRIM_RX
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cfg |= 0x03; // PWR_UP, and PRIM_RX
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@@ -279,7 +279,7 @@ uint8_t nrf24_set_rx_mode(FuriHalSpiBusHandle* handle) {
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return cfg;
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return cfg;
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}
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}
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-uint8_t nrf24_set_tx_mode(FuriHalSpiBusHandle* handle) {
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+uint8_t nrf24_set_tx_mode(const FuriHalSpiBusHandle* handle) {
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uint8_t reg;
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uint8_t reg;
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furi_hal_gpio_write(nrf24_CE_PIN, false);
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furi_hal_gpio_write(nrf24_CE_PIN, false);
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//nrf24_write_reg(handle, REG_STATUS, TX_DS | MAX_RT);
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//nrf24_write_reg(handle, REG_STATUS, TX_DS | MAX_RT);
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