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@@ -17,6 +17,13 @@
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#include <main.h>
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#include <furi-hal-pwm.h>
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+#define IRDA_TX_DEBUG 0
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+
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+#if IRDA_TX_DEBUG == 1
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+#define gpio_irda_tx gpio_irda_tx_debug
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+const GpioPin gpio_irda_tx_debug = {.port = GPIOA, .pin = GPIO_PIN_7};
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+#endif
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+
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#define IRDA_TIM_TX_DMA_BUFFER_SIZE 200
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#define IRDA_POLARITY_SHIFT 1
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@@ -46,6 +53,9 @@ typedef struct {
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void* signal_sent_context;
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IrdaTxBuf buffer[2];
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osSemaphoreId_t stop_semaphore;
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+ uint32_t tx_timing_rest_duration; /** if timing is too long (> 0xFFFF), send it in few iterations */
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+ bool tx_timing_rest_level;
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+ FuriHalIrdaTxGetDataState tx_timing_rest_status;
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} IrdaTimTx;
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typedef enum {
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@@ -62,7 +72,7 @@ static volatile IrdaState furi_hal_irda_state = IrdaStateIdle;
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static IrdaTimTx irda_tim_tx;
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static IrdaTimRx irda_tim_rx;
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-static bool furi_hal_irda_tx_fill_buffer(uint8_t buf_num, uint8_t polarity_shift);
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+static void furi_hal_irda_tx_fill_buffer(uint8_t buf_num, uint8_t polarity_shift);
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static void furi_hal_irda_async_tx_free_resources(void);
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static void furi_hal_irda_tx_dma_set_polarity(uint8_t buf_num, uint8_t polarity_shift);
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static void furi_hal_irda_tx_dma_set_buffer(uint8_t buf_num);
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@@ -72,6 +82,7 @@ static void furi_hal_irda_tx_dma_polarity_isr();
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static void furi_hal_irda_tx_dma_isr();
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static void furi_hal_irda_tim_rx_isr() {
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+ static uint32_t previous_captured_ch2 = 0;
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/* Timeout */
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if(LL_TIM_IsActiveFlag_CC3(TIM2)) {
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@@ -97,7 +108,7 @@ static void furi_hal_irda_tim_rx_isr() {
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if(READ_BIT(TIM2->CCMR1, TIM_CCMR1_CC1S)) {
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/* Low pin level is a Mark state of IRDA signal. Invert level for further processing. */
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- uint32_t duration = LL_TIM_IC_GetCaptureCH1(TIM2) - LL_TIM_IC_GetCaptureCH2(TIM2);
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+ uint32_t duration = LL_TIM_IC_GetCaptureCH1(TIM2) - previous_captured_ch2;
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if (irda_tim_rx.capture_callback)
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irda_tim_rx.capture_callback(irda_tim_rx.capture_context, 1, duration);
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} else {
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@@ -113,6 +124,7 @@ static void furi_hal_irda_tim_rx_isr() {
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if(READ_BIT(TIM2->CCMR1, TIM_CCMR1_CC2S)) {
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/* High pin level is a Space state of IRDA signal. Invert level for further processing. */
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uint32_t duration = LL_TIM_IC_GetCaptureCH2(TIM2);
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+ previous_captured_ch2 = duration;
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if (irda_tim_rx.capture_callback)
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irda_tim_rx.capture_callback(irda_tim_rx.capture_context, 0, duration);
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} else {
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@@ -258,14 +270,10 @@ static void furi_hal_irda_tx_dma_isr() {
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if (irda_tim_tx.buffer[buf_num].last_packet_end) {
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LL_DMA_DisableIT_HT(DMA1, LL_DMA_CHANNEL_2);
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} else if (!irda_tim_tx.buffer[buf_num].packet_end || (furi_hal_irda_state == IrdaStateAsyncTx)) {
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- bool result = furi_hal_irda_tx_fill_buffer(next_buf_num, 0);
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+ furi_hal_irda_tx_fill_buffer(next_buf_num, 0);
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if (irda_tim_tx.buffer[next_buf_num].last_packet_end) {
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LL_DMA_DisableIT_HT(DMA1, LL_DMA_CHANNEL_2);
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}
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- if (!result) {
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- furi_assert(0);
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- furi_hal_irda_state = IrdaStateAsyncTxStopReq;
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- }
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} else if (furi_hal_irda_state == IrdaStateAsyncTxStopReq) {
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/* fallthrough */
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} else {
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@@ -291,7 +299,7 @@ static void furi_hal_irda_tx_dma_isr() {
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/* if it's not end of the packet - continue receiving */
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furi_hal_irda_tx_dma_set_buffer(next_buf_num);
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}
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- if (irda_tim_tx.signal_sent_callback) {
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+ if (irda_tim_tx.signal_sent_callback && irda_tim_tx.buffer[buf_num].packet_end && (furi_hal_irda_state != IrdaStateAsyncTxStopped)) {
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irda_tim_tx.signal_sent_callback(irda_tim_tx.signal_sent_context);
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}
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}
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@@ -309,6 +317,16 @@ static void furi_hal_irda_configure_tim_pwm_tx(uint32_t freq, float duty_cycle)
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LL_TIM_SetCounterMode(TIM1, LL_TIM_COUNTERMODE_UP);
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LL_TIM_EnableARRPreload(TIM1);
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LL_TIM_SetAutoReload(TIM1, __LL_TIM_CALC_ARR(SystemCoreClock, LL_TIM_GetPrescaler(TIM1), freq));
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+#if IRDA_TX_DEBUG == 1
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+ LL_TIM_OC_SetCompareCH1(TIM1, ( (LL_TIM_GetAutoReload(TIM1) + 1 ) * (1 - duty_cycle)));
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+ LL_TIM_OC_EnablePreload(TIM1, LL_TIM_CHANNEL_CH1);
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+ /* LL_TIM_OCMODE_PWM2 set by DMA */
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+ LL_TIM_OC_SetMode(TIM1, LL_TIM_CHANNEL_CH1, LL_TIM_OCMODE_FORCED_INACTIVE);
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+ LL_TIM_OC_SetPolarity(TIM1, LL_TIM_CHANNEL_CH1N, LL_TIM_OCPOLARITY_HIGH);
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+ LL_TIM_OC_DisableFast(TIM1, LL_TIM_CHANNEL_CH1);
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+ LL_TIM_CC_EnableChannel(TIM1, LL_TIM_CHANNEL_CH1N);
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+ LL_TIM_DisableIT_CC1(TIM1);
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+#else
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LL_TIM_OC_SetCompareCH3(TIM1, ( (LL_TIM_GetAutoReload(TIM1) + 1 ) * (1 - duty_cycle)));
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LL_TIM_OC_EnablePreload(TIM1, LL_TIM_CHANNEL_CH3);
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/* LL_TIM_OCMODE_PWM2 set by DMA */
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@@ -317,6 +335,7 @@ static void furi_hal_irda_configure_tim_pwm_tx(uint32_t freq, float duty_cycle)
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LL_TIM_OC_DisableFast(TIM1, LL_TIM_CHANNEL_CH3);
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LL_TIM_CC_EnableChannel(TIM1, LL_TIM_CHANNEL_CH3N);
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LL_TIM_DisableIT_CC3(TIM1);
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+#endif
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LL_TIM_DisableMasterSlaveMode(TIM1);
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LL_TIM_EnableAllOutputs(TIM1);
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LL_TIM_DisableIT_UPDATE(TIM1);
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@@ -330,7 +349,11 @@ static void furi_hal_irda_configure_tim_cmgr2_dma_tx(void) {
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LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMA1);
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LL_DMA_InitTypeDef dma_config = {0};
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+#if IRDA_TX_DEBUG == 1
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+ dma_config.PeriphOrM2MSrcAddress = (uint32_t)&(TIM1->CCMR1);
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+#else
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dma_config.PeriphOrM2MSrcAddress = (uint32_t)&(TIM1->CCMR2);
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+#endif
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dma_config.MemoryOrM2MDstAddress = (uint32_t) NULL;
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dma_config.Direction = LL_DMA_DIRECTION_MEMORY_TO_PERIPH;
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dma_config.Mode = LL_DMA_MODE_NORMAL;
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@@ -399,7 +422,7 @@ static void furi_hal_irda_tx_fill_buffer_last(uint8_t buf_num) {
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irda_tim_tx.buffer[buf_num].packet_end = true;
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}
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-static bool furi_hal_irda_tx_fill_buffer(uint8_t buf_num, uint8_t polarity_shift) {
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+static void furi_hal_irda_tx_fill_buffer(uint8_t buf_num, uint8_t polarity_shift) {
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furi_assert(buf_num < 2);
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furi_assert(furi_hal_irda_state != IrdaStateAsyncRx);
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furi_assert(furi_hal_irda_state < IrdaStateMAX);
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@@ -418,28 +441,53 @@ static bool furi_hal_irda_tx_fill_buffer(uint8_t buf_num, uint8_t polarity_shift
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}
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for (*size = 0; (*size < IRDA_TIM_TX_DMA_BUFFER_SIZE) && (status == FuriHalIrdaTxGetDataStateOk); ++(*size), ++polarity_counter) {
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- status = irda_tim_tx.data_callback(irda_tim_tx.data_context, &duration, &level);
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- if (status == FuriHalIrdaTxGetDataStateError) {
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- furi_assert(0);
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- break;
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+ if (irda_tim_tx.tx_timing_rest_duration > 0) {
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+ if (irda_tim_tx.tx_timing_rest_duration > 0xFFFF) {
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+ buffer->data[*size] = 0xFFFF;
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+ status = FuriHalIrdaTxGetDataStateOk;
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+ } else {
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+ buffer->data[*size] = irda_tim_tx.tx_timing_rest_duration;
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+ status = irda_tim_tx.tx_timing_rest_status;
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+ }
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+ irda_tim_tx.tx_timing_rest_duration -= buffer->data[*size];
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+ buffer->polarity[polarity_counter] = irda_tim_tx.tx_timing_rest_level ? IRDA_TX_CCMR_HIGH : IRDA_TX_CCMR_LOW;
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+ continue;
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}
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+ status = irda_tim_tx.data_callback(irda_tim_tx.data_context, &duration, &level);
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+
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uint32_t num_of_impulses = roundf(duration / irda_tim_tx.cycle_duration);
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- if ((buffer->data[*size] + num_of_impulses - 1) > 0xFFFF) {
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- furi_assert(0);
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- status = FuriHalIrdaTxGetDataStateError;
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- break;
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+ if (num_of_impulses == 0) {
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+ if ((*size == 0) && (status == FuriHalIrdaTxGetDataStateDone)) {
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+ /* if this is one sample in current buffer, but we
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+ * have more to send - continue
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+ */
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+ status = FuriHalIrdaTxGetDataStateOk;
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+ }
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+ --(*size);
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+ --polarity_counter;
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+ } else if ((num_of_impulses - 1) > 0xFFFF) {
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+ irda_tim_tx.tx_timing_rest_duration = num_of_impulses - 1;
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+ irda_tim_tx.tx_timing_rest_status = status;
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+ irda_tim_tx.tx_timing_rest_level = level;
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+ buffer->polarity[polarity_counter] = level ? IRDA_TX_CCMR_HIGH : IRDA_TX_CCMR_LOW;
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+ buffer->data[*size] = 0xFFFF;
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+ status = FuriHalIrdaTxGetDataStateOk;
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+ } else {
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+ buffer->polarity[polarity_counter] = level ? IRDA_TX_CCMR_HIGH : IRDA_TX_CCMR_LOW;
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+ buffer->data[*size] = num_of_impulses - 1;
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}
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-
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- buffer->polarity[polarity_counter] = level ? IRDA_TX_CCMR_HIGH : IRDA_TX_CCMR_LOW;
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- buffer->data[*size] = num_of_impulses - 1;
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}
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buffer->last_packet_end = (status == FuriHalIrdaTxGetDataStateLastDone);
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buffer->packet_end = buffer->last_packet_end || (status == FuriHalIrdaTxGetDataStateDone);
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- return status != FuriHalIrdaTxGetDataStateError;
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+ if (*size == 0) {
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+ buffer->data[0] = 0; // 1 pulse
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+ buffer->polarity[0] = IRDA_TX_CCMR_LOW;
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+ buffer->size = 1;
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+ }
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}
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static void furi_hal_irda_tx_dma_set_polarity(uint8_t buf_num, uint8_t polarity_shift) {
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@@ -505,10 +553,9 @@ static void furi_hal_irda_async_tx_free_resources(void) {
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irda_tim_tx.buffer[1].polarity = NULL;
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}
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-bool furi_hal_irda_async_tx_start(uint32_t freq, float duty_cycle) {
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- if ((duty_cycle > 1) || (duty_cycle < 0) || (freq > 40000) || (freq < 10000) || (irda_tim_tx.data_callback == NULL)) {
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- furi_assert(0);
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- return false;
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+void furi_hal_irda_async_tx_start(uint32_t freq, float duty_cycle) {
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+ if ((duty_cycle > 1) || (duty_cycle <= 0) || (freq > IRDA_MAX_FREQUENCY) || (freq < IRDA_MIN_FREQUENCY) || (irda_tim_tx.data_callback == NULL)) {
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+ furi_check(0);
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}
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furi_assert(furi_hal_irda_state == IrdaStateIdle);
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@@ -527,37 +574,31 @@ bool furi_hal_irda_async_tx_start(uint32_t freq, float duty_cycle) {
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irda_tim_tx.stop_semaphore = osSemaphoreNew(1, 0, NULL);
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irda_tim_tx.cycle_duration = 1000000.0 / freq;
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+ irda_tim_tx.tx_timing_rest_duration = 0;
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- bool result = furi_hal_irda_tx_fill_buffer(0, IRDA_POLARITY_SHIFT);
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-
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- if (result) {
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- furi_hal_irda_configure_tim_pwm_tx(freq, duty_cycle);
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- furi_hal_irda_configure_tim_cmgr2_dma_tx();
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- furi_hal_irda_configure_tim_rcr_dma_tx();
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- furi_hal_irda_tx_dma_set_polarity(0, IRDA_POLARITY_SHIFT);
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- furi_hal_irda_tx_dma_set_buffer(0);
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-
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- furi_hal_irda_state = IrdaStateAsyncTx;
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+ furi_hal_irda_tx_fill_buffer(0, IRDA_POLARITY_SHIFT);
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- LL_TIM_ClearFlag_UPDATE(TIM1);
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- LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_1);
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- LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_2);
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- delay_us(5);
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- LL_TIM_GenerateEvent_UPDATE(TIM1); /* DMA -> TIMx_RCR */
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- delay_us(5);
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- LL_GPIO_ResetOutputPin(gpio_irda_tx.port, gpio_irda_tx.pin); /* when disable it prevents false pulse */
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- hal_gpio_init_ex(&gpio_irda_tx, GpioModeAltFunctionPushPull, GpioPullUp, GpioSpeedHigh, GpioAltFn1TIM1);
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+ furi_hal_irda_configure_tim_pwm_tx(freq, duty_cycle);
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+ furi_hal_irda_configure_tim_cmgr2_dma_tx();
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+ furi_hal_irda_configure_tim_rcr_dma_tx();
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+ furi_hal_irda_tx_dma_set_polarity(0, IRDA_POLARITY_SHIFT);
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+ furi_hal_irda_tx_dma_set_buffer(0);
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- __disable_irq();
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- LL_TIM_GenerateEvent_UPDATE(TIM1); /* TIMx_RCR -> Repetition counter */
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- LL_TIM_EnableCounter(TIM1);
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- __enable_irq();
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+ furi_hal_irda_state = IrdaStateAsyncTx;
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- } else {
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- furi_hal_irda_async_tx_free_resources();
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- }
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+ LL_TIM_ClearFlag_UPDATE(TIM1);
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+ LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_1);
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+ LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_2);
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+ delay_us(5);
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+ LL_TIM_GenerateEvent_UPDATE(TIM1); /* DMA -> TIMx_RCR */
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+ delay_us(5);
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+ LL_GPIO_ResetOutputPin(gpio_irda_tx.port, gpio_irda_tx.pin); /* when disable it prevents false pulse */
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+ hal_gpio_init_ex(&gpio_irda_tx, GpioModeAltFunctionPushPull, GpioPullUp, GpioSpeedHigh, GpioAltFn1TIM1);
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- return result;
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+ __disable_irq();
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+ LL_TIM_GenerateEvent_UPDATE(TIM1); /* TIMx_RCR -> Repetition counter */
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+ LL_TIM_EnableCounter(TIM1);
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+ __enable_irq();
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}
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void furi_hal_irda_async_tx_wait_termination(void) {
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