F1 family.

cmake/FindCMSIS.cmake

@@ -1,5 +1,5 @@
 if(NOT CMSIS_FIND_COMPONENTS)
-    set(CMSIS_FIND_COMPONENTS STM32F0 STM32F4)
+    set(CMSIS_FIND_COMPONENTS STM32F0 STM32F1 STM32F4)
 endif()
 
 include(stm32/devices)

cmake/stm32/common.cmake

@@ -69,7 +69,7 @@ function(stm32_get_memory_info FAMILY DEVICE
     FLASH_SIZE RAM_SIZE CCRAM_SIZE STACK_SIZE HEAP_SIZE 
     FLASH_ORIGIN RAM_ORIGIN CCRAM_ORIGIN
 )
-    string(REGEX REPLACE "^[FHL][0-9][0-9][0-9].([468BCDEGHI])$" "\\1" SIZE_CODE ${DEVICE})
+    string(REGEX REPLACE "^[FGHL][0-9][0-9][0-9].([468BCDEFGHI])$" "\\1" SIZE_CODE ${DEVICE})
     
     if(SIZE_CODE STREQUAL "4")
         set(FLASH "16K")
@@ -85,6 +85,8 @@ function(stm32_get_memory_info FAMILY DEVICE
         set(FLASH "384K")
     elseif(SIZE_CODE STREQUAL "E")
         set(FLASH "512K")
+    elseif(SIZE_CODE STREQUAL "F")
+        set(FLASH "768K")
     elseif(SIZE_CODE STREQUAL "G")
         set(FLASH "1024K")
     elseif(SIZE_CODE STREQUAL "H")
@@ -100,6 +102,11 @@ function(stm32_get_memory_info FAMILY DEVICE
     list(FIND STM32_${FAMILY}_TYPES ${TYPE} TYPE_INDEX)
     list(GET STM32_${FAMILY}_RAM_SIZES ${TYPE_INDEX} RAM)
     list(GET STM32_${FAMILY}_CCRAM_SIZES ${TYPE_INDEX} CCRAM)
+    
+    if(FAMILY STREQUAL "F1")
+        stm32f1_get_memory_info(${DEVICE} ${TYPE} FLASH RAM)
+    endif()
+    
 
     set(${FLASH_SIZE} ${FLASH} PARENT_SCOPE)
     set(${RAM_SIZE} ${RAM} PARENT_SCOPE)
@@ -124,5 +131,6 @@ endif()
 
 include(stm32/utilities)
 include(stm32/f0)
+include(stm32/f1)
 include(stm32/f4)
 

cmake/stm32/f1.cmake

@@ -0,0 +1,78 @@
+set(STM32_F1_TYPES 
+    100xB 100xE 101x6 101xB 101xE 101xG 102x6 102xB 
+    103x6 103xB 103xE 103xG 105xC 107xC
+)
+set(STM32_F1_TYPE_MATCH 
+    "F100.[468B]" "F100.[CDE]" "F101.[46]" "F101.[8B]" "F101.[CDE]" "F101.[FG]" "F102.[46]" "F102.[8B]" 
+    "F103.[46]" "F103.[8B]" "F103.[CDE]" "F103.[FG]" "F105.[8BC]" "F107.[BC]"
+)
+set(STM32_F1_RAM_SIZES 
+     0K  0K  0K  0K  0K  0K  0K  0K
+     0K  0K  0K  0K  0K  0K
+)
+set(STM32_F1_CCRAM_SIZES 
+     0K  0K  0K  0K  0K  0K  0K  0K
+     0K  0K  0K  0K  0K  0K
+)
+
+stm32_util_create_family_targets(F1)
+
+target_compile_options(STM32::F1 INTERFACE 
+    -mcpu=cortex-m3
+)
+target_link_options(STM32::F1 INTERFACE 
+    -mcpu=cortex-m3
+)
+
+function(stm32f1_get_memory_info DEVICE TYPE FLASH_SIZE RAM_SIZE)
+    string(REGEX REPLACE "F1[0-9][0-9].([468BCDEFGHI])" "\\1" SIZE_CODE ${DEVICE})
+    
+    if((TYPE STREQUAL "100xB") OR (TYPE STREQUAL "100xE"))
+        if((SIZE_CODE STREQUAL "4") OR (SIZE_CODE STREQUAL "6"))
+            set(RAM "4K")
+        elseif((SIZE_CODE STREQUAL "8") OR (SIZE_CODE STREQUAL "B"))
+            set(RAM "8K")
+        elseif(SIZE_CODE STREQUAL "C")
+            set(RAM "24K")
+        elseif((SIZE_CODE STREQUAL "D") OR (SIZE_CODE STREQUAL "E"))
+            set(RAM "32K")
+        endif()
+    elseif((TYPE STREQUAL "101x6") OR (TYPE STREQUAL "101xB") OR 
+           (TYPE STREQUAL "101xE") OR (TYPE STREQUAL "101xG") OR
+           (TYPE STREQUAL "102x6") OR (TYPE STREQUAL "102xB"))
+        if(SIZE_CODE STREQUAL "4")
+            set(RAM "4K")
+        elseif(SIZE_CODE STREQUAL "6")
+            set(RAM "6K")
+        elseif(SIZE_CODE STREQUAL "8")
+            set(RAM "10K")
+        elseif(SIZE_CODE STREQUAL "B")
+            set(RAM "16K")
+        elseif(SIZE_CODE STREQUAL "C")
+            set(RAM "32K")
+        elseif((SIZE_CODE STREQUAL "D") OR (SIZE_CODE STREQUAL "E"))
+            set(RAM "48K")
+        elseif((SIZE_CODE STREQUAL "F") OR (SIZE_CODE STREQUAL "G"))
+            set(RAM "80K")
+        endif()
+    elseif((TYPE STREQUAL "103x6") OR (TYPE STREQUAL "103xB") OR
+           (TYPE STREQUAL "103xE") OR (TYPE STREQUAL "103xG"))
+        if(SIZE_CODE STREQUAL "4")
+            set(RAM "6K")
+        elseif(SIZE_CODE STREQUAL "6")
+            set(RAM "10K")
+        elseif((SIZE_CODE STREQUAL "8") OR (SIZE_CODE STREQUAL "B"))
+            set(RAM "20K")
+        elseif(SIZE_CODE STREQUAL "C")
+            set(RAM "48K")
+        elseif((SIZE_CODE STREQUAL "D") OR (SIZE_CODE STREQUAL "E"))
+            set(RAM "64K")
+        elseif((SIZE_CODE STREQUAL "F") OR (SIZE_CODE STREQUAL "G"))
+            set(RAM "96K")
+        endif()
+    elseif((TYPE STREQUAL "105xC") OR (TYPE STREQUAL "107xC"))
+        set(RAM "64K")
+    endif()
+    
+    set(${RAM_SIZE} ${RAM} PARENT_SCOPE)
+endfunction()

tests/cmsis/CMakeLists.txt

@@ -2,7 +2,7 @@ cmake_minimum_required(VERSION 3.8)
 set(CMAKE_TOOLCHAIN_FILE ${CMAKE_CURRENT_SOURCE_DIR}/../../cmake/stm32_gcc.cmake)
 
 if(NOT TEST_FAMILIES)
-    set(TEST_FAMILIES F0 F4)
+    set(TEST_FAMILIES F0 F1 F4)
 endif()
 
 project(cmsis-test C ASM)