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+/* Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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+ *
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+ * Licensed under the Apache License, Version 2.0 (the "License");
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+ * you may not use this file except in compliance with the License.
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+ * You may obtain a copy of the License at
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+ *
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+ * http://www.apache.org/licenses/LICENSE-2.0
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+ *
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+ * Unless required by applicable law or agreed to in writing, software
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+ * distributed under the License is distributed on an "AS IS" BASIS,
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+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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+ * See the License for the specific language governing permissions and
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+ * limitations under the License.
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+ */
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+
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+#include "esp_targets.h"
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+#include <stddef.h>
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+
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+typedef esp_loader_error_t (*read_spi_config_t)(uint32_t efuse_base, uint32_t *spi_config);
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+
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+typedef struct {
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+ target_registers_t regs;
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+ uint32_t efuse_base;
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+ uint32_t chip_magic_value;
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+ read_spi_config_t read_spi_config;
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+} esp_target_t;
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+
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+// This ROM address has a different value on each chip model
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+#define CHIP_DETECT_MAGIC_REG_ADDR 0x40001000
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+
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+#define ESP8266_SPI_REG_BASE 0x60000200
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+#define ESP32S2_SPI_REG_BASE 0x3f402000
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+#define ESP32_SPI_REG_BASE 0x3ff42000
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+
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+static esp_loader_error_t spi_config_esp32(uint32_t efuse_base, uint32_t *spi_config);
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+static esp_loader_error_t spi_config_esp32s2(uint32_t efuse_base, uint32_t *spi_config);
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+
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+static const esp_target_t esp_target[ESP_MAX_CHIP] = {
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+
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+ // ESP8266
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+ {
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+ .regs = {
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+ .cmd = ESP8266_SPI_REG_BASE + 0x00,
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+ .usr = ESP8266_SPI_REG_BASE + 0x1c,
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+ .usr1 = ESP8266_SPI_REG_BASE + 0x20,
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+ .usr2 = ESP8266_SPI_REG_BASE + 0x24,
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+ .w0 = ESP8266_SPI_REG_BASE + 0x40,
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+ .mosi_dlen = 0,
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+ .miso_dlen = 0,
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+ },
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+ .efuse_base = 0, // Not used
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+ .chip_magic_value = 0xfff0c101,
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+ .read_spi_config = NULL, // Not used
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+ },
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+
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+ // ESP32
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+ {
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+ .regs = {
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+ .cmd = ESP32_SPI_REG_BASE + 0x00,
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+ .usr = ESP32_SPI_REG_BASE + 0x1c,
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+ .usr1 = ESP32_SPI_REG_BASE + 0x20,
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+ .usr2 = ESP32_SPI_REG_BASE + 0x24,
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+ .w0 = ESP32_SPI_REG_BASE + 0x80,
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+ .mosi_dlen = ESP32_SPI_REG_BASE + 0x28,
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+ .miso_dlen = ESP32_SPI_REG_BASE + 0x2c,
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+ },
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+ .efuse_base = 0x3ff5A000,
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+ .chip_magic_value = 0x00f01d83,
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+ .read_spi_config = spi_config_esp32,
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+ },
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+
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+ // ESP32S2
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+ {
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+ .regs = {
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+ .cmd = ESP32S2_SPI_REG_BASE + 0x00,
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+ .usr = ESP32S2_SPI_REG_BASE + 0x18,
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+ .usr1 = ESP32S2_SPI_REG_BASE + 0x1c,
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+ .usr2 = ESP32S2_SPI_REG_BASE + 0x20,
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+ .w0 = ESP32S2_SPI_REG_BASE + 0x58,
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+ .mosi_dlen = ESP32S2_SPI_REG_BASE + 0x24,
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+ .miso_dlen = ESP32S2_SPI_REG_BASE + 0x28,
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+ },
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+ .efuse_base = 0x3f41A000,
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+ .chip_magic_value = 0x000007c6,
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+ .read_spi_config = spi_config_esp32s2,
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+ }
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+};
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+
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+const target_registers_t *get_esp_target_data(target_chip_t chip)
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+{
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+ return (target_registers_t *)&esp_target[chip];
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+}
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+
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+esp_loader_error_t loader_detect_chip(target_chip_t *target_chip, const target_registers_t **target_data)
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+{
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+ uint32_t magic_value;
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+ RETURN_ON_ERROR( esp_loader_read_register(CHIP_DETECT_MAGIC_REG_ADDR, &magic_value) );
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+
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+ for (int chip = 0; chip < ESP_MAX_CHIP; chip++) {
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+ if (magic_value == esp_target[chip].chip_magic_value) {
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+ *target_chip = (target_chip_t)chip;
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+ *target_data = (target_registers_t*)&esp_target[chip];
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+ return ESP_LOADER_SUCCESS;
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+ }
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+ }
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+
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+ return ESP_LOADER_ERROR_INVALID_TARGET;
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+}
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+
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+esp_loader_error_t loader_read_spi_config(target_chip_t target_chip, uint32_t *spi_config)
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+{
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+ const esp_target_t *target = &esp_target[target_chip];
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+ return target->read_spi_config(target->efuse_base, spi_config);
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+}
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+
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+static inline uint32_t efuse_word_addr(uint32_t efuse_base, uint32_t n)
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+{
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+ return efuse_base + (n * 4);
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+}
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+
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+// 30->GPIO32 | 31->GPIO33
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+static inline uint8_t adjust_pin_number(uint8_t num)
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+{
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+ return (num >= 30) ? num + 2 : num;
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+}
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+
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+
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+static esp_loader_error_t spi_config_esp32(uint32_t efuse_base, uint32_t *spi_config)
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+{
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+ *spi_config = 0;
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+
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+ uint32_t reg5, reg3;
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+ RETURN_ON_ERROR( esp_loader_read_register(efuse_word_addr(efuse_base, 5), ®5) );
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+ RETURN_ON_ERROR( esp_loader_read_register(efuse_word_addr(efuse_base, 3), ®3) );
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+
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+ uint32_t pins = reg5 & 0xfffff;
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+
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+ if (pins == 0 || pins == 0xfffff) {
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+ return ESP_LOADER_SUCCESS;
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+ }
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+
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+ uint8_t clk = adjust_pin_number( (pins >> 0) & 0x1f );
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+ uint8_t q = adjust_pin_number( (pins >> 5) & 0x1f );
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+ uint8_t d = adjust_pin_number( (pins >> 10) & 0x1f );
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+ uint8_t cs = adjust_pin_number( (pins >> 15) & 0x1f );
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+ uint8_t hd = adjust_pin_number( (reg3 >> 4) & 0x1f );
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+
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+ if (clk == cs || clk == d || clk == q || q == cs || q == d || q == d) {
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+ return ESP_LOADER_SUCCESS;
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+ }
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+
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+ *spi_config = (hd << 24) | (cs << 18) | (d << 12) | (q << 6) | clk;
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+
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+ return ESP_LOADER_SUCCESS;
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+}
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+
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+static esp_loader_error_t spi_config_esp32s2(uint32_t efuse_base, uint32_t *spi_config)
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+{
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+ *spi_config = 0;
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+
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+ uint32_t reg1, reg2;
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+ RETURN_ON_ERROR( esp_loader_read_register(efuse_word_addr(efuse_base, 18), ®1) );
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+ RETURN_ON_ERROR( esp_loader_read_register(efuse_word_addr(efuse_base, 19), ®2) );
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+
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+ uint32_t pins = ((reg1 >> 16) | ((reg2 & 0xfffff) << 16)) & 0x3fffffff;
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+
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+ if (pins == 0 || pins == 0xffffffff) {
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+ return ESP_LOADER_SUCCESS;
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+ }
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+
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+ *spi_config = pins;
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+ return ESP_LOADER_SUCCESS;
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+}
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