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@@ -64,9 +64,9 @@
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#define RP_SSI_XIP_SPI_CTRL0_FORMAT_STD_SPI (0U << 0U)
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#define RP_SSI_XIP_SPI_CTRL0_FORMAT_SPLIT (1U << 0U)
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#define RP_SSI_XIP_SPI_CTRL0_FORMAT_FRF (2U << 0U)
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-#define RP_SSI_XIP_SPI_CTRL0_ADDRESS_LENGTH(x) (((x)*2U) << 2U)
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+#define RP_SSI_XIP_SPI_CTRL0_ADDRESS_LENGTH(x) (((x) * 2U) << 2U)
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#define RP_SSI_XIP_SPI_CTRL0_INSTR_LENGTH_8b (2U << 8U)
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-#define RP_SSI_XIP_SPI_CTRL0_WAIT_CYCLES(x) (((x)*8U) << 11U)
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+#define RP_SSI_XIP_SPI_CTRL0_WAIT_CYCLES(x) (((x) * 8U) << 11U)
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#define RP_SSI_XIP_SPI_CTRL0_XIP_CMD_SHIFT 24U
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#define RP_SSI_XIP_SPI_CTRL0_XIP_CMD(x) ((x) << RP_SSI_XIP_SPI_CTRL0_XIP_CMD_SHIFT)
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#define RP_SSI_XIP_SPI_CTRL0_TRANS_1C1A (0U << 0U)
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@@ -94,7 +94,7 @@
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// SPI Flash defines
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#define SPI_FLASH_OPCODE_MASK 0x00ffU
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-#define SPI_FLASH_OPCODE(x) ((x)&SPI_FLASH_OPCODE_MASK)
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+#define SPI_FLASH_OPCODE(x) ((x) & SPI_FLASH_OPCODE_MASK)
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#define SPI_FLASH_DUMMY_MASK 0x0700U
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#define SPI_FLASH_DUMMY_SHIFT 8U
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#define SPI_FLASH_DUMMY_LEN(x) (((x) << SPI_FLASH_DUMMY_SHIFT) & SPI_FLASH_DUMMY_MASK)
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