ChibiOS 3 support for F4/F1.

Preparing for using STM32CubeMX instead of StdPeriphLib.

cmake/Modules/ChibiOS3_HAL.cmake

@@ -48,8 +48,45 @@ IF(STM32_FAMILY STREQUAL "F1")
     )
     SET(CHIBIOS_hal_PLATFORM_SEARCH_HEADERS
         hal_lld.h
+        stm32_dma.h
+        nvic.h
+    )
+    SET(CHIBIOS_hal_PLATFORM_SOURCES  
+        hal_lld.c
+        stm32_dma.c
+        nvic.c
+    )
+ELSEIF(STM32_FAMILY STREQUAL "F4")
+    SET(CHIBIOS_HAL_PLATFORM_MODULES adc can dac ext gpt i2c icu mac pal pwm rtc sdc serial spi st uart usb)
+    SET(CHIBIOS_HAL_PLATFORM_MODULES_PATHES 
+      STM32F4xx 
+      LLD
+      LLD/DACv1
+      LLD
+      LLD/TIMv1
+      LLD/I2Cv1
+      LLD/TIMv1
+      LLD
+      LLD/GPIOv2
+      LLD/TIMv1
+      LLD/RTCv2
+      LLD
+      LLD/USARTv1 
+      LLD/SPIv1
+      LLD/TIMv1
+      LLD/USARTv1
+      LLD/OTGv1
+    )
+    
+    SET(CHIBIOS_hal_PLATFORM_SEARCH_PATH
+        ${CHIBIOS_ROOT}/os/hal/ports/common/ARMCMx
+        ${CHIBIOS_ROOT}/os/hal/ports/STM32/STM32F4xx
+        ${CHIBIOS_ROOT}/os/hal/ports/STM32
+    )
+    SET(CHIBIOS_hal_PLATFORM_SEARCH_HEADERS
+        hal_lld.h
+        stm32_dma.h
         nvic.h
-        stm32_registry.h
     )
     SET(CHIBIOS_hal_PLATFORM_SOURCES  
         hal_lld.c

cmake/Modules/ChibiOS3_LD.cmake

@@ -1,4 +1,4 @@
-IF(NOT CHIBIOS_PROCESS_STACK_SIZE)
+ IF(NOT CHIBIOS_PROCESS_STACK_SIZE)
   SET(CHIBIOS_PROCESS_STACK_SIZE 0x400)
   MESSAGE(STATUS "No CHIBIOS_PROCESS_STACK_SIZE specified, using default: ${CHIBIOS_PROCESS_STACK_SIZE}")
 ENDIF()
@@ -14,6 +14,24 @@ SET(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -Wl,--defsym=__main_stack_
 
 # Auto-generate linker script
 IF(NOT ChibiOS_LINKER_SCRIPT)
-    FILE(WRITE ${CMAKE_BINARY_DIR}/chibios_link.ld.in "MEMORY\n{\nflash : org = 0x08000000, len = \${STM32_FLASH_SIZE}\nram : org = 0x20000000, len = \${STM32_RAM_SIZE}\n}\nINCLUDE rules.ld\n")
+    FILE(WRITE ${CMAKE_BINARY_DIR}/chibios_link.ld.in 
+      "MEMORY\n"
+      "{\n"
+      "  flash : org = 0x08000000, len = \${STM32_FLASH_SIZE}\n"
+      "  ram0 : org = 0x20000000, len = \${STM32_RAM_SIZE}\n"
+      "  ram1 : org = 0x00000000, len = 0\n"
+      "  ram2 : org = 0x00000000, len = 0\n"
+      "  ram3 : org = 0x00000000, len = 0\n"
+      "  ram4 : org = 0x00000000, len = 0\n"
+      "  ram5 : org = 0x00000000, len = 0\n"
+      "  ram6 : org = 0x00000000, len = 0\n"
+      "  ram7 : org = 0x00000000, len = 0\n"
+      "}\n"
+      "REGION_ALIAS(\"MAIN_STACK_RAM\", ram0);\n"
+      "REGION_ALIAS(\"PROCESS_STACK_RAM\", ram0);\n"
+      "REGION_ALIAS(\"DATA_RAM\", ram0);\n"
+      "REGION_ALIAS(\"BSS_RAM\", ram0);\n"
+      "INCLUDE rules.ld\n"      
+    )
     SET(ChibiOS_LINKER_SCRIPT ${CMAKE_BINARY_DIR}/chibios_link.ld.in)
 ENDIF()     

cmake/Modules/ChibiOS3_NIL.cmake

@@ -12,7 +12,8 @@ SET(CHIBIOS_nil_SEARCH_HEADERS
   niltypes.h
 )
 SET(CHIBIOS_nil_SOURCES  
-  crt0.c
+  crt0_v7m.s
+  crt1.c
   vectors.c
   nilcore.c
   nilcore_v7m.c
@@ -31,4 +32,15 @@ IF(STM32_FAMILY STREQUAL "F1")
     stm32f10x.h
     cmparams.h
   )
+ELSEIF(STM32_FAMILY STREQUAL "F4")
+  SET(CHIBIOS_nil_PLATFORM_SEARCH_PATH
+    ${CHIBIOS_ROOT}/os/common/ports/ARMCMx/devices/STM32F4xx
+    ${CHIBIOS_ROOT}/os/ext/CMSIS/include
+    ${CHIBIOS_ROOT}/os/ext/CMSIS/ST
+  )
+  SET(CHIBIOS_nil_PLATFORM_SEARCH_HEADERS
+    core_cm4.h
+    stm32f4xx.h
+    cmparams.h
+  )
 ENDIF()

gcc_stm32f4.cmake

@@ -5,9 +5,8 @@ SET(CMAKE_ASM_FLAGS "-mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softf
 SET(CMAKE_EXE_LINKER_FLAGS "-nostartfiles -Wl,--gc-sections -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -mabi=aapcs" CACHE INTERNAL "executable linker flags")
 SET(CMAKE_MODULE_LINKER_FLAGS "-mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -mabi=aapcs" CACHE INTERNAL "module linker flags")
 SET(CMAKE_SHARED_LINKER_FLAGS "-mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -mabi=aapcs" CACHE INTERNAL "shared linker flags")
-
-SET(STM32_CHIP_TYPES 401xx 40_41xxx 427_437xx 429_439xx CACHE INTERNAL "stm32f4 chip types")
-SET(STM32_CODES "401.[BC]" "4[01][57].[EG]" "4[23]7.[EGI]" "4[23]9.[EGI]")
+SET(STM32_CHIP_TYPES 405xx 415xx 407xx 417xx 427xx 437xx 429xx 439xx 401xC 401xE 411xE CACHE INTERNAL "stm32f4 chip types")
+SET(STM32_CODES "405.." "415.." "407.." "417.." "427.." "437.." "429.." "439.." "401.[CB]" "401.[ED]" "411.[ED]")
 
 MACRO(STM32_GET_CHIP_TYPE CHIP CHIP_TYPE)
     STRING(REGEX REPLACE "^[sS][tT][mM]32[fF](4[0123][1579].[BCEGI]).+$" "\\1" STM32_CODE ${CHIP})
@@ -40,14 +39,28 @@ MACRO(STM32_GET_CHIP_PARAMETERS CHIP FLASH_SIZE RAM_SIZE)
     
     STM32_GET_CHIP_TYPE(${CHIP} TYPE)
     
-    IF(${TYPE} STREQUAL "401xx")
+    IF(${TYPE} STREQUAL "401xC")
         SET(RAM "64K")
-    ELSEIF(${TYPE} STREQUAL "40_41xxx")
+    ELSEIF(${TYPE} STREQUAL "401xE")
+        SET(RAM "96K")
+    ELSEIF(${TYPE} STREQUAL "411xE")
         SET(RAM "128K")
-    ELSEIF(${TYPE} STREQUAL "427_437xx")
+    ELSEIF(${TYPE} STREQUAL "405xx")
+        SET(RAM "192K")
+    ELSEIF(${TYPE} STREQUAL "415xx")
+        SET(RAM "192K")
+    ELSEIF(${TYPE} STREQUAL "407xx")
         SET(RAM "192K")
-    ELSEIF(${TYPE} STREQUAL "429_439xx")
+    ELSEIF(${TYPE} STREQUAL "417xx")
         SET(RAM "192K")
+    ELSEIF(${TYPE} STREQUAL "427xx")
+        SET(RAM "256K")
+    ELSEIF(${TYPE} STREQUAL "437xx")
+        SET(RAM "256K")
+    ELSEIF(${TYPE} STREQUAL "429xx")
+        SET(RAM "256K")
+    ELSEIF(${TYPE} STREQUAL "439xx")
+        SET(RAM "256K")
     ENDIF()
     
     SET(${FLASH_SIZE} ${FLASH})
@@ -65,5 +78,6 @@ FUNCTION(STM32_SET_CHIP_DEFINITIONS TARGET CHIP_TYPE)
     ELSE()
         SET(TARGET_DEFS "STM32F4;STM32F${CHIP_TYPE}")
     ENDIF()
+        
     SET_TARGET_PROPERTIES(${TARGET} PROPERTIES COMPILE_DEFINITIONS "${TARGET_DEFS}")
 ENDFUNCTION()